1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 1994 Linus Torvalds 4 * 5 * Pentium III FXSR, SSE support 6 * General FPU state handling cleanups 7 * Gareth Hughes <gareth@valinux.com>, May 2000 8 * x86-64 work by Andi Kleen 2002 9 */ 10 11 #ifndef _ASM_X86_FPU_API_H 12 #define _ASM_X86_FPU_API_H 13 #include <linux/bottom_half.h> 14 15 /* 16 * Use kernel_fpu_begin/end() if you intend to use FPU in kernel context. It 17 * disables preemption so be careful if you intend to use it for long periods 18 * of time. 19 * If you intend to use the FPU in irq/softirq you need to check first with 20 * irq_fpu_usable() if it is possible. 21 */ 22 23 /* Kernel FPU states to initialize in kernel_fpu_begin_mask() */ 24 #define KFPU_387 _BITUL(0) /* 387 state will be initialized */ 25 #define KFPU_MXCSR _BITUL(1) /* MXCSR will be initialized */ 26 27 extern void kernel_fpu_begin_mask(unsigned int kfpu_mask); 28 extern void kernel_fpu_end(void); 29 extern bool irq_fpu_usable(void); 30 extern void fpregs_mark_activate(void); 31 32 /* Code that is unaware of kernel_fpu_begin_mask() can use this */ 33 static inline void kernel_fpu_begin(void) 34 { 35 kernel_fpu_begin_mask(KFPU_387 | KFPU_MXCSR); 36 } 37 38 /* 39 * Use fpregs_lock() while editing CPU's FPU registers or fpu->state. 40 * A context switch will (and softirq might) save CPU's FPU registers to 41 * fpu->state and set TIF_NEED_FPU_LOAD leaving CPU's FPU registers in 42 * a random state. 43 * 44 * local_bh_disable() protects against both preemption and soft interrupts 45 * on !RT kernels. 46 * 47 * On RT kernels local_bh_disable() is not sufficient because it only 48 * serializes soft interrupt related sections via a local lock, but stays 49 * preemptible. Disabling preemption is the right choice here as bottom 50 * half processing is always in thread context on RT kernels so it 51 * implicitly prevents bottom half processing as well. 52 * 53 * Disabling preemption also serializes against kernel_fpu_begin(). 54 */ 55 static inline void fpregs_lock(void) 56 { 57 if (!IS_ENABLED(CONFIG_PREEMPT_RT)) 58 local_bh_disable(); 59 else 60 preempt_disable(); 61 } 62 63 static inline void fpregs_unlock(void) 64 { 65 if (!IS_ENABLED(CONFIG_PREEMPT_RT)) 66 local_bh_enable(); 67 else 68 preempt_enable(); 69 } 70 71 #ifdef CONFIG_X86_DEBUG_FPU 72 extern void fpregs_assert_state_consistent(void); 73 #else 74 static inline void fpregs_assert_state_consistent(void) { } 75 #endif 76 77 /* 78 * Load the task FPU state before returning to userspace. 79 */ 80 extern void switch_fpu_return(void); 81 82 /* 83 * Query the presence of one or more xfeatures. Works on any legacy CPU as well. 84 * 85 * If 'feature_name' is set then put a human-readable description of 86 * the feature there as well - this can be used to print error (or success) 87 * messages. 88 */ 89 extern int cpu_has_xfeatures(u64 xfeatures_mask, const char **feature_name); 90 91 /* 92 * Tasks that are not using SVA have mm->pasid set to zero to note that they 93 * will not have the valid bit set in MSR_IA32_PASID while they are running. 94 */ 95 #define PASID_DISABLED 0 96 97 #ifdef CONFIG_IOMMU_SUPPORT 98 /* Update current's PASID MSR/state by mm's PASID. */ 99 void update_pasid(void); 100 #else 101 static inline void update_pasid(void) { } 102 #endif 103 #endif /* _ASM_X86_FPU_API_H */ 104