1 #ifndef _ASM_X86_DESC_H 2 #define _ASM_X86_DESC_H 3 4 #include <asm/desc_defs.h> 5 #include <asm/ldt.h> 6 #include <asm/mmu.h> 7 #include <asm/fixmap.h> 8 #include <asm/irq_vectors.h> 9 10 #include <linux/smp.h> 11 #include <linux/percpu.h> 12 13 static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info) 14 { 15 desc->limit0 = info->limit & 0x0ffff; 16 17 desc->base0 = (info->base_addr & 0x0000ffff); 18 desc->base1 = (info->base_addr & 0x00ff0000) >> 16; 19 20 desc->type = (info->read_exec_only ^ 1) << 1; 21 desc->type |= info->contents << 2; 22 23 desc->s = 1; 24 desc->dpl = 0x3; 25 desc->p = info->seg_not_present ^ 1; 26 desc->limit1 = (info->limit & 0xf0000) >> 16; 27 desc->avl = info->useable; 28 desc->d = info->seg_32bit; 29 desc->g = info->limit_in_pages; 30 31 desc->base2 = (info->base_addr & 0xff000000) >> 24; 32 /* 33 * Don't allow setting of the lm bit. It would confuse 34 * user_64bit_mode and would get overridden by sysret anyway. 35 */ 36 desc->l = 0; 37 } 38 39 extern struct desc_ptr idt_descr; 40 extern gate_desc idt_table[]; 41 extern const struct desc_ptr debug_idt_descr; 42 extern gate_desc debug_idt_table[]; 43 44 struct gdt_page { 45 struct desc_struct gdt[GDT_ENTRIES]; 46 } __attribute__((aligned(PAGE_SIZE))); 47 48 DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page); 49 50 /* Provide the original GDT */ 51 static inline struct desc_struct *get_cpu_gdt_rw(unsigned int cpu) 52 { 53 return per_cpu(gdt_page, cpu).gdt; 54 } 55 56 /* Provide the current original GDT */ 57 static inline struct desc_struct *get_current_gdt_rw(void) 58 { 59 return this_cpu_ptr(&gdt_page)->gdt; 60 } 61 62 /* Get the fixmap index for a specific processor */ 63 static inline unsigned int get_cpu_gdt_ro_index(int cpu) 64 { 65 return FIX_GDT_REMAP_BEGIN + cpu; 66 } 67 68 /* Provide the fixmap address of the remapped GDT */ 69 static inline struct desc_struct *get_cpu_gdt_ro(int cpu) 70 { 71 unsigned int idx = get_cpu_gdt_ro_index(cpu); 72 return (struct desc_struct *)__fix_to_virt(idx); 73 } 74 75 /* Provide the current read-only GDT */ 76 static inline struct desc_struct *get_current_gdt_ro(void) 77 { 78 return get_cpu_gdt_ro(smp_processor_id()); 79 } 80 81 /* Provide the physical address of the GDT page. */ 82 static inline phys_addr_t get_cpu_gdt_paddr(unsigned int cpu) 83 { 84 return per_cpu_ptr_to_phys(get_cpu_gdt_rw(cpu)); 85 } 86 87 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func, 88 unsigned dpl, unsigned ist, unsigned seg) 89 { 90 gate->offset_low = (u16) func; 91 gate->bits.p = 1; 92 gate->bits.dpl = dpl; 93 gate->bits.zero = 0; 94 gate->bits.type = type; 95 gate->offset_middle = (u16) (func >> 16); 96 #ifdef CONFIG_X86_64 97 gate->segment = __KERNEL_CS; 98 gate->bits.ist = ist; 99 gate->reserved = 0; 100 gate->offset_high = (u32) (func >> 32); 101 #else 102 gate->segment = seg; 103 gate->bits.ist = 0; 104 #endif 105 } 106 107 static inline int desc_empty(const void *ptr) 108 { 109 const u32 *desc = ptr; 110 111 return !(desc[0] | desc[1]); 112 } 113 114 #ifdef CONFIG_PARAVIRT 115 #include <asm/paravirt.h> 116 #else 117 #define load_TR_desc() native_load_tr_desc() 118 #define load_gdt(dtr) native_load_gdt(dtr) 119 #define load_idt(dtr) native_load_idt(dtr) 120 #define load_tr(tr) asm volatile("ltr %0"::"m" (tr)) 121 #define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt)) 122 123 #define store_gdt(dtr) native_store_gdt(dtr) 124 #define store_tr(tr) (tr = native_store_tr()) 125 126 #define load_TLS(t, cpu) native_load_tls(t, cpu) 127 #define set_ldt native_set_ldt 128 129 #define write_ldt_entry(dt, entry, desc) native_write_ldt_entry(dt, entry, desc) 130 #define write_gdt_entry(dt, entry, desc, type) native_write_gdt_entry(dt, entry, desc, type) 131 #define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g) 132 133 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) 134 { 135 } 136 137 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries) 138 { 139 } 140 #endif /* CONFIG_PARAVIRT */ 141 142 #define store_ldt(ldt) asm("sldt %0" : "=m"(ldt)) 143 144 static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate) 145 { 146 memcpy(&idt[entry], gate, sizeof(*gate)); 147 } 148 149 static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc) 150 { 151 memcpy(&ldt[entry], desc, 8); 152 } 153 154 static inline void 155 native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type) 156 { 157 unsigned int size; 158 159 switch (type) { 160 case DESC_TSS: size = sizeof(tss_desc); break; 161 case DESC_LDT: size = sizeof(ldt_desc); break; 162 default: size = sizeof(*gdt); break; 163 } 164 165 memcpy(&gdt[entry], desc, size); 166 } 167 168 static inline void set_tssldt_descriptor(void *d, unsigned long addr, 169 unsigned type, unsigned size) 170 { 171 struct ldttss_desc *desc = d; 172 173 memset(desc, 0, sizeof(*desc)); 174 175 desc->limit0 = (u16) size; 176 desc->base0 = (u16) addr; 177 desc->base1 = (addr >> 16) & 0xFF; 178 desc->type = type; 179 desc->p = 1; 180 desc->limit1 = (size >> 16) & 0xF; 181 desc->base2 = (addr >> 24) & 0xFF; 182 #ifdef CONFIG_X86_64 183 desc->base3 = (u32) (addr >> 32); 184 #endif 185 } 186 187 static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr) 188 { 189 struct desc_struct *d = get_cpu_gdt_rw(cpu); 190 tss_desc tss; 191 192 set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS, 193 __KERNEL_TSS_LIMIT); 194 write_gdt_entry(d, entry, &tss, DESC_TSS); 195 } 196 197 #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr) 198 199 static inline void native_set_ldt(const void *addr, unsigned int entries) 200 { 201 if (likely(entries == 0)) 202 asm volatile("lldt %w0"::"q" (0)); 203 else { 204 unsigned cpu = smp_processor_id(); 205 ldt_desc ldt; 206 207 set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT, 208 entries * LDT_ENTRY_SIZE - 1); 209 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_LDT, 210 &ldt, DESC_LDT); 211 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8)); 212 } 213 } 214 215 static inline void native_load_gdt(const struct desc_ptr *dtr) 216 { 217 asm volatile("lgdt %0"::"m" (*dtr)); 218 } 219 220 static inline void native_load_idt(const struct desc_ptr *dtr) 221 { 222 asm volatile("lidt %0"::"m" (*dtr)); 223 } 224 225 static inline void native_store_gdt(struct desc_ptr *dtr) 226 { 227 asm volatile("sgdt %0":"=m" (*dtr)); 228 } 229 230 static inline void store_idt(struct desc_ptr *dtr) 231 { 232 asm volatile("sidt %0":"=m" (*dtr)); 233 } 234 235 /* 236 * The LTR instruction marks the TSS GDT entry as busy. On 64-bit, the GDT is 237 * a read-only remapping. To prevent a page fault, the GDT is switched to the 238 * original writeable version when needed. 239 */ 240 #ifdef CONFIG_X86_64 241 static inline void native_load_tr_desc(void) 242 { 243 struct desc_ptr gdt; 244 int cpu = raw_smp_processor_id(); 245 bool restore = 0; 246 struct desc_struct *fixmap_gdt; 247 248 native_store_gdt(&gdt); 249 fixmap_gdt = get_cpu_gdt_ro(cpu); 250 251 /* 252 * If the current GDT is the read-only fixmap, swap to the original 253 * writeable version. Swap back at the end. 254 */ 255 if (gdt.address == (unsigned long)fixmap_gdt) { 256 load_direct_gdt(cpu); 257 restore = 1; 258 } 259 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); 260 if (restore) 261 load_fixmap_gdt(cpu); 262 } 263 #else 264 static inline void native_load_tr_desc(void) 265 { 266 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); 267 } 268 #endif 269 270 static inline unsigned long native_store_tr(void) 271 { 272 unsigned long tr; 273 274 asm volatile("str %0":"=r" (tr)); 275 276 return tr; 277 } 278 279 static inline void native_load_tls(struct thread_struct *t, unsigned int cpu) 280 { 281 struct desc_struct *gdt = get_cpu_gdt_rw(cpu); 282 unsigned int i; 283 284 for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++) 285 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]; 286 } 287 288 DECLARE_PER_CPU(bool, __tss_limit_invalid); 289 290 static inline void force_reload_TR(void) 291 { 292 struct desc_struct *d = get_current_gdt_rw(); 293 tss_desc tss; 294 295 memcpy(&tss, &d[GDT_ENTRY_TSS], sizeof(tss_desc)); 296 297 /* 298 * LTR requires an available TSS, and the TSS is currently 299 * busy. Make it be available so that LTR will work. 300 */ 301 tss.type = DESC_TSS; 302 write_gdt_entry(d, GDT_ENTRY_TSS, &tss, DESC_TSS); 303 304 load_TR_desc(); 305 this_cpu_write(__tss_limit_invalid, false); 306 } 307 308 /* 309 * Call this if you need the TSS limit to be correct, which should be the case 310 * if and only if you have TIF_IO_BITMAP set or you're switching to a task 311 * with TIF_IO_BITMAP set. 312 */ 313 static inline void refresh_tss_limit(void) 314 { 315 DEBUG_LOCKS_WARN_ON(preemptible()); 316 317 if (unlikely(this_cpu_read(__tss_limit_invalid))) 318 force_reload_TR(); 319 } 320 321 /* 322 * If you do something evil that corrupts the cached TSS limit (I'm looking 323 * at you, VMX exits), call this function. 324 * 325 * The optimization here is that the TSS limit only matters for Linux if the 326 * IO bitmap is in use. If the TSS limit gets forced to its minimum value, 327 * everything works except that IO bitmap will be ignored and all CPL 3 IO 328 * instructions will #GP, which is exactly what we want for normal tasks. 329 */ 330 static inline void invalidate_tss_limit(void) 331 { 332 DEBUG_LOCKS_WARN_ON(preemptible()); 333 334 if (unlikely(test_thread_flag(TIF_IO_BITMAP))) 335 force_reload_TR(); 336 else 337 this_cpu_write(__tss_limit_invalid, true); 338 } 339 340 /* This intentionally ignores lm, since 32-bit apps don't have that field. */ 341 #define LDT_empty(info) \ 342 ((info)->base_addr == 0 && \ 343 (info)->limit == 0 && \ 344 (info)->contents == 0 && \ 345 (info)->read_exec_only == 1 && \ 346 (info)->seg_32bit == 0 && \ 347 (info)->limit_in_pages == 0 && \ 348 (info)->seg_not_present == 1 && \ 349 (info)->useable == 0) 350 351 /* Lots of programs expect an all-zero user_desc to mean "no segment at all". */ 352 static inline bool LDT_zero(const struct user_desc *info) 353 { 354 return (info->base_addr == 0 && 355 info->limit == 0 && 356 info->contents == 0 && 357 info->read_exec_only == 0 && 358 info->seg_32bit == 0 && 359 info->limit_in_pages == 0 && 360 info->seg_not_present == 0 && 361 info->useable == 0); 362 } 363 364 static inline void clear_LDT(void) 365 { 366 set_ldt(NULL, 0); 367 } 368 369 static inline unsigned long get_desc_base(const struct desc_struct *desc) 370 { 371 return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24)); 372 } 373 374 static inline void set_desc_base(struct desc_struct *desc, unsigned long base) 375 { 376 desc->base0 = base & 0xffff; 377 desc->base1 = (base >> 16) & 0xff; 378 desc->base2 = (base >> 24) & 0xff; 379 } 380 381 static inline unsigned long get_desc_limit(const struct desc_struct *desc) 382 { 383 return desc->limit0 | (desc->limit1 << 16); 384 } 385 386 static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit) 387 { 388 desc->limit0 = limit & 0xffff; 389 desc->limit1 = (limit >> 16) & 0xf; 390 } 391 392 void update_intr_gate(unsigned int n, const void *addr); 393 void alloc_intr_gate(unsigned int n, const void *addr); 394 395 extern unsigned long used_vectors[]; 396 397 #ifdef CONFIG_X86_64 398 DECLARE_PER_CPU(u32, debug_idt_ctr); 399 static inline bool is_debug_idt_enabled(void) 400 { 401 if (this_cpu_read(debug_idt_ctr)) 402 return true; 403 404 return false; 405 } 406 407 static inline void load_debug_idt(void) 408 { 409 load_idt((const struct desc_ptr *)&debug_idt_descr); 410 } 411 #else 412 static inline bool is_debug_idt_enabled(void) 413 { 414 return false; 415 } 416 417 static inline void load_debug_idt(void) 418 { 419 } 420 #endif 421 422 /* 423 * The load_current_idt() must be called with interrupts disabled 424 * to avoid races. That way the IDT will always be set back to the expected 425 * descriptor. It's also called when a CPU is being initialized, and 426 * that doesn't need to disable interrupts, as nothing should be 427 * bothering the CPU then. 428 */ 429 static inline void load_current_idt(void) 430 { 431 if (is_debug_idt_enabled()) 432 load_debug_idt(); 433 else 434 load_idt((const struct desc_ptr *)&idt_descr); 435 } 436 437 extern void idt_setup_early_handler(void); 438 extern void idt_setup_early_traps(void); 439 extern void idt_setup_traps(void); 440 extern void idt_setup_apic_and_irq_gates(void); 441 442 #ifdef CONFIG_X86_64 443 extern void idt_setup_early_pf(void); 444 extern void idt_setup_ist_traps(void); 445 extern void idt_setup_debugidt_traps(void); 446 #else 447 static inline void idt_setup_early_pf(void) { } 448 static inline void idt_setup_ist_traps(void) { } 449 static inline void idt_setup_debugidt_traps(void) { } 450 #endif 451 452 extern void idt_invalidate(void *addr); 453 454 #endif /* _ASM_X86_DESC_H */ 455