xref: /linux/arch/x86/include/asm/cpufeature.h (revision 2ba9268dd603d23e17643437b2246acb6844953b)
1 /*
2  * Defines x86 CPU feature bits
3  */
4 #ifndef _ASM_X86_CPUFEATURE_H
5 #define _ASM_X86_CPUFEATURE_H
6 
7 #ifndef _ASM_X86_REQUIRED_FEATURES_H
8 #include <asm/required-features.h>
9 #endif
10 
11 #ifndef _ASM_X86_DISABLED_FEATURES_H
12 #include <asm/disabled-features.h>
13 #endif
14 
15 #define NCAPINTS	11	/* N 32-bit words worth of info */
16 #define NBUGINTS	1	/* N 32-bit bug flags */
17 
18 /*
19  * Note: If the comment begins with a quoted string, that string is used
20  * in /proc/cpuinfo instead of the macro name.  If the string is "",
21  * this feature bit is not displayed in /proc/cpuinfo at all.
22  */
23 
24 /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
25 #define X86_FEATURE_FPU		( 0*32+ 0) /* Onboard FPU */
26 #define X86_FEATURE_VME		( 0*32+ 1) /* Virtual Mode Extensions */
27 #define X86_FEATURE_DE		( 0*32+ 2) /* Debugging Extensions */
28 #define X86_FEATURE_PSE		( 0*32+ 3) /* Page Size Extensions */
29 #define X86_FEATURE_TSC		( 0*32+ 4) /* Time Stamp Counter */
30 #define X86_FEATURE_MSR		( 0*32+ 5) /* Model-Specific Registers */
31 #define X86_FEATURE_PAE		( 0*32+ 6) /* Physical Address Extensions */
32 #define X86_FEATURE_MCE		( 0*32+ 7) /* Machine Check Exception */
33 #define X86_FEATURE_CX8		( 0*32+ 8) /* CMPXCHG8 instruction */
34 #define X86_FEATURE_APIC	( 0*32+ 9) /* Onboard APIC */
35 #define X86_FEATURE_SEP		( 0*32+11) /* SYSENTER/SYSEXIT */
36 #define X86_FEATURE_MTRR	( 0*32+12) /* Memory Type Range Registers */
37 #define X86_FEATURE_PGE		( 0*32+13) /* Page Global Enable */
38 #define X86_FEATURE_MCA		( 0*32+14) /* Machine Check Architecture */
39 #define X86_FEATURE_CMOV	( 0*32+15) /* CMOV instructions */
40 					  /* (plus FCMOVcc, FCOMI with FPU) */
41 #define X86_FEATURE_PAT		( 0*32+16) /* Page Attribute Table */
42 #define X86_FEATURE_PSE36	( 0*32+17) /* 36-bit PSEs */
43 #define X86_FEATURE_PN		( 0*32+18) /* Processor serial number */
44 #define X86_FEATURE_CLFLUSH	( 0*32+19) /* CLFLUSH instruction */
45 #define X86_FEATURE_DS		( 0*32+21) /* "dts" Debug Store */
46 #define X86_FEATURE_ACPI	( 0*32+22) /* ACPI via MSR */
47 #define X86_FEATURE_MMX		( 0*32+23) /* Multimedia Extensions */
48 #define X86_FEATURE_FXSR	( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
49 #define X86_FEATURE_XMM		( 0*32+25) /* "sse" */
50 #define X86_FEATURE_XMM2	( 0*32+26) /* "sse2" */
51 #define X86_FEATURE_SELFSNOOP	( 0*32+27) /* "ss" CPU self snoop */
52 #define X86_FEATURE_HT		( 0*32+28) /* Hyper-Threading */
53 #define X86_FEATURE_ACC		( 0*32+29) /* "tm" Automatic clock control */
54 #define X86_FEATURE_IA64	( 0*32+30) /* IA-64 processor */
55 #define X86_FEATURE_PBE		( 0*32+31) /* Pending Break Enable */
56 
57 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
58 /* Don't duplicate feature flags which are redundant with Intel! */
59 #define X86_FEATURE_SYSCALL	( 1*32+11) /* SYSCALL/SYSRET */
60 #define X86_FEATURE_MP		( 1*32+19) /* MP Capable. */
61 #define X86_FEATURE_NX		( 1*32+20) /* Execute Disable */
62 #define X86_FEATURE_MMXEXT	( 1*32+22) /* AMD MMX extensions */
63 #define X86_FEATURE_FXSR_OPT	( 1*32+25) /* FXSAVE/FXRSTOR optimizations */
64 #define X86_FEATURE_GBPAGES	( 1*32+26) /* "pdpe1gb" GB pages */
65 #define X86_FEATURE_RDTSCP	( 1*32+27) /* RDTSCP */
66 #define X86_FEATURE_LM		( 1*32+29) /* Long Mode (x86-64) */
67 #define X86_FEATURE_3DNOWEXT	( 1*32+30) /* AMD 3DNow! extensions */
68 #define X86_FEATURE_3DNOW	( 1*32+31) /* 3DNow! */
69 
70 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
71 #define X86_FEATURE_RECOVERY	( 2*32+ 0) /* CPU in recovery mode */
72 #define X86_FEATURE_LONGRUN	( 2*32+ 1) /* Longrun power control */
73 #define X86_FEATURE_LRTI	( 2*32+ 3) /* LongRun table interface */
74 
75 /* Other features, Linux-defined mapping, word 3 */
76 /* This range is used for feature bits which conflict or are synthesized */
77 #define X86_FEATURE_CXMMX	( 3*32+ 0) /* Cyrix MMX extensions */
78 #define X86_FEATURE_K6_MTRR	( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
79 #define X86_FEATURE_CYRIX_ARR	( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
80 #define X86_FEATURE_CENTAUR_MCR	( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
81 /* cpu types for specific tunings: */
82 #define X86_FEATURE_K8		( 3*32+ 4) /* "" Opteron, Athlon64 */
83 #define X86_FEATURE_K7		( 3*32+ 5) /* "" Athlon */
84 #define X86_FEATURE_P3		( 3*32+ 6) /* "" P3 */
85 #define X86_FEATURE_P4		( 3*32+ 7) /* "" P4 */
86 #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
87 #define X86_FEATURE_UP		( 3*32+ 9) /* smp kernel running on up */
88 /* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */
89 #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */
90 #define X86_FEATURE_PEBS	( 3*32+12) /* Precise-Event Based Sampling */
91 #define X86_FEATURE_BTS		( 3*32+13) /* Branch Trace Store */
92 #define X86_FEATURE_SYSCALL32	( 3*32+14) /* "" syscall in ia32 userspace */
93 #define X86_FEATURE_SYSENTER32	( 3*32+15) /* "" sysenter in ia32 userspace */
94 #define X86_FEATURE_REP_GOOD	( 3*32+16) /* rep microcode works well */
95 #define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */
96 #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */
97 /* free, was #define X86_FEATURE_11AP	( 3*32+19) * "" Bad local APIC aka 11AP */
98 #define X86_FEATURE_NOPL	( 3*32+20) /* The NOPL (0F 1F) instructions */
99 #define X86_FEATURE_ALWAYS	( 3*32+21) /* "" Always-present feature */
100 #define X86_FEATURE_XTOPOLOGY	( 3*32+22) /* cpu topology enum extensions */
101 #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
102 #define X86_FEATURE_NONSTOP_TSC	( 3*32+24) /* TSC does not stop in C states */
103 /* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
104 #define X86_FEATURE_EXTD_APICID	( 3*32+26) /* has extended APICID (8 bits) */
105 #define X86_FEATURE_AMD_DCM     ( 3*32+27) /* multi-node processor */
106 #define X86_FEATURE_APERFMPERF	( 3*32+28) /* APERFMPERF */
107 #define X86_FEATURE_EAGER_FPU	( 3*32+29) /* "eagerfpu" Non lazy FPU restore */
108 #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
109 
110 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
111 #define X86_FEATURE_XMM3	( 4*32+ 0) /* "pni" SSE-3 */
112 #define X86_FEATURE_PCLMULQDQ	( 4*32+ 1) /* PCLMULQDQ instruction */
113 #define X86_FEATURE_DTES64	( 4*32+ 2) /* 64-bit Debug Store */
114 #define X86_FEATURE_MWAIT	( 4*32+ 3) /* "monitor" Monitor/Mwait support */
115 #define X86_FEATURE_DSCPL	( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
116 #define X86_FEATURE_VMX		( 4*32+ 5) /* Hardware virtualization */
117 #define X86_FEATURE_SMX		( 4*32+ 6) /* Safer mode */
118 #define X86_FEATURE_EST		( 4*32+ 7) /* Enhanced SpeedStep */
119 #define X86_FEATURE_TM2		( 4*32+ 8) /* Thermal Monitor 2 */
120 #define X86_FEATURE_SSSE3	( 4*32+ 9) /* Supplemental SSE-3 */
121 #define X86_FEATURE_CID		( 4*32+10) /* Context ID */
122 #define X86_FEATURE_FMA		( 4*32+12) /* Fused multiply-add */
123 #define X86_FEATURE_CX16	( 4*32+13) /* CMPXCHG16B */
124 #define X86_FEATURE_XTPR	( 4*32+14) /* Send Task Priority Messages */
125 #define X86_FEATURE_PDCM	( 4*32+15) /* Performance Capabilities */
126 #define X86_FEATURE_PCID	( 4*32+17) /* Process Context Identifiers */
127 #define X86_FEATURE_DCA		( 4*32+18) /* Direct Cache Access */
128 #define X86_FEATURE_XMM4_1	( 4*32+19) /* "sse4_1" SSE-4.1 */
129 #define X86_FEATURE_XMM4_2	( 4*32+20) /* "sse4_2" SSE-4.2 */
130 #define X86_FEATURE_X2APIC	( 4*32+21) /* x2APIC */
131 #define X86_FEATURE_MOVBE	( 4*32+22) /* MOVBE instruction */
132 #define X86_FEATURE_POPCNT      ( 4*32+23) /* POPCNT instruction */
133 #define X86_FEATURE_TSC_DEADLINE_TIMER	( 4*32+24) /* Tsc deadline timer */
134 #define X86_FEATURE_AES		( 4*32+25) /* AES instructions */
135 #define X86_FEATURE_XSAVE	( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
136 #define X86_FEATURE_OSXSAVE	( 4*32+27) /* "" XSAVE enabled in the OS */
137 #define X86_FEATURE_AVX		( 4*32+28) /* Advanced Vector Extensions */
138 #define X86_FEATURE_F16C	( 4*32+29) /* 16-bit fp conversions */
139 #define X86_FEATURE_RDRAND	( 4*32+30) /* The RDRAND instruction */
140 #define X86_FEATURE_HYPERVISOR	( 4*32+31) /* Running on a hypervisor */
141 
142 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
143 #define X86_FEATURE_XSTORE	( 5*32+ 2) /* "rng" RNG present (xstore) */
144 #define X86_FEATURE_XSTORE_EN	( 5*32+ 3) /* "rng_en" RNG enabled */
145 #define X86_FEATURE_XCRYPT	( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
146 #define X86_FEATURE_XCRYPT_EN	( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
147 #define X86_FEATURE_ACE2	( 5*32+ 8) /* Advanced Cryptography Engine v2 */
148 #define X86_FEATURE_ACE2_EN	( 5*32+ 9) /* ACE v2 enabled */
149 #define X86_FEATURE_PHE		( 5*32+10) /* PadLock Hash Engine */
150 #define X86_FEATURE_PHE_EN	( 5*32+11) /* PHE enabled */
151 #define X86_FEATURE_PMM		( 5*32+12) /* PadLock Montgomery Multiplier */
152 #define X86_FEATURE_PMM_EN	( 5*32+13) /* PMM enabled */
153 
154 /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
155 #define X86_FEATURE_LAHF_LM	( 6*32+ 0) /* LAHF/SAHF in long mode */
156 #define X86_FEATURE_CMP_LEGACY	( 6*32+ 1) /* If yes HyperThreading not valid */
157 #define X86_FEATURE_SVM		( 6*32+ 2) /* Secure virtual machine */
158 #define X86_FEATURE_EXTAPIC	( 6*32+ 3) /* Extended APIC space */
159 #define X86_FEATURE_CR8_LEGACY	( 6*32+ 4) /* CR8 in 32-bit mode */
160 #define X86_FEATURE_ABM		( 6*32+ 5) /* Advanced bit manipulation */
161 #define X86_FEATURE_SSE4A	( 6*32+ 6) /* SSE-4A */
162 #define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */
163 #define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */
164 #define X86_FEATURE_OSVW	( 6*32+ 9) /* OS Visible Workaround */
165 #define X86_FEATURE_IBS		( 6*32+10) /* Instruction Based Sampling */
166 #define X86_FEATURE_XOP		( 6*32+11) /* extended AVX instructions */
167 #define X86_FEATURE_SKINIT	( 6*32+12) /* SKINIT/STGI instructions */
168 #define X86_FEATURE_WDT		( 6*32+13) /* Watchdog timer */
169 #define X86_FEATURE_LWP		( 6*32+15) /* Light Weight Profiling */
170 #define X86_FEATURE_FMA4	( 6*32+16) /* 4 operands MAC instructions */
171 #define X86_FEATURE_TCE		( 6*32+17) /* translation cache extension */
172 #define X86_FEATURE_NODEID_MSR	( 6*32+19) /* NodeId MSR */
173 #define X86_FEATURE_TBM		( 6*32+21) /* trailing bit manipulations */
174 #define X86_FEATURE_TOPOEXT	( 6*32+22) /* topology extensions CPUID leafs */
175 #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */
176 #define X86_FEATURE_PERFCTR_NB  ( 6*32+24) /* NB performance counter extensions */
177 #define X86_FEATURE_BPEXT	(6*32+26) /* data breakpoint extension */
178 #define X86_FEATURE_PERFCTR_L2	( 6*32+28) /* L2 performance counter extensions */
179 
180 /*
181  * Auxiliary flags: Linux defined - For features scattered in various
182  * CPUID levels like 0x6, 0xA etc, word 7
183  */
184 #define X86_FEATURE_IDA		( 7*32+ 0) /* Intel Dynamic Acceleration */
185 #define X86_FEATURE_ARAT	( 7*32+ 1) /* Always Running APIC Timer */
186 #define X86_FEATURE_CPB		( 7*32+ 2) /* AMD Core Performance Boost */
187 #define X86_FEATURE_EPB		( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
188 #define X86_FEATURE_PLN		( 7*32+ 5) /* Intel Power Limit Notification */
189 #define X86_FEATURE_PTS		( 7*32+ 6) /* Intel Package Thermal Status */
190 #define X86_FEATURE_DTHERM	( 7*32+ 7) /* Digital Thermal Sensor */
191 #define X86_FEATURE_HW_PSTATE	( 7*32+ 8) /* AMD HW-PState */
192 #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
193 #define X86_FEATURE_HWP		( 7*32+ 10) /* "hwp" Intel HWP */
194 #define X86_FEATURE_HWP_NOITFY	( 7*32+ 11) /* Intel HWP_NOTIFY */
195 #define X86_FEATURE_HWP_ACT_WINDOW ( 7*32+ 12) /* Intel HWP_ACT_WINDOW */
196 #define X86_FEATURE_HWP_EPP	( 7*32+13) /* Intel HWP_EPP */
197 #define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */
198 
199 /* Virtualization flags: Linux defined, word 8 */
200 #define X86_FEATURE_TPR_SHADOW  ( 8*32+ 0) /* Intel TPR Shadow */
201 #define X86_FEATURE_VNMI        ( 8*32+ 1) /* Intel Virtual NMI */
202 #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
203 #define X86_FEATURE_EPT         ( 8*32+ 3) /* Intel Extended Page Table */
204 #define X86_FEATURE_VPID        ( 8*32+ 4) /* Intel Virtual Processor ID */
205 #define X86_FEATURE_NPT		( 8*32+ 5) /* AMD Nested Page Table support */
206 #define X86_FEATURE_LBRV	( 8*32+ 6) /* AMD LBR Virtualization support */
207 #define X86_FEATURE_SVML	( 8*32+ 7) /* "svm_lock" AMD SVM locking MSR */
208 #define X86_FEATURE_NRIPS	( 8*32+ 8) /* "nrip_save" AMD SVM next_rip save */
209 #define X86_FEATURE_TSCRATEMSR  ( 8*32+ 9) /* "tsc_scale" AMD TSC scaling support */
210 #define X86_FEATURE_VMCBCLEAN   ( 8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */
211 #define X86_FEATURE_FLUSHBYASID ( 8*32+11) /* AMD flush-by-ASID support */
212 #define X86_FEATURE_DECODEASSISTS ( 8*32+12) /* AMD Decode Assists support */
213 #define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */
214 #define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */
215 #define X86_FEATURE_VMMCALL     ( 8*32+15) /* Prefer vmmcall to vmcall */
216 
217 
218 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
219 #define X86_FEATURE_FSGSBASE	( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
220 #define X86_FEATURE_TSC_ADJUST	( 9*32+ 1) /* TSC adjustment MSR 0x3b */
221 #define X86_FEATURE_BMI1	( 9*32+ 3) /* 1st group bit manipulation extensions */
222 #define X86_FEATURE_HLE		( 9*32+ 4) /* Hardware Lock Elision */
223 #define X86_FEATURE_AVX2	( 9*32+ 5) /* AVX2 instructions */
224 #define X86_FEATURE_SMEP	( 9*32+ 7) /* Supervisor Mode Execution Protection */
225 #define X86_FEATURE_BMI2	( 9*32+ 8) /* 2nd group bit manipulation extensions */
226 #define X86_FEATURE_ERMS	( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */
227 #define X86_FEATURE_INVPCID	( 9*32+10) /* Invalidate Processor Context ID */
228 #define X86_FEATURE_RTM		( 9*32+11) /* Restricted Transactional Memory */
229 #define X86_FEATURE_MPX		( 9*32+14) /* Memory Protection Extension */
230 #define X86_FEATURE_AVX512F	( 9*32+16) /* AVX-512 Foundation */
231 #define X86_FEATURE_RDSEED	( 9*32+18) /* The RDSEED instruction */
232 #define X86_FEATURE_ADX		( 9*32+19) /* The ADCX and ADOX instructions */
233 #define X86_FEATURE_SMAP	( 9*32+20) /* Supervisor Mode Access Prevention */
234 #define X86_FEATURE_CLFLUSHOPT	( 9*32+23) /* CLFLUSHOPT instruction */
235 #define X86_FEATURE_AVX512PF	( 9*32+26) /* AVX-512 Prefetch */
236 #define X86_FEATURE_AVX512ER	( 9*32+27) /* AVX-512 Exponential and Reciprocal */
237 #define X86_FEATURE_AVX512CD	( 9*32+28) /* AVX-512 Conflict Detection */
238 
239 /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
240 #define X86_FEATURE_XSAVEOPT	(10*32+ 0) /* XSAVEOPT */
241 #define X86_FEATURE_XSAVEC	(10*32+ 1) /* XSAVEC */
242 #define X86_FEATURE_XGETBV1	(10*32+ 2) /* XGETBV with ECX = 1 */
243 #define X86_FEATURE_XSAVES	(10*32+ 3) /* XSAVES/XRSTORS */
244 
245 /*
246  * BUG word(s)
247  */
248 #define X86_BUG(x)		(NCAPINTS*32 + (x))
249 
250 #define X86_BUG_F00F		X86_BUG(0) /* Intel F00F */
251 #define X86_BUG_FDIV		X86_BUG(1) /* FPU FDIV */
252 #define X86_BUG_COMA		X86_BUG(2) /* Cyrix 6x86 coma */
253 #define X86_BUG_AMD_TLB_MMATCH	X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
254 #define X86_BUG_AMD_APIC_C1E	X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */
255 #define X86_BUG_11AP		X86_BUG(5) /* Bad local APIC aka 11AP */
256 #define X86_BUG_FXSAVE_LEAK	X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
257 #define X86_BUG_CLFLUSH_MONITOR	X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
258 
259 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
260 
261 #include <asm/asm.h>
262 #include <linux/bitops.h>
263 
264 #ifdef CONFIG_X86_FEATURE_NAMES
265 extern const char * const x86_cap_flags[NCAPINTS*32];
266 extern const char * const x86_power_flags[32];
267 #define X86_CAP_FMT "%s"
268 #define x86_cap_flag(flag) x86_cap_flags[flag]
269 #else
270 #define X86_CAP_FMT "%d:%d"
271 #define x86_cap_flag(flag) ((flag) >> 5), ((flag) & 31)
272 #endif
273 
274 /*
275  * In order to save room, we index into this array by doing
276  * X86_BUG_<name> - NCAPINTS*32.
277  */
278 extern const char * const x86_bug_flags[NBUGINTS*32];
279 
280 #define test_cpu_cap(c, bit)						\
281 	 test_bit(bit, (unsigned long *)((c)->x86_capability))
282 
283 #define REQUIRED_MASK_BIT_SET(bit)					\
284 	 ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) ||	\
285 	   (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) ||	\
286 	   (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) ||	\
287 	   (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) ||	\
288 	   (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) ||	\
289 	   (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) ||	\
290 	   (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ||	\
291 	   (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ||	\
292 	   (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) ||	\
293 	   (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) )
294 
295 #define DISABLED_MASK_BIT_SET(bit)					\
296 	 ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0)) ||	\
297 	   (((bit)>>5)==1 && (1UL<<((bit)&31) & DISABLED_MASK1)) ||	\
298 	   (((bit)>>5)==2 && (1UL<<((bit)&31) & DISABLED_MASK2)) ||	\
299 	   (((bit)>>5)==3 && (1UL<<((bit)&31) & DISABLED_MASK3)) ||	\
300 	   (((bit)>>5)==4 && (1UL<<((bit)&31) & DISABLED_MASK4)) ||	\
301 	   (((bit)>>5)==5 && (1UL<<((bit)&31) & DISABLED_MASK5)) ||	\
302 	   (((bit)>>5)==6 && (1UL<<((bit)&31) & DISABLED_MASK6)) ||	\
303 	   (((bit)>>5)==7 && (1UL<<((bit)&31) & DISABLED_MASK7)) ||	\
304 	   (((bit)>>5)==8 && (1UL<<((bit)&31) & DISABLED_MASK8)) ||	\
305 	   (((bit)>>5)==9 && (1UL<<((bit)&31) & DISABLED_MASK9)) )
306 
307 #define cpu_has(c, bit)							\
308 	(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 :	\
309 	 test_cpu_cap(c, bit))
310 
311 #define this_cpu_has(bit)						\
312 	(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : 	\
313 	 x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability))
314 
315 /*
316  * This macro is for detection of features which need kernel
317  * infrastructure to be used.  It may *not* directly test the CPU
318  * itself.  Use the cpu_has() family if you want true runtime
319  * testing of CPU features, like in hypervisor code where you are
320  * supporting a possible guest feature where host support for it
321  * is not relevant.
322  */
323 #define cpu_feature_enabled(bit)	\
324 	(__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 :	\
325 	 cpu_has(&boot_cpu_data, bit))
326 
327 #define boot_cpu_has(bit)	cpu_has(&boot_cpu_data, bit)
328 
329 #define set_cpu_cap(c, bit)	set_bit(bit, (unsigned long *)((c)->x86_capability))
330 #define clear_cpu_cap(c, bit)	clear_bit(bit, (unsigned long *)((c)->x86_capability))
331 #define setup_clear_cpu_cap(bit) do { \
332 	clear_cpu_cap(&boot_cpu_data, bit);	\
333 	set_bit(bit, (unsigned long *)cpu_caps_cleared); \
334 } while (0)
335 #define setup_force_cpu_cap(bit) do { \
336 	set_cpu_cap(&boot_cpu_data, bit);	\
337 	set_bit(bit, (unsigned long *)cpu_caps_set);	\
338 } while (0)
339 
340 #define cpu_has_fpu		boot_cpu_has(X86_FEATURE_FPU)
341 #define cpu_has_de		boot_cpu_has(X86_FEATURE_DE)
342 #define cpu_has_pse		boot_cpu_has(X86_FEATURE_PSE)
343 #define cpu_has_tsc		boot_cpu_has(X86_FEATURE_TSC)
344 #define cpu_has_pge		boot_cpu_has(X86_FEATURE_PGE)
345 #define cpu_has_apic		boot_cpu_has(X86_FEATURE_APIC)
346 #define cpu_has_sep		boot_cpu_has(X86_FEATURE_SEP)
347 #define cpu_has_mtrr		boot_cpu_has(X86_FEATURE_MTRR)
348 #define cpu_has_mmx		boot_cpu_has(X86_FEATURE_MMX)
349 #define cpu_has_fxsr		boot_cpu_has(X86_FEATURE_FXSR)
350 #define cpu_has_xmm		boot_cpu_has(X86_FEATURE_XMM)
351 #define cpu_has_xmm2		boot_cpu_has(X86_FEATURE_XMM2)
352 #define cpu_has_xmm3		boot_cpu_has(X86_FEATURE_XMM3)
353 #define cpu_has_ssse3		boot_cpu_has(X86_FEATURE_SSSE3)
354 #define cpu_has_aes		boot_cpu_has(X86_FEATURE_AES)
355 #define cpu_has_avx		boot_cpu_has(X86_FEATURE_AVX)
356 #define cpu_has_avx2		boot_cpu_has(X86_FEATURE_AVX2)
357 #define cpu_has_ht		boot_cpu_has(X86_FEATURE_HT)
358 #define cpu_has_nx		boot_cpu_has(X86_FEATURE_NX)
359 #define cpu_has_xstore		boot_cpu_has(X86_FEATURE_XSTORE)
360 #define cpu_has_xstore_enabled	boot_cpu_has(X86_FEATURE_XSTORE_EN)
361 #define cpu_has_xcrypt		boot_cpu_has(X86_FEATURE_XCRYPT)
362 #define cpu_has_xcrypt_enabled	boot_cpu_has(X86_FEATURE_XCRYPT_EN)
363 #define cpu_has_ace2		boot_cpu_has(X86_FEATURE_ACE2)
364 #define cpu_has_ace2_enabled	boot_cpu_has(X86_FEATURE_ACE2_EN)
365 #define cpu_has_phe		boot_cpu_has(X86_FEATURE_PHE)
366 #define cpu_has_phe_enabled	boot_cpu_has(X86_FEATURE_PHE_EN)
367 #define cpu_has_pmm		boot_cpu_has(X86_FEATURE_PMM)
368 #define cpu_has_pmm_enabled	boot_cpu_has(X86_FEATURE_PMM_EN)
369 #define cpu_has_ds		boot_cpu_has(X86_FEATURE_DS)
370 #define cpu_has_pebs		boot_cpu_has(X86_FEATURE_PEBS)
371 #define cpu_has_clflush		boot_cpu_has(X86_FEATURE_CLFLUSH)
372 #define cpu_has_bts		boot_cpu_has(X86_FEATURE_BTS)
373 #define cpu_has_gbpages		boot_cpu_has(X86_FEATURE_GBPAGES)
374 #define cpu_has_arch_perfmon	boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
375 #define cpu_has_pat		boot_cpu_has(X86_FEATURE_PAT)
376 #define cpu_has_xmm4_1		boot_cpu_has(X86_FEATURE_XMM4_1)
377 #define cpu_has_xmm4_2		boot_cpu_has(X86_FEATURE_XMM4_2)
378 #define cpu_has_x2apic		boot_cpu_has(X86_FEATURE_X2APIC)
379 #define cpu_has_xsave		boot_cpu_has(X86_FEATURE_XSAVE)
380 #define cpu_has_xsaveopt	boot_cpu_has(X86_FEATURE_XSAVEOPT)
381 #define cpu_has_xsaves		boot_cpu_has(X86_FEATURE_XSAVES)
382 #define cpu_has_osxsave		boot_cpu_has(X86_FEATURE_OSXSAVE)
383 #define cpu_has_hypervisor	boot_cpu_has(X86_FEATURE_HYPERVISOR)
384 #define cpu_has_pclmulqdq	boot_cpu_has(X86_FEATURE_PCLMULQDQ)
385 #define cpu_has_perfctr_core	boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
386 #define cpu_has_perfctr_nb	boot_cpu_has(X86_FEATURE_PERFCTR_NB)
387 #define cpu_has_perfctr_l2	boot_cpu_has(X86_FEATURE_PERFCTR_L2)
388 #define cpu_has_cx8		boot_cpu_has(X86_FEATURE_CX8)
389 #define cpu_has_cx16		boot_cpu_has(X86_FEATURE_CX16)
390 #define cpu_has_eager_fpu	boot_cpu_has(X86_FEATURE_EAGER_FPU)
391 #define cpu_has_topoext		boot_cpu_has(X86_FEATURE_TOPOEXT)
392 #define cpu_has_bpext		boot_cpu_has(X86_FEATURE_BPEXT)
393 
394 #if __GNUC__ >= 4
395 extern void warn_pre_alternatives(void);
396 extern bool __static_cpu_has_safe(u16 bit);
397 
398 /*
399  * Static testing of CPU features.  Used the same as boot_cpu_has().
400  * These are only valid after alternatives have run, but will statically
401  * patch the target code for additional performance.
402  */
403 static __always_inline __pure bool __static_cpu_has(u16 bit)
404 {
405 #ifdef CC_HAVE_ASM_GOTO
406 
407 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
408 
409 		/*
410 		 * Catch too early usage of this before alternatives
411 		 * have run.
412 		 */
413 		asm_volatile_goto("1: jmp %l[t_warn]\n"
414 			 "2:\n"
415 			 ".section .altinstructions,\"a\"\n"
416 			 " .long 1b - .\n"
417 			 " .long 0\n"		/* no replacement */
418 			 " .word %P0\n"		/* 1: do replace */
419 			 " .byte 2b - 1b\n"	/* source len */
420 			 " .byte 0\n"		/* replacement len */
421 			 ".previous\n"
422 			 /* skipping size check since replacement size = 0 */
423 			 : : "i" (X86_FEATURE_ALWAYS) : : t_warn);
424 
425 #endif
426 
427 		asm_volatile_goto("1: jmp %l[t_no]\n"
428 			 "2:\n"
429 			 ".section .altinstructions,\"a\"\n"
430 			 " .long 1b - .\n"
431 			 " .long 0\n"		/* no replacement */
432 			 " .word %P0\n"		/* feature bit */
433 			 " .byte 2b - 1b\n"	/* source len */
434 			 " .byte 0\n"		/* replacement len */
435 			 ".previous\n"
436 			 /* skipping size check since replacement size = 0 */
437 			 : : "i" (bit) : : t_no);
438 		return true;
439 	t_no:
440 		return false;
441 
442 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
443 	t_warn:
444 		warn_pre_alternatives();
445 		return false;
446 #endif
447 
448 #else /* CC_HAVE_ASM_GOTO */
449 
450 		u8 flag;
451 		/* Open-coded due to __stringify() in ALTERNATIVE() */
452 		asm volatile("1: movb $0,%0\n"
453 			     "2:\n"
454 			     ".section .altinstructions,\"a\"\n"
455 			     " .long 1b - .\n"
456 			     " .long 3f - .\n"
457 			     " .word %P1\n"		/* feature bit */
458 			     " .byte 2b - 1b\n"		/* source len */
459 			     " .byte 4f - 3f\n"		/* replacement len */
460 			     ".previous\n"
461 			     ".section .discard,\"aw\",@progbits\n"
462 			     " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */
463 			     ".previous\n"
464 			     ".section .altinstr_replacement,\"ax\"\n"
465 			     "3: movb $1,%0\n"
466 			     "4:\n"
467 			     ".previous\n"
468 			     : "=qm" (flag) : "i" (bit));
469 		return flag;
470 
471 #endif /* CC_HAVE_ASM_GOTO */
472 }
473 
474 #define static_cpu_has(bit)					\
475 (								\
476 	__builtin_constant_p(boot_cpu_has(bit)) ?		\
477 		boot_cpu_has(bit) :				\
478 	__builtin_constant_p(bit) ?				\
479 		__static_cpu_has(bit) :				\
480 		boot_cpu_has(bit)				\
481 )
482 
483 static __always_inline __pure bool _static_cpu_has_safe(u16 bit)
484 {
485 #ifdef CC_HAVE_ASM_GOTO
486 /*
487  * We need to spell the jumps to the compiler because, depending on the offset,
488  * the replacement jump can be bigger than the original jump, and this we cannot
489  * have. Thus, we force the jump to the widest, 4-byte, signed relative
490  * offset even though the last would often fit in less bytes.
491  */
492 		asm_volatile_goto("1: .byte 0xe9\n .long %l[t_dynamic] - 2f\n"
493 			 "2:\n"
494 			 ".section .altinstructions,\"a\"\n"
495 			 " .long 1b - .\n"		/* src offset */
496 			 " .long 3f - .\n"		/* repl offset */
497 			 " .word %P1\n"			/* always replace */
498 			 " .byte 2b - 1b\n"		/* src len */
499 			 " .byte 4f - 3f\n"		/* repl len */
500 			 ".previous\n"
501 			 ".section .altinstr_replacement,\"ax\"\n"
502 			 "3: .byte 0xe9\n .long %l[t_no] - 2b\n"
503 			 "4:\n"
504 			 ".previous\n"
505 			 ".section .altinstructions,\"a\"\n"
506 			 " .long 1b - .\n"		/* src offset */
507 			 " .long 0\n"			/* no replacement */
508 			 " .word %P0\n"			/* feature bit */
509 			 " .byte 2b - 1b\n"		/* src len */
510 			 " .byte 0\n"			/* repl len */
511 			 ".previous\n"
512 			 : : "i" (bit), "i" (X86_FEATURE_ALWAYS)
513 			 : : t_dynamic, t_no);
514 		return true;
515 	t_no:
516 		return false;
517 	t_dynamic:
518 		return __static_cpu_has_safe(bit);
519 #else
520 		u8 flag;
521 		/* Open-coded due to __stringify() in ALTERNATIVE() */
522 		asm volatile("1: movb $2,%0\n"
523 			     "2:\n"
524 			     ".section .altinstructions,\"a\"\n"
525 			     " .long 1b - .\n"		/* src offset */
526 			     " .long 3f - .\n"		/* repl offset */
527 			     " .word %P2\n"		/* always replace */
528 			     " .byte 2b - 1b\n"		/* source len */
529 			     " .byte 4f - 3f\n"		/* replacement len */
530 			     ".previous\n"
531 			     ".section .discard,\"aw\",@progbits\n"
532 			     " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */
533 			     ".previous\n"
534 			     ".section .altinstr_replacement,\"ax\"\n"
535 			     "3: movb $0,%0\n"
536 			     "4:\n"
537 			     ".previous\n"
538 			     ".section .altinstructions,\"a\"\n"
539 			     " .long 1b - .\n"		/* src offset */
540 			     " .long 5f - .\n"		/* repl offset */
541 			     " .word %P1\n"		/* feature bit */
542 			     " .byte 4b - 3b\n"		/* src len */
543 			     " .byte 6f - 5f\n"		/* repl len */
544 			     ".previous\n"
545 			     ".section .discard,\"aw\",@progbits\n"
546 			     " .byte 0xff + (6f-5f) - (4b-3b)\n" /* size check */
547 			     ".previous\n"
548 			     ".section .altinstr_replacement,\"ax\"\n"
549 			     "5: movb $1,%0\n"
550 			     "6:\n"
551 			     ".previous\n"
552 			     : "=qm" (flag)
553 			     : "i" (bit), "i" (X86_FEATURE_ALWAYS));
554 		return (flag == 2 ? __static_cpu_has_safe(bit) : flag);
555 #endif /* CC_HAVE_ASM_GOTO */
556 }
557 
558 #define static_cpu_has_safe(bit)				\
559 (								\
560 	__builtin_constant_p(boot_cpu_has(bit)) ?		\
561 		boot_cpu_has(bit) :				\
562 		_static_cpu_has_safe(bit)			\
563 )
564 #else
565 /*
566  * gcc 3.x is too stupid to do the static test; fall back to dynamic.
567  */
568 #define static_cpu_has(bit)		boot_cpu_has(bit)
569 #define static_cpu_has_safe(bit)	boot_cpu_has(bit)
570 #endif
571 
572 #define cpu_has_bug(c, bit)		cpu_has(c, (bit))
573 #define set_cpu_bug(c, bit)		set_cpu_cap(c, (bit))
574 #define clear_cpu_bug(c, bit)		clear_cpu_cap(c, (bit))
575 
576 #define static_cpu_has_bug(bit)		static_cpu_has((bit))
577 #define static_cpu_has_bug_safe(bit)	static_cpu_has_safe((bit))
578 #define boot_cpu_has_bug(bit)		cpu_has_bug(&boot_cpu_data, (bit))
579 
580 #define MAX_CPU_FEATURES		(NCAPINTS * 32)
581 #define cpu_have_feature		boot_cpu_has
582 
583 #define CPU_FEATURE_TYPEFMT		"x86,ven%04Xfam%04Xmod%04X"
584 #define CPU_FEATURE_TYPEVAL		boot_cpu_data.x86_vendor, boot_cpu_data.x86, \
585 					boot_cpu_data.x86_model
586 
587 #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
588 #endif /* _ASM_X86_CPUFEATURE_H */
589