1 #ifndef _ASM_X86_APICDEF_H 2 #define _ASM_X86_APICDEF_H 3 4 /* 5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) 6 * 7 * Alan Cox <Alan.Cox@linux.org>, 1995. 8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000 9 */ 10 11 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000 12 #define APIC_DEFAULT_PHYS_BASE 0xfee00000 13 14 /* 15 * This is the IO-APIC register space as specified 16 * by Intel docs: 17 */ 18 #define IO_APIC_SLOT_SIZE 1024 19 20 #define APIC_ID 0x20 21 22 #define APIC_LVR 0x30 23 #define APIC_LVR_MASK 0xFF00FF 24 #define APIC_LVR_DIRECTED_EOI (1 << 24) 25 #define GET_APIC_VERSION(x) ((x) & 0xFFu) 26 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) 27 #ifdef CONFIG_X86_32 28 # define APIC_INTEGRATED(x) ((x) & 0xF0u) 29 #else 30 # define APIC_INTEGRATED(x) (1) 31 #endif 32 #define APIC_XAPIC(x) ((x) >= 0x14) 33 #define APIC_EXT_SPACE(x) ((x) & 0x80000000) 34 #define APIC_TASKPRI 0x80 35 #define APIC_TPRI_MASK 0xFFu 36 #define APIC_ARBPRI 0x90 37 #define APIC_ARBPRI_MASK 0xFFu 38 #define APIC_PROCPRI 0xA0 39 #define APIC_EOI 0xB0 40 #define APIC_EOI_ACK 0x0 /* Docs say 0 for future compat. */ 41 #define APIC_RRR 0xC0 42 #define APIC_LDR 0xD0 43 #define APIC_LDR_MASK (0xFFu << 24) 44 #define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) 45 #define SET_APIC_LOGICAL_ID(x) (((x) << 24)) 46 #define APIC_ALL_CPUS 0xFFu 47 #define APIC_DFR 0xE0 48 #define APIC_DFR_CLUSTER 0x0FFFFFFFul 49 #define APIC_DFR_FLAT 0xFFFFFFFFul 50 #define APIC_SPIV 0xF0 51 #define APIC_SPIV_DIRECTED_EOI (1 << 12) 52 #define APIC_SPIV_FOCUS_DISABLED (1 << 9) 53 #define APIC_SPIV_APIC_ENABLED (1 << 8) 54 #define APIC_ISR 0x100 55 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ 56 #define APIC_TMR 0x180 57 #define APIC_IRR 0x200 58 #define APIC_ESR 0x280 59 #define APIC_ESR_SEND_CS 0x00001 60 #define APIC_ESR_RECV_CS 0x00002 61 #define APIC_ESR_SEND_ACC 0x00004 62 #define APIC_ESR_RECV_ACC 0x00008 63 #define APIC_ESR_SENDILL 0x00020 64 #define APIC_ESR_RECVILL 0x00040 65 #define APIC_ESR_ILLREGA 0x00080 66 #define APIC_LVTCMCI 0x2f0 67 #define APIC_ICR 0x300 68 #define APIC_DEST_SELF 0x40000 69 #define APIC_DEST_ALLINC 0x80000 70 #define APIC_DEST_ALLBUT 0xC0000 71 #define APIC_ICR_RR_MASK 0x30000 72 #define APIC_ICR_RR_INVALID 0x00000 73 #define APIC_ICR_RR_INPROG 0x10000 74 #define APIC_ICR_RR_VALID 0x20000 75 #define APIC_INT_LEVELTRIG 0x08000 76 #define APIC_INT_ASSERT 0x04000 77 #define APIC_ICR_BUSY 0x01000 78 #define APIC_DEST_LOGICAL 0x00800 79 #define APIC_DEST_PHYSICAL 0x00000 80 #define APIC_DM_FIXED 0x00000 81 #define APIC_DM_FIXED_MASK 0x00700 82 #define APIC_DM_LOWEST 0x00100 83 #define APIC_DM_SMI 0x00200 84 #define APIC_DM_REMRD 0x00300 85 #define APIC_DM_NMI 0x00400 86 #define APIC_DM_INIT 0x00500 87 #define APIC_DM_STARTUP 0x00600 88 #define APIC_DM_EXTINT 0x00700 89 #define APIC_VECTOR_MASK 0x000FF 90 #define APIC_ICR2 0x310 91 #define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) 92 #define SET_APIC_DEST_FIELD(x) ((x) << 24) 93 #define APIC_LVTT 0x320 94 #define APIC_LVTTHMR 0x330 95 #define APIC_LVTPC 0x340 96 #define APIC_LVT0 0x350 97 #define APIC_LVT_TIMER_BASE_MASK (0x3 << 18) 98 #define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3) 99 #define SET_APIC_TIMER_BASE(x) (((x) << 18)) 100 #define APIC_TIMER_BASE_CLKIN 0x0 101 #define APIC_TIMER_BASE_TMBASE 0x1 102 #define APIC_TIMER_BASE_DIV 0x2 103 #define APIC_LVT_TIMER_ONESHOT (0 << 17) 104 #define APIC_LVT_TIMER_PERIODIC (1 << 17) 105 #define APIC_LVT_TIMER_TSCDEADLINE (2 << 17) 106 #define APIC_LVT_MASKED (1 << 16) 107 #define APIC_LVT_LEVEL_TRIGGER (1 << 15) 108 #define APIC_LVT_REMOTE_IRR (1 << 14) 109 #define APIC_INPUT_POLARITY (1 << 13) 110 #define APIC_SEND_PENDING (1 << 12) 111 #define APIC_MODE_MASK 0x700 112 #define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) 113 #define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) 114 #define APIC_MODE_FIXED 0x0 115 #define APIC_MODE_NMI 0x4 116 #define APIC_MODE_EXTINT 0x7 117 #define APIC_LVT1 0x360 118 #define APIC_LVTERR 0x370 119 #define APIC_TMICT 0x380 120 #define APIC_TMCCT 0x390 121 #define APIC_TDCR 0x3E0 122 #define APIC_SELF_IPI 0x3F0 123 #define APIC_TDR_DIV_TMBASE (1 << 2) 124 #define APIC_TDR_DIV_1 0xB 125 #define APIC_TDR_DIV_2 0x0 126 #define APIC_TDR_DIV_4 0x1 127 #define APIC_TDR_DIV_8 0x2 128 #define APIC_TDR_DIV_16 0x3 129 #define APIC_TDR_DIV_32 0x8 130 #define APIC_TDR_DIV_64 0x9 131 #define APIC_TDR_DIV_128 0xA 132 #define APIC_EFEAT 0x400 133 #define APIC_ECTRL 0x410 134 #define APIC_EILVTn(n) (0x500 + 0x10 * n) 135 #define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ 136 #define APIC_EILVT_NR_AMD_10H 4 137 #define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H 138 #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) 139 #define APIC_EILVT_MSG_FIX 0x0 140 #define APIC_EILVT_MSG_SMI 0x2 141 #define APIC_EILVT_MSG_NMI 0x4 142 #define APIC_EILVT_MSG_EXT 0x7 143 #define APIC_EILVT_MASKED (1 << 16) 144 145 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) 146 #define APIC_BASE_MSR 0x800 147 #define XAPIC_ENABLE (1UL << 11) 148 #define X2APIC_ENABLE (1UL << 10) 149 150 #ifdef CONFIG_X86_32 151 # define MAX_IO_APICS 64 152 # define MAX_LOCAL_APIC 256 153 #else 154 # define MAX_IO_APICS 128 155 # define MAX_LOCAL_APIC 32768 156 #endif 157 158 /* 159 * All x86-64 systems are xAPIC compatible. 160 * In the following, "apicid" is a physical APIC ID. 161 */ 162 #define XAPIC_DEST_CPUS_SHIFT 4 163 #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) 164 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) 165 #define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) 166 #define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT) 167 #define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK) 168 #define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT) 169 170 /* 171 * the local APIC register structure, memory mapped. Not terribly well 172 * tested, but we might eventually use this one in the future - the 173 * problem why we cannot use it right now is the P5 APIC, it has an 174 * errata which cannot take 8-bit reads and writes, only 32-bit ones ... 175 */ 176 #define u32 unsigned int 177 178 struct local_apic { 179 180 /*000*/ struct { u32 __reserved[4]; } __reserved_01; 181 182 /*010*/ struct { u32 __reserved[4]; } __reserved_02; 183 184 /*020*/ struct { /* APIC ID Register */ 185 u32 __reserved_1 : 24, 186 phys_apic_id : 4, 187 __reserved_2 : 4; 188 u32 __reserved[3]; 189 } id; 190 191 /*030*/ const 192 struct { /* APIC Version Register */ 193 u32 version : 8, 194 __reserved_1 : 8, 195 max_lvt : 8, 196 __reserved_2 : 8; 197 u32 __reserved[3]; 198 } version; 199 200 /*040*/ struct { u32 __reserved[4]; } __reserved_03; 201 202 /*050*/ struct { u32 __reserved[4]; } __reserved_04; 203 204 /*060*/ struct { u32 __reserved[4]; } __reserved_05; 205 206 /*070*/ struct { u32 __reserved[4]; } __reserved_06; 207 208 /*080*/ struct { /* Task Priority Register */ 209 u32 priority : 8, 210 __reserved_1 : 24; 211 u32 __reserved_2[3]; 212 } tpr; 213 214 /*090*/ const 215 struct { /* Arbitration Priority Register */ 216 u32 priority : 8, 217 __reserved_1 : 24; 218 u32 __reserved_2[3]; 219 } apr; 220 221 /*0A0*/ const 222 struct { /* Processor Priority Register */ 223 u32 priority : 8, 224 __reserved_1 : 24; 225 u32 __reserved_2[3]; 226 } ppr; 227 228 /*0B0*/ struct { /* End Of Interrupt Register */ 229 u32 eoi; 230 u32 __reserved[3]; 231 } eoi; 232 233 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07; 234 235 /*0D0*/ struct { /* Logical Destination Register */ 236 u32 __reserved_1 : 24, 237 logical_dest : 8; 238 u32 __reserved_2[3]; 239 } ldr; 240 241 /*0E0*/ struct { /* Destination Format Register */ 242 u32 __reserved_1 : 28, 243 model : 4; 244 u32 __reserved_2[3]; 245 } dfr; 246 247 /*0F0*/ struct { /* Spurious Interrupt Vector Register */ 248 u32 spurious_vector : 8, 249 apic_enabled : 1, 250 focus_cpu : 1, 251 __reserved_2 : 22; 252 u32 __reserved_3[3]; 253 } svr; 254 255 /*100*/ struct { /* In Service Register */ 256 /*170*/ u32 bitfield; 257 u32 __reserved[3]; 258 } isr [8]; 259 260 /*180*/ struct { /* Trigger Mode Register */ 261 /*1F0*/ u32 bitfield; 262 u32 __reserved[3]; 263 } tmr [8]; 264 265 /*200*/ struct { /* Interrupt Request Register */ 266 /*270*/ u32 bitfield; 267 u32 __reserved[3]; 268 } irr [8]; 269 270 /*280*/ union { /* Error Status Register */ 271 struct { 272 u32 send_cs_error : 1, 273 receive_cs_error : 1, 274 send_accept_error : 1, 275 receive_accept_error : 1, 276 __reserved_1 : 1, 277 send_illegal_vector : 1, 278 receive_illegal_vector : 1, 279 illegal_register_address : 1, 280 __reserved_2 : 24; 281 u32 __reserved_3[3]; 282 } error_bits; 283 struct { 284 u32 errors; 285 u32 __reserved_3[3]; 286 } all_errors; 287 } esr; 288 289 /*290*/ struct { u32 __reserved[4]; } __reserved_08; 290 291 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09; 292 293 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10; 294 295 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11; 296 297 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12; 298 299 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13; 300 301 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14; 302 303 /*300*/ struct { /* Interrupt Command Register 1 */ 304 u32 vector : 8, 305 delivery_mode : 3, 306 destination_mode : 1, 307 delivery_status : 1, 308 __reserved_1 : 1, 309 level : 1, 310 trigger : 1, 311 __reserved_2 : 2, 312 shorthand : 2, 313 __reserved_3 : 12; 314 u32 __reserved_4[3]; 315 } icr1; 316 317 /*310*/ struct { /* Interrupt Command Register 2 */ 318 union { 319 u32 __reserved_1 : 24, 320 phys_dest : 4, 321 __reserved_2 : 4; 322 u32 __reserved_3 : 24, 323 logical_dest : 8; 324 } dest; 325 u32 __reserved_4[3]; 326 } icr2; 327 328 /*320*/ struct { /* LVT - Timer */ 329 u32 vector : 8, 330 __reserved_1 : 4, 331 delivery_status : 1, 332 __reserved_2 : 3, 333 mask : 1, 334 timer_mode : 1, 335 __reserved_3 : 14; 336 u32 __reserved_4[3]; 337 } lvt_timer; 338 339 /*330*/ struct { /* LVT - Thermal Sensor */ 340 u32 vector : 8, 341 delivery_mode : 3, 342 __reserved_1 : 1, 343 delivery_status : 1, 344 __reserved_2 : 3, 345 mask : 1, 346 __reserved_3 : 15; 347 u32 __reserved_4[3]; 348 } lvt_thermal; 349 350 /*340*/ struct { /* LVT - Performance Counter */ 351 u32 vector : 8, 352 delivery_mode : 3, 353 __reserved_1 : 1, 354 delivery_status : 1, 355 __reserved_2 : 3, 356 mask : 1, 357 __reserved_3 : 15; 358 u32 __reserved_4[3]; 359 } lvt_pc; 360 361 /*350*/ struct { /* LVT - LINT0 */ 362 u32 vector : 8, 363 delivery_mode : 3, 364 __reserved_1 : 1, 365 delivery_status : 1, 366 polarity : 1, 367 remote_irr : 1, 368 trigger : 1, 369 mask : 1, 370 __reserved_2 : 15; 371 u32 __reserved_3[3]; 372 } lvt_lint0; 373 374 /*360*/ struct { /* LVT - LINT1 */ 375 u32 vector : 8, 376 delivery_mode : 3, 377 __reserved_1 : 1, 378 delivery_status : 1, 379 polarity : 1, 380 remote_irr : 1, 381 trigger : 1, 382 mask : 1, 383 __reserved_2 : 15; 384 u32 __reserved_3[3]; 385 } lvt_lint1; 386 387 /*370*/ struct { /* LVT - Error */ 388 u32 vector : 8, 389 __reserved_1 : 4, 390 delivery_status : 1, 391 __reserved_2 : 3, 392 mask : 1, 393 __reserved_3 : 15; 394 u32 __reserved_4[3]; 395 } lvt_error; 396 397 /*380*/ struct { /* Timer Initial Count Register */ 398 u32 initial_count; 399 u32 __reserved_2[3]; 400 } timer_icr; 401 402 /*390*/ const 403 struct { /* Timer Current Count Register */ 404 u32 curr_count; 405 u32 __reserved_2[3]; 406 } timer_ccr; 407 408 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16; 409 410 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17; 411 412 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18; 413 414 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19; 415 416 /*3E0*/ struct { /* Timer Divide Configuration Register */ 417 u32 divisor : 4, 418 __reserved_1 : 28; 419 u32 __reserved_2[3]; 420 } timer_dcr; 421 422 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20; 423 424 } __attribute__ ((packed)); 425 426 #undef u32 427 428 #ifdef CONFIG_X86_32 429 #define BAD_APICID 0xFFu 430 #else 431 #define BAD_APICID 0xFFFFu 432 #endif 433 434 enum ioapic_irq_destination_types { 435 dest_Fixed = 0, 436 dest_LowestPrio = 1, 437 dest_SMI = 2, 438 dest__reserved_1 = 3, 439 dest_NMI = 4, 440 dest_INIT = 5, 441 dest__reserved_2 = 6, 442 dest_ExtINT = 7 443 }; 444 445 #endif /* _ASM_X86_APICDEF_H */ 446