1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _ASM_X86_APIC_H 3 #define _ASM_X86_APIC_H 4 5 #include <linux/cpumask.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/apicdef.h> 10 #include <linux/atomic.h> 11 #include <asm/fixmap.h> 12 #include <asm/mpspec.h> 13 #include <asm/msr.h> 14 #include <asm/hardirq.h> 15 16 #define ARCH_APICTIMER_STOPS_ON_C3 1 17 18 /* 19 * Debugging macros 20 */ 21 #define APIC_QUIET 0 22 #define APIC_VERBOSE 1 23 #define APIC_DEBUG 2 24 25 /* Macros for apic_extnmi which controls external NMI masking */ 26 #define APIC_EXTNMI_BSP 0 /* Default */ 27 #define APIC_EXTNMI_ALL 1 28 #define APIC_EXTNMI_NONE 2 29 30 /* 31 * Define the default level of output to be very little 32 * This can be turned up by using apic=verbose for more 33 * information and apic=debug for _lots_ of information. 34 * apic_verbosity is defined in apic.c 35 */ 36 #define apic_printk(v, s, a...) do { \ 37 if ((v) <= apic_verbosity) \ 38 printk(s, ##a); \ 39 } while (0) 40 41 42 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 43 extern void generic_apic_probe(void); 44 #else 45 static inline void generic_apic_probe(void) 46 { 47 } 48 #endif 49 50 #ifdef CONFIG_X86_LOCAL_APIC 51 52 extern int apic_verbosity; 53 extern int local_apic_timer_c2_ok; 54 55 extern int disable_apic; 56 extern unsigned int lapic_timer_period; 57 58 extern enum apic_intr_mode_id apic_intr_mode; 59 enum apic_intr_mode_id { 60 APIC_PIC, 61 APIC_VIRTUAL_WIRE, 62 APIC_VIRTUAL_WIRE_NO_CONFIG, 63 APIC_SYMMETRIC_IO, 64 APIC_SYMMETRIC_IO_NO_ROUTING 65 }; 66 67 #ifdef CONFIG_SMP 68 extern void __inquire_remote_apic(int apicid); 69 #else /* CONFIG_SMP */ 70 static inline void __inquire_remote_apic(int apicid) 71 { 72 } 73 #endif /* CONFIG_SMP */ 74 75 static inline void default_inquire_remote_apic(int apicid) 76 { 77 if (apic_verbosity >= APIC_DEBUG) 78 __inquire_remote_apic(apicid); 79 } 80 81 /* 82 * With 82489DX we can't rely on apic feature bit 83 * retrieved via cpuid but still have to deal with 84 * such an apic chip so we assume that SMP configuration 85 * is found from MP table (64bit case uses ACPI mostly 86 * which set smp presence flag as well so we are safe 87 * to use this helper too). 88 */ 89 static inline bool apic_from_smp_config(void) 90 { 91 return smp_found_config && !disable_apic; 92 } 93 94 /* 95 * Basic functions accessing APICs. 96 */ 97 #ifdef CONFIG_PARAVIRT 98 #include <asm/paravirt.h> 99 #endif 100 101 static inline void native_apic_mem_write(u32 reg, u32 v) 102 { 103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 104 105 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 106 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 107 ASM_OUTPUT2("0" (v), "m" (*addr))); 108 } 109 110 static inline u32 native_apic_mem_read(u32 reg) 111 { 112 return *((volatile u32 *)(APIC_BASE + reg)); 113 } 114 115 extern void native_apic_wait_icr_idle(void); 116 extern u32 native_safe_apic_wait_icr_idle(void); 117 extern void native_apic_icr_write(u32 low, u32 id); 118 extern u64 native_apic_icr_read(void); 119 120 static inline bool apic_is_x2apic_enabled(void) 121 { 122 u64 msr; 123 124 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 125 return false; 126 return msr & X2APIC_ENABLE; 127 } 128 129 extern void enable_IR_x2apic(void); 130 131 extern int get_physical_broadcast(void); 132 133 extern int lapic_get_maxlvt(void); 134 extern void clear_local_APIC(void); 135 extern void disconnect_bsp_APIC(int virt_wire_setup); 136 extern void disable_local_APIC(void); 137 extern void apic_soft_disable(void); 138 extern void lapic_shutdown(void); 139 extern void sync_Arb_IDs(void); 140 extern void init_bsp_APIC(void); 141 extern void apic_intr_mode_select(void); 142 extern void apic_intr_mode_init(void); 143 extern void init_apic_mappings(void); 144 void register_lapic_address(unsigned long address); 145 extern void setup_boot_APIC_clock(void); 146 extern void setup_secondary_APIC_clock(void); 147 extern void lapic_update_tsc_freq(void); 148 149 #ifdef CONFIG_X86_64 150 static inline int apic_force_enable(unsigned long addr) 151 { 152 return -1; 153 } 154 #else 155 extern int apic_force_enable(unsigned long addr); 156 #endif 157 158 extern void apic_ap_setup(void); 159 160 /* 161 * On 32bit this is mach-xxx local 162 */ 163 #ifdef CONFIG_X86_64 164 extern int apic_is_clustered_box(void); 165 #else 166 static inline int apic_is_clustered_box(void) 167 { 168 return 0; 169 } 170 #endif 171 172 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 173 extern void lapic_assign_system_vectors(void); 174 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); 175 extern void lapic_update_legacy_vectors(void); 176 extern void lapic_online(void); 177 extern void lapic_offline(void); 178 extern bool apic_needs_pit(void); 179 180 extern void apic_send_IPI_allbutself(unsigned int vector); 181 182 #else /* !CONFIG_X86_LOCAL_APIC */ 183 static inline void lapic_shutdown(void) { } 184 #define local_apic_timer_c2_ok 1 185 static inline void init_apic_mappings(void) { } 186 static inline void disable_local_APIC(void) { } 187 # define setup_boot_APIC_clock x86_init_noop 188 # define setup_secondary_APIC_clock x86_init_noop 189 static inline void lapic_update_tsc_freq(void) { } 190 static inline void init_bsp_APIC(void) { } 191 static inline void apic_intr_mode_select(void) { } 192 static inline void apic_intr_mode_init(void) { } 193 static inline void lapic_assign_system_vectors(void) { } 194 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } 195 static inline bool apic_needs_pit(void) { return true; } 196 #endif /* !CONFIG_X86_LOCAL_APIC */ 197 198 #ifdef CONFIG_X86_X2APIC 199 static inline void native_apic_msr_write(u32 reg, u32 v) 200 { 201 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 202 reg == APIC_LVR) 203 return; 204 205 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 206 } 207 208 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 209 { 210 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 211 } 212 213 static inline u32 native_apic_msr_read(u32 reg) 214 { 215 u64 msr; 216 217 if (reg == APIC_DFR) 218 return -1; 219 220 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 221 return (u32)msr; 222 } 223 224 static inline void native_x2apic_wait_icr_idle(void) 225 { 226 /* no need to wait for icr idle in x2apic */ 227 return; 228 } 229 230 static inline u32 native_safe_x2apic_wait_icr_idle(void) 231 { 232 /* no need to wait for icr idle in x2apic */ 233 return 0; 234 } 235 236 static inline void native_x2apic_icr_write(u32 low, u32 id) 237 { 238 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 239 } 240 241 static inline u64 native_x2apic_icr_read(void) 242 { 243 unsigned long val; 244 245 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 246 return val; 247 } 248 249 extern int x2apic_mode; 250 extern int x2apic_phys; 251 extern void __init x2apic_set_max_apicid(u32 apicid); 252 extern void __init check_x2apic(void); 253 extern void x2apic_setup(void); 254 static inline int x2apic_enabled(void) 255 { 256 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 257 } 258 259 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 260 #else /* !CONFIG_X86_X2APIC */ 261 static inline void check_x2apic(void) { } 262 static inline void x2apic_setup(void) { } 263 static inline int x2apic_enabled(void) { return 0; } 264 265 #define x2apic_mode (0) 266 #define x2apic_supported() (0) 267 #endif /* !CONFIG_X86_X2APIC */ 268 269 struct irq_data; 270 271 /* 272 * Copyright 2004 James Cleverdon, IBM. 273 * 274 * Generic APIC sub-arch data struct. 275 * 276 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 277 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 278 * James Cleverdon. 279 */ 280 struct apic { 281 /* Hotpath functions first */ 282 void (*eoi_write)(u32 reg, u32 v); 283 void (*native_eoi_write)(u32 reg, u32 v); 284 void (*write)(u32 reg, u32 v); 285 u32 (*read)(u32 reg); 286 287 /* IPI related functions */ 288 void (*wait_icr_idle)(void); 289 u32 (*safe_wait_icr_idle)(void); 290 291 void (*send_IPI)(int cpu, int vector); 292 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 293 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 294 void (*send_IPI_allbutself)(int vector); 295 void (*send_IPI_all)(int vector); 296 void (*send_IPI_self)(int vector); 297 298 u32 disable_esr; 299 300 enum apic_delivery_modes delivery_mode; 301 bool dest_mode_logical; 302 303 u32 (*calc_dest_apicid)(unsigned int cpu); 304 305 /* ICR related functions */ 306 u64 (*icr_read)(void); 307 void (*icr_write)(u32 low, u32 high); 308 309 /* Probe, setup and smpboot functions */ 310 int (*probe)(void); 311 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 312 int (*apic_id_valid)(u32 apicid); 313 int (*apic_id_registered)(void); 314 315 bool (*check_apicid_used)(physid_mask_t *map, int apicid); 316 void (*init_apic_ldr)(void); 317 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 318 void (*setup_apic_routing)(void); 319 int (*cpu_present_to_apicid)(int mps_cpu); 320 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 321 int (*check_phys_apicid_present)(int phys_apicid); 322 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 323 324 u32 (*get_apic_id)(unsigned long x); 325 u32 (*set_apic_id)(unsigned int id); 326 327 /* wakeup_secondary_cpu */ 328 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 329 /* wakeup secondary CPU using 64-bit wakeup point */ 330 int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); 331 332 void (*inquire_remote_apic)(int apicid); 333 334 #ifdef CONFIG_X86_32 335 /* 336 * Called very early during boot from get_smp_config(). It should 337 * return the logical apicid. x86_[bios]_cpu_to_apicid is 338 * initialized before this function is called. 339 * 340 * If logical apicid can't be determined that early, the function 341 * may return BAD_APICID. Logical apicid will be configured after 342 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 343 * won't be applied properly during early boot in this case. 344 */ 345 int (*x86_32_early_logical_apicid)(int cpu); 346 #endif 347 char *name; 348 }; 349 350 /* 351 * Pointer to the local APIC driver in use on this system (there's 352 * always just one such driver in use - the kernel decides via an 353 * early probing process which one it picks - and then sticks to it): 354 */ 355 extern struct apic *apic; 356 357 /* 358 * APIC drivers are probed based on how they are listed in the .apicdrivers 359 * section. So the order is important and enforced by the ordering 360 * of different apic driver files in the Makefile. 361 * 362 * For the files having two apic drivers, we use apic_drivers() 363 * to enforce the order with in them. 364 */ 365 #define apic_driver(sym) \ 366 static const struct apic *__apicdrivers_##sym __used \ 367 __aligned(sizeof(struct apic *)) \ 368 __section(".apicdrivers") = { &sym } 369 370 #define apic_drivers(sym1, sym2) \ 371 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 372 __aligned(sizeof(struct apic *)) \ 373 __section(".apicdrivers") = { &sym1, &sym2 } 374 375 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 376 377 /* 378 * APIC functionality to boot other CPUs - only used on SMP: 379 */ 380 #ifdef CONFIG_SMP 381 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 382 extern int lapic_can_unplug_cpu(void); 383 #endif 384 385 #ifdef CONFIG_X86_LOCAL_APIC 386 387 static inline u32 apic_read(u32 reg) 388 { 389 return apic->read(reg); 390 } 391 392 static inline void apic_write(u32 reg, u32 val) 393 { 394 apic->write(reg, val); 395 } 396 397 static inline void apic_eoi(void) 398 { 399 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 400 } 401 402 static inline u64 apic_icr_read(void) 403 { 404 return apic->icr_read(); 405 } 406 407 static inline void apic_icr_write(u32 low, u32 high) 408 { 409 apic->icr_write(low, high); 410 } 411 412 static inline void apic_wait_icr_idle(void) 413 { 414 apic->wait_icr_idle(); 415 } 416 417 static inline u32 safe_apic_wait_icr_idle(void) 418 { 419 return apic->safe_wait_icr_idle(); 420 } 421 422 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 423 424 #else /* CONFIG_X86_LOCAL_APIC */ 425 426 static inline u32 apic_read(u32 reg) { return 0; } 427 static inline void apic_write(u32 reg, u32 val) { } 428 static inline void apic_eoi(void) { } 429 static inline u64 apic_icr_read(void) { return 0; } 430 static inline void apic_icr_write(u32 low, u32 high) { } 431 static inline void apic_wait_icr_idle(void) { } 432 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 433 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 434 435 #endif /* CONFIG_X86_LOCAL_APIC */ 436 437 extern void apic_ack_irq(struct irq_data *data); 438 439 static inline void ack_APIC_irq(void) 440 { 441 /* 442 * ack_APIC_irq() actually gets compiled as a single instruction 443 * ... yummie. 444 */ 445 apic_eoi(); 446 } 447 448 449 static inline bool lapic_vector_set_in_irr(unsigned int vector) 450 { 451 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 452 453 return !!(irr & (1U << (vector % 32))); 454 } 455 456 static inline unsigned default_get_apic_id(unsigned long x) 457 { 458 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 459 460 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 461 return (x >> 24) & 0xFF; 462 else 463 return (x >> 24) & 0x0F; 464 } 465 466 /* 467 * Warm reset vector position: 468 */ 469 #define TRAMPOLINE_PHYS_LOW 0x467 470 #define TRAMPOLINE_PHYS_HIGH 0x469 471 472 extern void generic_bigsmp_probe(void); 473 474 #ifdef CONFIG_X86_LOCAL_APIC 475 476 #include <asm/smp.h> 477 478 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 479 480 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 481 482 extern struct apic apic_noop; 483 484 static inline unsigned int read_apic_id(void) 485 { 486 unsigned int reg = apic_read(APIC_ID); 487 488 return apic->get_apic_id(reg); 489 } 490 491 #ifdef CONFIG_X86_64 492 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); 493 extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler); 494 #endif 495 496 extern int default_apic_id_valid(u32 apicid); 497 extern int default_acpi_madt_oem_check(char *, char *); 498 extern void default_setup_apic_routing(void); 499 500 extern u32 apic_default_calc_apicid(unsigned int cpu); 501 extern u32 apic_flat_calc_apicid(unsigned int cpu); 502 503 extern bool default_check_apicid_used(physid_mask_t *map, int apicid); 504 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); 505 extern int default_cpu_present_to_apicid(int mps_cpu); 506 extern int default_check_phys_apicid_present(int phys_apicid); 507 508 #endif /* CONFIG_X86_LOCAL_APIC */ 509 510 #ifdef CONFIG_SMP 511 bool apic_id_is_primary_thread(unsigned int id); 512 void apic_smt_update(void); 513 #else 514 static inline bool apic_id_is_primary_thread(unsigned int id) { return false; } 515 static inline void apic_smt_update(void) { } 516 #endif 517 518 struct msi_msg; 519 struct irq_cfg; 520 521 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, 522 bool dmar); 523 524 extern void ioapic_zap_locks(void); 525 526 #endif /* _ASM_X86_APIC_H */ 527