1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_AMD_NB_H 3 #define _ASM_X86_AMD_NB_H 4 5 #include <linux/ioport.h> 6 #include <linux/pci.h> 7 #include <asm/amd_node.h> 8 9 struct amd_nb_bus_dev_range { 10 u8 bus; 11 u8 dev_base; 12 u8 dev_limit; 13 }; 14 15 extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[]; 16 17 extern bool early_is_amd_nb(u32 value); 18 extern struct resource *amd_get_mmconfig_range(struct resource *res); 19 extern void amd_flush_garts(void); 20 extern int amd_numa_init(void); 21 extern int amd_get_subcaches(int); 22 extern int amd_set_subcaches(int, unsigned long); 23 24 struct amd_l3_cache { 25 unsigned indices; 26 u8 subcaches[4]; 27 }; 28 29 struct amd_northbridge { 30 struct pci_dev *root; 31 struct pci_dev *misc; 32 struct pci_dev *link; 33 struct amd_l3_cache l3_cache; 34 }; 35 36 struct amd_northbridge_info { 37 u16 num; 38 u64 flags; 39 struct amd_northbridge *nb; 40 }; 41 42 #define AMD_NB_GART BIT(0) 43 #define AMD_NB_L3_INDEX_DISABLE BIT(1) 44 #define AMD_NB_L3_PARTITIONING BIT(2) 45 46 #ifdef CONFIG_AMD_NB 47 48 u16 amd_nb_num(void); 49 bool amd_nb_has_feature(unsigned int feature); 50 struct amd_northbridge *node_to_amd_nb(int node); 51 52 static inline bool amd_gart_present(void) 53 { 54 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) 55 return false; 56 57 /* GART present only on Fam15h, up to model 0fh */ 58 if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 || 59 (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10)) 60 return true; 61 62 return false; 63 } 64 65 #else 66 67 #define amd_nb_num(x) 0 68 #define amd_nb_has_feature(x) false 69 static inline struct amd_northbridge *node_to_amd_nb(int node) 70 { 71 return NULL; 72 } 73 #define amd_gart_present(x) false 74 75 #endif 76 77 78 #endif /* _ASM_X86_AMD_NB_H */ 79