1 #ifndef _ASM_X86_AMD_NB_H 2 #define _ASM_X86_AMD_NB_H 3 4 #include <linux/pci.h> 5 6 struct amd_nb_bus_dev_range { 7 u8 bus; 8 u8 dev_base; 9 u8 dev_limit; 10 }; 11 12 extern const struct pci_device_id amd_nb_misc_ids[]; 13 extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[]; 14 15 extern bool early_is_amd_nb(u32 value); 16 extern int amd_cache_northbridges(void); 17 extern void amd_flush_garts(void); 18 extern int amd_numa_init(void); 19 extern int amd_get_subcaches(int); 20 extern int amd_set_subcaches(int, int); 21 22 struct amd_l3_cache { 23 unsigned indices; 24 u8 subcaches[4]; 25 }; 26 27 struct amd_northbridge { 28 struct pci_dev *misc; 29 struct pci_dev *link; 30 struct amd_l3_cache l3_cache; 31 }; 32 33 struct amd_northbridge_info { 34 u16 num; 35 u64 flags; 36 struct amd_northbridge *nb; 37 }; 38 extern struct amd_northbridge_info amd_northbridges; 39 40 #define AMD_NB_GART BIT(0) 41 #define AMD_NB_L3_INDEX_DISABLE BIT(1) 42 #define AMD_NB_L3_PARTITIONING BIT(2) 43 44 #ifdef CONFIG_AMD_NB 45 46 static inline u16 amd_nb_num(void) 47 { 48 return amd_northbridges.num; 49 } 50 51 static inline bool amd_nb_has_feature(unsigned feature) 52 { 53 return ((amd_northbridges.flags & feature) == feature); 54 } 55 56 static inline struct amd_northbridge *node_to_amd_nb(int node) 57 { 58 return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL; 59 } 60 61 #else 62 63 #define amd_nb_num(x) 0 64 #define amd_nb_has_feature(x) false 65 #define node_to_amd_nb(x) NULL 66 67 #endif 68 69 70 #endif /* _ASM_X86_AMD_NB_H */ 71