1*7bfe3b8eSNaman Jain // SPDX-License-Identifier: GPL-2.0
2*7bfe3b8eSNaman Jain /*
3*7bfe3b8eSNaman Jain * Generate definitions needed by assembly language modules.
4*7bfe3b8eSNaman Jain * This code generates raw asm output which is post-processed to extract
5*7bfe3b8eSNaman Jain * and format the required data.
6*7bfe3b8eSNaman Jain *
7*7bfe3b8eSNaman Jain * Copyright (c) 2025, Microsoft Corporation.
8*7bfe3b8eSNaman Jain *
9*7bfe3b8eSNaman Jain * Author:
10*7bfe3b8eSNaman Jain * Naman Jain <namjain@microsoft.com>
11*7bfe3b8eSNaman Jain */
12*7bfe3b8eSNaman Jain #define COMPILE_OFFSETS
13*7bfe3b8eSNaman Jain
14*7bfe3b8eSNaman Jain #include <linux/kbuild.h>
15*7bfe3b8eSNaman Jain #include <asm/mshyperv.h>
16*7bfe3b8eSNaman Jain
common(void)17*7bfe3b8eSNaman Jain static void __used common(void)
18*7bfe3b8eSNaman Jain {
19*7bfe3b8eSNaman Jain if (IS_ENABLED(CONFIG_HYPERV_VTL_MODE)) {
20*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_rax, mshv_vtl_cpu_context, rax);
21*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_rcx, mshv_vtl_cpu_context, rcx);
22*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_rdx, mshv_vtl_cpu_context, rdx);
23*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_rbx, mshv_vtl_cpu_context, rbx);
24*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_rbp, mshv_vtl_cpu_context, rbp);
25*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_rsi, mshv_vtl_cpu_context, rsi);
26*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_rdi, mshv_vtl_cpu_context, rdi);
27*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_r8, mshv_vtl_cpu_context, r8);
28*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_r9, mshv_vtl_cpu_context, r9);
29*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_r10, mshv_vtl_cpu_context, r10);
30*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_r11, mshv_vtl_cpu_context, r11);
31*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_r12, mshv_vtl_cpu_context, r12);
32*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_r13, mshv_vtl_cpu_context, r13);
33*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_r14, mshv_vtl_cpu_context, r14);
34*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_r15, mshv_vtl_cpu_context, r15);
35*7bfe3b8eSNaman Jain OFFSET(MSHV_VTL_CPU_CONTEXT_cr2, mshv_vtl_cpu_context, cr2);
36*7bfe3b8eSNaman Jain }
37*7bfe3b8eSNaman Jain }
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