xref: /linux/arch/x86/hyperv/hv_apic.c (revision bd628c1bed7902ec1f24ba0fe70758949146abbe)
1 // SPDX-License-Identifier: GPL-2.0
2 
3 /*
4  * Hyper-V specific APIC code.
5  *
6  * Copyright (C) 2018, Microsoft, Inc.
7  *
8  * Author : K. Y. Srinivasan <kys@microsoft.com>
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms of the GNU General Public License version 2 as published
12  * by the Free Software Foundation.
13  *
14  * This program is distributed in the hope that it will be useful, but
15  * WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
17  * NON INFRINGEMENT.  See the GNU General Public License for more
18  * details.
19  *
20  */
21 
22 #include <linux/types.h>
23 #include <linux/vmalloc.h>
24 #include <linux/mm.h>
25 #include <linux/clockchips.h>
26 #include <linux/hyperv.h>
27 #include <linux/slab.h>
28 #include <linux/cpuhotplug.h>
29 #include <asm/hypervisor.h>
30 #include <asm/mshyperv.h>
31 #include <asm/apic.h>
32 
33 #include <asm/trace/hyperv.h>
34 
35 static struct apic orig_apic;
36 
37 static u64 hv_apic_icr_read(void)
38 {
39 	u64 reg_val;
40 
41 	rdmsrl(HV_X64_MSR_ICR, reg_val);
42 	return reg_val;
43 }
44 
45 static void hv_apic_icr_write(u32 low, u32 id)
46 {
47 	u64 reg_val;
48 
49 	reg_val = SET_APIC_DEST_FIELD(id);
50 	reg_val = reg_val << 32;
51 	reg_val |= low;
52 
53 	wrmsrl(HV_X64_MSR_ICR, reg_val);
54 }
55 
56 static u32 hv_apic_read(u32 reg)
57 {
58 	u32 reg_val, hi;
59 
60 	switch (reg) {
61 	case APIC_EOI:
62 		rdmsr(HV_X64_MSR_EOI, reg_val, hi);
63 		return reg_val;
64 	case APIC_TASKPRI:
65 		rdmsr(HV_X64_MSR_TPR, reg_val, hi);
66 		return reg_val;
67 
68 	default:
69 		return native_apic_mem_read(reg);
70 	}
71 }
72 
73 static void hv_apic_write(u32 reg, u32 val)
74 {
75 	switch (reg) {
76 	case APIC_EOI:
77 		wrmsr(HV_X64_MSR_EOI, val, 0);
78 		break;
79 	case APIC_TASKPRI:
80 		wrmsr(HV_X64_MSR_TPR, val, 0);
81 		break;
82 	default:
83 		native_apic_mem_write(reg, val);
84 	}
85 }
86 
87 static void hv_apic_eoi_write(u32 reg, u32 val)
88 {
89 	wrmsr(HV_X64_MSR_EOI, val, 0);
90 }
91 
92 /*
93  * IPI implementation on Hyper-V.
94  */
95 static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector)
96 {
97 	struct hv_send_ipi_ex **arg;
98 	struct hv_send_ipi_ex *ipi_arg;
99 	unsigned long flags;
100 	int nr_bank = 0;
101 	int ret = 1;
102 
103 	if (!(ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
104 		return false;
105 
106 	local_irq_save(flags);
107 	arg = (struct hv_send_ipi_ex **)this_cpu_ptr(hyperv_pcpu_input_arg);
108 
109 	ipi_arg = *arg;
110 	if (unlikely(!ipi_arg))
111 		goto ipi_mask_ex_done;
112 
113 	ipi_arg->vector = vector;
114 	ipi_arg->reserved = 0;
115 	ipi_arg->vp_set.valid_bank_mask = 0;
116 
117 	if (!cpumask_equal(mask, cpu_present_mask)) {
118 		ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K;
119 		nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask);
120 	}
121 	if (nr_bank < 0)
122 		goto ipi_mask_ex_done;
123 	if (!nr_bank)
124 		ipi_arg->vp_set.format = HV_GENERIC_SET_ALL;
125 
126 	ret = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank,
127 			      ipi_arg, NULL);
128 
129 ipi_mask_ex_done:
130 	local_irq_restore(flags);
131 	return ((ret == 0) ? true : false);
132 }
133 
134 static bool __send_ipi_mask(const struct cpumask *mask, int vector)
135 {
136 	int cur_cpu, vcpu;
137 	struct hv_send_ipi ipi_arg;
138 	int ret = 1;
139 
140 	trace_hyperv_send_ipi_mask(mask, vector);
141 
142 	if (cpumask_empty(mask))
143 		return true;
144 
145 	if (!hv_hypercall_pg)
146 		return false;
147 
148 	if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR))
149 		return false;
150 
151 	/*
152 	 * From the supplied CPU set we need to figure out if we can get away
153 	 * with cheaper HVCALL_SEND_IPI hypercall. This is possible when the
154 	 * highest VP number in the set is < 64. As VP numbers are usually in
155 	 * ascending order and match Linux CPU ids, here is an optimization:
156 	 * we check the VP number for the highest bit in the supplied set first
157 	 * so we can quickly find out if using HVCALL_SEND_IPI_EX hypercall is
158 	 * a must. We will also check all VP numbers when walking the supplied
159 	 * CPU set to remain correct in all cases.
160 	 */
161 	if (hv_cpu_number_to_vp_number(cpumask_last(mask)) >= 64)
162 		goto do_ex_hypercall;
163 
164 	ipi_arg.vector = vector;
165 	ipi_arg.cpu_mask = 0;
166 
167 	for_each_cpu(cur_cpu, mask) {
168 		vcpu = hv_cpu_number_to_vp_number(cur_cpu);
169 		if (vcpu == VP_INVAL)
170 			return false;
171 
172 		/*
173 		 * This particular version of the IPI hypercall can
174 		 * only target upto 64 CPUs.
175 		 */
176 		if (vcpu >= 64)
177 			goto do_ex_hypercall;
178 
179 		__set_bit(vcpu, (unsigned long *)&ipi_arg.cpu_mask);
180 	}
181 
182 	ret = hv_do_fast_hypercall16(HVCALL_SEND_IPI, ipi_arg.vector,
183 				     ipi_arg.cpu_mask);
184 	return ((ret == 0) ? true : false);
185 
186 do_ex_hypercall:
187 	return __send_ipi_mask_ex(mask, vector);
188 }
189 
190 static bool __send_ipi_one(int cpu, int vector)
191 {
192 	struct cpumask mask = CPU_MASK_NONE;
193 
194 	cpumask_set_cpu(cpu, &mask);
195 	return __send_ipi_mask(&mask, vector);
196 }
197 
198 static void hv_send_ipi(int cpu, int vector)
199 {
200 	if (!__send_ipi_one(cpu, vector))
201 		orig_apic.send_IPI(cpu, vector);
202 }
203 
204 static void hv_send_ipi_mask(const struct cpumask *mask, int vector)
205 {
206 	if (!__send_ipi_mask(mask, vector))
207 		orig_apic.send_IPI_mask(mask, vector);
208 }
209 
210 static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)
211 {
212 	unsigned int this_cpu = smp_processor_id();
213 	struct cpumask new_mask;
214 	const struct cpumask *local_mask;
215 
216 	cpumask_copy(&new_mask, mask);
217 	cpumask_clear_cpu(this_cpu, &new_mask);
218 	local_mask = &new_mask;
219 	if (!__send_ipi_mask(local_mask, vector))
220 		orig_apic.send_IPI_mask_allbutself(mask, vector);
221 }
222 
223 static void hv_send_ipi_allbutself(int vector)
224 {
225 	hv_send_ipi_mask_allbutself(cpu_online_mask, vector);
226 }
227 
228 static void hv_send_ipi_all(int vector)
229 {
230 	if (!__send_ipi_mask(cpu_online_mask, vector))
231 		orig_apic.send_IPI_all(vector);
232 }
233 
234 static void hv_send_ipi_self(int vector)
235 {
236 	if (!__send_ipi_one(smp_processor_id(), vector))
237 		orig_apic.send_IPI_self(vector);
238 }
239 
240 void __init hv_apic_init(void)
241 {
242 	if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) {
243 		pr_info("Hyper-V: Using IPI hypercalls\n");
244 		/*
245 		 * Set the IPI entry points.
246 		 */
247 		orig_apic = *apic;
248 
249 		apic->send_IPI = hv_send_ipi;
250 		apic->send_IPI_mask = hv_send_ipi_mask;
251 		apic->send_IPI_mask_allbutself = hv_send_ipi_mask_allbutself;
252 		apic->send_IPI_allbutself = hv_send_ipi_allbutself;
253 		apic->send_IPI_all = hv_send_ipi_all;
254 		apic->send_IPI_self = hv_send_ipi_self;
255 	}
256 
257 	if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) {
258 		pr_info("Hyper-V: Using MSR based APIC access\n");
259 		apic_set_eoi_write(hv_apic_eoi_write);
260 		apic->read      = hv_apic_read;
261 		apic->write     = hv_apic_write;
262 		apic->icr_write = hv_apic_icr_write;
263 		apic->icr_read  = hv_apic_icr_read;
264 	}
265 }
266