1 // SPDX-License-Identifier: GPL-2.0 2 3 /* 4 * Hyper-V specific APIC code. 5 * 6 * Copyright (C) 2018, Microsoft, Inc. 7 * 8 * Author : K. Y. Srinivasan <kys@microsoft.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 17 * NON INFRINGEMENT. See the GNU General Public License for more 18 * details. 19 * 20 */ 21 22 #include <linux/types.h> 23 #include <linux/vmalloc.h> 24 #include <linux/mm.h> 25 #include <linux/clockchips.h> 26 #include <linux/slab.h> 27 #include <linux/cpuhotplug.h> 28 #include <asm/hypervisor.h> 29 #include <asm/mshyperv.h> 30 #include <asm/apic.h> 31 32 #include <asm/trace/hyperv.h> 33 34 static struct apic orig_apic; 35 36 static u64 hv_apic_icr_read(void) 37 { 38 u64 reg_val; 39 40 rdmsrl(HV_X64_MSR_ICR, reg_val); 41 return reg_val; 42 } 43 44 static void hv_apic_icr_write(u32 low, u32 id) 45 { 46 u64 reg_val; 47 48 reg_val = SET_XAPIC_DEST_FIELD(id); 49 reg_val = reg_val << 32; 50 reg_val |= low; 51 52 wrmsrl(HV_X64_MSR_ICR, reg_val); 53 } 54 55 static u32 hv_apic_read(u32 reg) 56 { 57 u32 reg_val, hi; 58 59 switch (reg) { 60 case APIC_EOI: 61 rdmsr(HV_X64_MSR_EOI, reg_val, hi); 62 (void)hi; 63 return reg_val; 64 case APIC_TASKPRI: 65 rdmsr(HV_X64_MSR_TPR, reg_val, hi); 66 (void)hi; 67 return reg_val; 68 69 default: 70 return native_apic_mem_read(reg); 71 } 72 } 73 74 static void hv_apic_write(u32 reg, u32 val) 75 { 76 switch (reg) { 77 case APIC_EOI: 78 wrmsr(HV_X64_MSR_EOI, val, 0); 79 break; 80 case APIC_TASKPRI: 81 wrmsr(HV_X64_MSR_TPR, val, 0); 82 break; 83 default: 84 native_apic_mem_write(reg, val); 85 } 86 } 87 88 static void hv_apic_eoi_write(void) 89 { 90 struct hv_vp_assist_page *hvp = hv_vp_assist_page[smp_processor_id()]; 91 92 if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1)) 93 return; 94 95 wrmsr(HV_X64_MSR_EOI, APIC_EOI_ACK, 0); 96 } 97 98 static bool cpu_is_self(int cpu) 99 { 100 return cpu == smp_processor_id(); 101 } 102 103 /* 104 * IPI implementation on Hyper-V. 105 */ 106 static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector, 107 bool exclude_self) 108 { 109 struct hv_send_ipi_ex *ipi_arg; 110 unsigned long flags; 111 int nr_bank = 0; 112 u64 status = HV_STATUS_INVALID_PARAMETER; 113 114 if (!(ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED)) 115 return false; 116 117 local_irq_save(flags); 118 ipi_arg = *this_cpu_ptr(hyperv_pcpu_input_arg); 119 120 if (unlikely(!ipi_arg)) 121 goto ipi_mask_ex_done; 122 123 ipi_arg->vector = vector; 124 ipi_arg->reserved = 0; 125 ipi_arg->vp_set.valid_bank_mask = 0; 126 127 /* 128 * Use HV_GENERIC_SET_ALL and avoid converting cpumask to VP_SET 129 * when the IPI is sent to all currently present CPUs. 130 */ 131 if (!cpumask_equal(mask, cpu_present_mask) || exclude_self) { 132 ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K; 133 134 nr_bank = cpumask_to_vpset_skip(&ipi_arg->vp_set, mask, 135 exclude_self ? cpu_is_self : NULL); 136 137 /* 138 * 'nr_bank <= 0' means some CPUs in cpumask can't be 139 * represented in VP_SET. Return an error and fall back to 140 * native (architectural) method of sending IPIs. 141 */ 142 if (nr_bank <= 0) 143 goto ipi_mask_ex_done; 144 } else { 145 ipi_arg->vp_set.format = HV_GENERIC_SET_ALL; 146 } 147 148 /* 149 * For this hypercall, Hyper-V treats the valid_bank_mask field 150 * of ipi_arg->vp_set as part of the fixed size input header. 151 * So the variable input header size is equal to nr_bank. 152 */ 153 status = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank, 154 ipi_arg, NULL); 155 156 ipi_mask_ex_done: 157 local_irq_restore(flags); 158 return hv_result_success(status); 159 } 160 161 static bool __send_ipi_mask(const struct cpumask *mask, int vector, 162 bool exclude_self) 163 { 164 int cur_cpu, vcpu, this_cpu = smp_processor_id(); 165 struct hv_send_ipi ipi_arg; 166 u64 status; 167 unsigned int weight; 168 169 trace_hyperv_send_ipi_mask(mask, vector); 170 171 weight = cpumask_weight(mask); 172 173 /* 174 * Do nothing if 175 * 1. the mask is empty 176 * 2. the mask only contains self when exclude_self is true 177 */ 178 if (weight == 0 || 179 (exclude_self && weight == 1 && cpumask_test_cpu(this_cpu, mask))) 180 return true; 181 182 /* A fully enlightened TDX VM uses GHCI rather than hv_hypercall_pg. */ 183 if (!hv_hypercall_pg) { 184 if (ms_hyperv.paravisor_present || !hv_isolation_type_tdx()) 185 return false; 186 } 187 188 if (vector < HV_IPI_LOW_VECTOR || vector > HV_IPI_HIGH_VECTOR) 189 return false; 190 191 /* 192 * From the supplied CPU set we need to figure out if we can get away 193 * with cheaper HVCALL_SEND_IPI hypercall. This is possible when the 194 * highest VP number in the set is < 64. As VP numbers are usually in 195 * ascending order and match Linux CPU ids, here is an optimization: 196 * we check the VP number for the highest bit in the supplied set first 197 * so we can quickly find out if using HVCALL_SEND_IPI_EX hypercall is 198 * a must. We will also check all VP numbers when walking the supplied 199 * CPU set to remain correct in all cases. 200 */ 201 if (hv_cpu_number_to_vp_number(cpumask_last(mask)) >= 64) 202 goto do_ex_hypercall; 203 204 ipi_arg.vector = vector; 205 ipi_arg.cpu_mask = 0; 206 207 for_each_cpu(cur_cpu, mask) { 208 if (exclude_self && cur_cpu == this_cpu) 209 continue; 210 vcpu = hv_cpu_number_to_vp_number(cur_cpu); 211 if (vcpu == VP_INVAL) 212 return false; 213 214 /* 215 * This particular version of the IPI hypercall can 216 * only target up to 64 CPUs. 217 */ 218 if (vcpu >= 64) 219 goto do_ex_hypercall; 220 221 __set_bit(vcpu, (unsigned long *)&ipi_arg.cpu_mask); 222 } 223 224 status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, ipi_arg.vector, 225 ipi_arg.cpu_mask); 226 return hv_result_success(status); 227 228 do_ex_hypercall: 229 return __send_ipi_mask_ex(mask, vector, exclude_self); 230 } 231 232 static bool __send_ipi_one(int cpu, int vector) 233 { 234 int vp = hv_cpu_number_to_vp_number(cpu); 235 u64 status; 236 237 trace_hyperv_send_ipi_one(cpu, vector); 238 239 if (vp == VP_INVAL) 240 return false; 241 242 /* A fully enlightened TDX VM uses GHCI rather than hv_hypercall_pg. */ 243 if (!hv_hypercall_pg) { 244 if (ms_hyperv.paravisor_present || !hv_isolation_type_tdx()) 245 return false; 246 } 247 248 if (vector < HV_IPI_LOW_VECTOR || vector > HV_IPI_HIGH_VECTOR) 249 return false; 250 251 if (vp >= 64) 252 return __send_ipi_mask_ex(cpumask_of(cpu), vector, false); 253 254 status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, vector, BIT_ULL(vp)); 255 return hv_result_success(status); 256 } 257 258 static void hv_send_ipi(int cpu, int vector) 259 { 260 if (!__send_ipi_one(cpu, vector)) 261 orig_apic.send_IPI(cpu, vector); 262 } 263 264 static void hv_send_ipi_mask(const struct cpumask *mask, int vector) 265 { 266 if (!__send_ipi_mask(mask, vector, false)) 267 orig_apic.send_IPI_mask(mask, vector); 268 } 269 270 static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector) 271 { 272 if (!__send_ipi_mask(mask, vector, true)) 273 orig_apic.send_IPI_mask_allbutself(mask, vector); 274 } 275 276 static void hv_send_ipi_allbutself(int vector) 277 { 278 hv_send_ipi_mask_allbutself(cpu_online_mask, vector); 279 } 280 281 static void hv_send_ipi_all(int vector) 282 { 283 if (!__send_ipi_mask(cpu_online_mask, vector, false)) 284 orig_apic.send_IPI_all(vector); 285 } 286 287 static void hv_send_ipi_self(int vector) 288 { 289 if (!__send_ipi_one(smp_processor_id(), vector)) 290 orig_apic.send_IPI_self(vector); 291 } 292 293 void __init hv_apic_init(void) 294 { 295 if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) { 296 pr_info("Hyper-V: Using IPI hypercalls\n"); 297 /* 298 * Set the IPI entry points. 299 */ 300 orig_apic = *apic; 301 302 apic_update_callback(send_IPI, hv_send_ipi); 303 apic_update_callback(send_IPI_mask, hv_send_ipi_mask); 304 apic_update_callback(send_IPI_mask_allbutself, hv_send_ipi_mask_allbutself); 305 apic_update_callback(send_IPI_allbutself, hv_send_ipi_allbutself); 306 apic_update_callback(send_IPI_all, hv_send_ipi_all); 307 apic_update_callback(send_IPI_self, hv_send_ipi_self); 308 } 309 310 if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) { 311 pr_info("Hyper-V: Using enlightened APIC (%s mode)", 312 x2apic_enabled() ? "x2apic" : "xapic"); 313 /* 314 * When in x2apic mode, don't use the Hyper-V specific APIC 315 * accessors since the field layout in the ICR register is 316 * different in x2apic mode. Furthermore, the architectural 317 * x2apic MSRs function just as well as the Hyper-V 318 * synthetic APIC MSRs, so there's no benefit in having 319 * separate Hyper-V accessors for x2apic mode. The only 320 * exception is hv_apic_eoi_write, because it benefits from 321 * lazy EOI when available, but the same accessor works for 322 * both xapic and x2apic because the field layout is the same. 323 */ 324 apic_update_callback(eoi, hv_apic_eoi_write); 325 if (!x2apic_enabled()) { 326 apic_update_callback(read, hv_apic_read); 327 apic_update_callback(write, hv_apic_write); 328 apic_update_callback(icr_write, hv_apic_icr_write); 329 apic_update_callback(icr_read, hv_apic_icr_read); 330 } 331 } 332 } 333