1 // SPDX-License-Identifier: GPL-2.0 2 3 /* 4 * Hyper-V specific APIC code. 5 * 6 * Copyright (C) 2018, Microsoft, Inc. 7 * 8 * Author : K. Y. Srinivasan <kys@microsoft.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 17 * NON INFRINGEMENT. See the GNU General Public License for more 18 * details. 19 * 20 */ 21 22 #include <linux/types.h> 23 #include <linux/vmalloc.h> 24 #include <linux/mm.h> 25 #include <linux/clockchips.h> 26 #include <linux/slab.h> 27 #include <linux/cpuhotplug.h> 28 #include <asm/hypervisor.h> 29 #include <asm/mshyperv.h> 30 #include <asm/apic.h> 31 #include <asm/msr.h> 32 33 #include <asm/trace/hyperv.h> 34 35 static struct apic orig_apic; 36 37 static u64 hv_apic_icr_read(void) 38 { 39 u64 reg_val; 40 41 rdmsrq(HV_X64_MSR_ICR, reg_val); 42 return reg_val; 43 } 44 45 static void hv_apic_icr_write(u32 low, u32 id) 46 { 47 u64 reg_val; 48 49 reg_val = SET_XAPIC_DEST_FIELD(id); 50 reg_val = reg_val << 32; 51 reg_val |= low; 52 53 wrmsrq(HV_X64_MSR_ICR, reg_val); 54 } 55 56 void hv_enable_coco_interrupt(unsigned int cpu, unsigned int vector, bool set) 57 { 58 apic_update_vector(cpu, vector, set); 59 } 60 61 static u32 hv_apic_read(u32 reg) 62 { 63 struct msr reg_val; 64 65 switch (reg) { 66 case APIC_EOI: 67 rdmsrq(HV_X64_MSR_EOI, reg_val.q); 68 return reg_val.l; 69 case APIC_TASKPRI: 70 rdmsrq(HV_X64_MSR_TPR, reg_val.q); 71 return reg_val.l; 72 73 default: 74 return native_apic_mem_read(reg); 75 } 76 } 77 78 static void hv_apic_write(u32 reg, u32 val) 79 { 80 switch (reg) { 81 case APIC_EOI: 82 wrmsrq(HV_X64_MSR_EOI, val); 83 break; 84 case APIC_TASKPRI: 85 wrmsrq(HV_X64_MSR_TPR, val); 86 break; 87 default: 88 native_apic_mem_write(reg, val); 89 } 90 } 91 92 static void hv_apic_eoi_write(void) 93 { 94 struct hv_vp_assist_page *hvp = hv_vp_assist_page[smp_processor_id()]; 95 96 if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1)) 97 return; 98 99 wrmsrq(HV_X64_MSR_EOI, APIC_EOI_ACK); 100 } 101 102 static bool cpu_is_self(int cpu) 103 { 104 return cpu == smp_processor_id(); 105 } 106 107 /* 108 * IPI implementation on Hyper-V. 109 */ 110 static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector, 111 bool exclude_self) 112 { 113 struct hv_send_ipi_ex *ipi_arg; 114 unsigned long flags; 115 int nr_bank = 0; 116 u64 status = HV_STATUS_INVALID_PARAMETER; 117 118 if (!(ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED)) 119 return false; 120 121 local_irq_save(flags); 122 ipi_arg = *this_cpu_ptr(hyperv_pcpu_input_arg); 123 124 if (unlikely(!ipi_arg)) 125 goto ipi_mask_ex_done; 126 127 ipi_arg->vector = vector; 128 ipi_arg->reserved = 0; 129 ipi_arg->vp_set.valid_bank_mask = 0; 130 131 /* 132 * Use HV_GENERIC_SET_ALL and avoid converting cpumask to VP_SET 133 * when the IPI is sent to all currently present CPUs. 134 */ 135 if (!cpumask_equal(mask, cpu_present_mask) || exclude_self) { 136 ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K; 137 138 nr_bank = cpumask_to_vpset_skip(&ipi_arg->vp_set, mask, 139 exclude_self ? cpu_is_self : NULL); 140 141 /* 142 * 'nr_bank <= 0' means some CPUs in cpumask can't be 143 * represented in VP_SET. Return an error and fall back to 144 * native (architectural) method of sending IPIs. 145 */ 146 if (nr_bank <= 0) 147 goto ipi_mask_ex_done; 148 } else { 149 ipi_arg->vp_set.format = HV_GENERIC_SET_ALL; 150 } 151 152 /* 153 * For this hypercall, Hyper-V treats the valid_bank_mask field 154 * of ipi_arg->vp_set as part of the fixed size input header. 155 * So the variable input header size is equal to nr_bank. 156 */ 157 status = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank, 158 ipi_arg, NULL); 159 160 ipi_mask_ex_done: 161 local_irq_restore(flags); 162 return hv_result_success(status); 163 } 164 165 static bool __send_ipi_mask(const struct cpumask *mask, int vector, 166 bool exclude_self) 167 { 168 int cur_cpu, vcpu, this_cpu = smp_processor_id(); 169 struct hv_send_ipi ipi_arg; 170 u64 status; 171 unsigned int weight; 172 173 trace_hyperv_send_ipi_mask(mask, vector); 174 175 weight = cpumask_weight(mask); 176 177 /* 178 * Do nothing if 179 * 1. the mask is empty 180 * 2. the mask only contains self when exclude_self is true 181 */ 182 if (weight == 0 || 183 (exclude_self && weight == 1 && cpumask_test_cpu(this_cpu, mask))) 184 return true; 185 186 /* A fully enlightened TDX VM uses GHCI rather than hv_hypercall_pg. */ 187 if (!hv_hypercall_pg) { 188 if (ms_hyperv.paravisor_present || !hv_isolation_type_tdx()) 189 return false; 190 } 191 192 if (vector < HV_IPI_LOW_VECTOR || vector > HV_IPI_HIGH_VECTOR) 193 return false; 194 195 /* 196 * From the supplied CPU set we need to figure out if we can get away 197 * with cheaper HVCALL_SEND_IPI hypercall. This is possible when the 198 * highest VP number in the set is < 64. As VP numbers are usually in 199 * ascending order and match Linux CPU ids, here is an optimization: 200 * we check the VP number for the highest bit in the supplied set first 201 * so we can quickly find out if using HVCALL_SEND_IPI_EX hypercall is 202 * a must. We will also check all VP numbers when walking the supplied 203 * CPU set to remain correct in all cases. 204 */ 205 if (hv_cpu_number_to_vp_number(cpumask_last(mask)) >= 64) 206 goto do_ex_hypercall; 207 208 ipi_arg.vector = vector; 209 ipi_arg.cpu_mask = 0; 210 211 for_each_cpu(cur_cpu, mask) { 212 if (exclude_self && cur_cpu == this_cpu) 213 continue; 214 vcpu = hv_cpu_number_to_vp_number(cur_cpu); 215 if (vcpu == VP_INVAL) 216 return false; 217 218 /* 219 * This particular version of the IPI hypercall can 220 * only target up to 64 CPUs. 221 */ 222 if (vcpu >= 64) 223 goto do_ex_hypercall; 224 225 __set_bit(vcpu, (unsigned long *)&ipi_arg.cpu_mask); 226 } 227 228 status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, ipi_arg.vector, 229 ipi_arg.cpu_mask); 230 return hv_result_success(status); 231 232 do_ex_hypercall: 233 return __send_ipi_mask_ex(mask, vector, exclude_self); 234 } 235 236 static bool __send_ipi_one(int cpu, int vector) 237 { 238 int vp = hv_cpu_number_to_vp_number(cpu); 239 u64 status; 240 241 trace_hyperv_send_ipi_one(cpu, vector); 242 243 if (vp == VP_INVAL) 244 return false; 245 246 /* A fully enlightened TDX VM uses GHCI rather than hv_hypercall_pg. */ 247 if (!hv_hypercall_pg) { 248 if (ms_hyperv.paravisor_present || !hv_isolation_type_tdx()) 249 return false; 250 } 251 252 if (vector < HV_IPI_LOW_VECTOR || vector > HV_IPI_HIGH_VECTOR) 253 return false; 254 255 if (vp >= 64) 256 return __send_ipi_mask_ex(cpumask_of(cpu), vector, false); 257 258 status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, vector, BIT_ULL(vp)); 259 return hv_result_success(status); 260 } 261 262 static void hv_send_ipi(int cpu, int vector) 263 { 264 if (!__send_ipi_one(cpu, vector)) 265 orig_apic.send_IPI(cpu, vector); 266 } 267 268 static void hv_send_ipi_mask(const struct cpumask *mask, int vector) 269 { 270 if (!__send_ipi_mask(mask, vector, false)) 271 orig_apic.send_IPI_mask(mask, vector); 272 } 273 274 static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector) 275 { 276 if (!__send_ipi_mask(mask, vector, true)) 277 orig_apic.send_IPI_mask_allbutself(mask, vector); 278 } 279 280 static void hv_send_ipi_allbutself(int vector) 281 { 282 hv_send_ipi_mask_allbutself(cpu_online_mask, vector); 283 } 284 285 static void hv_send_ipi_all(int vector) 286 { 287 if (!__send_ipi_mask(cpu_online_mask, vector, false)) 288 orig_apic.send_IPI_all(vector); 289 } 290 291 static void hv_send_ipi_self(int vector) 292 { 293 if (!__send_ipi_one(smp_processor_id(), vector)) 294 orig_apic.send_IPI_self(vector); 295 } 296 297 void __init hv_apic_init(void) 298 { 299 if (cc_platform_has(CC_ATTR_SNP_SECURE_AVIC)) 300 return; 301 302 if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) { 303 pr_info("Hyper-V: Using IPI hypercalls\n"); 304 /* 305 * Set the IPI entry points. 306 */ 307 orig_apic = *apic; 308 309 apic_update_callback(send_IPI, hv_send_ipi); 310 apic_update_callback(send_IPI_mask, hv_send_ipi_mask); 311 apic_update_callback(send_IPI_mask_allbutself, hv_send_ipi_mask_allbutself); 312 apic_update_callback(send_IPI_allbutself, hv_send_ipi_allbutself); 313 apic_update_callback(send_IPI_all, hv_send_ipi_all); 314 apic_update_callback(send_IPI_self, hv_send_ipi_self); 315 } 316 317 if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) { 318 pr_info("Hyper-V: Using enlightened APIC (%s mode)", 319 x2apic_enabled() ? "x2apic" : "xapic"); 320 /* 321 * When in x2apic mode, don't use the Hyper-V specific APIC 322 * accessors since the field layout in the ICR register is 323 * different in x2apic mode. Furthermore, the architectural 324 * x2apic MSRs function just as well as the Hyper-V 325 * synthetic APIC MSRs, so there's no benefit in having 326 * separate Hyper-V accessors for x2apic mode. The only 327 * exception is hv_apic_eoi_write, because it benefits from 328 * lazy EOI when available, but the same accessor works for 329 * both xapic and x2apic because the field layout is the same. 330 */ 331 apic_update_callback(eoi, hv_apic_eoi_write); 332 if (!x2apic_enabled()) { 333 apic_update_callback(read, hv_apic_read); 334 apic_update_callback(write, hv_apic_write); 335 apic_update_callback(icr_write, hv_apic_icr_write); 336 apic_update_callback(icr_read, hv_apic_icr_read); 337 } 338 } 339 } 340