1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Support Intel/AMD RAPL energy consumption counters 4 * Copyright (C) 2013 Google, Inc., Stephane Eranian 5 * 6 * Intel RAPL interface is specified in the IA-32 Manual Vol3b 7 * section 14.7.1 (September 2013) 8 * 9 * AMD RAPL interface for Fam17h is described in the public PPR: 10 * https://bugzilla.kernel.org/show_bug.cgi?id=206537 11 * 12 * RAPL provides more controls than just reporting energy consumption 13 * however here we only expose the 3 energy consumption free running 14 * counters (pp0, pkg, dram). 15 * 16 * Each of those counters increments in a power unit defined by the 17 * RAPL_POWER_UNIT MSR. On SandyBridge, this unit is 1/(2^16) Joules 18 * but it can vary. 19 * 20 * Counter to rapl events mappings: 21 * 22 * pp0 counter: consumption of all physical cores (power plane 0) 23 * event: rapl_energy_cores 24 * perf code: 0x1 25 * 26 * pkg counter: consumption of the whole processor package 27 * event: rapl_energy_pkg 28 * perf code: 0x2 29 * 30 * dram counter: consumption of the dram domain (servers only) 31 * event: rapl_energy_dram 32 * perf code: 0x3 33 * 34 * gpu counter: consumption of the builtin-gpu domain (client only) 35 * event: rapl_energy_gpu 36 * perf code: 0x4 37 * 38 * psys counter: consumption of the builtin-psys domain (client only) 39 * event: rapl_energy_psys 40 * perf code: 0x5 41 * 42 * We manage those counters as free running (read-only). They may be 43 * use simultaneously by other tools, such as turbostat. 44 * 45 * The events only support system-wide mode counting. There is no 46 * sampling support because it does not make sense and is not 47 * supported by the RAPL hardware. 48 * 49 * Because we want to avoid floating-point operations in the kernel, 50 * the events are all reported in fixed point arithmetic (32.32). 51 * Tools must adjust the counts to convert them to Watts using 52 * the duration of the measurement. Tools may use a function such as 53 * ldexp(raw_count, -32); 54 */ 55 56 #define pr_fmt(fmt) "RAPL PMU: " fmt 57 58 #include <linux/module.h> 59 #include <linux/slab.h> 60 #include <linux/perf_event.h> 61 #include <linux/nospec.h> 62 #include <asm/cpu_device_id.h> 63 #include <asm/intel-family.h> 64 #include "perf_event.h" 65 #include "probe.h" 66 67 MODULE_DESCRIPTION("Support Intel/AMD RAPL energy consumption counters"); 68 MODULE_LICENSE("GPL"); 69 70 /* 71 * RAPL energy status counters 72 */ 73 enum perf_rapl_events { 74 PERF_RAPL_PP0 = 0, /* all cores */ 75 PERF_RAPL_PKG, /* entire package */ 76 PERF_RAPL_RAM, /* DRAM */ 77 PERF_RAPL_PP1, /* gpu */ 78 PERF_RAPL_PSYS, /* psys */ 79 80 PERF_RAPL_MAX, 81 NR_RAPL_DOMAINS = PERF_RAPL_MAX, 82 }; 83 84 static const char *const rapl_domain_names[NR_RAPL_DOMAINS] __initconst = { 85 "pp0-core", 86 "package", 87 "dram", 88 "pp1-gpu", 89 "psys", 90 }; 91 92 /* 93 * event code: LSB 8 bits, passed in attr->config 94 * any other bit is reserved 95 */ 96 #define RAPL_EVENT_MASK 0xFFULL 97 #define RAPL_CNTR_WIDTH 32 98 99 #define RAPL_EVENT_ATTR_STR(_name, v, str) \ 100 static struct perf_pmu_events_attr event_attr_##v = { \ 101 .attr = __ATTR(_name, 0444, perf_event_sysfs_show, NULL), \ 102 .id = 0, \ 103 .event_str = str, \ 104 }; 105 106 /* 107 * RAPL Package energy counter scope: 108 * 1. AMD/HYGON platforms have a per-PKG package energy counter 109 * 2. For Intel platforms 110 * 2.1. CLX-AP is multi-die and its RAPL MSRs are die-scope 111 * 2.2. Other Intel platforms are single die systems so the scope can be 112 * considered as either pkg-scope or die-scope, and we are considering 113 * them as die-scope. 114 */ 115 #define rapl_pmu_is_pkg_scope() \ 116 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || \ 117 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 118 119 struct rapl_pmu { 120 raw_spinlock_t lock; 121 int n_active; 122 int cpu; 123 struct list_head active_list; 124 struct pmu *pmu; 125 ktime_t timer_interval; 126 struct hrtimer hrtimer; 127 }; 128 129 struct rapl_pmus { 130 struct pmu pmu; 131 unsigned int nr_rapl_pmu; 132 struct rapl_pmu *pmus[] __counted_by(nr_rapl_pmu); 133 }; 134 135 enum rapl_unit_quirk { 136 RAPL_UNIT_QUIRK_NONE, 137 RAPL_UNIT_QUIRK_INTEL_HSW, 138 RAPL_UNIT_QUIRK_INTEL_SPR, 139 }; 140 141 struct rapl_model { 142 struct perf_msr *rapl_msrs; 143 unsigned long events; 144 unsigned int msr_power_unit; 145 enum rapl_unit_quirk unit_quirk; 146 }; 147 148 /* 1/2^hw_unit Joule */ 149 static int rapl_hw_unit[NR_RAPL_DOMAINS] __read_mostly; 150 static struct rapl_pmus *rapl_pmus; 151 static unsigned int rapl_cntr_mask; 152 static u64 rapl_timer_ms; 153 static struct perf_msr *rapl_msrs; 154 155 /* 156 * Helper functions to get the correct topology macros according to the 157 * RAPL PMU scope. 158 */ 159 static inline unsigned int get_rapl_pmu_idx(int cpu) 160 { 161 return rapl_pmu_is_pkg_scope() ? topology_logical_package_id(cpu) : 162 topology_logical_die_id(cpu); 163 } 164 165 static inline const struct cpumask *get_rapl_pmu_cpumask(int cpu) 166 { 167 return rapl_pmu_is_pkg_scope() ? topology_core_cpumask(cpu) : 168 topology_die_cpumask(cpu); 169 } 170 171 static inline struct rapl_pmu *cpu_to_rapl_pmu(unsigned int cpu) 172 { 173 unsigned int rapl_pmu_idx = get_rapl_pmu_idx(cpu); 174 175 /* 176 * The unsigned check also catches the '-1' return value for non 177 * existent mappings in the topology map. 178 */ 179 return rapl_pmu_idx < rapl_pmus->nr_rapl_pmu ? rapl_pmus->pmus[rapl_pmu_idx] : NULL; 180 } 181 182 static inline u64 rapl_read_counter(struct perf_event *event) 183 { 184 u64 raw; 185 rdmsrl(event->hw.event_base, raw); 186 return raw; 187 } 188 189 static inline u64 rapl_scale(u64 v, int cfg) 190 { 191 if (cfg > NR_RAPL_DOMAINS) { 192 pr_warn("Invalid domain %d, failed to scale data\n", cfg); 193 return v; 194 } 195 /* 196 * scale delta to smallest unit (1/2^32) 197 * users must then scale back: count * 1/(1e9*2^32) to get Joules 198 * or use ldexp(count, -32). 199 * Watts = Joules/Time delta 200 */ 201 return v << (32 - rapl_hw_unit[cfg - 1]); 202 } 203 204 static u64 rapl_event_update(struct perf_event *event) 205 { 206 struct hw_perf_event *hwc = &event->hw; 207 u64 prev_raw_count, new_raw_count; 208 s64 delta, sdelta; 209 int shift = RAPL_CNTR_WIDTH; 210 211 prev_raw_count = local64_read(&hwc->prev_count); 212 do { 213 rdmsrl(event->hw.event_base, new_raw_count); 214 } while (!local64_try_cmpxchg(&hwc->prev_count, 215 &prev_raw_count, new_raw_count)); 216 217 /* 218 * Now we have the new raw value and have updated the prev 219 * timestamp already. We can now calculate the elapsed delta 220 * (event-)time and add that to the generic event. 221 * 222 * Careful, not all hw sign-extends above the physical width 223 * of the count. 224 */ 225 delta = (new_raw_count << shift) - (prev_raw_count << shift); 226 delta >>= shift; 227 228 sdelta = rapl_scale(delta, event->hw.config); 229 230 local64_add(sdelta, &event->count); 231 232 return new_raw_count; 233 } 234 235 static void rapl_start_hrtimer(struct rapl_pmu *pmu) 236 { 237 hrtimer_start(&pmu->hrtimer, pmu->timer_interval, 238 HRTIMER_MODE_REL_PINNED); 239 } 240 241 static enum hrtimer_restart rapl_hrtimer_handle(struct hrtimer *hrtimer) 242 { 243 struct rapl_pmu *pmu = container_of(hrtimer, struct rapl_pmu, hrtimer); 244 struct perf_event *event; 245 unsigned long flags; 246 247 if (!pmu->n_active) 248 return HRTIMER_NORESTART; 249 250 raw_spin_lock_irqsave(&pmu->lock, flags); 251 252 list_for_each_entry(event, &pmu->active_list, active_entry) 253 rapl_event_update(event); 254 255 raw_spin_unlock_irqrestore(&pmu->lock, flags); 256 257 hrtimer_forward_now(hrtimer, pmu->timer_interval); 258 259 return HRTIMER_RESTART; 260 } 261 262 static void rapl_hrtimer_init(struct rapl_pmu *pmu) 263 { 264 struct hrtimer *hr = &pmu->hrtimer; 265 266 hrtimer_init(hr, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 267 hr->function = rapl_hrtimer_handle; 268 } 269 270 static void __rapl_pmu_event_start(struct rapl_pmu *pmu, 271 struct perf_event *event) 272 { 273 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) 274 return; 275 276 event->hw.state = 0; 277 278 list_add_tail(&event->active_entry, &pmu->active_list); 279 280 local64_set(&event->hw.prev_count, rapl_read_counter(event)); 281 282 pmu->n_active++; 283 if (pmu->n_active == 1) 284 rapl_start_hrtimer(pmu); 285 } 286 287 static void rapl_pmu_event_start(struct perf_event *event, int mode) 288 { 289 struct rapl_pmu *pmu = event->pmu_private; 290 unsigned long flags; 291 292 raw_spin_lock_irqsave(&pmu->lock, flags); 293 __rapl_pmu_event_start(pmu, event); 294 raw_spin_unlock_irqrestore(&pmu->lock, flags); 295 } 296 297 static void rapl_pmu_event_stop(struct perf_event *event, int mode) 298 { 299 struct rapl_pmu *pmu = event->pmu_private; 300 struct hw_perf_event *hwc = &event->hw; 301 unsigned long flags; 302 303 raw_spin_lock_irqsave(&pmu->lock, flags); 304 305 /* mark event as deactivated and stopped */ 306 if (!(hwc->state & PERF_HES_STOPPED)) { 307 WARN_ON_ONCE(pmu->n_active <= 0); 308 pmu->n_active--; 309 if (pmu->n_active == 0) 310 hrtimer_cancel(&pmu->hrtimer); 311 312 list_del(&event->active_entry); 313 314 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); 315 hwc->state |= PERF_HES_STOPPED; 316 } 317 318 /* check if update of sw counter is necessary */ 319 if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { 320 /* 321 * Drain the remaining delta count out of a event 322 * that we are disabling: 323 */ 324 rapl_event_update(event); 325 hwc->state |= PERF_HES_UPTODATE; 326 } 327 328 raw_spin_unlock_irqrestore(&pmu->lock, flags); 329 } 330 331 static int rapl_pmu_event_add(struct perf_event *event, int mode) 332 { 333 struct rapl_pmu *pmu = event->pmu_private; 334 struct hw_perf_event *hwc = &event->hw; 335 unsigned long flags; 336 337 raw_spin_lock_irqsave(&pmu->lock, flags); 338 339 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; 340 341 if (mode & PERF_EF_START) 342 __rapl_pmu_event_start(pmu, event); 343 344 raw_spin_unlock_irqrestore(&pmu->lock, flags); 345 346 return 0; 347 } 348 349 static void rapl_pmu_event_del(struct perf_event *event, int flags) 350 { 351 rapl_pmu_event_stop(event, PERF_EF_UPDATE); 352 } 353 354 static int rapl_pmu_event_init(struct perf_event *event) 355 { 356 u64 cfg = event->attr.config & RAPL_EVENT_MASK; 357 int bit, ret = 0; 358 struct rapl_pmu *pmu; 359 360 /* only look at RAPL events */ 361 if (event->attr.type != rapl_pmus->pmu.type) 362 return -ENOENT; 363 364 /* check only supported bits are set */ 365 if (event->attr.config & ~RAPL_EVENT_MASK) 366 return -EINVAL; 367 368 if (event->cpu < 0) 369 return -EINVAL; 370 371 if (!cfg || cfg >= NR_RAPL_DOMAINS + 1) 372 return -EINVAL; 373 374 cfg = array_index_nospec((long)cfg, NR_RAPL_DOMAINS + 1); 375 bit = cfg - 1; 376 377 /* check event supported */ 378 if (!(rapl_cntr_mask & (1 << bit))) 379 return -EINVAL; 380 381 /* unsupported modes and filters */ 382 if (event->attr.sample_period) /* no sampling */ 383 return -EINVAL; 384 385 /* must be done before validate_group */ 386 pmu = cpu_to_rapl_pmu(event->cpu); 387 if (!pmu) 388 return -EINVAL; 389 event->pmu_private = pmu; 390 event->hw.event_base = rapl_msrs[bit].msr; 391 event->hw.config = cfg; 392 event->hw.idx = bit; 393 394 return ret; 395 } 396 397 static void rapl_pmu_event_read(struct perf_event *event) 398 { 399 rapl_event_update(event); 400 } 401 402 RAPL_EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01"); 403 RAPL_EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02"); 404 RAPL_EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03"); 405 RAPL_EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=0x04"); 406 RAPL_EVENT_ATTR_STR(energy-psys, rapl_psys, "event=0x05"); 407 408 RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules"); 409 RAPL_EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules"); 410 RAPL_EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules"); 411 RAPL_EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules"); 412 RAPL_EVENT_ATTR_STR(energy-psys.unit, rapl_psys_unit, "Joules"); 413 414 /* 415 * we compute in 0.23 nJ increments regardless of MSR 416 */ 417 RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10"); 418 RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10"); 419 RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10"); 420 RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10"); 421 RAPL_EVENT_ATTR_STR(energy-psys.scale, rapl_psys_scale, "2.3283064365386962890625e-10"); 422 423 /* 424 * There are no default events, but we need to create 425 * "events" group (with empty attrs) before updating 426 * it with detected events. 427 */ 428 static struct attribute *attrs_empty[] = { 429 NULL, 430 }; 431 432 static struct attribute_group rapl_pmu_events_group = { 433 .name = "events", 434 .attrs = attrs_empty, 435 }; 436 437 PMU_FORMAT_ATTR(event, "config:0-7"); 438 static struct attribute *rapl_formats_attr[] = { 439 &format_attr_event.attr, 440 NULL, 441 }; 442 443 static struct attribute_group rapl_pmu_format_group = { 444 .name = "format", 445 .attrs = rapl_formats_attr, 446 }; 447 448 static const struct attribute_group *rapl_attr_groups[] = { 449 &rapl_pmu_format_group, 450 &rapl_pmu_events_group, 451 NULL, 452 }; 453 454 static struct attribute *rapl_events_cores[] = { 455 EVENT_PTR(rapl_cores), 456 EVENT_PTR(rapl_cores_unit), 457 EVENT_PTR(rapl_cores_scale), 458 NULL, 459 }; 460 461 static struct attribute_group rapl_events_cores_group = { 462 .name = "events", 463 .attrs = rapl_events_cores, 464 }; 465 466 static struct attribute *rapl_events_pkg[] = { 467 EVENT_PTR(rapl_pkg), 468 EVENT_PTR(rapl_pkg_unit), 469 EVENT_PTR(rapl_pkg_scale), 470 NULL, 471 }; 472 473 static struct attribute_group rapl_events_pkg_group = { 474 .name = "events", 475 .attrs = rapl_events_pkg, 476 }; 477 478 static struct attribute *rapl_events_ram[] = { 479 EVENT_PTR(rapl_ram), 480 EVENT_PTR(rapl_ram_unit), 481 EVENT_PTR(rapl_ram_scale), 482 NULL, 483 }; 484 485 static struct attribute_group rapl_events_ram_group = { 486 .name = "events", 487 .attrs = rapl_events_ram, 488 }; 489 490 static struct attribute *rapl_events_gpu[] = { 491 EVENT_PTR(rapl_gpu), 492 EVENT_PTR(rapl_gpu_unit), 493 EVENT_PTR(rapl_gpu_scale), 494 NULL, 495 }; 496 497 static struct attribute_group rapl_events_gpu_group = { 498 .name = "events", 499 .attrs = rapl_events_gpu, 500 }; 501 502 static struct attribute *rapl_events_psys[] = { 503 EVENT_PTR(rapl_psys), 504 EVENT_PTR(rapl_psys_unit), 505 EVENT_PTR(rapl_psys_scale), 506 NULL, 507 }; 508 509 static struct attribute_group rapl_events_psys_group = { 510 .name = "events", 511 .attrs = rapl_events_psys, 512 }; 513 514 static bool test_msr(int idx, void *data) 515 { 516 return test_bit(idx, (unsigned long *) data); 517 } 518 519 /* Only lower 32bits of the MSR represents the energy counter */ 520 #define RAPL_MSR_MASK 0xFFFFFFFF 521 522 static struct perf_msr intel_rapl_msrs[] = { 523 [PERF_RAPL_PP0] = { MSR_PP0_ENERGY_STATUS, &rapl_events_cores_group, test_msr, false, RAPL_MSR_MASK }, 524 [PERF_RAPL_PKG] = { MSR_PKG_ENERGY_STATUS, &rapl_events_pkg_group, test_msr, false, RAPL_MSR_MASK }, 525 [PERF_RAPL_RAM] = { MSR_DRAM_ENERGY_STATUS, &rapl_events_ram_group, test_msr, false, RAPL_MSR_MASK }, 526 [PERF_RAPL_PP1] = { MSR_PP1_ENERGY_STATUS, &rapl_events_gpu_group, test_msr, false, RAPL_MSR_MASK }, 527 [PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, &rapl_events_psys_group, test_msr, false, RAPL_MSR_MASK }, 528 }; 529 530 static struct perf_msr intel_rapl_spr_msrs[] = { 531 [PERF_RAPL_PP0] = { MSR_PP0_ENERGY_STATUS, &rapl_events_cores_group, test_msr, false, RAPL_MSR_MASK }, 532 [PERF_RAPL_PKG] = { MSR_PKG_ENERGY_STATUS, &rapl_events_pkg_group, test_msr, false, RAPL_MSR_MASK }, 533 [PERF_RAPL_RAM] = { MSR_DRAM_ENERGY_STATUS, &rapl_events_ram_group, test_msr, false, RAPL_MSR_MASK }, 534 [PERF_RAPL_PP1] = { MSR_PP1_ENERGY_STATUS, &rapl_events_gpu_group, test_msr, false, RAPL_MSR_MASK }, 535 [PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, &rapl_events_psys_group, test_msr, true, RAPL_MSR_MASK }, 536 }; 537 538 /* 539 * Force to PERF_RAPL_MAX size due to: 540 * - perf_msr_probe(PERF_RAPL_MAX) 541 * - want to use same event codes across both architectures 542 */ 543 static struct perf_msr amd_rapl_msrs[] = { 544 [PERF_RAPL_PP0] = { 0, &rapl_events_cores_group, NULL, false, 0 }, 545 [PERF_RAPL_PKG] = { MSR_AMD_PKG_ENERGY_STATUS, &rapl_events_pkg_group, test_msr, false, RAPL_MSR_MASK }, 546 [PERF_RAPL_RAM] = { 0, &rapl_events_ram_group, NULL, false, 0 }, 547 [PERF_RAPL_PP1] = { 0, &rapl_events_gpu_group, NULL, false, 0 }, 548 [PERF_RAPL_PSYS] = { 0, &rapl_events_psys_group, NULL, false, 0 }, 549 }; 550 551 static int rapl_check_hw_unit(struct rapl_model *rm) 552 { 553 u64 msr_rapl_power_unit_bits; 554 int i; 555 556 /* protect rdmsrl() to handle virtualization */ 557 if (rdmsrl_safe(rm->msr_power_unit, &msr_rapl_power_unit_bits)) 558 return -1; 559 for (i = 0; i < NR_RAPL_DOMAINS; i++) 560 rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL; 561 562 switch (rm->unit_quirk) { 563 /* 564 * DRAM domain on HSW server and KNL has fixed energy unit which can be 565 * different than the unit from power unit MSR. See 566 * "Intel Xeon Processor E5-1600 and E5-2600 v3 Product Families, V2 567 * of 2. Datasheet, September 2014, Reference Number: 330784-001 " 568 */ 569 case RAPL_UNIT_QUIRK_INTEL_HSW: 570 rapl_hw_unit[PERF_RAPL_RAM] = 16; 571 break; 572 /* SPR uses a fixed energy unit for Psys domain. */ 573 case RAPL_UNIT_QUIRK_INTEL_SPR: 574 rapl_hw_unit[PERF_RAPL_PSYS] = 0; 575 break; 576 default: 577 break; 578 } 579 580 581 /* 582 * Calculate the timer rate: 583 * Use reference of 200W for scaling the timeout to avoid counter 584 * overflows. 200W = 200 Joules/sec 585 * Divide interval by 2 to avoid lockstep (2 * 100) 586 * if hw unit is 32, then we use 2 ms 1/200/2 587 */ 588 rapl_timer_ms = 2; 589 if (rapl_hw_unit[0] < 32) { 590 rapl_timer_ms = (1000 / (2 * 100)); 591 rapl_timer_ms *= (1ULL << (32 - rapl_hw_unit[0] - 1)); 592 } 593 return 0; 594 } 595 596 static void __init rapl_advertise(void) 597 { 598 int i; 599 600 pr_info("API unit is 2^-32 Joules, %d fixed counters, %llu ms ovfl timer\n", 601 hweight32(rapl_cntr_mask), rapl_timer_ms); 602 603 for (i = 0; i < NR_RAPL_DOMAINS; i++) { 604 if (rapl_cntr_mask & (1 << i)) { 605 pr_info("hw unit of domain %s 2^-%d Joules\n", 606 rapl_domain_names[i], rapl_hw_unit[i]); 607 } 608 } 609 } 610 611 static void cleanup_rapl_pmus(void) 612 { 613 int i; 614 615 for (i = 0; i < rapl_pmus->nr_rapl_pmu; i++) 616 kfree(rapl_pmus->pmus[i]); 617 kfree(rapl_pmus); 618 } 619 620 static const struct attribute_group *rapl_attr_update[] = { 621 &rapl_events_cores_group, 622 &rapl_events_pkg_group, 623 &rapl_events_ram_group, 624 &rapl_events_gpu_group, 625 &rapl_events_psys_group, 626 NULL, 627 }; 628 629 static int __init init_rapl_pmu(void) 630 { 631 struct rapl_pmu *pmu; 632 int idx; 633 634 for (idx = 0; idx < rapl_pmus->nr_rapl_pmu; idx++) { 635 pmu = kzalloc(sizeof(*pmu), GFP_KERNEL); 636 if (!pmu) 637 goto free; 638 639 raw_spin_lock_init(&pmu->lock); 640 INIT_LIST_HEAD(&pmu->active_list); 641 pmu->pmu = &rapl_pmus->pmu; 642 pmu->timer_interval = ms_to_ktime(rapl_timer_ms); 643 rapl_hrtimer_init(pmu); 644 645 rapl_pmus->pmus[idx] = pmu; 646 } 647 648 return 0; 649 free: 650 for (; idx > 0; idx--) 651 kfree(rapl_pmus->pmus[idx - 1]); 652 return -ENOMEM; 653 } 654 655 static int __init init_rapl_pmus(void) 656 { 657 int nr_rapl_pmu = topology_max_packages(); 658 int rapl_pmu_scope = PERF_PMU_SCOPE_PKG; 659 660 if (!rapl_pmu_is_pkg_scope()) { 661 nr_rapl_pmu *= topology_max_dies_per_package(); 662 rapl_pmu_scope = PERF_PMU_SCOPE_DIE; 663 } 664 665 rapl_pmus = kzalloc(struct_size(rapl_pmus, pmus, nr_rapl_pmu), GFP_KERNEL); 666 if (!rapl_pmus) 667 return -ENOMEM; 668 669 rapl_pmus->nr_rapl_pmu = nr_rapl_pmu; 670 rapl_pmus->pmu.attr_groups = rapl_attr_groups; 671 rapl_pmus->pmu.attr_update = rapl_attr_update; 672 rapl_pmus->pmu.task_ctx_nr = perf_invalid_context; 673 rapl_pmus->pmu.event_init = rapl_pmu_event_init; 674 rapl_pmus->pmu.add = rapl_pmu_event_add; 675 rapl_pmus->pmu.del = rapl_pmu_event_del; 676 rapl_pmus->pmu.start = rapl_pmu_event_start; 677 rapl_pmus->pmu.stop = rapl_pmu_event_stop; 678 rapl_pmus->pmu.read = rapl_pmu_event_read; 679 rapl_pmus->pmu.scope = rapl_pmu_scope; 680 rapl_pmus->pmu.module = THIS_MODULE; 681 rapl_pmus->pmu.capabilities = PERF_PMU_CAP_NO_EXCLUDE; 682 683 return init_rapl_pmu(); 684 } 685 686 static struct rapl_model model_snb = { 687 .events = BIT(PERF_RAPL_PP0) | 688 BIT(PERF_RAPL_PKG) | 689 BIT(PERF_RAPL_PP1), 690 .msr_power_unit = MSR_RAPL_POWER_UNIT, 691 .rapl_msrs = intel_rapl_msrs, 692 }; 693 694 static struct rapl_model model_snbep = { 695 .events = BIT(PERF_RAPL_PP0) | 696 BIT(PERF_RAPL_PKG) | 697 BIT(PERF_RAPL_RAM), 698 .msr_power_unit = MSR_RAPL_POWER_UNIT, 699 .rapl_msrs = intel_rapl_msrs, 700 }; 701 702 static struct rapl_model model_hsw = { 703 .events = BIT(PERF_RAPL_PP0) | 704 BIT(PERF_RAPL_PKG) | 705 BIT(PERF_RAPL_RAM) | 706 BIT(PERF_RAPL_PP1), 707 .msr_power_unit = MSR_RAPL_POWER_UNIT, 708 .rapl_msrs = intel_rapl_msrs, 709 }; 710 711 static struct rapl_model model_hsx = { 712 .events = BIT(PERF_RAPL_PP0) | 713 BIT(PERF_RAPL_PKG) | 714 BIT(PERF_RAPL_RAM), 715 .unit_quirk = RAPL_UNIT_QUIRK_INTEL_HSW, 716 .msr_power_unit = MSR_RAPL_POWER_UNIT, 717 .rapl_msrs = intel_rapl_msrs, 718 }; 719 720 static struct rapl_model model_knl = { 721 .events = BIT(PERF_RAPL_PKG) | 722 BIT(PERF_RAPL_RAM), 723 .unit_quirk = RAPL_UNIT_QUIRK_INTEL_HSW, 724 .msr_power_unit = MSR_RAPL_POWER_UNIT, 725 .rapl_msrs = intel_rapl_msrs, 726 }; 727 728 static struct rapl_model model_skl = { 729 .events = BIT(PERF_RAPL_PP0) | 730 BIT(PERF_RAPL_PKG) | 731 BIT(PERF_RAPL_RAM) | 732 BIT(PERF_RAPL_PP1) | 733 BIT(PERF_RAPL_PSYS), 734 .msr_power_unit = MSR_RAPL_POWER_UNIT, 735 .rapl_msrs = intel_rapl_msrs, 736 }; 737 738 static struct rapl_model model_spr = { 739 .events = BIT(PERF_RAPL_PP0) | 740 BIT(PERF_RAPL_PKG) | 741 BIT(PERF_RAPL_RAM) | 742 BIT(PERF_RAPL_PSYS), 743 .unit_quirk = RAPL_UNIT_QUIRK_INTEL_SPR, 744 .msr_power_unit = MSR_RAPL_POWER_UNIT, 745 .rapl_msrs = intel_rapl_spr_msrs, 746 }; 747 748 static struct rapl_model model_amd_hygon = { 749 .events = BIT(PERF_RAPL_PKG), 750 .msr_power_unit = MSR_AMD_RAPL_POWER_UNIT, 751 .rapl_msrs = amd_rapl_msrs, 752 }; 753 754 static const struct x86_cpu_id rapl_model_match[] __initconst = { 755 X86_MATCH_FEATURE(X86_FEATURE_RAPL, &model_amd_hygon), 756 X86_MATCH_VFM(INTEL_SANDYBRIDGE, &model_snb), 757 X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &model_snbep), 758 X86_MATCH_VFM(INTEL_IVYBRIDGE, &model_snb), 759 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &model_snbep), 760 X86_MATCH_VFM(INTEL_HASWELL, &model_hsw), 761 X86_MATCH_VFM(INTEL_HASWELL_X, &model_hsx), 762 X86_MATCH_VFM(INTEL_HASWELL_L, &model_hsw), 763 X86_MATCH_VFM(INTEL_HASWELL_G, &model_hsw), 764 X86_MATCH_VFM(INTEL_BROADWELL, &model_hsw), 765 X86_MATCH_VFM(INTEL_BROADWELL_G, &model_hsw), 766 X86_MATCH_VFM(INTEL_BROADWELL_X, &model_hsx), 767 X86_MATCH_VFM(INTEL_BROADWELL_D, &model_hsx), 768 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &model_knl), 769 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &model_knl), 770 X86_MATCH_VFM(INTEL_SKYLAKE_L, &model_skl), 771 X86_MATCH_VFM(INTEL_SKYLAKE, &model_skl), 772 X86_MATCH_VFM(INTEL_SKYLAKE_X, &model_hsx), 773 X86_MATCH_VFM(INTEL_KABYLAKE_L, &model_skl), 774 X86_MATCH_VFM(INTEL_KABYLAKE, &model_skl), 775 X86_MATCH_VFM(INTEL_CANNONLAKE_L, &model_skl), 776 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &model_hsw), 777 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &model_hsw), 778 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &model_hsw), 779 X86_MATCH_VFM(INTEL_ICELAKE_L, &model_skl), 780 X86_MATCH_VFM(INTEL_ICELAKE, &model_skl), 781 X86_MATCH_VFM(INTEL_ICELAKE_D, &model_hsx), 782 X86_MATCH_VFM(INTEL_ICELAKE_X, &model_hsx), 783 X86_MATCH_VFM(INTEL_COMETLAKE_L, &model_skl), 784 X86_MATCH_VFM(INTEL_COMETLAKE, &model_skl), 785 X86_MATCH_VFM(INTEL_TIGERLAKE_L, &model_skl), 786 X86_MATCH_VFM(INTEL_TIGERLAKE, &model_skl), 787 X86_MATCH_VFM(INTEL_ALDERLAKE, &model_skl), 788 X86_MATCH_VFM(INTEL_ALDERLAKE_L, &model_skl), 789 X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &model_skl), 790 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &model_spr), 791 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &model_spr), 792 X86_MATCH_VFM(INTEL_RAPTORLAKE, &model_skl), 793 X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &model_skl), 794 X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &model_skl), 795 X86_MATCH_VFM(INTEL_METEORLAKE, &model_skl), 796 X86_MATCH_VFM(INTEL_METEORLAKE_L, &model_skl), 797 X86_MATCH_VFM(INTEL_ARROWLAKE_H, &model_skl), 798 X86_MATCH_VFM(INTEL_ARROWLAKE, &model_skl), 799 X86_MATCH_VFM(INTEL_LUNARLAKE_M, &model_skl), 800 {}, 801 }; 802 MODULE_DEVICE_TABLE(x86cpu, rapl_model_match); 803 804 static int __init rapl_pmu_init(void) 805 { 806 const struct x86_cpu_id *id; 807 struct rapl_model *rm; 808 int ret; 809 810 id = x86_match_cpu(rapl_model_match); 811 if (!id) 812 return -ENODEV; 813 814 rm = (struct rapl_model *) id->driver_data; 815 816 rapl_msrs = rm->rapl_msrs; 817 818 rapl_cntr_mask = perf_msr_probe(rapl_msrs, PERF_RAPL_MAX, 819 false, (void *) &rm->events); 820 821 ret = rapl_check_hw_unit(rm); 822 if (ret) 823 return ret; 824 825 ret = init_rapl_pmus(); 826 if (ret) 827 return ret; 828 829 ret = perf_pmu_register(&rapl_pmus->pmu, "power", -1); 830 if (ret) 831 goto out; 832 833 rapl_advertise(); 834 return 0; 835 836 out: 837 pr_warn("Initialization failed (%d), disabled\n", ret); 838 cleanup_rapl_pmus(); 839 return ret; 840 } 841 module_init(rapl_pmu_init); 842 843 static void __exit intel_rapl_exit(void) 844 { 845 perf_pmu_unregister(&rapl_pmus->pmu); 846 cleanup_rapl_pmus(); 847 } 848 module_exit(intel_rapl_exit); 849