1 /* 2 * Performance events x86 architecture header 3 * 4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2009 Jaswinder Singh Rajput 7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 10 * Copyright (C) 2009 Google, Inc., Stephane Eranian 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 15 #include <linux/perf_event.h> 16 17 #include <asm/fpu/xstate.h> 18 #include <asm/intel_ds.h> 19 #include <asm/cpu.h> 20 21 /* To enable MSR tracing please use the generic trace points. */ 22 23 /* 24 * | NHM/WSM | SNB | 25 * register ------------------------------- 26 * | HT | no HT | HT | no HT | 27 *----------------------------------------- 28 * offcore | core | core | cpu | core | 29 * lbr_sel | core | core | cpu | core | 30 * ld_lat | cpu | core | cpu | core | 31 *----------------------------------------- 32 * 33 * Given that there is a small number of shared regs, 34 * we can pre-allocate their slot in the per-cpu 35 * per-core reg tables. 36 */ 37 enum extra_reg_type { 38 EXTRA_REG_NONE = -1, /* not used */ 39 40 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ 41 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ 42 EXTRA_REG_LBR = 2, /* lbr_select */ 43 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ 44 EXTRA_REG_FE = 4, /* fe_* */ 45 EXTRA_REG_SNOOP_0 = 5, /* snoop response 0 */ 46 EXTRA_REG_SNOOP_1 = 6, /* snoop response 1 */ 47 48 EXTRA_REG_MAX /* number of entries needed */ 49 }; 50 51 struct event_constraint { 52 union { 53 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 54 u64 idxmsk64; 55 }; 56 u64 code; 57 u64 cmask; 58 int weight; 59 int overlap; 60 int flags; 61 unsigned int size; 62 }; 63 64 static inline bool constraint_match(struct event_constraint *c, u64 ecode) 65 { 66 return ((ecode & c->cmask) - c->code) <= (u64)c->size; 67 } 68 69 #define PERF_ARCH(name, val) \ 70 PERF_X86_EVENT_##name = val, 71 72 /* 73 * struct hw_perf_event.flags flags 74 */ 75 enum { 76 #include "perf_event_flags.h" 77 }; 78 79 #undef PERF_ARCH 80 81 #define PERF_ARCH(name, val) \ 82 static_assert((PERF_X86_EVENT_##name & PERF_EVENT_FLAG_ARCH) == \ 83 PERF_X86_EVENT_##name); 84 85 #include "perf_event_flags.h" 86 87 #undef PERF_ARCH 88 89 static inline bool is_topdown_count(struct perf_event *event) 90 { 91 return event->hw.flags & PERF_X86_EVENT_TOPDOWN; 92 } 93 94 static inline bool is_metric_event(struct perf_event *event) 95 { 96 u64 config = event->attr.config; 97 98 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) && 99 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) && 100 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX); 101 } 102 103 static inline bool is_slots_event(struct perf_event *event) 104 { 105 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS; 106 } 107 108 static inline bool is_topdown_event(struct perf_event *event) 109 { 110 return is_metric_event(event) || is_slots_event(event); 111 } 112 113 static inline bool is_branch_counters_group(struct perf_event *event) 114 { 115 return event->group_leader->hw.flags & PERF_X86_EVENT_BRANCH_COUNTERS; 116 } 117 118 static inline bool is_pebs_counter_event_group(struct perf_event *event) 119 { 120 return event->group_leader->hw.flags & PERF_X86_EVENT_PEBS_CNTR; 121 } 122 123 struct amd_nb { 124 int nb_id; /* NorthBridge id */ 125 int refcnt; /* reference count */ 126 struct perf_event *owners[X86_PMC_IDX_MAX]; 127 struct event_constraint event_constraints[X86_PMC_IDX_MAX]; 128 }; 129 130 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) 131 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60) 132 #define PEBS_OUTPUT_OFFSET 61 133 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET) 134 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET) 135 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD) 136 137 /* 138 * Flags PEBS can handle without an PMI. 139 * 140 * TID can only be handled by flushing at context switch. 141 * REGS_USER can be handled for events limited to ring 3. 142 * 143 */ 144 #define LARGE_PEBS_FLAGS \ 145 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 146 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 147 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 148 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ 149 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \ 150 PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE | \ 151 PERF_SAMPLE_WEIGHT_TYPE) 152 153 #define PEBS_GP_REGS \ 154 ((1ULL << PERF_REG_X86_AX) | \ 155 (1ULL << PERF_REG_X86_BX) | \ 156 (1ULL << PERF_REG_X86_CX) | \ 157 (1ULL << PERF_REG_X86_DX) | \ 158 (1ULL << PERF_REG_X86_DI) | \ 159 (1ULL << PERF_REG_X86_SI) | \ 160 (1ULL << PERF_REG_X86_SP) | \ 161 (1ULL << PERF_REG_X86_BP) | \ 162 (1ULL << PERF_REG_X86_IP) | \ 163 (1ULL << PERF_REG_X86_FLAGS) | \ 164 (1ULL << PERF_REG_X86_R8) | \ 165 (1ULL << PERF_REG_X86_R9) | \ 166 (1ULL << PERF_REG_X86_R10) | \ 167 (1ULL << PERF_REG_X86_R11) | \ 168 (1ULL << PERF_REG_X86_R12) | \ 169 (1ULL << PERF_REG_X86_R13) | \ 170 (1ULL << PERF_REG_X86_R14) | \ 171 (1ULL << PERF_REG_X86_R15)) 172 173 /* 174 * Per register state. 175 */ 176 struct er_account { 177 raw_spinlock_t lock; /* per-core: protect structure */ 178 u64 config; /* extra MSR config */ 179 u64 reg; /* extra MSR number */ 180 atomic_t ref; /* reference count */ 181 }; 182 183 /* 184 * Per core/cpu state 185 * 186 * Used to coordinate shared registers between HT threads or 187 * among events on a single PMU. 188 */ 189 struct intel_shared_regs { 190 struct er_account regs[EXTRA_REG_MAX]; 191 int refcnt; /* per-core: #HT threads */ 192 unsigned core_id; /* per-core: core id */ 193 }; 194 195 enum intel_excl_state_type { 196 INTEL_EXCL_UNUSED = 0, /* counter is unused */ 197 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ 198 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ 199 }; 200 201 struct intel_excl_states { 202 enum intel_excl_state_type state[X86_PMC_IDX_MAX]; 203 bool sched_started; /* true if scheduling has started */ 204 }; 205 206 struct intel_excl_cntrs { 207 raw_spinlock_t lock; 208 209 struct intel_excl_states states[2]; 210 211 union { 212 u16 has_exclusive[2]; 213 u32 exclusive_present; 214 }; 215 216 int refcnt; /* per-core: #HT threads */ 217 unsigned core_id; /* per-core: core id */ 218 }; 219 220 struct x86_perf_task_context; 221 #define MAX_LBR_ENTRIES 32 222 223 enum { 224 LBR_FORMAT_32 = 0x00, 225 LBR_FORMAT_LIP = 0x01, 226 LBR_FORMAT_EIP = 0x02, 227 LBR_FORMAT_EIP_FLAGS = 0x03, 228 LBR_FORMAT_EIP_FLAGS2 = 0x04, 229 LBR_FORMAT_INFO = 0x05, 230 LBR_FORMAT_TIME = 0x06, 231 LBR_FORMAT_INFO2 = 0x07, 232 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_INFO2, 233 }; 234 235 enum { 236 X86_PERF_KFREE_SHARED = 0, 237 X86_PERF_KFREE_EXCL = 1, 238 X86_PERF_KFREE_MAX 239 }; 240 241 struct cpu_hw_events { 242 /* 243 * Generic x86 PMC bits 244 */ 245 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ 246 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 247 unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 248 int enabled; 249 250 int n_events; /* the # of events in the below arrays */ 251 int n_added; /* the # last events in the below arrays; 252 they've never been enabled yet */ 253 int n_txn; /* the # last events in the below arrays; 254 added in the current transaction */ 255 int n_txn_pair; 256 int n_txn_metric; 257 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ 258 u64 tags[X86_PMC_IDX_MAX]; 259 260 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ 261 struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; 262 263 int n_excl; /* the number of exclusive events */ 264 265 unsigned int txn_flags; 266 int is_fake; 267 268 /* 269 * Intel DebugStore bits 270 */ 271 struct debug_store *ds; 272 void *ds_pebs_vaddr; 273 void *ds_bts_vaddr; 274 u64 pebs_enabled; 275 int n_pebs; 276 int n_large_pebs; 277 int n_pebs_via_pt; 278 int pebs_output; 279 280 /* Current super set of events hardware configuration */ 281 u64 pebs_data_cfg; 282 u64 active_pebs_data_cfg; 283 int pebs_record_size; 284 285 /* Intel Fixed counter configuration */ 286 u64 fixed_ctrl_val; 287 u64 active_fixed_ctrl_val; 288 289 /* 290 * Intel LBR bits 291 */ 292 int lbr_users; 293 int lbr_pebs_users; 294 struct perf_branch_stack lbr_stack; 295 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; 296 u64 lbr_counters[MAX_LBR_ENTRIES]; /* branch stack extra */ 297 union { 298 struct er_account *lbr_sel; 299 struct er_account *lbr_ctl; 300 }; 301 u64 br_sel; 302 void *last_task_ctx; 303 int last_log_id; 304 int lbr_select; 305 void *lbr_xsave; 306 307 /* 308 * Intel host/guest exclude bits 309 */ 310 u64 intel_ctrl_guest_mask; 311 u64 intel_ctrl_host_mask; 312 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; 313 314 /* 315 * Intel checkpoint mask 316 */ 317 u64 intel_cp_status; 318 319 /* 320 * manage shared (per-core, per-cpu) registers 321 * used on Intel NHM/WSM/SNB 322 */ 323 struct intel_shared_regs *shared_regs; 324 /* 325 * manage exclusive counter access between hyperthread 326 */ 327 struct event_constraint *constraint_list; /* in enable order */ 328 struct intel_excl_cntrs *excl_cntrs; 329 int excl_thread_id; /* 0 or 1 */ 330 331 /* 332 * SKL TSX_FORCE_ABORT shadow 333 */ 334 u64 tfa_shadow; 335 336 /* 337 * Perf Metrics 338 */ 339 /* number of accepted metrics events */ 340 int n_metric; 341 342 /* 343 * AMD specific bits 344 */ 345 struct amd_nb *amd_nb; 346 int brs_active; /* BRS is enabled */ 347 348 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ 349 u64 perf_ctr_virt_mask; 350 int n_pair; /* Large increment events */ 351 352 void *kfree_on_online[X86_PERF_KFREE_MAX]; 353 354 struct pmu *pmu; 355 }; 356 357 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \ 358 { .idxmsk64 = (n) }, \ 359 .code = (c), \ 360 .size = (e) - (c), \ 361 .cmask = (m), \ 362 .weight = (w), \ 363 .overlap = (o), \ 364 .flags = f, \ 365 } 366 367 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ 368 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f) 369 370 #define EVENT_CONSTRAINT(c, n, m) \ 371 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) 372 373 /* 374 * The constraint_match() function only works for 'simple' event codes 375 * and not for extended (AMD64_EVENTSEL_EVENT) events codes. 376 */ 377 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \ 378 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0) 379 380 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ 381 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ 382 0, PERF_X86_EVENT_EXCL) 383 384 /* 385 * The overlap flag marks event constraints with overlapping counter 386 * masks. This is the case if the counter mask of such an event is not 387 * a subset of any other counter mask of a constraint with an equal or 388 * higher weight, e.g.: 389 * 390 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); 391 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); 392 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); 393 * 394 * The event scheduler may not select the correct counter in the first 395 * cycle because it needs to know which subsequent events will be 396 * scheduled. It may fail to schedule the events then. So we set the 397 * overlap flag for such constraints to give the scheduler a hint which 398 * events to select for counter rescheduling. 399 * 400 * Care must be taken as the rescheduling algorithm is O(n!) which 401 * will increase scheduling cycles for an over-committed system 402 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros 403 * and its counter masks must be kept at a minimum. 404 */ 405 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ 406 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) 407 408 /* 409 * Constraint on the Event code. 410 */ 411 #define INTEL_EVENT_CONSTRAINT(c, n) \ 412 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) 413 414 /* 415 * Constraint on a range of Event codes 416 */ 417 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \ 418 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT) 419 420 /* 421 * Constraint on the Event code + UMask + fixed-mask 422 * 423 * filter mask to validate fixed counter events. 424 * the following filters disqualify for fixed counters: 425 * - inv 426 * - edge 427 * - cnt-mask 428 * - in_tx 429 * - in_tx_checkpointed 430 * The other filters are supported by fixed counters. 431 * The any-thread option is supported starting with v3. 432 */ 433 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) 434 #define FIXED_EVENT_CONSTRAINT(c, n) \ 435 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) 436 437 /* 438 * The special metric counters do not actually exist. They are calculated from 439 * the combination of the FxCtr3 + MSR_PERF_METRICS. 440 * 441 * The special metric counters are mapped to a dummy offset for the scheduler. 442 * The sharing between multiple users of the same metric without multiplexing 443 * is not allowed, even though the hardware supports that in principle. 444 */ 445 446 #define METRIC_EVENT_CONSTRAINT(c, n) \ 447 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \ 448 INTEL_ARCH_EVENT_MASK) 449 450 /* 451 * Constraint on the Event code + UMask 452 */ 453 #define INTEL_UEVENT_CONSTRAINT(c, n) \ 454 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) 455 456 /* Constraint on specific umask bit only + event */ 457 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \ 458 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c)) 459 460 /* Like UEVENT_CONSTRAINT, but match flags too */ 461 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ 462 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) 463 464 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ 465 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ 466 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) 467 468 #define INTEL_PLD_CONSTRAINT(c, n) \ 469 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 470 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) 471 472 #define INTEL_PSD_CONSTRAINT(c, n) \ 473 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 474 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT) 475 476 #define INTEL_PST_CONSTRAINT(c, n) \ 477 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 478 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) 479 480 #define INTEL_HYBRID_LAT_CONSTRAINT(c, n) \ 481 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 482 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID) 483 484 #define INTEL_HYBRID_LDLAT_CONSTRAINT(c, n) \ 485 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 486 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_LD_HSW) 487 488 #define INTEL_HYBRID_STLAT_CONSTRAINT(c, n) \ 489 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 490 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_ST_HSW) 491 492 /* Event constraint, but match on all event flags too. */ 493 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ 494 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 495 496 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ 497 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 498 499 /* Check only flags, but allow all event/umask */ 500 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ 501 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) 502 503 /* Check flags and event code, and set the HSW store flag */ 504 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ 505 __EVENT_CONSTRAINT(code, n, \ 506 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 507 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 508 509 /* Check flags and event code, and set the HSW load flag */ 510 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ 511 __EVENT_CONSTRAINT(code, n, \ 512 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 513 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 514 515 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \ 516 __EVENT_CONSTRAINT_RANGE(code, end, n, \ 517 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 518 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 519 520 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ 521 __EVENT_CONSTRAINT(code, n, \ 522 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 523 HWEIGHT(n), 0, \ 524 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 525 526 /* Check flags and event code/umask, and set the HSW store flag */ 527 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ 528 __EVENT_CONSTRAINT(code, n, \ 529 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 530 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 531 532 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ 533 __EVENT_CONSTRAINT(code, n, \ 534 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 535 HWEIGHT(n), 0, \ 536 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) 537 538 /* Check flags and event code/umask, and set the HSW load flag */ 539 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ 540 __EVENT_CONSTRAINT(code, n, \ 541 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 542 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 543 544 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ 545 __EVENT_CONSTRAINT(code, n, \ 546 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 547 HWEIGHT(n), 0, \ 548 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 549 550 /* Check flags and event code/umask, and set the HSW N/A flag */ 551 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ 552 __EVENT_CONSTRAINT(code, n, \ 553 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 554 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) 555 556 557 /* 558 * We define the end marker as having a weight of -1 559 * to enable blacklisting of events using a counter bitmask 560 * of zero and thus a weight of zero. 561 * The end marker has a weight that cannot possibly be 562 * obtained from counting the bits in the bitmask. 563 */ 564 #define EVENT_CONSTRAINT_END { .weight = -1 } 565 566 /* 567 * Check for end marker with weight == -1 568 */ 569 #define for_each_event_constraint(e, c) \ 570 for ((e) = (c); (e)->weight != -1; (e)++) 571 572 /* 573 * Extra registers for specific events. 574 * 575 * Some events need large masks and require external MSRs. 576 * Those extra MSRs end up being shared for all events on 577 * a PMU and sometimes between PMU of sibling HT threads. 578 * In either case, the kernel needs to handle conflicting 579 * accesses to those extra, shared, regs. The data structure 580 * to manage those registers is stored in cpu_hw_event. 581 */ 582 struct extra_reg { 583 unsigned int event; 584 unsigned int msr; 585 u64 config_mask; 586 u64 valid_mask; 587 int idx; /* per_xxx->regs[] reg index */ 588 bool extra_msr_access; 589 }; 590 591 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ 592 .event = (e), \ 593 .msr = (ms), \ 594 .config_mask = (m), \ 595 .valid_mask = (vm), \ 596 .idx = EXTRA_REG_##i, \ 597 .extra_msr_access = true, \ 598 } 599 600 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ 601 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) 602 603 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ 604 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ 605 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) 606 607 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ 608 INTEL_UEVENT_EXTRA_REG(c, \ 609 MSR_PEBS_LD_LAT_THRESHOLD, \ 610 0xffff, \ 611 LDLAT) 612 613 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) 614 615 union perf_capabilities { 616 struct { 617 u64 lbr_format:6; 618 u64 pebs_trap:1; 619 u64 pebs_arch_reg:1; 620 u64 pebs_format:4; 621 u64 smm_freeze:1; 622 /* 623 * PMU supports separate counter range for writing 624 * values > 32bit. 625 */ 626 u64 full_width_write:1; 627 u64 pebs_baseline:1; 628 u64 perf_metrics:1; 629 u64 pebs_output_pt_available:1; 630 u64 pebs_timing_info:1; 631 u64 anythread_deprecated:1; 632 u64 rdpmc_metrics_clear:1; 633 }; 634 u64 capabilities; 635 }; 636 637 struct x86_pmu_quirk { 638 struct x86_pmu_quirk *next; 639 void (*func)(void); 640 }; 641 642 union x86_pmu_config { 643 struct { 644 u64 event:8, 645 umask:8, 646 usr:1, 647 os:1, 648 edge:1, 649 pc:1, 650 interrupt:1, 651 __reserved1:1, 652 en:1, 653 inv:1, 654 cmask:8, 655 event2:4, 656 __reserved2:4, 657 go:1, 658 ho:1; 659 } bits; 660 u64 value; 661 }; 662 663 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value 664 665 enum { 666 x86_lbr_exclusive_lbr, 667 x86_lbr_exclusive_bts, 668 x86_lbr_exclusive_pt, 669 x86_lbr_exclusive_max, 670 }; 671 672 #define PERF_PEBS_DATA_SOURCE_MAX 0x100 673 #define PERF_PEBS_DATA_SOURCE_MASK (PERF_PEBS_DATA_SOURCE_MAX - 1) 674 #define PERF_PEBS_DATA_SOURCE_GRT_MAX 0x10 675 #define PERF_PEBS_DATA_SOURCE_GRT_MASK (PERF_PEBS_DATA_SOURCE_GRT_MAX - 1) 676 677 #define X86_HYBRID_PMU_ATOM_IDX 0 678 #define X86_HYBRID_PMU_CORE_IDX 1 679 #define X86_HYBRID_PMU_TINY_IDX 2 680 681 enum hybrid_pmu_type { 682 not_hybrid, 683 hybrid_small = BIT(X86_HYBRID_PMU_ATOM_IDX), 684 hybrid_big = BIT(X86_HYBRID_PMU_CORE_IDX), 685 hybrid_tiny = BIT(X86_HYBRID_PMU_TINY_IDX), 686 687 /* The belows are only used for matching */ 688 hybrid_big_small = hybrid_big | hybrid_small, 689 hybrid_small_tiny = hybrid_small | hybrid_tiny, 690 hybrid_big_small_tiny = hybrid_big | hybrid_small_tiny, 691 }; 692 693 struct x86_hybrid_pmu { 694 struct pmu pmu; 695 const char *name; 696 enum hybrid_pmu_type pmu_type; 697 cpumask_t supported_cpus; 698 union perf_capabilities intel_cap; 699 u64 intel_ctrl; 700 u64 pebs_events_mask; 701 u64 config_mask; 702 union { 703 u64 cntr_mask64; 704 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 705 }; 706 union { 707 u64 fixed_cntr_mask64; 708 unsigned long fixed_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 709 }; 710 struct event_constraint unconstrained; 711 712 u64 hw_cache_event_ids 713 [PERF_COUNT_HW_CACHE_MAX] 714 [PERF_COUNT_HW_CACHE_OP_MAX] 715 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 716 u64 hw_cache_extra_regs 717 [PERF_COUNT_HW_CACHE_MAX] 718 [PERF_COUNT_HW_CACHE_OP_MAX] 719 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 720 struct event_constraint *event_constraints; 721 struct event_constraint *pebs_constraints; 722 struct extra_reg *extra_regs; 723 724 unsigned int late_ack :1, 725 mid_ack :1, 726 enabled_ack :1; 727 728 u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX]; 729 }; 730 731 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu) 732 { 733 return container_of(pmu, struct x86_hybrid_pmu, pmu); 734 } 735 736 extern struct static_key_false perf_is_hybrid; 737 #define is_hybrid() static_branch_unlikely(&perf_is_hybrid) 738 739 #define hybrid(_pmu, _field) \ 740 (*({ \ 741 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \ 742 \ 743 if (is_hybrid() && (_pmu)) \ 744 __Fp = &hybrid_pmu(_pmu)->_field; \ 745 \ 746 __Fp; \ 747 })) 748 749 #define hybrid_var(_pmu, _var) \ 750 (*({ \ 751 typeof(&_var) __Fp = &_var; \ 752 \ 753 if (is_hybrid() && (_pmu)) \ 754 __Fp = &hybrid_pmu(_pmu)->_var; \ 755 \ 756 __Fp; \ 757 })) 758 759 #define hybrid_bit(_pmu, _field) \ 760 ({ \ 761 bool __Fp = x86_pmu._field; \ 762 \ 763 if (is_hybrid() && (_pmu)) \ 764 __Fp = hybrid_pmu(_pmu)->_field; \ 765 \ 766 __Fp; \ 767 }) 768 769 /* 770 * struct x86_pmu - generic x86 pmu 771 */ 772 struct x86_pmu { 773 /* 774 * Generic x86 PMC bits 775 */ 776 const char *name; 777 int version; 778 int (*handle_irq)(struct pt_regs *); 779 void (*disable_all)(void); 780 void (*enable_all)(int added); 781 void (*enable)(struct perf_event *); 782 void (*disable)(struct perf_event *); 783 void (*assign)(struct perf_event *event, int idx); 784 void (*add)(struct perf_event *); 785 void (*del)(struct perf_event *); 786 void (*read)(struct perf_event *event); 787 int (*set_period)(struct perf_event *event); 788 u64 (*update)(struct perf_event *event); 789 int (*hw_config)(struct perf_event *event); 790 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); 791 void (*late_setup)(void); 792 unsigned eventsel; 793 unsigned perfctr; 794 unsigned fixedctr; 795 int (*addr_offset)(int index, bool eventsel); 796 int (*rdpmc_index)(int index); 797 u64 (*event_map)(int); 798 int max_events; 799 u64 config_mask; 800 union { 801 u64 cntr_mask64; 802 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 803 }; 804 union { 805 u64 fixed_cntr_mask64; 806 unsigned long fixed_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 807 }; 808 int cntval_bits; 809 u64 cntval_mask; 810 union { 811 unsigned long events_maskl; 812 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; 813 }; 814 int events_mask_len; 815 int apic; 816 u64 max_period; 817 struct event_constraint * 818 (*get_event_constraints)(struct cpu_hw_events *cpuc, 819 int idx, 820 struct perf_event *event); 821 822 void (*put_event_constraints)(struct cpu_hw_events *cpuc, 823 struct perf_event *event); 824 825 void (*start_scheduling)(struct cpu_hw_events *cpuc); 826 827 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); 828 829 void (*stop_scheduling)(struct cpu_hw_events *cpuc); 830 831 struct event_constraint *event_constraints; 832 struct x86_pmu_quirk *quirks; 833 void (*limit_period)(struct perf_event *event, s64 *l); 834 835 /* PMI handler bits */ 836 unsigned int late_ack :1, 837 mid_ack :1, 838 enabled_ack :1; 839 /* 840 * sysfs attrs 841 */ 842 int attr_rdpmc_broken; 843 int attr_rdpmc; 844 struct attribute **format_attrs; 845 846 ssize_t (*events_sysfs_show)(char *page, u64 config); 847 const struct attribute_group **attr_update; 848 849 unsigned long attr_freeze_on_smi; 850 851 /* 852 * CPU Hotplug hooks 853 */ 854 int (*cpu_prepare)(int cpu); 855 void (*cpu_starting)(int cpu); 856 void (*cpu_dying)(int cpu); 857 void (*cpu_dead)(int cpu); 858 859 void (*check_microcode)(void); 860 void (*sched_task)(struct perf_event_pmu_context *pmu_ctx, 861 struct task_struct *task, bool sched_in); 862 863 /* 864 * Intel Arch Perfmon v2+ 865 */ 866 u64 intel_ctrl; 867 union perf_capabilities intel_cap; 868 869 /* 870 * Intel DebugStore bits 871 */ 872 unsigned int bts :1, 873 bts_active :1, 874 pebs :1, 875 pebs_active :1, 876 pebs_broken :1, 877 pebs_prec_dist :1, 878 pebs_no_tlb :1, 879 pebs_no_isolation :1, 880 pebs_block :1, 881 pebs_ept :1; 882 int pebs_record_size; 883 int pebs_buffer_size; 884 u64 pebs_events_mask; 885 void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data); 886 struct event_constraint *pebs_constraints; 887 void (*pebs_aliases)(struct perf_event *event); 888 u64 (*pebs_latency_data)(struct perf_event *event, u64 status); 889 unsigned long large_pebs_flags; 890 u64 rtm_abort_event; 891 u64 pebs_capable; 892 893 /* 894 * Intel LBR 895 */ 896 unsigned int lbr_tos, lbr_from, lbr_to, 897 lbr_info, lbr_nr; /* LBR base regs and size */ 898 union { 899 u64 lbr_sel_mask; /* LBR_SELECT valid bits */ 900 u64 lbr_ctl_mask; /* LBR_CTL valid bits */ 901 }; 902 union { 903 const int *lbr_sel_map; /* lbr_select mappings */ 904 int *lbr_ctl_map; /* LBR_CTL mappings */ 905 }; 906 u64 lbr_callstack_users; /* lbr callstack system wide users */ 907 bool lbr_double_abort; /* duplicated lbr aborts */ 908 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ 909 910 unsigned int lbr_has_info:1; 911 unsigned int lbr_has_tsx:1; 912 unsigned int lbr_from_flags:1; 913 unsigned int lbr_to_cycles:1; 914 915 /* 916 * Intel Architectural LBR CPUID Enumeration 917 */ 918 unsigned int lbr_depth_mask:8; 919 unsigned int lbr_deep_c_reset:1; 920 unsigned int lbr_lip:1; 921 unsigned int lbr_cpl:1; 922 unsigned int lbr_filter:1; 923 unsigned int lbr_call_stack:1; 924 unsigned int lbr_mispred:1; 925 unsigned int lbr_timed_lbr:1; 926 unsigned int lbr_br_type:1; 927 unsigned int lbr_counters:4; 928 929 void (*lbr_reset)(void); 930 void (*lbr_read)(struct cpu_hw_events *cpuc); 931 void (*lbr_save)(void *ctx); 932 void (*lbr_restore)(void *ctx); 933 934 /* 935 * Intel PT/LBR/BTS are exclusive 936 */ 937 atomic_t lbr_exclusive[x86_lbr_exclusive_max]; 938 939 /* 940 * Intel perf metrics 941 */ 942 int num_topdown_events; 943 944 /* 945 * AMD bits 946 */ 947 unsigned int amd_nb_constraints : 1; 948 u64 perf_ctr_pair_en; 949 950 /* 951 * Extra registers for events 952 */ 953 struct extra_reg *extra_regs; 954 unsigned int flags; 955 956 /* 957 * Intel host/guest support (KVM) 958 */ 959 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr, void *data); 960 961 /* 962 * Check period value for PERF_EVENT_IOC_PERIOD ioctl. 963 */ 964 int (*check_period) (struct perf_event *event, u64 period); 965 966 int (*aux_output_match) (struct perf_event *event); 967 968 void (*filter)(struct pmu *pmu, int cpu, bool *ret); 969 /* 970 * Hybrid support 971 * 972 * Most PMU capabilities are the same among different hybrid PMUs. 973 * The global x86_pmu saves the architecture capabilities, which 974 * are available for all PMUs. The hybrid_pmu only includes the 975 * unique capabilities. 976 */ 977 int num_hybrid_pmus; 978 struct x86_hybrid_pmu *hybrid_pmu; 979 enum intel_cpu_type (*get_hybrid_cpu_type) (void); 980 }; 981 982 struct x86_perf_task_context_opt { 983 int lbr_callstack_users; 984 int lbr_stack_state; 985 int log_id; 986 }; 987 988 struct x86_perf_task_context { 989 u64 lbr_sel; 990 int tos; 991 int valid_lbrs; 992 struct x86_perf_task_context_opt opt; 993 struct lbr_entry lbr[MAX_LBR_ENTRIES]; 994 }; 995 996 struct x86_perf_task_context_arch_lbr { 997 struct x86_perf_task_context_opt opt; 998 struct lbr_entry entries[]; 999 }; 1000 1001 /* 1002 * Add padding to guarantee the 64-byte alignment of the state buffer. 1003 * 1004 * The structure is dynamically allocated. The size of the LBR state may vary 1005 * based on the number of LBR registers. 1006 * 1007 * Do not put anything after the LBR state. 1008 */ 1009 struct x86_perf_task_context_arch_lbr_xsave { 1010 struct x86_perf_task_context_opt opt; 1011 1012 union { 1013 struct xregs_state xsave; 1014 struct { 1015 struct fxregs_state i387; 1016 struct xstate_header header; 1017 struct arch_lbr_state lbr; 1018 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT))); 1019 }; 1020 }; 1021 1022 #define x86_add_quirk(func_) \ 1023 do { \ 1024 static struct x86_pmu_quirk __quirk __initdata = { \ 1025 .func = func_, \ 1026 }; \ 1027 __quirk.next = x86_pmu.quirks; \ 1028 x86_pmu.quirks = &__quirk; \ 1029 } while (0) 1030 1031 /* 1032 * x86_pmu flags 1033 */ 1034 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ 1035 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ 1036 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ 1037 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ 1038 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */ 1039 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */ 1040 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */ 1041 #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */ 1042 #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */ 1043 #define PMU_FL_RETIRE_LATENCY 0x200 /* Support Retire Latency in PEBS */ 1044 #define PMU_FL_BR_CNTR 0x400 /* Support branch counter logging */ 1045 1046 #define EVENT_VAR(_id) event_attr_##_id 1047 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr 1048 1049 #define EVENT_ATTR(_name, _id) \ 1050 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ 1051 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 1052 .id = PERF_COUNT_HW_##_id, \ 1053 .event_str = NULL, \ 1054 }; 1055 1056 #define EVENT_ATTR_STR(_name, v, str) \ 1057 static struct perf_pmu_events_attr event_attr_##v = { \ 1058 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 1059 .id = 0, \ 1060 .event_str = str, \ 1061 }; 1062 1063 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \ 1064 static struct perf_pmu_events_ht_attr event_attr_##v = { \ 1065 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\ 1066 .id = 0, \ 1067 .event_str_noht = noht, \ 1068 .event_str_ht = ht, \ 1069 } 1070 1071 #define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \ 1072 static struct perf_pmu_events_hybrid_attr event_attr_##v = { \ 1073 .attr = __ATTR(_name, 0444, events_hybrid_sysfs_show, NULL),\ 1074 .id = 0, \ 1075 .event_str = str, \ 1076 .pmu_type = _pmu, \ 1077 } 1078 1079 #define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr) 1080 1081 #define FORMAT_ATTR_HYBRID(_name, _pmu) \ 1082 static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\ 1083 .attr = __ATTR_RO(_name), \ 1084 .pmu_type = _pmu, \ 1085 } 1086 1087 struct pmu *x86_get_pmu(unsigned int cpu); 1088 extern struct x86_pmu x86_pmu __read_mostly; 1089 1090 DECLARE_STATIC_CALL(x86_pmu_set_period, *x86_pmu.set_period); 1091 DECLARE_STATIC_CALL(x86_pmu_update, *x86_pmu.update); 1092 DECLARE_STATIC_CALL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs); 1093 DECLARE_STATIC_CALL(x86_pmu_late_setup, *x86_pmu.late_setup); 1094 1095 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx) 1096 { 1097 if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 1098 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt; 1099 1100 return &((struct x86_perf_task_context *)ctx)->opt; 1101 } 1102 1103 static inline bool x86_pmu_has_lbr_callstack(void) 1104 { 1105 return x86_pmu.lbr_sel_map && 1106 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; 1107 } 1108 1109 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 1110 DECLARE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); 1111 1112 int x86_perf_event_set_period(struct perf_event *event); 1113 1114 /* 1115 * Generalized hw caching related hw_event table, filled 1116 * in on a per model basis. A value of 0 means 1117 * 'not supported', -1 means 'hw_event makes no sense on 1118 * this CPU', any other value means the raw hw_event 1119 * ID. 1120 */ 1121 1122 #define C(x) PERF_COUNT_HW_CACHE_##x 1123 1124 extern u64 __read_mostly hw_cache_event_ids 1125 [PERF_COUNT_HW_CACHE_MAX] 1126 [PERF_COUNT_HW_CACHE_OP_MAX] 1127 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1128 extern u64 __read_mostly hw_cache_extra_regs 1129 [PERF_COUNT_HW_CACHE_MAX] 1130 [PERF_COUNT_HW_CACHE_OP_MAX] 1131 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1132 1133 u64 x86_perf_event_update(struct perf_event *event); 1134 1135 static inline u64 intel_pmu_topdown_event_update(struct perf_event *event, u64 *val) 1136 { 1137 return x86_perf_event_update(event); 1138 } 1139 DECLARE_STATIC_CALL(intel_pmu_update_topdown_event, intel_pmu_topdown_event_update); 1140 1141 static inline unsigned int x86_pmu_config_addr(int index) 1142 { 1143 return x86_pmu.eventsel + (x86_pmu.addr_offset ? 1144 x86_pmu.addr_offset(index, true) : index); 1145 } 1146 1147 static inline unsigned int x86_pmu_event_addr(int index) 1148 { 1149 return x86_pmu.perfctr + (x86_pmu.addr_offset ? 1150 x86_pmu.addr_offset(index, false) : index); 1151 } 1152 1153 static inline unsigned int x86_pmu_fixed_ctr_addr(int index) 1154 { 1155 return x86_pmu.fixedctr + (x86_pmu.addr_offset ? 1156 x86_pmu.addr_offset(index, false) : index); 1157 } 1158 1159 static inline int x86_pmu_rdpmc_index(int index) 1160 { 1161 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; 1162 } 1163 1164 bool check_hw_exists(struct pmu *pmu, unsigned long *cntr_mask, 1165 unsigned long *fixed_cntr_mask); 1166 1167 int x86_add_exclusive(unsigned int what); 1168 1169 void x86_del_exclusive(unsigned int what); 1170 1171 int x86_reserve_hardware(void); 1172 1173 void x86_release_hardware(void); 1174 1175 int x86_pmu_max_precise(void); 1176 1177 void hw_perf_lbr_event_destroy(struct perf_event *event); 1178 1179 int x86_setup_perfctr(struct perf_event *event); 1180 1181 int x86_pmu_hw_config(struct perf_event *event); 1182 1183 void x86_pmu_disable_all(void); 1184 1185 static inline bool has_amd_brs(struct hw_perf_event *hwc) 1186 { 1187 return hwc->flags & PERF_X86_EVENT_AMD_BRS; 1188 } 1189 1190 static inline bool is_counter_pair(struct hw_perf_event *hwc) 1191 { 1192 return hwc->flags & PERF_X86_EVENT_PAIR; 1193 } 1194 1195 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, 1196 u64 enable_mask) 1197 { 1198 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1199 1200 if (hwc->extra_reg.reg) 1201 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); 1202 1203 /* 1204 * Add enabled Merge event on next counter 1205 * if large increment event being enabled on this counter 1206 */ 1207 if (is_counter_pair(hwc)) 1208 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); 1209 1210 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 1211 } 1212 1213 void x86_pmu_enable_all(int added); 1214 1215 int perf_assign_events(struct event_constraint **constraints, int n, 1216 int wmin, int wmax, int gpmax, int *assign); 1217 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); 1218 1219 void x86_pmu_stop(struct perf_event *event, int flags); 1220 1221 static inline void x86_pmu_disable_event(struct perf_event *event) 1222 { 1223 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1224 struct hw_perf_event *hwc = &event->hw; 1225 1226 wrmsrl(hwc->config_base, hwc->config & ~disable_mask); 1227 1228 if (is_counter_pair(hwc)) 1229 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0); 1230 } 1231 1232 void x86_pmu_enable_event(struct perf_event *event); 1233 1234 int x86_pmu_handle_irq(struct pt_regs *regs); 1235 1236 void x86_pmu_show_pmu_cap(struct pmu *pmu); 1237 1238 static inline int x86_pmu_num_counters(struct pmu *pmu) 1239 { 1240 return hweight64(hybrid(pmu, cntr_mask64)); 1241 } 1242 1243 static inline int x86_pmu_max_num_counters(struct pmu *pmu) 1244 { 1245 return fls64(hybrid(pmu, cntr_mask64)); 1246 } 1247 1248 static inline int x86_pmu_num_counters_fixed(struct pmu *pmu) 1249 { 1250 return hweight64(hybrid(pmu, fixed_cntr_mask64)); 1251 } 1252 1253 static inline int x86_pmu_max_num_counters_fixed(struct pmu *pmu) 1254 { 1255 return fls64(hybrid(pmu, fixed_cntr_mask64)); 1256 } 1257 1258 static inline u64 x86_pmu_get_event_config(struct perf_event *event) 1259 { 1260 return event->attr.config & hybrid(event->pmu, config_mask); 1261 } 1262 1263 extern struct event_constraint emptyconstraint; 1264 1265 extern struct event_constraint unconstrained; 1266 1267 static inline bool kernel_ip(unsigned long ip) 1268 { 1269 #ifdef CONFIG_X86_32 1270 return ip > PAGE_OFFSET; 1271 #else 1272 return (long)ip < 0; 1273 #endif 1274 } 1275 1276 /* 1277 * Not all PMUs provide the right context information to place the reported IP 1278 * into full context. Specifically segment registers are typically not 1279 * supplied. 1280 * 1281 * Assuming the address is a linear address (it is for IBS), we fake the CS and 1282 * vm86 mode using the known zero-based code segment and 'fix up' the registers 1283 * to reflect this. 1284 * 1285 * Intel PEBS/LBR appear to typically provide the effective address, nothing 1286 * much we can do about that but pray and treat it like a linear address. 1287 */ 1288 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) 1289 { 1290 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; 1291 if (regs->flags & X86_VM_MASK) 1292 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); 1293 regs->ip = ip; 1294 } 1295 1296 /* 1297 * x86control flow change classification 1298 * x86control flow changes include branches, interrupts, traps, faults 1299 */ 1300 enum { 1301 X86_BR_NONE = 0, /* unknown */ 1302 1303 X86_BR_USER = 1 << 0, /* branch target is user */ 1304 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */ 1305 1306 X86_BR_CALL = 1 << 2, /* call */ 1307 X86_BR_RET = 1 << 3, /* return */ 1308 X86_BR_SYSCALL = 1 << 4, /* syscall */ 1309 X86_BR_SYSRET = 1 << 5, /* syscall return */ 1310 X86_BR_INT = 1 << 6, /* sw interrupt */ 1311 X86_BR_IRET = 1 << 7, /* return from interrupt */ 1312 X86_BR_JCC = 1 << 8, /* conditional */ 1313 X86_BR_JMP = 1 << 9, /* jump */ 1314 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */ 1315 X86_BR_IND_CALL = 1 << 11,/* indirect calls */ 1316 X86_BR_ABORT = 1 << 12,/* transaction abort */ 1317 X86_BR_IN_TX = 1 << 13,/* in transaction */ 1318 X86_BR_NO_TX = 1 << 14,/* not in transaction */ 1319 X86_BR_ZERO_CALL = 1 << 15,/* zero length call */ 1320 X86_BR_CALL_STACK = 1 << 16,/* call stack */ 1321 X86_BR_IND_JMP = 1 << 17,/* indirect jump */ 1322 1323 X86_BR_TYPE_SAVE = 1 << 18,/* indicate to save branch type */ 1324 1325 }; 1326 1327 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL) 1328 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX) 1329 1330 #define X86_BR_ANY \ 1331 (X86_BR_CALL |\ 1332 X86_BR_RET |\ 1333 X86_BR_SYSCALL |\ 1334 X86_BR_SYSRET |\ 1335 X86_BR_INT |\ 1336 X86_BR_IRET |\ 1337 X86_BR_JCC |\ 1338 X86_BR_JMP |\ 1339 X86_BR_IRQ |\ 1340 X86_BR_ABORT |\ 1341 X86_BR_IND_CALL |\ 1342 X86_BR_IND_JMP |\ 1343 X86_BR_ZERO_CALL) 1344 1345 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY) 1346 1347 #define X86_BR_ANY_CALL \ 1348 (X86_BR_CALL |\ 1349 X86_BR_IND_CALL |\ 1350 X86_BR_ZERO_CALL |\ 1351 X86_BR_SYSCALL |\ 1352 X86_BR_IRQ |\ 1353 X86_BR_INT) 1354 1355 int common_branch_type(int type); 1356 int branch_type(unsigned long from, unsigned long to, int abort); 1357 int branch_type_fused(unsigned long from, unsigned long to, int abort, 1358 int *offset); 1359 1360 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); 1361 ssize_t intel_event_sysfs_show(char *page, u64 config); 1362 1363 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, 1364 char *page); 1365 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 1366 char *page); 1367 ssize_t events_hybrid_sysfs_show(struct device *dev, 1368 struct device_attribute *attr, 1369 char *page); 1370 1371 static inline bool fixed_counter_disabled(int i, struct pmu *pmu) 1372 { 1373 u64 intel_ctrl = hybrid(pmu, intel_ctrl); 1374 1375 return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED)); 1376 } 1377 1378 #ifdef CONFIG_CPU_SUP_AMD 1379 1380 int amd_pmu_init(void); 1381 1382 int amd_pmu_lbr_init(void); 1383 void amd_pmu_lbr_reset(void); 1384 void amd_pmu_lbr_read(void); 1385 void amd_pmu_lbr_add(struct perf_event *event); 1386 void amd_pmu_lbr_del(struct perf_event *event); 1387 void amd_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx, 1388 struct task_struct *task, bool sched_in); 1389 void amd_pmu_lbr_enable_all(void); 1390 void amd_pmu_lbr_disable_all(void); 1391 int amd_pmu_lbr_hw_config(struct perf_event *event); 1392 1393 static __always_inline void __amd_pmu_lbr_disable(void) 1394 { 1395 u64 dbg_ctl, dbg_extn_cfg; 1396 1397 rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg); 1398 wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN); 1399 1400 if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) { 1401 rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl); 1402 wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 1403 } 1404 } 1405 1406 #ifdef CONFIG_PERF_EVENTS_AMD_BRS 1407 1408 #define AMD_FAM19H_BRS_EVENT 0xc4 /* RETIRED_TAKEN_BRANCH_INSTRUCTIONS */ 1409 1410 int amd_brs_init(void); 1411 void amd_brs_disable(void); 1412 void amd_brs_enable(void); 1413 void amd_brs_enable_all(void); 1414 void amd_brs_disable_all(void); 1415 void amd_brs_drain(void); 1416 void amd_brs_lopwr_init(void); 1417 int amd_brs_hw_config(struct perf_event *event); 1418 void amd_brs_reset(void); 1419 1420 static inline void amd_pmu_brs_add(struct perf_event *event) 1421 { 1422 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1423 1424 perf_sched_cb_inc(event->pmu); 1425 cpuc->lbr_users++; 1426 /* 1427 * No need to reset BRS because it is reset 1428 * on brs_enable() and it is saturating 1429 */ 1430 } 1431 1432 static inline void amd_pmu_brs_del(struct perf_event *event) 1433 { 1434 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1435 1436 cpuc->lbr_users--; 1437 WARN_ON_ONCE(cpuc->lbr_users < 0); 1438 1439 perf_sched_cb_dec(event->pmu); 1440 } 1441 1442 void amd_pmu_brs_sched_task(struct perf_event_pmu_context *pmu_ctx, 1443 struct task_struct *task, bool sched_in); 1444 #else 1445 static inline int amd_brs_init(void) 1446 { 1447 return 0; 1448 } 1449 static inline void amd_brs_disable(void) {} 1450 static inline void amd_brs_enable(void) {} 1451 static inline void amd_brs_drain(void) {} 1452 static inline void amd_brs_lopwr_init(void) {} 1453 static inline void amd_brs_disable_all(void) {} 1454 static inline int amd_brs_hw_config(struct perf_event *event) 1455 { 1456 return 0; 1457 } 1458 static inline void amd_brs_reset(void) {} 1459 1460 static inline void amd_pmu_brs_add(struct perf_event *event) 1461 { 1462 } 1463 1464 static inline void amd_pmu_brs_del(struct perf_event *event) 1465 { 1466 } 1467 1468 static inline void amd_pmu_brs_sched_task(struct perf_event_pmu_context *pmu_ctx, 1469 struct task_struct *task, bool sched_in) 1470 { 1471 } 1472 1473 static inline void amd_brs_enable_all(void) 1474 { 1475 } 1476 1477 #endif 1478 1479 #else /* CONFIG_CPU_SUP_AMD */ 1480 1481 static inline int amd_pmu_init(void) 1482 { 1483 return 0; 1484 } 1485 1486 static inline int amd_brs_init(void) 1487 { 1488 return -EOPNOTSUPP; 1489 } 1490 1491 static inline void amd_brs_drain(void) 1492 { 1493 } 1494 1495 static inline void amd_brs_enable_all(void) 1496 { 1497 } 1498 1499 static inline void amd_brs_disable_all(void) 1500 { 1501 } 1502 #endif /* CONFIG_CPU_SUP_AMD */ 1503 1504 static inline int is_pebs_pt(struct perf_event *event) 1505 { 1506 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT); 1507 } 1508 1509 #ifdef CONFIG_CPU_SUP_INTEL 1510 1511 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period) 1512 { 1513 struct hw_perf_event *hwc = &event->hw; 1514 unsigned int hw_event, bts_event; 1515 1516 if (event->attr.freq) 1517 return false; 1518 1519 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 1520 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 1521 1522 return hw_event == bts_event && period == 1; 1523 } 1524 1525 static inline bool intel_pmu_has_bts(struct perf_event *event) 1526 { 1527 struct hw_perf_event *hwc = &event->hw; 1528 1529 return intel_pmu_has_bts_period(event, hwc->sample_period); 1530 } 1531 1532 static __always_inline void __intel_pmu_pebs_disable_all(void) 1533 { 1534 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 1535 } 1536 1537 static __always_inline void __intel_pmu_arch_lbr_disable(void) 1538 { 1539 wrmsrl(MSR_ARCH_LBR_CTL, 0); 1540 } 1541 1542 static __always_inline void __intel_pmu_lbr_disable(void) 1543 { 1544 u64 debugctl; 1545 1546 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1547 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 1548 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1549 } 1550 1551 int intel_pmu_save_and_restart(struct perf_event *event); 1552 1553 struct event_constraint * 1554 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 1555 struct perf_event *event); 1556 1557 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu); 1558 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc); 1559 1560 int intel_pmu_init(void); 1561 1562 void init_debug_store_on_cpu(int cpu); 1563 1564 void fini_debug_store_on_cpu(int cpu); 1565 1566 void release_ds_buffers(void); 1567 1568 void reserve_ds_buffers(void); 1569 1570 void release_lbr_buffers(void); 1571 1572 void reserve_lbr_buffers(void); 1573 1574 extern struct event_constraint bts_constraint; 1575 extern struct event_constraint vlbr_constraint; 1576 1577 void intel_pmu_enable_bts(u64 config); 1578 1579 void intel_pmu_disable_bts(void); 1580 1581 int intel_pmu_drain_bts_buffer(void); 1582 1583 u64 grt_latency_data(struct perf_event *event, u64 status); 1584 1585 u64 cmt_latency_data(struct perf_event *event, u64 status); 1586 1587 u64 lnl_latency_data(struct perf_event *event, u64 status); 1588 1589 u64 arl_h_latency_data(struct perf_event *event, u64 status); 1590 1591 extern struct event_constraint intel_core2_pebs_event_constraints[]; 1592 1593 extern struct event_constraint intel_atom_pebs_event_constraints[]; 1594 1595 extern struct event_constraint intel_slm_pebs_event_constraints[]; 1596 1597 extern struct event_constraint intel_glm_pebs_event_constraints[]; 1598 1599 extern struct event_constraint intel_glp_pebs_event_constraints[]; 1600 1601 extern struct event_constraint intel_grt_pebs_event_constraints[]; 1602 1603 extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 1604 1605 extern struct event_constraint intel_westmere_pebs_event_constraints[]; 1606 1607 extern struct event_constraint intel_snb_pebs_event_constraints[]; 1608 1609 extern struct event_constraint intel_ivb_pebs_event_constraints[]; 1610 1611 extern struct event_constraint intel_hsw_pebs_event_constraints[]; 1612 1613 extern struct event_constraint intel_bdw_pebs_event_constraints[]; 1614 1615 extern struct event_constraint intel_skl_pebs_event_constraints[]; 1616 1617 extern struct event_constraint intel_icl_pebs_event_constraints[]; 1618 1619 extern struct event_constraint intel_glc_pebs_event_constraints[]; 1620 1621 extern struct event_constraint intel_lnc_pebs_event_constraints[]; 1622 1623 struct event_constraint *intel_pebs_constraints(struct perf_event *event); 1624 1625 void intel_pmu_pebs_add(struct perf_event *event); 1626 1627 void intel_pmu_pebs_del(struct perf_event *event); 1628 1629 void intel_pmu_pebs_enable(struct perf_event *event); 1630 1631 void intel_pmu_pebs_disable(struct perf_event *event); 1632 1633 void intel_pmu_pebs_enable_all(void); 1634 1635 void intel_pmu_pebs_disable_all(void); 1636 1637 void intel_pmu_pebs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in); 1638 1639 void intel_pmu_drain_pebs_buffer(void); 1640 1641 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr); 1642 1643 void intel_ds_init(void); 1644 1645 void intel_pmu_lbr_save_brstack(struct perf_sample_data *data, 1646 struct cpu_hw_events *cpuc, 1647 struct perf_event *event); 1648 1649 void intel_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx, 1650 struct task_struct *task, bool sched_in); 1651 1652 u64 lbr_from_signext_quirk_wr(u64 val); 1653 1654 void intel_pmu_lbr_reset(void); 1655 1656 void intel_pmu_lbr_reset_32(void); 1657 1658 void intel_pmu_lbr_reset_64(void); 1659 1660 void intel_pmu_lbr_add(struct perf_event *event); 1661 1662 void intel_pmu_lbr_del(struct perf_event *event); 1663 1664 void intel_pmu_lbr_enable_all(bool pmi); 1665 1666 void intel_pmu_lbr_disable_all(void); 1667 1668 void intel_pmu_lbr_read(void); 1669 1670 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc); 1671 1672 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc); 1673 1674 void intel_pmu_lbr_save(void *ctx); 1675 1676 void intel_pmu_lbr_restore(void *ctx); 1677 1678 void intel_pmu_lbr_init_core(void); 1679 1680 void intel_pmu_lbr_init_nhm(void); 1681 1682 void intel_pmu_lbr_init_atom(void); 1683 1684 void intel_pmu_lbr_init_slm(void); 1685 1686 void intel_pmu_lbr_init_snb(void); 1687 1688 void intel_pmu_lbr_init_hsw(void); 1689 1690 void intel_pmu_lbr_init_skl(void); 1691 1692 void intel_pmu_lbr_init_knl(void); 1693 1694 void intel_pmu_lbr_init(void); 1695 1696 void intel_pmu_arch_lbr_init(void); 1697 1698 void intel_pmu_pebs_data_source_nhm(void); 1699 1700 void intel_pmu_pebs_data_source_skl(bool pmem); 1701 1702 void intel_pmu_pebs_data_source_adl(void); 1703 1704 void intel_pmu_pebs_data_source_grt(void); 1705 1706 void intel_pmu_pebs_data_source_mtl(void); 1707 1708 void intel_pmu_pebs_data_source_arl_h(void); 1709 1710 void intel_pmu_pebs_data_source_cmt(void); 1711 1712 void intel_pmu_pebs_data_source_lnl(void); 1713 1714 int intel_pmu_setup_lbr_filter(struct perf_event *event); 1715 1716 void intel_pt_interrupt(void); 1717 1718 int intel_bts_interrupt(void); 1719 1720 void intel_bts_enable_local(void); 1721 1722 void intel_bts_disable_local(void); 1723 1724 int p4_pmu_init(void); 1725 1726 int p6_pmu_init(void); 1727 1728 int knc_pmu_init(void); 1729 1730 static inline int is_ht_workaround_enabled(void) 1731 { 1732 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); 1733 } 1734 1735 static inline u64 intel_pmu_pebs_mask(u64 cntr_mask) 1736 { 1737 return MAX_PEBS_EVENTS_MASK & cntr_mask; 1738 } 1739 1740 static inline int intel_pmu_max_num_pebs(struct pmu *pmu) 1741 { 1742 static_assert(MAX_PEBS_EVENTS == 32); 1743 return fls((u32)hybrid(pmu, pebs_events_mask)); 1744 } 1745 1746 #else /* CONFIG_CPU_SUP_INTEL */ 1747 1748 static inline void reserve_ds_buffers(void) 1749 { 1750 } 1751 1752 static inline void release_ds_buffers(void) 1753 { 1754 } 1755 1756 static inline void release_lbr_buffers(void) 1757 { 1758 } 1759 1760 static inline void reserve_lbr_buffers(void) 1761 { 1762 } 1763 1764 static inline int intel_pmu_init(void) 1765 { 1766 return 0; 1767 } 1768 1769 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 1770 { 1771 return 0; 1772 } 1773 1774 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc) 1775 { 1776 } 1777 1778 static inline int is_ht_workaround_enabled(void) 1779 { 1780 return 0; 1781 } 1782 #endif /* CONFIG_CPU_SUP_INTEL */ 1783 1784 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN)) 1785 int zhaoxin_pmu_init(void); 1786 #else 1787 static inline int zhaoxin_pmu_init(void) 1788 { 1789 return 0; 1790 } 1791 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/ 1792