1 /* 2 * Performance events x86 architecture header 3 * 4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2009 Jaswinder Singh Rajput 7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 10 * Copyright (C) 2009 Google, Inc., Stephane Eranian 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 15 #include <linux/perf_event.h> 16 17 #include <asm/fpu/xstate.h> 18 #include <asm/intel_ds.h> 19 #include <asm/cpu.h> 20 21 /* To enable MSR tracing please use the generic trace points. */ 22 23 /* 24 * | NHM/WSM | SNB | 25 * register ------------------------------- 26 * | HT | no HT | HT | no HT | 27 *----------------------------------------- 28 * offcore | core | core | cpu | core | 29 * lbr_sel | core | core | cpu | core | 30 * ld_lat | cpu | core | cpu | core | 31 *----------------------------------------- 32 * 33 * Given that there is a small number of shared regs, 34 * we can pre-allocate their slot in the per-cpu 35 * per-core reg tables. 36 */ 37 enum extra_reg_type { 38 EXTRA_REG_NONE = -1, /* not used */ 39 40 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ 41 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ 42 EXTRA_REG_LBR = 2, /* lbr_select */ 43 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ 44 EXTRA_REG_FE = 4, /* fe_* */ 45 46 EXTRA_REG_MAX /* number of entries needed */ 47 }; 48 49 struct event_constraint { 50 union { 51 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 52 u64 idxmsk64; 53 }; 54 u64 code; 55 u64 cmask; 56 int weight; 57 int overlap; 58 int flags; 59 unsigned int size; 60 }; 61 62 static inline bool constraint_match(struct event_constraint *c, u64 ecode) 63 { 64 return ((ecode & c->cmask) - c->code) <= (u64)c->size; 65 } 66 67 #define PERF_ARCH(name, val) \ 68 PERF_X86_EVENT_##name = val, 69 70 /* 71 * struct hw_perf_event.flags flags 72 */ 73 enum { 74 #include "perf_event_flags.h" 75 }; 76 77 #undef PERF_ARCH 78 79 #define PERF_ARCH(name, val) \ 80 static_assert((PERF_X86_EVENT_##name & PERF_EVENT_FLAG_ARCH) == \ 81 PERF_X86_EVENT_##name); 82 83 #include "perf_event_flags.h" 84 85 #undef PERF_ARCH 86 87 static inline bool is_topdown_count(struct perf_event *event) 88 { 89 return event->hw.flags & PERF_X86_EVENT_TOPDOWN; 90 } 91 92 static inline bool is_metric_event(struct perf_event *event) 93 { 94 u64 config = event->attr.config; 95 96 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) && 97 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) && 98 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX); 99 } 100 101 static inline bool is_slots_event(struct perf_event *event) 102 { 103 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS; 104 } 105 106 static inline bool is_topdown_event(struct perf_event *event) 107 { 108 return is_metric_event(event) || is_slots_event(event); 109 } 110 111 struct amd_nb { 112 int nb_id; /* NorthBridge id */ 113 int refcnt; /* reference count */ 114 struct perf_event *owners[X86_PMC_IDX_MAX]; 115 struct event_constraint event_constraints[X86_PMC_IDX_MAX]; 116 }; 117 118 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) 119 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60) 120 #define PEBS_OUTPUT_OFFSET 61 121 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET) 122 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET) 123 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD) 124 125 /* 126 * Flags PEBS can handle without an PMI. 127 * 128 * TID can only be handled by flushing at context switch. 129 * REGS_USER can be handled for events limited to ring 3. 130 * 131 */ 132 #define LARGE_PEBS_FLAGS \ 133 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 134 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 135 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 136 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ 137 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \ 138 PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE | \ 139 PERF_SAMPLE_WEIGHT_TYPE) 140 141 #define PEBS_GP_REGS \ 142 ((1ULL << PERF_REG_X86_AX) | \ 143 (1ULL << PERF_REG_X86_BX) | \ 144 (1ULL << PERF_REG_X86_CX) | \ 145 (1ULL << PERF_REG_X86_DX) | \ 146 (1ULL << PERF_REG_X86_DI) | \ 147 (1ULL << PERF_REG_X86_SI) | \ 148 (1ULL << PERF_REG_X86_SP) | \ 149 (1ULL << PERF_REG_X86_BP) | \ 150 (1ULL << PERF_REG_X86_IP) | \ 151 (1ULL << PERF_REG_X86_FLAGS) | \ 152 (1ULL << PERF_REG_X86_R8) | \ 153 (1ULL << PERF_REG_X86_R9) | \ 154 (1ULL << PERF_REG_X86_R10) | \ 155 (1ULL << PERF_REG_X86_R11) | \ 156 (1ULL << PERF_REG_X86_R12) | \ 157 (1ULL << PERF_REG_X86_R13) | \ 158 (1ULL << PERF_REG_X86_R14) | \ 159 (1ULL << PERF_REG_X86_R15)) 160 161 /* 162 * Per register state. 163 */ 164 struct er_account { 165 raw_spinlock_t lock; /* per-core: protect structure */ 166 u64 config; /* extra MSR config */ 167 u64 reg; /* extra MSR number */ 168 atomic_t ref; /* reference count */ 169 }; 170 171 /* 172 * Per core/cpu state 173 * 174 * Used to coordinate shared registers between HT threads or 175 * among events on a single PMU. 176 */ 177 struct intel_shared_regs { 178 struct er_account regs[EXTRA_REG_MAX]; 179 int refcnt; /* per-core: #HT threads */ 180 unsigned core_id; /* per-core: core id */ 181 }; 182 183 enum intel_excl_state_type { 184 INTEL_EXCL_UNUSED = 0, /* counter is unused */ 185 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ 186 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ 187 }; 188 189 struct intel_excl_states { 190 enum intel_excl_state_type state[X86_PMC_IDX_MAX]; 191 bool sched_started; /* true if scheduling has started */ 192 }; 193 194 struct intel_excl_cntrs { 195 raw_spinlock_t lock; 196 197 struct intel_excl_states states[2]; 198 199 union { 200 u16 has_exclusive[2]; 201 u32 exclusive_present; 202 }; 203 204 int refcnt; /* per-core: #HT threads */ 205 unsigned core_id; /* per-core: core id */ 206 }; 207 208 struct x86_perf_task_context; 209 #define MAX_LBR_ENTRIES 32 210 211 enum { 212 LBR_FORMAT_32 = 0x00, 213 LBR_FORMAT_LIP = 0x01, 214 LBR_FORMAT_EIP = 0x02, 215 LBR_FORMAT_EIP_FLAGS = 0x03, 216 LBR_FORMAT_EIP_FLAGS2 = 0x04, 217 LBR_FORMAT_INFO = 0x05, 218 LBR_FORMAT_TIME = 0x06, 219 LBR_FORMAT_INFO2 = 0x07, 220 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_INFO2, 221 }; 222 223 enum { 224 X86_PERF_KFREE_SHARED = 0, 225 X86_PERF_KFREE_EXCL = 1, 226 X86_PERF_KFREE_MAX 227 }; 228 229 struct cpu_hw_events { 230 /* 231 * Generic x86 PMC bits 232 */ 233 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ 234 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 235 unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 236 int enabled; 237 238 int n_events; /* the # of events in the below arrays */ 239 int n_added; /* the # last events in the below arrays; 240 they've never been enabled yet */ 241 int n_txn; /* the # last events in the below arrays; 242 added in the current transaction */ 243 int n_txn_pair; 244 int n_txn_metric; 245 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ 246 u64 tags[X86_PMC_IDX_MAX]; 247 248 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ 249 struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; 250 251 int n_excl; /* the number of exclusive events */ 252 253 unsigned int txn_flags; 254 int is_fake; 255 256 /* 257 * Intel DebugStore bits 258 */ 259 struct debug_store *ds; 260 void *ds_pebs_vaddr; 261 void *ds_bts_vaddr; 262 u64 pebs_enabled; 263 int n_pebs; 264 int n_large_pebs; 265 int n_pebs_via_pt; 266 int pebs_output; 267 268 /* Current super set of events hardware configuration */ 269 u64 pebs_data_cfg; 270 u64 active_pebs_data_cfg; 271 int pebs_record_size; 272 273 /* Intel Fixed counter configuration */ 274 u64 fixed_ctrl_val; 275 u64 active_fixed_ctrl_val; 276 277 /* 278 * Intel LBR bits 279 */ 280 int lbr_users; 281 int lbr_pebs_users; 282 struct perf_branch_stack lbr_stack; 283 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; 284 union { 285 struct er_account *lbr_sel; 286 struct er_account *lbr_ctl; 287 }; 288 u64 br_sel; 289 void *last_task_ctx; 290 int last_log_id; 291 int lbr_select; 292 void *lbr_xsave; 293 294 /* 295 * Intel host/guest exclude bits 296 */ 297 u64 intel_ctrl_guest_mask; 298 u64 intel_ctrl_host_mask; 299 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; 300 301 /* 302 * Intel checkpoint mask 303 */ 304 u64 intel_cp_status; 305 306 /* 307 * manage shared (per-core, per-cpu) registers 308 * used on Intel NHM/WSM/SNB 309 */ 310 struct intel_shared_regs *shared_regs; 311 /* 312 * manage exclusive counter access between hyperthread 313 */ 314 struct event_constraint *constraint_list; /* in enable order */ 315 struct intel_excl_cntrs *excl_cntrs; 316 int excl_thread_id; /* 0 or 1 */ 317 318 /* 319 * SKL TSX_FORCE_ABORT shadow 320 */ 321 u64 tfa_shadow; 322 323 /* 324 * Perf Metrics 325 */ 326 /* number of accepted metrics events */ 327 int n_metric; 328 329 /* 330 * AMD specific bits 331 */ 332 struct amd_nb *amd_nb; 333 int brs_active; /* BRS is enabled */ 334 335 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ 336 u64 perf_ctr_virt_mask; 337 int n_pair; /* Large increment events */ 338 339 void *kfree_on_online[X86_PERF_KFREE_MAX]; 340 341 struct pmu *pmu; 342 }; 343 344 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \ 345 { .idxmsk64 = (n) }, \ 346 .code = (c), \ 347 .size = (e) - (c), \ 348 .cmask = (m), \ 349 .weight = (w), \ 350 .overlap = (o), \ 351 .flags = f, \ 352 } 353 354 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ 355 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f) 356 357 #define EVENT_CONSTRAINT(c, n, m) \ 358 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) 359 360 /* 361 * The constraint_match() function only works for 'simple' event codes 362 * and not for extended (AMD64_EVENTSEL_EVENT) events codes. 363 */ 364 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \ 365 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0) 366 367 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ 368 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ 369 0, PERF_X86_EVENT_EXCL) 370 371 /* 372 * The overlap flag marks event constraints with overlapping counter 373 * masks. This is the case if the counter mask of such an event is not 374 * a subset of any other counter mask of a constraint with an equal or 375 * higher weight, e.g.: 376 * 377 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); 378 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); 379 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); 380 * 381 * The event scheduler may not select the correct counter in the first 382 * cycle because it needs to know which subsequent events will be 383 * scheduled. It may fail to schedule the events then. So we set the 384 * overlap flag for such constraints to give the scheduler a hint which 385 * events to select for counter rescheduling. 386 * 387 * Care must be taken as the rescheduling algorithm is O(n!) which 388 * will increase scheduling cycles for an over-committed system 389 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros 390 * and its counter masks must be kept at a minimum. 391 */ 392 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ 393 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) 394 395 /* 396 * Constraint on the Event code. 397 */ 398 #define INTEL_EVENT_CONSTRAINT(c, n) \ 399 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) 400 401 /* 402 * Constraint on a range of Event codes 403 */ 404 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \ 405 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT) 406 407 /* 408 * Constraint on the Event code + UMask + fixed-mask 409 * 410 * filter mask to validate fixed counter events. 411 * the following filters disqualify for fixed counters: 412 * - inv 413 * - edge 414 * - cnt-mask 415 * - in_tx 416 * - in_tx_checkpointed 417 * The other filters are supported by fixed counters. 418 * The any-thread option is supported starting with v3. 419 */ 420 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) 421 #define FIXED_EVENT_CONSTRAINT(c, n) \ 422 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) 423 424 /* 425 * The special metric counters do not actually exist. They are calculated from 426 * the combination of the FxCtr3 + MSR_PERF_METRICS. 427 * 428 * The special metric counters are mapped to a dummy offset for the scheduler. 429 * The sharing between multiple users of the same metric without multiplexing 430 * is not allowed, even though the hardware supports that in principle. 431 */ 432 433 #define METRIC_EVENT_CONSTRAINT(c, n) \ 434 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \ 435 INTEL_ARCH_EVENT_MASK) 436 437 /* 438 * Constraint on the Event code + UMask 439 */ 440 #define INTEL_UEVENT_CONSTRAINT(c, n) \ 441 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) 442 443 /* Constraint on specific umask bit only + event */ 444 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \ 445 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c)) 446 447 /* Like UEVENT_CONSTRAINT, but match flags too */ 448 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ 449 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) 450 451 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ 452 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ 453 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) 454 455 #define INTEL_PLD_CONSTRAINT(c, n) \ 456 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 457 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) 458 459 #define INTEL_PSD_CONSTRAINT(c, n) \ 460 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 461 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT) 462 463 #define INTEL_PST_CONSTRAINT(c, n) \ 464 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 465 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) 466 467 #define INTEL_HYBRID_LAT_CONSTRAINT(c, n) \ 468 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 469 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID) 470 471 /* Event constraint, but match on all event flags too. */ 472 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ 473 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 474 475 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ 476 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 477 478 /* Check only flags, but allow all event/umask */ 479 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ 480 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) 481 482 /* Check flags and event code, and set the HSW store flag */ 483 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ 484 __EVENT_CONSTRAINT(code, n, \ 485 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 486 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 487 488 /* Check flags and event code, and set the HSW load flag */ 489 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ 490 __EVENT_CONSTRAINT(code, n, \ 491 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 492 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 493 494 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \ 495 __EVENT_CONSTRAINT_RANGE(code, end, n, \ 496 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 497 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 498 499 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ 500 __EVENT_CONSTRAINT(code, n, \ 501 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 502 HWEIGHT(n), 0, \ 503 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 504 505 /* Check flags and event code/umask, and set the HSW store flag */ 506 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ 507 __EVENT_CONSTRAINT(code, n, \ 508 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 509 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 510 511 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ 512 __EVENT_CONSTRAINT(code, n, \ 513 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 514 HWEIGHT(n), 0, \ 515 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) 516 517 /* Check flags and event code/umask, and set the HSW load flag */ 518 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ 519 __EVENT_CONSTRAINT(code, n, \ 520 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 521 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 522 523 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ 524 __EVENT_CONSTRAINT(code, n, \ 525 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 526 HWEIGHT(n), 0, \ 527 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 528 529 /* Check flags and event code/umask, and set the HSW N/A flag */ 530 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ 531 __EVENT_CONSTRAINT(code, n, \ 532 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 533 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) 534 535 536 /* 537 * We define the end marker as having a weight of -1 538 * to enable blacklisting of events using a counter bitmask 539 * of zero and thus a weight of zero. 540 * The end marker has a weight that cannot possibly be 541 * obtained from counting the bits in the bitmask. 542 */ 543 #define EVENT_CONSTRAINT_END { .weight = -1 } 544 545 /* 546 * Check for end marker with weight == -1 547 */ 548 #define for_each_event_constraint(e, c) \ 549 for ((e) = (c); (e)->weight != -1; (e)++) 550 551 /* 552 * Extra registers for specific events. 553 * 554 * Some events need large masks and require external MSRs. 555 * Those extra MSRs end up being shared for all events on 556 * a PMU and sometimes between PMU of sibling HT threads. 557 * In either case, the kernel needs to handle conflicting 558 * accesses to those extra, shared, regs. The data structure 559 * to manage those registers is stored in cpu_hw_event. 560 */ 561 struct extra_reg { 562 unsigned int event; 563 unsigned int msr; 564 u64 config_mask; 565 u64 valid_mask; 566 int idx; /* per_xxx->regs[] reg index */ 567 bool extra_msr_access; 568 }; 569 570 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ 571 .event = (e), \ 572 .msr = (ms), \ 573 .config_mask = (m), \ 574 .valid_mask = (vm), \ 575 .idx = EXTRA_REG_##i, \ 576 .extra_msr_access = true, \ 577 } 578 579 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ 580 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) 581 582 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ 583 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ 584 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) 585 586 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ 587 INTEL_UEVENT_EXTRA_REG(c, \ 588 MSR_PEBS_LD_LAT_THRESHOLD, \ 589 0xffff, \ 590 LDLAT) 591 592 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) 593 594 union perf_capabilities { 595 struct { 596 u64 lbr_format:6; 597 u64 pebs_trap:1; 598 u64 pebs_arch_reg:1; 599 u64 pebs_format:4; 600 u64 smm_freeze:1; 601 /* 602 * PMU supports separate counter range for writing 603 * values > 32bit. 604 */ 605 u64 full_width_write:1; 606 u64 pebs_baseline:1; 607 u64 perf_metrics:1; 608 u64 pebs_output_pt_available:1; 609 u64 anythread_deprecated:1; 610 }; 611 u64 capabilities; 612 }; 613 614 struct x86_pmu_quirk { 615 struct x86_pmu_quirk *next; 616 void (*func)(void); 617 }; 618 619 union x86_pmu_config { 620 struct { 621 u64 event:8, 622 umask:8, 623 usr:1, 624 os:1, 625 edge:1, 626 pc:1, 627 interrupt:1, 628 __reserved1:1, 629 en:1, 630 inv:1, 631 cmask:8, 632 event2:4, 633 __reserved2:4, 634 go:1, 635 ho:1; 636 } bits; 637 u64 value; 638 }; 639 640 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value 641 642 enum { 643 x86_lbr_exclusive_lbr, 644 x86_lbr_exclusive_bts, 645 x86_lbr_exclusive_pt, 646 x86_lbr_exclusive_max, 647 }; 648 649 #define PERF_PEBS_DATA_SOURCE_MAX 0x10 650 651 struct x86_hybrid_pmu { 652 struct pmu pmu; 653 const char *name; 654 u8 cpu_type; 655 cpumask_t supported_cpus; 656 union perf_capabilities intel_cap; 657 u64 intel_ctrl; 658 int max_pebs_events; 659 int num_counters; 660 int num_counters_fixed; 661 struct event_constraint unconstrained; 662 663 u64 hw_cache_event_ids 664 [PERF_COUNT_HW_CACHE_MAX] 665 [PERF_COUNT_HW_CACHE_OP_MAX] 666 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 667 u64 hw_cache_extra_regs 668 [PERF_COUNT_HW_CACHE_MAX] 669 [PERF_COUNT_HW_CACHE_OP_MAX] 670 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 671 struct event_constraint *event_constraints; 672 struct event_constraint *pebs_constraints; 673 struct extra_reg *extra_regs; 674 675 unsigned int late_ack :1, 676 mid_ack :1, 677 enabled_ack :1; 678 679 u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX]; 680 }; 681 682 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu) 683 { 684 return container_of(pmu, struct x86_hybrid_pmu, pmu); 685 } 686 687 extern struct static_key_false perf_is_hybrid; 688 #define is_hybrid() static_branch_unlikely(&perf_is_hybrid) 689 690 #define hybrid(_pmu, _field) \ 691 (*({ \ 692 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \ 693 \ 694 if (is_hybrid() && (_pmu)) \ 695 __Fp = &hybrid_pmu(_pmu)->_field; \ 696 \ 697 __Fp; \ 698 })) 699 700 #define hybrid_var(_pmu, _var) \ 701 (*({ \ 702 typeof(&_var) __Fp = &_var; \ 703 \ 704 if (is_hybrid() && (_pmu)) \ 705 __Fp = &hybrid_pmu(_pmu)->_var; \ 706 \ 707 __Fp; \ 708 })) 709 710 #define hybrid_bit(_pmu, _field) \ 711 ({ \ 712 bool __Fp = x86_pmu._field; \ 713 \ 714 if (is_hybrid() && (_pmu)) \ 715 __Fp = hybrid_pmu(_pmu)->_field; \ 716 \ 717 __Fp; \ 718 }) 719 720 enum hybrid_pmu_type { 721 hybrid_big = 0x40, 722 hybrid_small = 0x20, 723 724 hybrid_big_small = hybrid_big | hybrid_small, 725 }; 726 727 #define X86_HYBRID_PMU_ATOM_IDX 0 728 #define X86_HYBRID_PMU_CORE_IDX 1 729 730 #define X86_HYBRID_NUM_PMUS 2 731 732 /* 733 * struct x86_pmu - generic x86 pmu 734 */ 735 struct x86_pmu { 736 /* 737 * Generic x86 PMC bits 738 */ 739 const char *name; 740 int version; 741 int (*handle_irq)(struct pt_regs *); 742 void (*disable_all)(void); 743 void (*enable_all)(int added); 744 void (*enable)(struct perf_event *); 745 void (*disable)(struct perf_event *); 746 void (*assign)(struct perf_event *event, int idx); 747 void (*add)(struct perf_event *); 748 void (*del)(struct perf_event *); 749 void (*read)(struct perf_event *event); 750 int (*set_period)(struct perf_event *event); 751 u64 (*update)(struct perf_event *event); 752 int (*hw_config)(struct perf_event *event); 753 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); 754 unsigned eventsel; 755 unsigned perfctr; 756 int (*addr_offset)(int index, bool eventsel); 757 int (*rdpmc_index)(int index); 758 u64 (*event_map)(int); 759 int max_events; 760 int num_counters; 761 int num_counters_fixed; 762 int cntval_bits; 763 u64 cntval_mask; 764 union { 765 unsigned long events_maskl; 766 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; 767 }; 768 int events_mask_len; 769 int apic; 770 u64 max_period; 771 struct event_constraint * 772 (*get_event_constraints)(struct cpu_hw_events *cpuc, 773 int idx, 774 struct perf_event *event); 775 776 void (*put_event_constraints)(struct cpu_hw_events *cpuc, 777 struct perf_event *event); 778 779 void (*start_scheduling)(struct cpu_hw_events *cpuc); 780 781 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); 782 783 void (*stop_scheduling)(struct cpu_hw_events *cpuc); 784 785 struct event_constraint *event_constraints; 786 struct x86_pmu_quirk *quirks; 787 void (*limit_period)(struct perf_event *event, s64 *l); 788 789 /* PMI handler bits */ 790 unsigned int late_ack :1, 791 mid_ack :1, 792 enabled_ack :1; 793 /* 794 * sysfs attrs 795 */ 796 int attr_rdpmc_broken; 797 int attr_rdpmc; 798 struct attribute **format_attrs; 799 800 ssize_t (*events_sysfs_show)(char *page, u64 config); 801 const struct attribute_group **attr_update; 802 803 unsigned long attr_freeze_on_smi; 804 805 /* 806 * CPU Hotplug hooks 807 */ 808 int (*cpu_prepare)(int cpu); 809 void (*cpu_starting)(int cpu); 810 void (*cpu_dying)(int cpu); 811 void (*cpu_dead)(int cpu); 812 813 void (*check_microcode)(void); 814 void (*sched_task)(struct perf_event_pmu_context *pmu_ctx, 815 bool sched_in); 816 817 /* 818 * Intel Arch Perfmon v2+ 819 */ 820 u64 intel_ctrl; 821 union perf_capabilities intel_cap; 822 823 /* 824 * Intel DebugStore bits 825 */ 826 unsigned int bts :1, 827 bts_active :1, 828 pebs :1, 829 pebs_active :1, 830 pebs_broken :1, 831 pebs_prec_dist :1, 832 pebs_no_tlb :1, 833 pebs_no_isolation :1, 834 pebs_block :1, 835 pebs_ept :1; 836 int pebs_record_size; 837 int pebs_buffer_size; 838 int max_pebs_events; 839 void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data); 840 struct event_constraint *pebs_constraints; 841 void (*pebs_aliases)(struct perf_event *event); 842 u64 (*pebs_latency_data)(struct perf_event *event, u64 status); 843 unsigned long large_pebs_flags; 844 u64 rtm_abort_event; 845 u64 pebs_capable; 846 847 /* 848 * Intel LBR 849 */ 850 unsigned int lbr_tos, lbr_from, lbr_to, 851 lbr_info, lbr_nr; /* LBR base regs and size */ 852 union { 853 u64 lbr_sel_mask; /* LBR_SELECT valid bits */ 854 u64 lbr_ctl_mask; /* LBR_CTL valid bits */ 855 }; 856 union { 857 const int *lbr_sel_map; /* lbr_select mappings */ 858 int *lbr_ctl_map; /* LBR_CTL mappings */ 859 }; 860 bool lbr_double_abort; /* duplicated lbr aborts */ 861 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ 862 863 unsigned int lbr_has_info:1; 864 unsigned int lbr_has_tsx:1; 865 unsigned int lbr_from_flags:1; 866 unsigned int lbr_to_cycles:1; 867 868 /* 869 * Intel Architectural LBR CPUID Enumeration 870 */ 871 unsigned int lbr_depth_mask:8; 872 unsigned int lbr_deep_c_reset:1; 873 unsigned int lbr_lip:1; 874 unsigned int lbr_cpl:1; 875 unsigned int lbr_filter:1; 876 unsigned int lbr_call_stack:1; 877 unsigned int lbr_mispred:1; 878 unsigned int lbr_timed_lbr:1; 879 unsigned int lbr_br_type:1; 880 881 void (*lbr_reset)(void); 882 void (*lbr_read)(struct cpu_hw_events *cpuc); 883 void (*lbr_save)(void *ctx); 884 void (*lbr_restore)(void *ctx); 885 886 /* 887 * Intel PT/LBR/BTS are exclusive 888 */ 889 atomic_t lbr_exclusive[x86_lbr_exclusive_max]; 890 891 /* 892 * Intel perf metrics 893 */ 894 int num_topdown_events; 895 896 /* 897 * perf task context (i.e. struct perf_event_pmu_context::task_ctx_data) 898 * switch helper to bridge calls from perf/core to perf/x86. 899 * See struct pmu::swap_task_ctx() usage for examples; 900 */ 901 void (*swap_task_ctx)(struct perf_event_pmu_context *prev_epc, 902 struct perf_event_pmu_context *next_epc); 903 904 /* 905 * AMD bits 906 */ 907 unsigned int amd_nb_constraints : 1; 908 u64 perf_ctr_pair_en; 909 910 /* 911 * Extra registers for events 912 */ 913 struct extra_reg *extra_regs; 914 unsigned int flags; 915 916 /* 917 * Intel host/guest support (KVM) 918 */ 919 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr, void *data); 920 921 /* 922 * Check period value for PERF_EVENT_IOC_PERIOD ioctl. 923 */ 924 int (*check_period) (struct perf_event *event, u64 period); 925 926 int (*aux_output_match) (struct perf_event *event); 927 928 void (*filter)(struct pmu *pmu, int cpu, bool *ret); 929 /* 930 * Hybrid support 931 * 932 * Most PMU capabilities are the same among different hybrid PMUs. 933 * The global x86_pmu saves the architecture capabilities, which 934 * are available for all PMUs. The hybrid_pmu only includes the 935 * unique capabilities. 936 */ 937 int num_hybrid_pmus; 938 struct x86_hybrid_pmu *hybrid_pmu; 939 u8 (*get_hybrid_cpu_type) (void); 940 }; 941 942 struct x86_perf_task_context_opt { 943 int lbr_callstack_users; 944 int lbr_stack_state; 945 int log_id; 946 }; 947 948 struct x86_perf_task_context { 949 u64 lbr_sel; 950 int tos; 951 int valid_lbrs; 952 struct x86_perf_task_context_opt opt; 953 struct lbr_entry lbr[MAX_LBR_ENTRIES]; 954 }; 955 956 struct x86_perf_task_context_arch_lbr { 957 struct x86_perf_task_context_opt opt; 958 struct lbr_entry entries[]; 959 }; 960 961 /* 962 * Add padding to guarantee the 64-byte alignment of the state buffer. 963 * 964 * The structure is dynamically allocated. The size of the LBR state may vary 965 * based on the number of LBR registers. 966 * 967 * Do not put anything after the LBR state. 968 */ 969 struct x86_perf_task_context_arch_lbr_xsave { 970 struct x86_perf_task_context_opt opt; 971 972 union { 973 struct xregs_state xsave; 974 struct { 975 struct fxregs_state i387; 976 struct xstate_header header; 977 struct arch_lbr_state lbr; 978 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT))); 979 }; 980 }; 981 982 #define x86_add_quirk(func_) \ 983 do { \ 984 static struct x86_pmu_quirk __quirk __initdata = { \ 985 .func = func_, \ 986 }; \ 987 __quirk.next = x86_pmu.quirks; \ 988 x86_pmu.quirks = &__quirk; \ 989 } while (0) 990 991 /* 992 * x86_pmu flags 993 */ 994 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ 995 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ 996 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ 997 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ 998 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */ 999 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */ 1000 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */ 1001 #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */ 1002 #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */ 1003 1004 #define EVENT_VAR(_id) event_attr_##_id 1005 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr 1006 1007 #define EVENT_ATTR(_name, _id) \ 1008 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ 1009 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 1010 .id = PERF_COUNT_HW_##_id, \ 1011 .event_str = NULL, \ 1012 }; 1013 1014 #define EVENT_ATTR_STR(_name, v, str) \ 1015 static struct perf_pmu_events_attr event_attr_##v = { \ 1016 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 1017 .id = 0, \ 1018 .event_str = str, \ 1019 }; 1020 1021 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \ 1022 static struct perf_pmu_events_ht_attr event_attr_##v = { \ 1023 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\ 1024 .id = 0, \ 1025 .event_str_noht = noht, \ 1026 .event_str_ht = ht, \ 1027 } 1028 1029 #define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \ 1030 static struct perf_pmu_events_hybrid_attr event_attr_##v = { \ 1031 .attr = __ATTR(_name, 0444, events_hybrid_sysfs_show, NULL),\ 1032 .id = 0, \ 1033 .event_str = str, \ 1034 .pmu_type = _pmu, \ 1035 } 1036 1037 #define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr) 1038 1039 #define FORMAT_ATTR_HYBRID(_name, _pmu) \ 1040 static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\ 1041 .attr = __ATTR_RO(_name), \ 1042 .pmu_type = _pmu, \ 1043 } 1044 1045 struct pmu *x86_get_pmu(unsigned int cpu); 1046 extern struct x86_pmu x86_pmu __read_mostly; 1047 1048 DECLARE_STATIC_CALL(x86_pmu_set_period, *x86_pmu.set_period); 1049 DECLARE_STATIC_CALL(x86_pmu_update, *x86_pmu.update); 1050 1051 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx) 1052 { 1053 if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 1054 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt; 1055 1056 return &((struct x86_perf_task_context *)ctx)->opt; 1057 } 1058 1059 static inline bool x86_pmu_has_lbr_callstack(void) 1060 { 1061 return x86_pmu.lbr_sel_map && 1062 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; 1063 } 1064 1065 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 1066 DECLARE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); 1067 1068 int x86_perf_event_set_period(struct perf_event *event); 1069 1070 /* 1071 * Generalized hw caching related hw_event table, filled 1072 * in on a per model basis. A value of 0 means 1073 * 'not supported', -1 means 'hw_event makes no sense on 1074 * this CPU', any other value means the raw hw_event 1075 * ID. 1076 */ 1077 1078 #define C(x) PERF_COUNT_HW_CACHE_##x 1079 1080 extern u64 __read_mostly hw_cache_event_ids 1081 [PERF_COUNT_HW_CACHE_MAX] 1082 [PERF_COUNT_HW_CACHE_OP_MAX] 1083 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1084 extern u64 __read_mostly hw_cache_extra_regs 1085 [PERF_COUNT_HW_CACHE_MAX] 1086 [PERF_COUNT_HW_CACHE_OP_MAX] 1087 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1088 1089 u64 x86_perf_event_update(struct perf_event *event); 1090 1091 static inline unsigned int x86_pmu_config_addr(int index) 1092 { 1093 return x86_pmu.eventsel + (x86_pmu.addr_offset ? 1094 x86_pmu.addr_offset(index, true) : index); 1095 } 1096 1097 static inline unsigned int x86_pmu_event_addr(int index) 1098 { 1099 return x86_pmu.perfctr + (x86_pmu.addr_offset ? 1100 x86_pmu.addr_offset(index, false) : index); 1101 } 1102 1103 static inline int x86_pmu_rdpmc_index(int index) 1104 { 1105 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; 1106 } 1107 1108 bool check_hw_exists(struct pmu *pmu, int num_counters, 1109 int num_counters_fixed); 1110 1111 int x86_add_exclusive(unsigned int what); 1112 1113 void x86_del_exclusive(unsigned int what); 1114 1115 int x86_reserve_hardware(void); 1116 1117 void x86_release_hardware(void); 1118 1119 int x86_pmu_max_precise(void); 1120 1121 void hw_perf_lbr_event_destroy(struct perf_event *event); 1122 1123 int x86_setup_perfctr(struct perf_event *event); 1124 1125 int x86_pmu_hw_config(struct perf_event *event); 1126 1127 void x86_pmu_disable_all(void); 1128 1129 static inline bool has_amd_brs(struct hw_perf_event *hwc) 1130 { 1131 return hwc->flags & PERF_X86_EVENT_AMD_BRS; 1132 } 1133 1134 static inline bool is_counter_pair(struct hw_perf_event *hwc) 1135 { 1136 return hwc->flags & PERF_X86_EVENT_PAIR; 1137 } 1138 1139 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, 1140 u64 enable_mask) 1141 { 1142 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1143 1144 if (hwc->extra_reg.reg) 1145 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); 1146 1147 /* 1148 * Add enabled Merge event on next counter 1149 * if large increment event being enabled on this counter 1150 */ 1151 if (is_counter_pair(hwc)) 1152 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); 1153 1154 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 1155 } 1156 1157 void x86_pmu_enable_all(int added); 1158 1159 int perf_assign_events(struct event_constraint **constraints, int n, 1160 int wmin, int wmax, int gpmax, int *assign); 1161 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); 1162 1163 void x86_pmu_stop(struct perf_event *event, int flags); 1164 1165 static inline void x86_pmu_disable_event(struct perf_event *event) 1166 { 1167 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1168 struct hw_perf_event *hwc = &event->hw; 1169 1170 wrmsrl(hwc->config_base, hwc->config & ~disable_mask); 1171 1172 if (is_counter_pair(hwc)) 1173 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0); 1174 } 1175 1176 void x86_pmu_enable_event(struct perf_event *event); 1177 1178 int x86_pmu_handle_irq(struct pt_regs *regs); 1179 1180 void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed, 1181 u64 intel_ctrl); 1182 1183 extern struct event_constraint emptyconstraint; 1184 1185 extern struct event_constraint unconstrained; 1186 1187 static inline bool kernel_ip(unsigned long ip) 1188 { 1189 #ifdef CONFIG_X86_32 1190 return ip > PAGE_OFFSET; 1191 #else 1192 return (long)ip < 0; 1193 #endif 1194 } 1195 1196 /* 1197 * Not all PMUs provide the right context information to place the reported IP 1198 * into full context. Specifically segment registers are typically not 1199 * supplied. 1200 * 1201 * Assuming the address is a linear address (it is for IBS), we fake the CS and 1202 * vm86 mode using the known zero-based code segment and 'fix up' the registers 1203 * to reflect this. 1204 * 1205 * Intel PEBS/LBR appear to typically provide the effective address, nothing 1206 * much we can do about that but pray and treat it like a linear address. 1207 */ 1208 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) 1209 { 1210 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; 1211 if (regs->flags & X86_VM_MASK) 1212 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); 1213 regs->ip = ip; 1214 } 1215 1216 /* 1217 * x86control flow change classification 1218 * x86control flow changes include branches, interrupts, traps, faults 1219 */ 1220 enum { 1221 X86_BR_NONE = 0, /* unknown */ 1222 1223 X86_BR_USER = 1 << 0, /* branch target is user */ 1224 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */ 1225 1226 X86_BR_CALL = 1 << 2, /* call */ 1227 X86_BR_RET = 1 << 3, /* return */ 1228 X86_BR_SYSCALL = 1 << 4, /* syscall */ 1229 X86_BR_SYSRET = 1 << 5, /* syscall return */ 1230 X86_BR_INT = 1 << 6, /* sw interrupt */ 1231 X86_BR_IRET = 1 << 7, /* return from interrupt */ 1232 X86_BR_JCC = 1 << 8, /* conditional */ 1233 X86_BR_JMP = 1 << 9, /* jump */ 1234 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */ 1235 X86_BR_IND_CALL = 1 << 11,/* indirect calls */ 1236 X86_BR_ABORT = 1 << 12,/* transaction abort */ 1237 X86_BR_IN_TX = 1 << 13,/* in transaction */ 1238 X86_BR_NO_TX = 1 << 14,/* not in transaction */ 1239 X86_BR_ZERO_CALL = 1 << 15,/* zero length call */ 1240 X86_BR_CALL_STACK = 1 << 16,/* call stack */ 1241 X86_BR_IND_JMP = 1 << 17,/* indirect jump */ 1242 1243 X86_BR_TYPE_SAVE = 1 << 18,/* indicate to save branch type */ 1244 1245 }; 1246 1247 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL) 1248 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX) 1249 1250 #define X86_BR_ANY \ 1251 (X86_BR_CALL |\ 1252 X86_BR_RET |\ 1253 X86_BR_SYSCALL |\ 1254 X86_BR_SYSRET |\ 1255 X86_BR_INT |\ 1256 X86_BR_IRET |\ 1257 X86_BR_JCC |\ 1258 X86_BR_JMP |\ 1259 X86_BR_IRQ |\ 1260 X86_BR_ABORT |\ 1261 X86_BR_IND_CALL |\ 1262 X86_BR_IND_JMP |\ 1263 X86_BR_ZERO_CALL) 1264 1265 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY) 1266 1267 #define X86_BR_ANY_CALL \ 1268 (X86_BR_CALL |\ 1269 X86_BR_IND_CALL |\ 1270 X86_BR_ZERO_CALL |\ 1271 X86_BR_SYSCALL |\ 1272 X86_BR_IRQ |\ 1273 X86_BR_INT) 1274 1275 int common_branch_type(int type); 1276 int branch_type(unsigned long from, unsigned long to, int abort); 1277 int branch_type_fused(unsigned long from, unsigned long to, int abort, 1278 int *offset); 1279 1280 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); 1281 ssize_t intel_event_sysfs_show(char *page, u64 config); 1282 1283 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, 1284 char *page); 1285 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 1286 char *page); 1287 ssize_t events_hybrid_sysfs_show(struct device *dev, 1288 struct device_attribute *attr, 1289 char *page); 1290 1291 static inline bool fixed_counter_disabled(int i, struct pmu *pmu) 1292 { 1293 u64 intel_ctrl = hybrid(pmu, intel_ctrl); 1294 1295 return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED)); 1296 } 1297 1298 #ifdef CONFIG_CPU_SUP_AMD 1299 1300 int amd_pmu_init(void); 1301 1302 int amd_pmu_lbr_init(void); 1303 void amd_pmu_lbr_reset(void); 1304 void amd_pmu_lbr_read(void); 1305 void amd_pmu_lbr_add(struct perf_event *event); 1306 void amd_pmu_lbr_del(struct perf_event *event); 1307 void amd_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in); 1308 void amd_pmu_lbr_enable_all(void); 1309 void amd_pmu_lbr_disable_all(void); 1310 int amd_pmu_lbr_hw_config(struct perf_event *event); 1311 1312 #ifdef CONFIG_PERF_EVENTS_AMD_BRS 1313 1314 #define AMD_FAM19H_BRS_EVENT 0xc4 /* RETIRED_TAKEN_BRANCH_INSTRUCTIONS */ 1315 1316 int amd_brs_init(void); 1317 void amd_brs_disable(void); 1318 void amd_brs_enable(void); 1319 void amd_brs_enable_all(void); 1320 void amd_brs_disable_all(void); 1321 void amd_brs_drain(void); 1322 void amd_brs_lopwr_init(void); 1323 int amd_brs_hw_config(struct perf_event *event); 1324 void amd_brs_reset(void); 1325 1326 static inline void amd_pmu_brs_add(struct perf_event *event) 1327 { 1328 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1329 1330 perf_sched_cb_inc(event->pmu); 1331 cpuc->lbr_users++; 1332 /* 1333 * No need to reset BRS because it is reset 1334 * on brs_enable() and it is saturating 1335 */ 1336 } 1337 1338 static inline void amd_pmu_brs_del(struct perf_event *event) 1339 { 1340 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1341 1342 cpuc->lbr_users--; 1343 WARN_ON_ONCE(cpuc->lbr_users < 0); 1344 1345 perf_sched_cb_dec(event->pmu); 1346 } 1347 1348 void amd_pmu_brs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in); 1349 #else 1350 static inline int amd_brs_init(void) 1351 { 1352 return 0; 1353 } 1354 static inline void amd_brs_disable(void) {} 1355 static inline void amd_brs_enable(void) {} 1356 static inline void amd_brs_drain(void) {} 1357 static inline void amd_brs_lopwr_init(void) {} 1358 static inline void amd_brs_disable_all(void) {} 1359 static inline int amd_brs_hw_config(struct perf_event *event) 1360 { 1361 return 0; 1362 } 1363 static inline void amd_brs_reset(void) {} 1364 1365 static inline void amd_pmu_brs_add(struct perf_event *event) 1366 { 1367 } 1368 1369 static inline void amd_pmu_brs_del(struct perf_event *event) 1370 { 1371 } 1372 1373 static inline void amd_pmu_brs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in) 1374 { 1375 } 1376 1377 static inline void amd_brs_enable_all(void) 1378 { 1379 } 1380 1381 #endif 1382 1383 #else /* CONFIG_CPU_SUP_AMD */ 1384 1385 static inline int amd_pmu_init(void) 1386 { 1387 return 0; 1388 } 1389 1390 static inline int amd_brs_init(void) 1391 { 1392 return -EOPNOTSUPP; 1393 } 1394 1395 static inline void amd_brs_drain(void) 1396 { 1397 } 1398 1399 static inline void amd_brs_enable_all(void) 1400 { 1401 } 1402 1403 static inline void amd_brs_disable_all(void) 1404 { 1405 } 1406 #endif /* CONFIG_CPU_SUP_AMD */ 1407 1408 static inline int is_pebs_pt(struct perf_event *event) 1409 { 1410 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT); 1411 } 1412 1413 #ifdef CONFIG_CPU_SUP_INTEL 1414 1415 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period) 1416 { 1417 struct hw_perf_event *hwc = &event->hw; 1418 unsigned int hw_event, bts_event; 1419 1420 if (event->attr.freq) 1421 return false; 1422 1423 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 1424 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 1425 1426 return hw_event == bts_event && period == 1; 1427 } 1428 1429 static inline bool intel_pmu_has_bts(struct perf_event *event) 1430 { 1431 struct hw_perf_event *hwc = &event->hw; 1432 1433 return intel_pmu_has_bts_period(event, hwc->sample_period); 1434 } 1435 1436 static __always_inline void __intel_pmu_pebs_disable_all(void) 1437 { 1438 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 1439 } 1440 1441 static __always_inline void __intel_pmu_arch_lbr_disable(void) 1442 { 1443 wrmsrl(MSR_ARCH_LBR_CTL, 0); 1444 } 1445 1446 static __always_inline void __intel_pmu_lbr_disable(void) 1447 { 1448 u64 debugctl; 1449 1450 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1451 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 1452 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1453 } 1454 1455 int intel_pmu_save_and_restart(struct perf_event *event); 1456 1457 struct event_constraint * 1458 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 1459 struct perf_event *event); 1460 1461 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu); 1462 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc); 1463 1464 int intel_pmu_init(void); 1465 1466 void init_debug_store_on_cpu(int cpu); 1467 1468 void fini_debug_store_on_cpu(int cpu); 1469 1470 void release_ds_buffers(void); 1471 1472 void reserve_ds_buffers(void); 1473 1474 void release_lbr_buffers(void); 1475 1476 void reserve_lbr_buffers(void); 1477 1478 extern struct event_constraint bts_constraint; 1479 extern struct event_constraint vlbr_constraint; 1480 1481 void intel_pmu_enable_bts(u64 config); 1482 1483 void intel_pmu_disable_bts(void); 1484 1485 int intel_pmu_drain_bts_buffer(void); 1486 1487 u64 adl_latency_data_small(struct perf_event *event, u64 status); 1488 1489 extern struct event_constraint intel_core2_pebs_event_constraints[]; 1490 1491 extern struct event_constraint intel_atom_pebs_event_constraints[]; 1492 1493 extern struct event_constraint intel_slm_pebs_event_constraints[]; 1494 1495 extern struct event_constraint intel_glm_pebs_event_constraints[]; 1496 1497 extern struct event_constraint intel_glp_pebs_event_constraints[]; 1498 1499 extern struct event_constraint intel_grt_pebs_event_constraints[]; 1500 1501 extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 1502 1503 extern struct event_constraint intel_westmere_pebs_event_constraints[]; 1504 1505 extern struct event_constraint intel_snb_pebs_event_constraints[]; 1506 1507 extern struct event_constraint intel_ivb_pebs_event_constraints[]; 1508 1509 extern struct event_constraint intel_hsw_pebs_event_constraints[]; 1510 1511 extern struct event_constraint intel_bdw_pebs_event_constraints[]; 1512 1513 extern struct event_constraint intel_skl_pebs_event_constraints[]; 1514 1515 extern struct event_constraint intel_icl_pebs_event_constraints[]; 1516 1517 extern struct event_constraint intel_spr_pebs_event_constraints[]; 1518 1519 struct event_constraint *intel_pebs_constraints(struct perf_event *event); 1520 1521 void intel_pmu_pebs_add(struct perf_event *event); 1522 1523 void intel_pmu_pebs_del(struct perf_event *event); 1524 1525 void intel_pmu_pebs_enable(struct perf_event *event); 1526 1527 void intel_pmu_pebs_disable(struct perf_event *event); 1528 1529 void intel_pmu_pebs_enable_all(void); 1530 1531 void intel_pmu_pebs_disable_all(void); 1532 1533 void intel_pmu_pebs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in); 1534 1535 void intel_pmu_auto_reload_read(struct perf_event *event); 1536 1537 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr); 1538 1539 void intel_ds_init(void); 1540 1541 void intel_pmu_lbr_swap_task_ctx(struct perf_event_pmu_context *prev_epc, 1542 struct perf_event_pmu_context *next_epc); 1543 1544 void intel_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in); 1545 1546 u64 lbr_from_signext_quirk_wr(u64 val); 1547 1548 void intel_pmu_lbr_reset(void); 1549 1550 void intel_pmu_lbr_reset_32(void); 1551 1552 void intel_pmu_lbr_reset_64(void); 1553 1554 void intel_pmu_lbr_add(struct perf_event *event); 1555 1556 void intel_pmu_lbr_del(struct perf_event *event); 1557 1558 void intel_pmu_lbr_enable_all(bool pmi); 1559 1560 void intel_pmu_lbr_disable_all(void); 1561 1562 void intel_pmu_lbr_read(void); 1563 1564 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc); 1565 1566 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc); 1567 1568 void intel_pmu_lbr_save(void *ctx); 1569 1570 void intel_pmu_lbr_restore(void *ctx); 1571 1572 void intel_pmu_lbr_init_core(void); 1573 1574 void intel_pmu_lbr_init_nhm(void); 1575 1576 void intel_pmu_lbr_init_atom(void); 1577 1578 void intel_pmu_lbr_init_slm(void); 1579 1580 void intel_pmu_lbr_init_snb(void); 1581 1582 void intel_pmu_lbr_init_hsw(void); 1583 1584 void intel_pmu_lbr_init_skl(void); 1585 1586 void intel_pmu_lbr_init_knl(void); 1587 1588 void intel_pmu_lbr_init(void); 1589 1590 void intel_pmu_arch_lbr_init(void); 1591 1592 void intel_pmu_pebs_data_source_nhm(void); 1593 1594 void intel_pmu_pebs_data_source_skl(bool pmem); 1595 1596 void intel_pmu_pebs_data_source_adl(void); 1597 1598 void intel_pmu_pebs_data_source_grt(void); 1599 1600 int intel_pmu_setup_lbr_filter(struct perf_event *event); 1601 1602 void intel_pt_interrupt(void); 1603 1604 int intel_bts_interrupt(void); 1605 1606 void intel_bts_enable_local(void); 1607 1608 void intel_bts_disable_local(void); 1609 1610 int p4_pmu_init(void); 1611 1612 int p6_pmu_init(void); 1613 1614 int knc_pmu_init(void); 1615 1616 static inline int is_ht_workaround_enabled(void) 1617 { 1618 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); 1619 } 1620 1621 #else /* CONFIG_CPU_SUP_INTEL */ 1622 1623 static inline void reserve_ds_buffers(void) 1624 { 1625 } 1626 1627 static inline void release_ds_buffers(void) 1628 { 1629 } 1630 1631 static inline void release_lbr_buffers(void) 1632 { 1633 } 1634 1635 static inline void reserve_lbr_buffers(void) 1636 { 1637 } 1638 1639 static inline int intel_pmu_init(void) 1640 { 1641 return 0; 1642 } 1643 1644 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 1645 { 1646 return 0; 1647 } 1648 1649 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc) 1650 { 1651 } 1652 1653 static inline int is_ht_workaround_enabled(void) 1654 { 1655 return 0; 1656 } 1657 #endif /* CONFIG_CPU_SUP_INTEL */ 1658 1659 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN)) 1660 int zhaoxin_pmu_init(void); 1661 #else 1662 static inline int zhaoxin_pmu_init(void) 1663 { 1664 return 0; 1665 } 1666 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/ 1667