127f6d22bSBorislav Petkov /* 227f6d22bSBorislav Petkov * Performance events x86 architecture header 327f6d22bSBorislav Petkov * 427f6d22bSBorislav Petkov * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 527f6d22bSBorislav Petkov * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 627f6d22bSBorislav Petkov * Copyright (C) 2009 Jaswinder Singh Rajput 727f6d22bSBorislav Petkov * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 827f6d22bSBorislav Petkov * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 927f6d22bSBorislav Petkov * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 1027f6d22bSBorislav Petkov * Copyright (C) 2009 Google, Inc., Stephane Eranian 1127f6d22bSBorislav Petkov * 1227f6d22bSBorislav Petkov * For licencing details see kernel-base/COPYING 1327f6d22bSBorislav Petkov */ 1427f6d22bSBorislav Petkov 1527f6d22bSBorislav Petkov #include <linux/perf_event.h> 1627f6d22bSBorislav Petkov 17b50854ecSThomas Gleixner #include <asm/fpu/xstate.h> 1810043e02SThomas Gleixner #include <asm/intel_ds.h> 19d9977c43SKan Liang #include <asm/cpu.h> 2010043e02SThomas Gleixner 2127f6d22bSBorislav Petkov /* To enable MSR tracing please use the generic trace points. */ 2227f6d22bSBorislav Petkov 2327f6d22bSBorislav Petkov /* 2427f6d22bSBorislav Petkov * | NHM/WSM | SNB | 2527f6d22bSBorislav Petkov * register ------------------------------- 2627f6d22bSBorislav Petkov * | HT | no HT | HT | no HT | 2727f6d22bSBorislav Petkov *----------------------------------------- 2827f6d22bSBorislav Petkov * offcore | core | core | cpu | core | 2927f6d22bSBorislav Petkov * lbr_sel | core | core | cpu | core | 3027f6d22bSBorislav Petkov * ld_lat | cpu | core | cpu | core | 3127f6d22bSBorislav Petkov *----------------------------------------- 3227f6d22bSBorislav Petkov * 3327f6d22bSBorislav Petkov * Given that there is a small number of shared regs, 3427f6d22bSBorislav Petkov * we can pre-allocate their slot in the per-cpu 3527f6d22bSBorislav Petkov * per-core reg tables. 3627f6d22bSBorislav Petkov */ 3727f6d22bSBorislav Petkov enum extra_reg_type { 3827f6d22bSBorislav Petkov EXTRA_REG_NONE = -1, /* not used */ 3927f6d22bSBorislav Petkov 4027f6d22bSBorislav Petkov EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ 4127f6d22bSBorislav Petkov EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ 4227f6d22bSBorislav Petkov EXTRA_REG_LBR = 2, /* lbr_select */ 4327f6d22bSBorislav Petkov EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ 4427f6d22bSBorislav Petkov EXTRA_REG_FE = 4, /* fe_* */ 4527f6d22bSBorislav Petkov 4627f6d22bSBorislav Petkov EXTRA_REG_MAX /* number of entries needed */ 4727f6d22bSBorislav Petkov }; 4827f6d22bSBorislav Petkov 4927f6d22bSBorislav Petkov struct event_constraint { 5027f6d22bSBorislav Petkov union { 5127f6d22bSBorislav Petkov unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 5227f6d22bSBorislav Petkov u64 idxmsk64; 5327f6d22bSBorislav Petkov }; 5427f6d22bSBorislav Petkov u64 code; 5527f6d22bSBorislav Petkov u64 cmask; 5627f6d22bSBorislav Petkov int weight; 5727f6d22bSBorislav Petkov int overlap; 5827f6d22bSBorislav Petkov int flags; 5963b79f6eSPeter Zijlstra unsigned int size; 6027f6d22bSBorislav Petkov }; 611f6a1e2dSPeter Zijlstra 6263b79f6eSPeter Zijlstra static inline bool constraint_match(struct event_constraint *c, u64 ecode) 6363b79f6eSPeter Zijlstra { 6463b79f6eSPeter Zijlstra return ((ecode & c->cmask) - c->code) <= (u64)c->size; 6563b79f6eSPeter Zijlstra } 6663b79f6eSPeter Zijlstra 6727f6d22bSBorislav Petkov /* 6827f6d22bSBorislav Petkov * struct hw_perf_event.flags flags 6927f6d22bSBorislav Petkov */ 70ada54345SStephane Eranian #define PERF_X86_EVENT_PEBS_LDLAT 0x00001 /* ld+ldlat data address sampling */ 71ada54345SStephane Eranian #define PERF_X86_EVENT_PEBS_ST 0x00002 /* st data address sampling */ 72ada54345SStephane Eranian #define PERF_X86_EVENT_PEBS_ST_HSW 0x00004 /* haswell style datala, store */ 73ada54345SStephane Eranian #define PERF_X86_EVENT_PEBS_LD_HSW 0x00008 /* haswell style datala, load */ 74ada54345SStephane Eranian #define PERF_X86_EVENT_PEBS_NA_HSW 0x00010 /* haswell style datala, unknown */ 75ada54345SStephane Eranian #define PERF_X86_EVENT_EXCL 0x00020 /* HT exclusivity on counter */ 76ada54345SStephane Eranian #define PERF_X86_EVENT_DYNAMIC 0x00040 /* dynamic alloc'd constraint */ 77369461ceSRob Herring 78ada54345SStephane Eranian #define PERF_X86_EVENT_EXCL_ACCT 0x00100 /* accounted EXCL event */ 79ada54345SStephane Eranian #define PERF_X86_EVENT_AUTO_RELOAD 0x00200 /* use PEBS auto-reload */ 80ada54345SStephane Eranian #define PERF_X86_EVENT_LARGE_PEBS 0x00400 /* use large PEBS */ 81ada54345SStephane Eranian #define PERF_X86_EVENT_PEBS_VIA_PT 0x00800 /* use PT buffer for PEBS */ 82ada54345SStephane Eranian #define PERF_X86_EVENT_PAIR 0x01000 /* Large Increment per Cycle */ 83ada54345SStephane Eranian #define PERF_X86_EVENT_LBR_SELECT 0x02000 /* Save/Restore MSR_LBR_SELECT */ 84ada54345SStephane Eranian #define PERF_X86_EVENT_TOPDOWN 0x04000 /* Count Topdown slots/metrics events */ 85ada54345SStephane Eranian #define PERF_X86_EVENT_PEBS_STLAT 0x08000 /* st+stlat data address sampling */ 86ada54345SStephane Eranian #define PERF_X86_EVENT_AMD_BRS 0x10000 /* AMD Branch Sampling */ 877b2c05a1SKan Liang 887b2c05a1SKan Liang static inline bool is_topdown_count(struct perf_event *event) 897b2c05a1SKan Liang { 907b2c05a1SKan Liang return event->hw.flags & PERF_X86_EVENT_TOPDOWN; 917b2c05a1SKan Liang } 927b2c05a1SKan Liang 937b2c05a1SKan Liang static inline bool is_metric_event(struct perf_event *event) 947b2c05a1SKan Liang { 957b2c05a1SKan Liang u64 config = event->attr.config; 967b2c05a1SKan Liang 977b2c05a1SKan Liang return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) && 987b2c05a1SKan Liang ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) && 997b2c05a1SKan Liang ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX); 1007b2c05a1SKan Liang } 1017b2c05a1SKan Liang 1027b2c05a1SKan Liang static inline bool is_slots_event(struct perf_event *event) 1037b2c05a1SKan Liang { 1047b2c05a1SKan Liang return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS; 1057b2c05a1SKan Liang } 1067b2c05a1SKan Liang 1077b2c05a1SKan Liang static inline bool is_topdown_event(struct perf_event *event) 1087b2c05a1SKan Liang { 1097b2c05a1SKan Liang return is_metric_event(event) || is_slots_event(event); 1107b2c05a1SKan Liang } 11127f6d22bSBorislav Petkov 11227f6d22bSBorislav Petkov struct amd_nb { 11327f6d22bSBorislav Petkov int nb_id; /* NorthBridge id */ 11427f6d22bSBorislav Petkov int refcnt; /* reference count */ 11527f6d22bSBorislav Petkov struct perf_event *owners[X86_PMC_IDX_MAX]; 11627f6d22bSBorislav Petkov struct event_constraint event_constraints[X86_PMC_IDX_MAX]; 11727f6d22bSBorislav Petkov }; 11827f6d22bSBorislav Petkov 119fd583ad1SKan Liang #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) 12042880f72SAlexander Shishkin #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60) 12142880f72SAlexander Shishkin #define PEBS_OUTPUT_OFFSET 61 12242880f72SAlexander Shishkin #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET) 12342880f72SAlexander Shishkin #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET) 12442880f72SAlexander Shishkin #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD) 12527f6d22bSBorislav Petkov 12627f6d22bSBorislav Petkov /* 12727f6d22bSBorislav Petkov * Flags PEBS can handle without an PMI. 12827f6d22bSBorislav Petkov * 12927f6d22bSBorislav Petkov * TID can only be handled by flushing at context switch. 1302fe1bc1fSAndi Kleen * REGS_USER can be handled for events limited to ring 3. 13127f6d22bSBorislav Petkov * 13227f6d22bSBorislav Petkov */ 133174afc3eSKan Liang #define LARGE_PEBS_FLAGS \ 13427f6d22bSBorislav Petkov (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 13527f6d22bSBorislav Petkov PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 13627f6d22bSBorislav Petkov PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 1372fe1bc1fSAndi Kleen PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ 13811974914SJiri Olsa PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \ 139995f088eSStephane Eranian PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE) 14027f6d22bSBorislav Petkov 1419d5dcc93SKan Liang #define PEBS_GP_REGS \ 1429d5dcc93SKan Liang ((1ULL << PERF_REG_X86_AX) | \ 1439d5dcc93SKan Liang (1ULL << PERF_REG_X86_BX) | \ 1449d5dcc93SKan Liang (1ULL << PERF_REG_X86_CX) | \ 1459d5dcc93SKan Liang (1ULL << PERF_REG_X86_DX) | \ 1469d5dcc93SKan Liang (1ULL << PERF_REG_X86_DI) | \ 1479d5dcc93SKan Liang (1ULL << PERF_REG_X86_SI) | \ 1489d5dcc93SKan Liang (1ULL << PERF_REG_X86_SP) | \ 1499d5dcc93SKan Liang (1ULL << PERF_REG_X86_BP) | \ 1509d5dcc93SKan Liang (1ULL << PERF_REG_X86_IP) | \ 1519d5dcc93SKan Liang (1ULL << PERF_REG_X86_FLAGS) | \ 1529d5dcc93SKan Liang (1ULL << PERF_REG_X86_R8) | \ 1539d5dcc93SKan Liang (1ULL << PERF_REG_X86_R9) | \ 1549d5dcc93SKan Liang (1ULL << PERF_REG_X86_R10) | \ 1559d5dcc93SKan Liang (1ULL << PERF_REG_X86_R11) | \ 1569d5dcc93SKan Liang (1ULL << PERF_REG_X86_R12) | \ 1579d5dcc93SKan Liang (1ULL << PERF_REG_X86_R13) | \ 1589d5dcc93SKan Liang (1ULL << PERF_REG_X86_R14) | \ 1599d5dcc93SKan Liang (1ULL << PERF_REG_X86_R15)) 1602fe1bc1fSAndi Kleen 16127f6d22bSBorislav Petkov /* 16227f6d22bSBorislav Petkov * Per register state. 16327f6d22bSBorislav Petkov */ 16427f6d22bSBorislav Petkov struct er_account { 16527f6d22bSBorislav Petkov raw_spinlock_t lock; /* per-core: protect structure */ 16627f6d22bSBorislav Petkov u64 config; /* extra MSR config */ 16727f6d22bSBorislav Petkov u64 reg; /* extra MSR number */ 16827f6d22bSBorislav Petkov atomic_t ref; /* reference count */ 16927f6d22bSBorislav Petkov }; 17027f6d22bSBorislav Petkov 17127f6d22bSBorislav Petkov /* 17227f6d22bSBorislav Petkov * Per core/cpu state 17327f6d22bSBorislav Petkov * 17427f6d22bSBorislav Petkov * Used to coordinate shared registers between HT threads or 17527f6d22bSBorislav Petkov * among events on a single PMU. 17627f6d22bSBorislav Petkov */ 17727f6d22bSBorislav Petkov struct intel_shared_regs { 17827f6d22bSBorislav Petkov struct er_account regs[EXTRA_REG_MAX]; 17927f6d22bSBorislav Petkov int refcnt; /* per-core: #HT threads */ 18027f6d22bSBorislav Petkov unsigned core_id; /* per-core: core id */ 18127f6d22bSBorislav Petkov }; 18227f6d22bSBorislav Petkov 18327f6d22bSBorislav Petkov enum intel_excl_state_type { 18427f6d22bSBorislav Petkov INTEL_EXCL_UNUSED = 0, /* counter is unused */ 18527f6d22bSBorislav Petkov INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ 18627f6d22bSBorislav Petkov INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ 18727f6d22bSBorislav Petkov }; 18827f6d22bSBorislav Petkov 18927f6d22bSBorislav Petkov struct intel_excl_states { 19027f6d22bSBorislav Petkov enum intel_excl_state_type state[X86_PMC_IDX_MAX]; 19127f6d22bSBorislav Petkov bool sched_started; /* true if scheduling has started */ 19227f6d22bSBorislav Petkov }; 19327f6d22bSBorislav Petkov 19427f6d22bSBorislav Petkov struct intel_excl_cntrs { 19527f6d22bSBorislav Petkov raw_spinlock_t lock; 19627f6d22bSBorislav Petkov 19727f6d22bSBorislav Petkov struct intel_excl_states states[2]; 19827f6d22bSBorislav Petkov 19927f6d22bSBorislav Petkov union { 20027f6d22bSBorislav Petkov u16 has_exclusive[2]; 20127f6d22bSBorislav Petkov u32 exclusive_present; 20227f6d22bSBorislav Petkov }; 20327f6d22bSBorislav Petkov 20427f6d22bSBorislav Petkov int refcnt; /* per-core: #HT threads */ 20527f6d22bSBorislav Petkov unsigned core_id; /* per-core: core id */ 20627f6d22bSBorislav Petkov }; 20727f6d22bSBorislav Petkov 2088b077e4aSKan Liang struct x86_perf_task_context; 20927f6d22bSBorislav Petkov #define MAX_LBR_ENTRIES 32 21027f6d22bSBorislav Petkov 21127f6d22bSBorislav Petkov enum { 2129f354a72SKan Liang LBR_FORMAT_32 = 0x00, 2139f354a72SKan Liang LBR_FORMAT_LIP = 0x01, 2149f354a72SKan Liang LBR_FORMAT_EIP = 0x02, 2159f354a72SKan Liang LBR_FORMAT_EIP_FLAGS = 0x03, 2169f354a72SKan Liang LBR_FORMAT_EIP_FLAGS2 = 0x04, 2179f354a72SKan Liang LBR_FORMAT_INFO = 0x05, 2189f354a72SKan Liang LBR_FORMAT_TIME = 0x06, 2191ac7fd81SPeter Zijlstra (Intel) LBR_FORMAT_INFO2 = 0x07, 2201ac7fd81SPeter Zijlstra (Intel) LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_INFO2, 2219f354a72SKan Liang }; 2229f354a72SKan Liang 2239f354a72SKan Liang enum { 22427f6d22bSBorislav Petkov X86_PERF_KFREE_SHARED = 0, 22527f6d22bSBorislav Petkov X86_PERF_KFREE_EXCL = 1, 22627f6d22bSBorislav Petkov X86_PERF_KFREE_MAX 22727f6d22bSBorislav Petkov }; 22827f6d22bSBorislav Petkov 22927f6d22bSBorislav Petkov struct cpu_hw_events { 23027f6d22bSBorislav Petkov /* 23127f6d22bSBorislav Petkov * Generic x86 PMC bits 23227f6d22bSBorislav Petkov */ 23327f6d22bSBorislav Petkov struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ 23427f6d22bSBorislav Petkov unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 2355471eea5SKan Liang unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 23627f6d22bSBorislav Petkov int enabled; 23727f6d22bSBorislav Petkov 23827f6d22bSBorislav Petkov int n_events; /* the # of events in the below arrays */ 23927f6d22bSBorislav Petkov int n_added; /* the # last events in the below arrays; 24027f6d22bSBorislav Petkov they've never been enabled yet */ 24127f6d22bSBorislav Petkov int n_txn; /* the # last events in the below arrays; 24227f6d22bSBorislav Petkov added in the current transaction */ 243871a93b0SPeter Zijlstra int n_txn_pair; 2443dbde695SPeter Zijlstra int n_txn_metric; 24527f6d22bSBorislav Petkov int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ 24627f6d22bSBorislav Petkov u64 tags[X86_PMC_IDX_MAX]; 24727f6d22bSBorislav Petkov 24827f6d22bSBorislav Petkov struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ 24927f6d22bSBorislav Petkov struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; 25027f6d22bSBorislav Petkov 25127f6d22bSBorislav Petkov int n_excl; /* the number of exclusive events */ 25227f6d22bSBorislav Petkov 25327f6d22bSBorislav Petkov unsigned int txn_flags; 25427f6d22bSBorislav Petkov int is_fake; 25527f6d22bSBorislav Petkov 25627f6d22bSBorislav Petkov /* 25727f6d22bSBorislav Petkov * Intel DebugStore bits 25827f6d22bSBorislav Petkov */ 25927f6d22bSBorislav Petkov struct debug_store *ds; 260c1961a46SHugh Dickins void *ds_pebs_vaddr; 261c1961a46SHugh Dickins void *ds_bts_vaddr; 26227f6d22bSBorislav Petkov u64 pebs_enabled; 26309e61b4fSPeter Zijlstra int n_pebs; 26409e61b4fSPeter Zijlstra int n_large_pebs; 26542880f72SAlexander Shishkin int n_pebs_via_pt; 26642880f72SAlexander Shishkin int pebs_output; 26727f6d22bSBorislav Petkov 268c22497f5SKan Liang /* Current super set of events hardware configuration */ 269c22497f5SKan Liang u64 pebs_data_cfg; 270c22497f5SKan Liang u64 active_pebs_data_cfg; 271c22497f5SKan Liang int pebs_record_size; 272c22497f5SKan Liang 27327f6d22bSBorislav Petkov /* 27427f6d22bSBorislav Petkov * Intel LBR bits 27527f6d22bSBorislav Petkov */ 27627f6d22bSBorislav Petkov int lbr_users; 277d3617b98SAndi Kleen int lbr_pebs_users; 27827f6d22bSBorislav Petkov struct perf_branch_stack lbr_stack; 27927f6d22bSBorislav Petkov struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; 28049d8184fSKan Liang union { 28127f6d22bSBorislav Petkov struct er_account *lbr_sel; 28249d8184fSKan Liang struct er_account *lbr_ctl; 28349d8184fSKan Liang }; 28427f6d22bSBorislav Petkov u64 br_sel; 285f42be865SKan Liang void *last_task_ctx; 2868b077e4aSKan Liang int last_log_id; 287e1ad1ac2SLike Xu int lbr_select; 288c085fb87SKan Liang void *lbr_xsave; 28927f6d22bSBorislav Petkov 29027f6d22bSBorislav Petkov /* 29127f6d22bSBorislav Petkov * Intel host/guest exclude bits 29227f6d22bSBorislav Petkov */ 29327f6d22bSBorislav Petkov u64 intel_ctrl_guest_mask; 29427f6d22bSBorislav Petkov u64 intel_ctrl_host_mask; 29527f6d22bSBorislav Petkov struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; 29627f6d22bSBorislav Petkov 29727f6d22bSBorislav Petkov /* 29827f6d22bSBorislav Petkov * Intel checkpoint mask 29927f6d22bSBorislav Petkov */ 30027f6d22bSBorislav Petkov u64 intel_cp_status; 30127f6d22bSBorislav Petkov 30227f6d22bSBorislav Petkov /* 30327f6d22bSBorislav Petkov * manage shared (per-core, per-cpu) registers 30427f6d22bSBorislav Petkov * used on Intel NHM/WSM/SNB 30527f6d22bSBorislav Petkov */ 30627f6d22bSBorislav Petkov struct intel_shared_regs *shared_regs; 30727f6d22bSBorislav Petkov /* 30827f6d22bSBorislav Petkov * manage exclusive counter access between hyperthread 30927f6d22bSBorislav Petkov */ 31027f6d22bSBorislav Petkov struct event_constraint *constraint_list; /* in enable order */ 31127f6d22bSBorislav Petkov struct intel_excl_cntrs *excl_cntrs; 31227f6d22bSBorislav Petkov int excl_thread_id; /* 0 or 1 */ 31327f6d22bSBorislav Petkov 31427f6d22bSBorislav Petkov /* 315400816f6SPeter Zijlstra (Intel) * SKL TSX_FORCE_ABORT shadow 316400816f6SPeter Zijlstra (Intel) */ 317400816f6SPeter Zijlstra (Intel) u64 tfa_shadow; 318400816f6SPeter Zijlstra (Intel) 319400816f6SPeter Zijlstra (Intel) /* 3207b2c05a1SKan Liang * Perf Metrics 3217b2c05a1SKan Liang */ 3227b2c05a1SKan Liang /* number of accepted metrics events */ 3237b2c05a1SKan Liang int n_metric; 3247b2c05a1SKan Liang 3257b2c05a1SKan Liang /* 32627f6d22bSBorislav Petkov * AMD specific bits 32727f6d22bSBorislav Petkov */ 32827f6d22bSBorislav Petkov struct amd_nb *amd_nb; 329ada54345SStephane Eranian int brs_active; /* BRS is enabled */ 330ada54345SStephane Eranian 33127f6d22bSBorislav Petkov /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ 33227f6d22bSBorislav Petkov u64 perf_ctr_virt_mask; 33357388912SKim Phillips int n_pair; /* Large increment events */ 33427f6d22bSBorislav Petkov 33527f6d22bSBorislav Petkov void *kfree_on_online[X86_PERF_KFREE_MAX]; 33661e76d53SKan Liang 33761e76d53SKan Liang struct pmu *pmu; 33827f6d22bSBorislav Petkov }; 33927f6d22bSBorislav Petkov 34063b79f6eSPeter Zijlstra #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \ 34127f6d22bSBorislav Petkov { .idxmsk64 = (n) }, \ 34227f6d22bSBorislav Petkov .code = (c), \ 34363b79f6eSPeter Zijlstra .size = (e) - (c), \ 34427f6d22bSBorislav Petkov .cmask = (m), \ 34527f6d22bSBorislav Petkov .weight = (w), \ 34627f6d22bSBorislav Petkov .overlap = (o), \ 34727f6d22bSBorislav Petkov .flags = f, \ 34827f6d22bSBorislav Petkov } 34927f6d22bSBorislav Petkov 35063b79f6eSPeter Zijlstra #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ 35163b79f6eSPeter Zijlstra __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f) 35263b79f6eSPeter Zijlstra 35327f6d22bSBorislav Petkov #define EVENT_CONSTRAINT(c, n, m) \ 35427f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) 35527f6d22bSBorislav Petkov 35663b79f6eSPeter Zijlstra /* 35763b79f6eSPeter Zijlstra * The constraint_match() function only works for 'simple' event codes 35863b79f6eSPeter Zijlstra * and not for extended (AMD64_EVENTSEL_EVENT) events codes. 35963b79f6eSPeter Zijlstra */ 36063b79f6eSPeter Zijlstra #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \ 36163b79f6eSPeter Zijlstra __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0) 36263b79f6eSPeter Zijlstra 36327f6d22bSBorislav Petkov #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ 36427f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ 36527f6d22bSBorislav Petkov 0, PERF_X86_EVENT_EXCL) 36627f6d22bSBorislav Petkov 36727f6d22bSBorislav Petkov /* 36827f6d22bSBorislav Petkov * The overlap flag marks event constraints with overlapping counter 36927f6d22bSBorislav Petkov * masks. This is the case if the counter mask of such an event is not 37027f6d22bSBorislav Petkov * a subset of any other counter mask of a constraint with an equal or 37127f6d22bSBorislav Petkov * higher weight, e.g.: 37227f6d22bSBorislav Petkov * 37327f6d22bSBorislav Petkov * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); 37427f6d22bSBorislav Petkov * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); 37527f6d22bSBorislav Petkov * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); 37627f6d22bSBorislav Petkov * 37727f6d22bSBorislav Petkov * The event scheduler may not select the correct counter in the first 37827f6d22bSBorislav Petkov * cycle because it needs to know which subsequent events will be 37927f6d22bSBorislav Petkov * scheduled. It may fail to schedule the events then. So we set the 38027f6d22bSBorislav Petkov * overlap flag for such constraints to give the scheduler a hint which 38127f6d22bSBorislav Petkov * events to select for counter rescheduling. 38227f6d22bSBorislav Petkov * 38327f6d22bSBorislav Petkov * Care must be taken as the rescheduling algorithm is O(n!) which 38400f52685SIngo Molnar * will increase scheduling cycles for an over-committed system 38527f6d22bSBorislav Petkov * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros 38627f6d22bSBorislav Petkov * and its counter masks must be kept at a minimum. 38727f6d22bSBorislav Petkov */ 38827f6d22bSBorislav Petkov #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ 38927f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) 39027f6d22bSBorislav Petkov 39127f6d22bSBorislav Petkov /* 39227f6d22bSBorislav Petkov * Constraint on the Event code. 39327f6d22bSBorislav Petkov */ 39427f6d22bSBorislav Petkov #define INTEL_EVENT_CONSTRAINT(c, n) \ 39527f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) 39627f6d22bSBorislav Petkov 39727f6d22bSBorislav Petkov /* 39863b79f6eSPeter Zijlstra * Constraint on a range of Event codes 39963b79f6eSPeter Zijlstra */ 40063b79f6eSPeter Zijlstra #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \ 40163b79f6eSPeter Zijlstra EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT) 40263b79f6eSPeter Zijlstra 40363b79f6eSPeter Zijlstra /* 40427f6d22bSBorislav Petkov * Constraint on the Event code + UMask + fixed-mask 40527f6d22bSBorislav Petkov * 40627f6d22bSBorislav Petkov * filter mask to validate fixed counter events. 40727f6d22bSBorislav Petkov * the following filters disqualify for fixed counters: 40827f6d22bSBorislav Petkov * - inv 40927f6d22bSBorislav Petkov * - edge 41027f6d22bSBorislav Petkov * - cnt-mask 41127f6d22bSBorislav Petkov * - in_tx 41227f6d22bSBorislav Petkov * - in_tx_checkpointed 41327f6d22bSBorislav Petkov * The other filters are supported by fixed counters. 41427f6d22bSBorislav Petkov * The any-thread option is supported starting with v3. 41527f6d22bSBorislav Petkov */ 41627f6d22bSBorislav Petkov #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) 41727f6d22bSBorislav Petkov #define FIXED_EVENT_CONSTRAINT(c, n) \ 41827f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) 41927f6d22bSBorislav Petkov 42027f6d22bSBorislav Petkov /* 42159a854e2SKan Liang * The special metric counters do not actually exist. They are calculated from 42259a854e2SKan Liang * the combination of the FxCtr3 + MSR_PERF_METRICS. 42359a854e2SKan Liang * 42459a854e2SKan Liang * The special metric counters are mapped to a dummy offset for the scheduler. 42559a854e2SKan Liang * The sharing between multiple users of the same metric without multiplexing 42659a854e2SKan Liang * is not allowed, even though the hardware supports that in principle. 42759a854e2SKan Liang */ 42859a854e2SKan Liang 42959a854e2SKan Liang #define METRIC_EVENT_CONSTRAINT(c, n) \ 43059a854e2SKan Liang EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \ 43159a854e2SKan Liang INTEL_ARCH_EVENT_MASK) 43259a854e2SKan Liang 43359a854e2SKan Liang /* 43427f6d22bSBorislav Petkov * Constraint on the Event code + UMask 43527f6d22bSBorislav Petkov */ 43627f6d22bSBorislav Petkov #define INTEL_UEVENT_CONSTRAINT(c, n) \ 43727f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) 43827f6d22bSBorislav Petkov 43927f6d22bSBorislav Petkov /* Constraint on specific umask bit only + event */ 44027f6d22bSBorislav Petkov #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \ 44127f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c)) 44227f6d22bSBorislav Petkov 44327f6d22bSBorislav Petkov /* Like UEVENT_CONSTRAINT, but match flags too */ 44427f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ 44527f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) 44627f6d22bSBorislav Petkov 44727f6d22bSBorislav Petkov #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ 44827f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ 44927f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) 45027f6d22bSBorislav Petkov 45127f6d22bSBorislav Petkov #define INTEL_PLD_CONSTRAINT(c, n) \ 45227f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 45327f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) 45427f6d22bSBorislav Petkov 45561b985e3SKan Liang #define INTEL_PSD_CONSTRAINT(c, n) \ 45661b985e3SKan Liang __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 45761b985e3SKan Liang HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT) 45861b985e3SKan Liang 45927f6d22bSBorislav Petkov #define INTEL_PST_CONSTRAINT(c, n) \ 46027f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 46127f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) 46227f6d22bSBorislav Petkov 46327f6d22bSBorislav Petkov /* Event constraint, but match on all event flags too. */ 46427f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ 4656b89d4c1SStephane Eranian EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 46627f6d22bSBorislav Petkov 46763b79f6eSPeter Zijlstra #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ 4686b89d4c1SStephane Eranian EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 46963b79f6eSPeter Zijlstra 47027f6d22bSBorislav Petkov /* Check only flags, but allow all event/umask */ 47127f6d22bSBorislav Petkov #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ 47227f6d22bSBorislav Petkov EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) 47327f6d22bSBorislav Petkov 47427f6d22bSBorislav Petkov /* Check flags and event code, and set the HSW store flag */ 47527f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ 47627f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 47727f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 47827f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 47927f6d22bSBorislav Petkov 48027f6d22bSBorislav Petkov /* Check flags and event code, and set the HSW load flag */ 48127f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ 48227f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 48327f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 48427f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 48527f6d22bSBorislav Petkov 48663b79f6eSPeter Zijlstra #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \ 48763b79f6eSPeter Zijlstra __EVENT_CONSTRAINT_RANGE(code, end, n, \ 48863b79f6eSPeter Zijlstra ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 48963b79f6eSPeter Zijlstra HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 49063b79f6eSPeter Zijlstra 49127f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ 49227f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 49327f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 49427f6d22bSBorislav Petkov HWEIGHT(n), 0, \ 49527f6d22bSBorislav Petkov PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 49627f6d22bSBorislav Petkov 49727f6d22bSBorislav Petkov /* Check flags and event code/umask, and set the HSW store flag */ 49827f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ 49927f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 50027f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 50127f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 50227f6d22bSBorislav Petkov 50327f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ 50427f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 50527f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 50627f6d22bSBorislav Petkov HWEIGHT(n), 0, \ 50727f6d22bSBorislav Petkov PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) 50827f6d22bSBorislav Petkov 50927f6d22bSBorislav Petkov /* Check flags and event code/umask, and set the HSW load flag */ 51027f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ 51127f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 51227f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 51327f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 51427f6d22bSBorislav Petkov 51527f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ 51627f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 51727f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 51827f6d22bSBorislav Petkov HWEIGHT(n), 0, \ 51927f6d22bSBorislav Petkov PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 52027f6d22bSBorislav Petkov 52127f6d22bSBorislav Petkov /* Check flags and event code/umask, and set the HSW N/A flag */ 52227f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ 52327f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 52427f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 52527f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) 52627f6d22bSBorislav Petkov 52727f6d22bSBorislav Petkov 52827f6d22bSBorislav Petkov /* 52927f6d22bSBorislav Petkov * We define the end marker as having a weight of -1 53027f6d22bSBorislav Petkov * to enable blacklisting of events using a counter bitmask 53127f6d22bSBorislav Petkov * of zero and thus a weight of zero. 53227f6d22bSBorislav Petkov * The end marker has a weight that cannot possibly be 53327f6d22bSBorislav Petkov * obtained from counting the bits in the bitmask. 53427f6d22bSBorislav Petkov */ 53527f6d22bSBorislav Petkov #define EVENT_CONSTRAINT_END { .weight = -1 } 53627f6d22bSBorislav Petkov 53727f6d22bSBorislav Petkov /* 53827f6d22bSBorislav Petkov * Check for end marker with weight == -1 53927f6d22bSBorislav Petkov */ 54027f6d22bSBorislav Petkov #define for_each_event_constraint(e, c) \ 54127f6d22bSBorislav Petkov for ((e) = (c); (e)->weight != -1; (e)++) 54227f6d22bSBorislav Petkov 54327f6d22bSBorislav Petkov /* 54427f6d22bSBorislav Petkov * Extra registers for specific events. 54527f6d22bSBorislav Petkov * 54627f6d22bSBorislav Petkov * Some events need large masks and require external MSRs. 54727f6d22bSBorislav Petkov * Those extra MSRs end up being shared for all events on 54827f6d22bSBorislav Petkov * a PMU and sometimes between PMU of sibling HT threads. 54927f6d22bSBorislav Petkov * In either case, the kernel needs to handle conflicting 55027f6d22bSBorislav Petkov * accesses to those extra, shared, regs. The data structure 55127f6d22bSBorislav Petkov * to manage those registers is stored in cpu_hw_event. 55227f6d22bSBorislav Petkov */ 55327f6d22bSBorislav Petkov struct extra_reg { 55427f6d22bSBorislav Petkov unsigned int event; 55527f6d22bSBorislav Petkov unsigned int msr; 55627f6d22bSBorislav Petkov u64 config_mask; 55727f6d22bSBorislav Petkov u64 valid_mask; 55827f6d22bSBorislav Petkov int idx; /* per_xxx->regs[] reg index */ 55927f6d22bSBorislav Petkov bool extra_msr_access; 56027f6d22bSBorislav Petkov }; 56127f6d22bSBorislav Petkov 56227f6d22bSBorislav Petkov #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ 56327f6d22bSBorislav Petkov .event = (e), \ 56427f6d22bSBorislav Petkov .msr = (ms), \ 56527f6d22bSBorislav Petkov .config_mask = (m), \ 56627f6d22bSBorislav Petkov .valid_mask = (vm), \ 56727f6d22bSBorislav Petkov .idx = EXTRA_REG_##i, \ 56827f6d22bSBorislav Petkov .extra_msr_access = true, \ 56927f6d22bSBorislav Petkov } 57027f6d22bSBorislav Petkov 57127f6d22bSBorislav Petkov #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ 57227f6d22bSBorislav Petkov EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) 57327f6d22bSBorislav Petkov 57427f6d22bSBorislav Petkov #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ 57527f6d22bSBorislav Petkov EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ 57627f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) 57727f6d22bSBorislav Petkov 57827f6d22bSBorislav Petkov #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ 57927f6d22bSBorislav Petkov INTEL_UEVENT_EXTRA_REG(c, \ 58027f6d22bSBorislav Petkov MSR_PEBS_LD_LAT_THRESHOLD, \ 58127f6d22bSBorislav Petkov 0xffff, \ 58227f6d22bSBorislav Petkov LDLAT) 58327f6d22bSBorislav Petkov 58427f6d22bSBorislav Petkov #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) 58527f6d22bSBorislav Petkov 58627f6d22bSBorislav Petkov union perf_capabilities { 58727f6d22bSBorislav Petkov struct { 58827f6d22bSBorislav Petkov u64 lbr_format:6; 58927f6d22bSBorislav Petkov u64 pebs_trap:1; 59027f6d22bSBorislav Petkov u64 pebs_arch_reg:1; 59127f6d22bSBorislav Petkov u64 pebs_format:4; 59227f6d22bSBorislav Petkov u64 smm_freeze:1; 59327f6d22bSBorislav Petkov /* 59427f6d22bSBorislav Petkov * PMU supports separate counter range for writing 59527f6d22bSBorislav Petkov * values > 32bit. 59627f6d22bSBorislav Petkov */ 59727f6d22bSBorislav Petkov u64 full_width_write:1; 598c22497f5SKan Liang u64 pebs_baseline:1; 599bbdbde2aSKan Liang u64 perf_metrics:1; 60042880f72SAlexander Shishkin u64 pebs_output_pt_available:1; 601cadbaa03SStephane Eranian u64 anythread_deprecated:1; 60227f6d22bSBorislav Petkov }; 60327f6d22bSBorislav Petkov u64 capabilities; 60427f6d22bSBorislav Petkov }; 60527f6d22bSBorislav Petkov 60627f6d22bSBorislav Petkov struct x86_pmu_quirk { 60727f6d22bSBorislav Petkov struct x86_pmu_quirk *next; 60827f6d22bSBorislav Petkov void (*func)(void); 60927f6d22bSBorislav Petkov }; 61027f6d22bSBorislav Petkov 61127f6d22bSBorislav Petkov union x86_pmu_config { 61227f6d22bSBorislav Petkov struct { 61327f6d22bSBorislav Petkov u64 event:8, 61427f6d22bSBorislav Petkov umask:8, 61527f6d22bSBorislav Petkov usr:1, 61627f6d22bSBorislav Petkov os:1, 61727f6d22bSBorislav Petkov edge:1, 61827f6d22bSBorislav Petkov pc:1, 61927f6d22bSBorislav Petkov interrupt:1, 62027f6d22bSBorislav Petkov __reserved1:1, 62127f6d22bSBorislav Petkov en:1, 62227f6d22bSBorislav Petkov inv:1, 62327f6d22bSBorislav Petkov cmask:8, 62427f6d22bSBorislav Petkov event2:4, 62527f6d22bSBorislav Petkov __reserved2:4, 62627f6d22bSBorislav Petkov go:1, 62727f6d22bSBorislav Petkov ho:1; 62827f6d22bSBorislav Petkov } bits; 62927f6d22bSBorislav Petkov u64 value; 63027f6d22bSBorislav Petkov }; 63127f6d22bSBorislav Petkov 63227f6d22bSBorislav Petkov #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value 63327f6d22bSBorislav Petkov 63427f6d22bSBorislav Petkov enum { 63527f6d22bSBorislav Petkov x86_lbr_exclusive_lbr, 63627f6d22bSBorislav Petkov x86_lbr_exclusive_bts, 63727f6d22bSBorislav Petkov x86_lbr_exclusive_pt, 63827f6d22bSBorislav Petkov x86_lbr_exclusive_max, 63927f6d22bSBorislav Petkov }; 64027f6d22bSBorislav Petkov 641d0946a88SKan Liang struct x86_hybrid_pmu { 642d0946a88SKan Liang struct pmu pmu; 643d9977c43SKan Liang const char *name; 644d9977c43SKan Liang u8 cpu_type; 645d9977c43SKan Liang cpumask_t supported_cpus; 646d0946a88SKan Liang union perf_capabilities intel_cap; 647fc4b8fcaSKan Liang u64 intel_ctrl; 648d4b294bfSKan Liang int max_pebs_events; 649d4b294bfSKan Liang int num_counters; 650d4b294bfSKan Liang int num_counters_fixed; 651eaacf07dSKan Liang struct event_constraint unconstrained; 6520d18f2dfSKan Liang 6530d18f2dfSKan Liang u64 hw_cache_event_ids 6540d18f2dfSKan Liang [PERF_COUNT_HW_CACHE_MAX] 6550d18f2dfSKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 6560d18f2dfSKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX]; 6570d18f2dfSKan Liang u64 hw_cache_extra_regs 6580d18f2dfSKan Liang [PERF_COUNT_HW_CACHE_MAX] 6590d18f2dfSKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 6600d18f2dfSKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX]; 66124ee38ffSKan Liang struct event_constraint *event_constraints; 66224ee38ffSKan Liang struct event_constraint *pebs_constraints; 663183af736SKan Liang struct extra_reg *extra_regs; 664acade637SKan Liang 665acade637SKan Liang unsigned int late_ack :1, 666acade637SKan Liang mid_ack :1, 667acade637SKan Liang enabled_ack :1; 668d0946a88SKan Liang }; 669d0946a88SKan Liang 670d0946a88SKan Liang static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu) 671d0946a88SKan Liang { 672d0946a88SKan Liang return container_of(pmu, struct x86_hybrid_pmu, pmu); 673d0946a88SKan Liang } 674d0946a88SKan Liang 675d0946a88SKan Liang extern struct static_key_false perf_is_hybrid; 676d0946a88SKan Liang #define is_hybrid() static_branch_unlikely(&perf_is_hybrid) 677d0946a88SKan Liang 678d0946a88SKan Liang #define hybrid(_pmu, _field) \ 679d0946a88SKan Liang (*({ \ 680d0946a88SKan Liang typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \ 681d0946a88SKan Liang \ 682d0946a88SKan Liang if (is_hybrid() && (_pmu)) \ 683d0946a88SKan Liang __Fp = &hybrid_pmu(_pmu)->_field; \ 684d0946a88SKan Liang \ 685d0946a88SKan Liang __Fp; \ 686d0946a88SKan Liang })) 687d0946a88SKan Liang 688eaacf07dSKan Liang #define hybrid_var(_pmu, _var) \ 689eaacf07dSKan Liang (*({ \ 690eaacf07dSKan Liang typeof(&_var) __Fp = &_var; \ 691eaacf07dSKan Liang \ 692eaacf07dSKan Liang if (is_hybrid() && (_pmu)) \ 693eaacf07dSKan Liang __Fp = &hybrid_pmu(_pmu)->_var; \ 694eaacf07dSKan Liang \ 695eaacf07dSKan Liang __Fp; \ 696eaacf07dSKan Liang })) 697eaacf07dSKan Liang 698acade637SKan Liang #define hybrid_bit(_pmu, _field) \ 699acade637SKan Liang ({ \ 700acade637SKan Liang bool __Fp = x86_pmu._field; \ 701acade637SKan Liang \ 702acade637SKan Liang if (is_hybrid() && (_pmu)) \ 703acade637SKan Liang __Fp = hybrid_pmu(_pmu)->_field; \ 704acade637SKan Liang \ 705acade637SKan Liang __Fp; \ 706acade637SKan Liang }) 707acade637SKan Liang 708d9977c43SKan Liang enum hybrid_pmu_type { 709d9977c43SKan Liang hybrid_big = 0x40, 710d9977c43SKan Liang hybrid_small = 0x20, 711d9977c43SKan Liang 712d9977c43SKan Liang hybrid_big_small = hybrid_big | hybrid_small, 713d9977c43SKan Liang }; 714d9977c43SKan Liang 715f83d2f91SKan Liang #define X86_HYBRID_PMU_ATOM_IDX 0 716f83d2f91SKan Liang #define X86_HYBRID_PMU_CORE_IDX 1 717f83d2f91SKan Liang 718f83d2f91SKan Liang #define X86_HYBRID_NUM_PMUS 2 719f83d2f91SKan Liang 72027f6d22bSBorislav Petkov /* 72127f6d22bSBorislav Petkov * struct x86_pmu - generic x86 pmu 72227f6d22bSBorislav Petkov */ 72327f6d22bSBorislav Petkov struct x86_pmu { 72427f6d22bSBorislav Petkov /* 72527f6d22bSBorislav Petkov * Generic x86 PMC bits 72627f6d22bSBorislav Petkov */ 72727f6d22bSBorislav Petkov const char *name; 72827f6d22bSBorislav Petkov int version; 72927f6d22bSBorislav Petkov int (*handle_irq)(struct pt_regs *); 73027f6d22bSBorislav Petkov void (*disable_all)(void); 73127f6d22bSBorislav Petkov void (*enable_all)(int added); 73227f6d22bSBorislav Petkov void (*enable)(struct perf_event *); 73327f6d22bSBorislav Petkov void (*disable)(struct perf_event *); 7348b8ff8ccSAdrian Hunter void (*assign)(struct perf_event *event, int idx); 73568f7082fSPeter Zijlstra void (*add)(struct perf_event *); 73668f7082fSPeter Zijlstra void (*del)(struct perf_event *); 737bcfbe5c4SKan Liang void (*read)(struct perf_event *event); 73827f6d22bSBorislav Petkov int (*hw_config)(struct perf_event *event); 73927f6d22bSBorislav Petkov int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); 74027f6d22bSBorislav Petkov unsigned eventsel; 74127f6d22bSBorislav Petkov unsigned perfctr; 74227f6d22bSBorislav Petkov int (*addr_offset)(int index, bool eventsel); 74327f6d22bSBorislav Petkov int (*rdpmc_index)(int index); 74427f6d22bSBorislav Petkov u64 (*event_map)(int); 74527f6d22bSBorislav Petkov int max_events; 74627f6d22bSBorislav Petkov int num_counters; 74727f6d22bSBorislav Petkov int num_counters_fixed; 74827f6d22bSBorislav Petkov int cntval_bits; 74927f6d22bSBorislav Petkov u64 cntval_mask; 75027f6d22bSBorislav Petkov union { 75127f6d22bSBorislav Petkov unsigned long events_maskl; 75227f6d22bSBorislav Petkov unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; 75327f6d22bSBorislav Petkov }; 75427f6d22bSBorislav Petkov int events_mask_len; 75527f6d22bSBorislav Petkov int apic; 75627f6d22bSBorislav Petkov u64 max_period; 75727f6d22bSBorislav Petkov struct event_constraint * 75827f6d22bSBorislav Petkov (*get_event_constraints)(struct cpu_hw_events *cpuc, 75927f6d22bSBorislav Petkov int idx, 76027f6d22bSBorislav Petkov struct perf_event *event); 76127f6d22bSBorislav Petkov 76227f6d22bSBorislav Petkov void (*put_event_constraints)(struct cpu_hw_events *cpuc, 76327f6d22bSBorislav Petkov struct perf_event *event); 76427f6d22bSBorislav Petkov 76527f6d22bSBorislav Petkov void (*start_scheduling)(struct cpu_hw_events *cpuc); 76627f6d22bSBorislav Petkov 76727f6d22bSBorislav Petkov void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); 76827f6d22bSBorislav Petkov 76927f6d22bSBorislav Petkov void (*stop_scheduling)(struct cpu_hw_events *cpuc); 77027f6d22bSBorislav Petkov 77127f6d22bSBorislav Petkov struct event_constraint *event_constraints; 77227f6d22bSBorislav Petkov struct x86_pmu_quirk *quirks; 77327f6d22bSBorislav Petkov int perfctr_second_write; 774f605cfcaSKan Liang u64 (*limit_period)(struct perf_event *event, u64 l); 77527f6d22bSBorislav Petkov 776af3bdb99SAndi Kleen /* PMI handler bits */ 777af3bdb99SAndi Kleen unsigned int late_ack :1, 778acade637SKan Liang mid_ack :1, 7793daa96d6SPeter Zijlstra enabled_ack :1; 78027f6d22bSBorislav Petkov /* 78127f6d22bSBorislav Petkov * sysfs attrs 78227f6d22bSBorislav Petkov */ 78327f6d22bSBorislav Petkov int attr_rdpmc_broken; 78427f6d22bSBorislav Petkov int attr_rdpmc; 78527f6d22bSBorislav Petkov struct attribute **format_attrs; 78627f6d22bSBorislav Petkov 78727f6d22bSBorislav Petkov ssize_t (*events_sysfs_show)(char *page, u64 config); 788baa0c833SJiri Olsa const struct attribute_group **attr_update; 78927f6d22bSBorislav Petkov 7906089327fSKan Liang unsigned long attr_freeze_on_smi; 7916089327fSKan Liang 79227f6d22bSBorislav Petkov /* 79327f6d22bSBorislav Petkov * CPU Hotplug hooks 79427f6d22bSBorislav Petkov */ 79527f6d22bSBorislav Petkov int (*cpu_prepare)(int cpu); 79627f6d22bSBorislav Petkov void (*cpu_starting)(int cpu); 79727f6d22bSBorislav Petkov void (*cpu_dying)(int cpu); 79827f6d22bSBorislav Petkov void (*cpu_dead)(int cpu); 79927f6d22bSBorislav Petkov 80027f6d22bSBorislav Petkov void (*check_microcode)(void); 80127f6d22bSBorislav Petkov void (*sched_task)(struct perf_event_context *ctx, 80227f6d22bSBorislav Petkov bool sched_in); 80327f6d22bSBorislav Petkov 80427f6d22bSBorislav Petkov /* 80527f6d22bSBorislav Petkov * Intel Arch Perfmon v2+ 80627f6d22bSBorislav Petkov */ 80727f6d22bSBorislav Petkov u64 intel_ctrl; 80827f6d22bSBorislav Petkov union perf_capabilities intel_cap; 80927f6d22bSBorislav Petkov 81027f6d22bSBorislav Petkov /* 81127f6d22bSBorislav Petkov * Intel DebugStore bits 81227f6d22bSBorislav Petkov */ 81327f6d22bSBorislav Petkov unsigned int bts :1, 81427f6d22bSBorislav Petkov bts_active :1, 81527f6d22bSBorislav Petkov pebs :1, 81627f6d22bSBorislav Petkov pebs_active :1, 81727f6d22bSBorislav Petkov pebs_broken :1, 81895298355SAndi Kleen pebs_prec_dist :1, 8199b545c04SAndi Kleen pebs_no_tlb :1, 82061b985e3SKan Liang pebs_no_isolation :1, 821*fb358e0bSLike Xu pebs_block :1, 822*fb358e0bSLike Xu pebs_ept :1; 82327f6d22bSBorislav Petkov int pebs_record_size; 824e72daf3fSJiri Olsa int pebs_buffer_size; 825c22497f5SKan Liang int max_pebs_events; 8269dfa9a5cSPeter Zijlstra void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data); 82727f6d22bSBorislav Petkov struct event_constraint *pebs_constraints; 82827f6d22bSBorislav Petkov void (*pebs_aliases)(struct perf_event *event); 829174afc3eSKan Liang unsigned long large_pebs_flags; 830c22497f5SKan Liang u64 rtm_abort_event; 83127f6d22bSBorislav Petkov 83227f6d22bSBorislav Petkov /* 83327f6d22bSBorislav Petkov * Intel LBR 83427f6d22bSBorislav Petkov */ 8353cb9d546SWei Wang unsigned int lbr_tos, lbr_from, lbr_to, 836fda1f99fSKan Liang lbr_info, lbr_nr; /* LBR base regs and size */ 83749d8184fSKan Liang union { 83827f6d22bSBorislav Petkov u64 lbr_sel_mask; /* LBR_SELECT valid bits */ 83949d8184fSKan Liang u64 lbr_ctl_mask; /* LBR_CTL valid bits */ 84049d8184fSKan Liang }; 84149d8184fSKan Liang union { 84227f6d22bSBorislav Petkov const int *lbr_sel_map; /* lbr_select mappings */ 84349d8184fSKan Liang int *lbr_ctl_map; /* LBR_CTL mappings */ 84449d8184fSKan Liang }; 84527f6d22bSBorislav Petkov bool lbr_double_abort; /* duplicated lbr aborts */ 846b0c1ef52SAndi Kleen bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ 84727f6d22bSBorislav Petkov 8481ac7fd81SPeter Zijlstra (Intel) unsigned int lbr_has_info:1; 8491ac7fd81SPeter Zijlstra (Intel) unsigned int lbr_has_tsx:1; 8501ac7fd81SPeter Zijlstra (Intel) unsigned int lbr_from_flags:1; 8511ac7fd81SPeter Zijlstra (Intel) unsigned int lbr_to_cycles:1; 8521ac7fd81SPeter Zijlstra (Intel) 853af6cf129SKan Liang /* 854af6cf129SKan Liang * Intel Architectural LBR CPUID Enumeration 855af6cf129SKan Liang */ 856af6cf129SKan Liang unsigned int lbr_depth_mask:8; 857af6cf129SKan Liang unsigned int lbr_deep_c_reset:1; 858af6cf129SKan Liang unsigned int lbr_lip:1; 859af6cf129SKan Liang unsigned int lbr_cpl:1; 860af6cf129SKan Liang unsigned int lbr_filter:1; 861af6cf129SKan Liang unsigned int lbr_call_stack:1; 862af6cf129SKan Liang unsigned int lbr_mispred:1; 863af6cf129SKan Liang unsigned int lbr_timed_lbr:1; 864af6cf129SKan Liang unsigned int lbr_br_type:1; 865af6cf129SKan Liang 8669f354a72SKan Liang void (*lbr_reset)(void); 867c301b1d8SKan Liang void (*lbr_read)(struct cpu_hw_events *cpuc); 868799571bfSKan Liang void (*lbr_save)(void *ctx); 869799571bfSKan Liang void (*lbr_restore)(void *ctx); 8709f354a72SKan Liang 87127f6d22bSBorislav Petkov /* 87227f6d22bSBorislav Petkov * Intel PT/LBR/BTS are exclusive 87327f6d22bSBorislav Petkov */ 87427f6d22bSBorislav Petkov atomic_t lbr_exclusive[x86_lbr_exclusive_max]; 87527f6d22bSBorislav Petkov 87627f6d22bSBorislav Petkov /* 8777b2c05a1SKan Liang * Intel perf metrics 8787b2c05a1SKan Liang */ 8791ab5f235SKan Liang int num_topdown_events; 8807b2c05a1SKan Liang u64 (*update_topdown_event)(struct perf_event *event); 8817b2c05a1SKan Liang int (*set_topdown_event_period)(struct perf_event *event); 8827b2c05a1SKan Liang 8837b2c05a1SKan Liang /* 884fc1adfe3SAlexey Budankov * perf task context (i.e. struct perf_event_context::task_ctx_data) 885fc1adfe3SAlexey Budankov * switch helper to bridge calls from perf/core to perf/x86. 886fc1adfe3SAlexey Budankov * See struct pmu::swap_task_ctx() usage for examples; 887fc1adfe3SAlexey Budankov */ 888fc1adfe3SAlexey Budankov void (*swap_task_ctx)(struct perf_event_context *prev, 889fc1adfe3SAlexey Budankov struct perf_event_context *next); 890fc1adfe3SAlexey Budankov 891fc1adfe3SAlexey Budankov /* 89232b62f44SPeter Zijlstra * AMD bits 89332b62f44SPeter Zijlstra */ 89432b62f44SPeter Zijlstra unsigned int amd_nb_constraints : 1; 89557388912SKim Phillips u64 perf_ctr_pair_en; 89632b62f44SPeter Zijlstra 89732b62f44SPeter Zijlstra /* 89827f6d22bSBorislav Petkov * Extra registers for events 89927f6d22bSBorislav Petkov */ 90027f6d22bSBorislav Petkov struct extra_reg *extra_regs; 90127f6d22bSBorislav Petkov unsigned int flags; 90227f6d22bSBorislav Petkov 90327f6d22bSBorislav Petkov /* 90427f6d22bSBorislav Petkov * Intel host/guest support (KVM) 90527f6d22bSBorislav Petkov */ 90627f6d22bSBorislav Petkov struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr); 90781ec3f3cSJiri Olsa 90881ec3f3cSJiri Olsa /* 90981ec3f3cSJiri Olsa * Check period value for PERF_EVENT_IOC_PERIOD ioctl. 91081ec3f3cSJiri Olsa */ 91181ec3f3cSJiri Olsa int (*check_period) (struct perf_event *event, u64 period); 91242880f72SAlexander Shishkin 91342880f72SAlexander Shishkin int (*aux_output_match) (struct perf_event *event); 914d0946a88SKan Liang 9153e9a8b21SKan Liang int (*filter_match)(struct perf_event *event); 916d0946a88SKan Liang /* 917d0946a88SKan Liang * Hybrid support 918d0946a88SKan Liang * 919d0946a88SKan Liang * Most PMU capabilities are the same among different hybrid PMUs. 920d0946a88SKan Liang * The global x86_pmu saves the architecture capabilities, which 921d0946a88SKan Liang * are available for all PMUs. The hybrid_pmu only includes the 922d0946a88SKan Liang * unique capabilities. 923d0946a88SKan Liang */ 924d4b294bfSKan Liang int num_hybrid_pmus; 925d0946a88SKan Liang struct x86_hybrid_pmu *hybrid_pmu; 926d9977c43SKan Liang u8 (*get_hybrid_cpu_type) (void); 92727f6d22bSBorislav Petkov }; 92827f6d22bSBorislav Petkov 929530bfff6SKan Liang struct x86_perf_task_context_opt { 930530bfff6SKan Liang int lbr_callstack_users; 931530bfff6SKan Liang int lbr_stack_state; 932530bfff6SKan Liang int log_id; 933530bfff6SKan Liang }; 934530bfff6SKan Liang 93527f6d22bSBorislav Petkov struct x86_perf_task_context { 936e1ad1ac2SLike Xu u64 lbr_sel; 93727f6d22bSBorislav Petkov int tos; 9380592e57bSKan Liang int valid_lbrs; 939530bfff6SKan Liang struct x86_perf_task_context_opt opt; 9405624986dSKan Liang struct lbr_entry lbr[MAX_LBR_ENTRIES]; 94127f6d22bSBorislav Petkov }; 94227f6d22bSBorislav Petkov 94347125db2SKan Liang struct x86_perf_task_context_arch_lbr { 94447125db2SKan Liang struct x86_perf_task_context_opt opt; 94547125db2SKan Liang struct lbr_entry entries[]; 94647125db2SKan Liang }; 94747125db2SKan Liang 948ce711ea3SKan Liang /* 949ce711ea3SKan Liang * Add padding to guarantee the 64-byte alignment of the state buffer. 950ce711ea3SKan Liang * 951ce711ea3SKan Liang * The structure is dynamically allocated. The size of the LBR state may vary 952ce711ea3SKan Liang * based on the number of LBR registers. 953ce711ea3SKan Liang * 954ce711ea3SKan Liang * Do not put anything after the LBR state. 955ce711ea3SKan Liang */ 956ce711ea3SKan Liang struct x86_perf_task_context_arch_lbr_xsave { 957ce711ea3SKan Liang struct x86_perf_task_context_opt opt; 958ce711ea3SKan Liang 959ce711ea3SKan Liang union { 960ce711ea3SKan Liang struct xregs_state xsave; 961ce711ea3SKan Liang struct { 962ce711ea3SKan Liang struct fxregs_state i387; 963ce711ea3SKan Liang struct xstate_header header; 964ce711ea3SKan Liang struct arch_lbr_state lbr; 965ce711ea3SKan Liang } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT))); 966ce711ea3SKan Liang }; 967ce711ea3SKan Liang }; 968ce711ea3SKan Liang 96927f6d22bSBorislav Petkov #define x86_add_quirk(func_) \ 97027f6d22bSBorislav Petkov do { \ 97127f6d22bSBorislav Petkov static struct x86_pmu_quirk __quirk __initdata = { \ 97227f6d22bSBorislav Petkov .func = func_, \ 97327f6d22bSBorislav Petkov }; \ 97427f6d22bSBorislav Petkov __quirk.next = x86_pmu.quirks; \ 97527f6d22bSBorislav Petkov x86_pmu.quirks = &__quirk; \ 97627f6d22bSBorislav Petkov } while (0) 97727f6d22bSBorislav Petkov 97827f6d22bSBorislav Petkov /* 97927f6d22bSBorislav Petkov * x86_pmu flags 98027f6d22bSBorislav Petkov */ 98127f6d22bSBorislav Petkov #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ 98227f6d22bSBorislav Petkov #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ 98327f6d22bSBorislav Petkov #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ 98427f6d22bSBorislav Petkov #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ 98531962340SKan Liang #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */ 986400816f6SPeter Zijlstra (Intel) #define PMU_FL_TFA 0x20 /* deal with TSX force abort */ 987471af006SKim Phillips #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */ 98861b985e3SKan Liang #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */ 98961b985e3SKan Liang #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */ 99027f6d22bSBorislav Petkov 99127f6d22bSBorislav Petkov #define EVENT_VAR(_id) event_attr_##_id 99227f6d22bSBorislav Petkov #define EVENT_PTR(_id) &event_attr_##_id.attr.attr 99327f6d22bSBorislav Petkov 99427f6d22bSBorislav Petkov #define EVENT_ATTR(_name, _id) \ 99527f6d22bSBorislav Petkov static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ 99627f6d22bSBorislav Petkov .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 99727f6d22bSBorislav Petkov .id = PERF_COUNT_HW_##_id, \ 99827f6d22bSBorislav Petkov .event_str = NULL, \ 99927f6d22bSBorislav Petkov }; 100027f6d22bSBorislav Petkov 100127f6d22bSBorislav Petkov #define EVENT_ATTR_STR(_name, v, str) \ 100227f6d22bSBorislav Petkov static struct perf_pmu_events_attr event_attr_##v = { \ 100327f6d22bSBorislav Petkov .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 100427f6d22bSBorislav Petkov .id = 0, \ 100527f6d22bSBorislav Petkov .event_str = str, \ 100627f6d22bSBorislav Petkov }; 100727f6d22bSBorislav Petkov 1008fc07e9f9SAndi Kleen #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \ 1009fc07e9f9SAndi Kleen static struct perf_pmu_events_ht_attr event_attr_##v = { \ 1010fc07e9f9SAndi Kleen .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\ 1011fc07e9f9SAndi Kleen .id = 0, \ 1012fc07e9f9SAndi Kleen .event_str_noht = noht, \ 1013fc07e9f9SAndi Kleen .event_str_ht = ht, \ 1014fc07e9f9SAndi Kleen } 1015fc07e9f9SAndi Kleen 1016a9c81ccdSKan Liang #define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \ 1017a9c81ccdSKan Liang static struct perf_pmu_events_hybrid_attr event_attr_##v = { \ 1018a9c81ccdSKan Liang .attr = __ATTR(_name, 0444, events_hybrid_sysfs_show, NULL),\ 1019a9c81ccdSKan Liang .id = 0, \ 1020a9c81ccdSKan Liang .event_str = str, \ 1021a9c81ccdSKan Liang .pmu_type = _pmu, \ 1022a9c81ccdSKan Liang } 1023a9c81ccdSKan Liang 1024a9c81ccdSKan Liang #define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr) 1025a9c81ccdSKan Liang 1026a9c81ccdSKan Liang #define FORMAT_ATTR_HYBRID(_name, _pmu) \ 1027a9c81ccdSKan Liang static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\ 1028a9c81ccdSKan Liang .attr = __ATTR_RO(_name), \ 1029a9c81ccdSKan Liang .pmu_type = _pmu, \ 1030a9c81ccdSKan Liang } 1031a9c81ccdSKan Liang 103261e76d53SKan Liang struct pmu *x86_get_pmu(unsigned int cpu); 103327f6d22bSBorislav Petkov extern struct x86_pmu x86_pmu __read_mostly; 103427f6d22bSBorislav Petkov 1035f42be865SKan Liang static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx) 1036f42be865SKan Liang { 103747125db2SKan Liang if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 103847125db2SKan Liang return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt; 103947125db2SKan Liang 1040f42be865SKan Liang return &((struct x86_perf_task_context *)ctx)->opt; 1041f42be865SKan Liang } 1042f42be865SKan Liang 104327f6d22bSBorislav Petkov static inline bool x86_pmu_has_lbr_callstack(void) 104427f6d22bSBorislav Petkov { 104527f6d22bSBorislav Petkov return x86_pmu.lbr_sel_map && 104627f6d22bSBorislav Petkov x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; 104727f6d22bSBorislav Petkov } 104827f6d22bSBorislav Petkov 104927f6d22bSBorislav Petkov DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 105027f6d22bSBorislav Petkov 105127f6d22bSBorislav Petkov int x86_perf_event_set_period(struct perf_event *event); 105227f6d22bSBorislav Petkov 105327f6d22bSBorislav Petkov /* 105427f6d22bSBorislav Petkov * Generalized hw caching related hw_event table, filled 105527f6d22bSBorislav Petkov * in on a per model basis. A value of 0 means 105627f6d22bSBorislav Petkov * 'not supported', -1 means 'hw_event makes no sense on 105727f6d22bSBorislav Petkov * this CPU', any other value means the raw hw_event 105827f6d22bSBorislav Petkov * ID. 105927f6d22bSBorislav Petkov */ 106027f6d22bSBorislav Petkov 106127f6d22bSBorislav Petkov #define C(x) PERF_COUNT_HW_CACHE_##x 106227f6d22bSBorislav Petkov 106327f6d22bSBorislav Petkov extern u64 __read_mostly hw_cache_event_ids 106427f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 106527f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 106627f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX]; 106727f6d22bSBorislav Petkov extern u64 __read_mostly hw_cache_extra_regs 106827f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 106927f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 107027f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX]; 107127f6d22bSBorislav Petkov 107227f6d22bSBorislav Petkov u64 x86_perf_event_update(struct perf_event *event); 107327f6d22bSBorislav Petkov 107427f6d22bSBorislav Petkov static inline unsigned int x86_pmu_config_addr(int index) 107527f6d22bSBorislav Petkov { 107627f6d22bSBorislav Petkov return x86_pmu.eventsel + (x86_pmu.addr_offset ? 107727f6d22bSBorislav Petkov x86_pmu.addr_offset(index, true) : index); 107827f6d22bSBorislav Petkov } 107927f6d22bSBorislav Petkov 108027f6d22bSBorislav Petkov static inline unsigned int x86_pmu_event_addr(int index) 108127f6d22bSBorislav Petkov { 108227f6d22bSBorislav Petkov return x86_pmu.perfctr + (x86_pmu.addr_offset ? 108327f6d22bSBorislav Petkov x86_pmu.addr_offset(index, false) : index); 108427f6d22bSBorislav Petkov } 108527f6d22bSBorislav Petkov 108627f6d22bSBorislav Petkov static inline int x86_pmu_rdpmc_index(int index) 108727f6d22bSBorislav Petkov { 108827f6d22bSBorislav Petkov return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; 108927f6d22bSBorislav Petkov } 109027f6d22bSBorislav Petkov 1091fc4b8fcaSKan Liang bool check_hw_exists(struct pmu *pmu, int num_counters, 1092fc4b8fcaSKan Liang int num_counters_fixed); 1093fc4b8fcaSKan Liang 109427f6d22bSBorislav Petkov int x86_add_exclusive(unsigned int what); 109527f6d22bSBorislav Petkov 109627f6d22bSBorislav Petkov void x86_del_exclusive(unsigned int what); 109727f6d22bSBorislav Petkov 109827f6d22bSBorislav Petkov int x86_reserve_hardware(void); 109927f6d22bSBorislav Petkov 110027f6d22bSBorislav Petkov void x86_release_hardware(void); 110127f6d22bSBorislav Petkov 1102b00233b5SAndi Kleen int x86_pmu_max_precise(void); 1103b00233b5SAndi Kleen 110427f6d22bSBorislav Petkov void hw_perf_lbr_event_destroy(struct perf_event *event); 110527f6d22bSBorislav Petkov 110627f6d22bSBorislav Petkov int x86_setup_perfctr(struct perf_event *event); 110727f6d22bSBorislav Petkov 110827f6d22bSBorislav Petkov int x86_pmu_hw_config(struct perf_event *event); 110927f6d22bSBorislav Petkov 111027f6d22bSBorislav Petkov void x86_pmu_disable_all(void); 111127f6d22bSBorislav Petkov 1112ada54345SStephane Eranian static inline bool has_amd_brs(struct hw_perf_event *hwc) 1113ada54345SStephane Eranian { 1114ada54345SStephane Eranian return hwc->flags & PERF_X86_EVENT_AMD_BRS; 1115ada54345SStephane Eranian } 1116ada54345SStephane Eranian 111757388912SKim Phillips static inline bool is_counter_pair(struct hw_perf_event *hwc) 111857388912SKim Phillips { 111957388912SKim Phillips return hwc->flags & PERF_X86_EVENT_PAIR; 112057388912SKim Phillips } 112157388912SKim Phillips 112227f6d22bSBorislav Petkov static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, 112327f6d22bSBorislav Petkov u64 enable_mask) 112427f6d22bSBorislav Petkov { 112527f6d22bSBorislav Petkov u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 112627f6d22bSBorislav Petkov 112727f6d22bSBorislav Petkov if (hwc->extra_reg.reg) 112827f6d22bSBorislav Petkov wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); 112957388912SKim Phillips 113057388912SKim Phillips /* 113157388912SKim Phillips * Add enabled Merge event on next counter 113257388912SKim Phillips * if large increment event being enabled on this counter 113357388912SKim Phillips */ 113457388912SKim Phillips if (is_counter_pair(hwc)) 113557388912SKim Phillips wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); 113657388912SKim Phillips 113727f6d22bSBorislav Petkov wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 113827f6d22bSBorislav Petkov } 113927f6d22bSBorislav Petkov 114027f6d22bSBorislav Petkov void x86_pmu_enable_all(int added); 114127f6d22bSBorislav Petkov 114227f6d22bSBorislav Petkov int perf_assign_events(struct event_constraint **constraints, int n, 114327f6d22bSBorislav Petkov int wmin, int wmax, int gpmax, int *assign); 114427f6d22bSBorislav Petkov int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); 114527f6d22bSBorislav Petkov 114627f6d22bSBorislav Petkov void x86_pmu_stop(struct perf_event *event, int flags); 114727f6d22bSBorislav Petkov 114827f6d22bSBorislav Petkov static inline void x86_pmu_disable_event(struct perf_event *event) 114927f6d22bSBorislav Petkov { 1150df51fe7eSLike Xu u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 115127f6d22bSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 115227f6d22bSBorislav Petkov 1153df51fe7eSLike Xu wrmsrl(hwc->config_base, hwc->config & ~disable_mask); 115457388912SKim Phillips 115557388912SKim Phillips if (is_counter_pair(hwc)) 115657388912SKim Phillips wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0); 115727f6d22bSBorislav Petkov } 115827f6d22bSBorislav Petkov 115927f6d22bSBorislav Petkov void x86_pmu_enable_event(struct perf_event *event); 116027f6d22bSBorislav Petkov 116127f6d22bSBorislav Petkov int x86_pmu_handle_irq(struct pt_regs *regs); 116227f6d22bSBorislav Petkov 1163e11c1a7eSKan Liang void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed, 1164e11c1a7eSKan Liang u64 intel_ctrl); 1165e11c1a7eSKan Liang 1166d9977c43SKan Liang void x86_pmu_update_cpu_context(struct pmu *pmu, int cpu); 1167d9977c43SKan Liang 116827f6d22bSBorislav Petkov extern struct event_constraint emptyconstraint; 116927f6d22bSBorislav Petkov 117027f6d22bSBorislav Petkov extern struct event_constraint unconstrained; 117127f6d22bSBorislav Petkov 117227f6d22bSBorislav Petkov static inline bool kernel_ip(unsigned long ip) 117327f6d22bSBorislav Petkov { 117427f6d22bSBorislav Petkov #ifdef CONFIG_X86_32 117527f6d22bSBorislav Petkov return ip > PAGE_OFFSET; 117627f6d22bSBorislav Petkov #else 117727f6d22bSBorislav Petkov return (long)ip < 0; 117827f6d22bSBorislav Petkov #endif 117927f6d22bSBorislav Petkov } 118027f6d22bSBorislav Petkov 118127f6d22bSBorislav Petkov /* 118227f6d22bSBorislav Petkov * Not all PMUs provide the right context information to place the reported IP 118327f6d22bSBorislav Petkov * into full context. Specifically segment registers are typically not 118427f6d22bSBorislav Petkov * supplied. 118527f6d22bSBorislav Petkov * 118627f6d22bSBorislav Petkov * Assuming the address is a linear address (it is for IBS), we fake the CS and 118727f6d22bSBorislav Petkov * vm86 mode using the known zero-based code segment and 'fix up' the registers 118827f6d22bSBorislav Petkov * to reflect this. 118927f6d22bSBorislav Petkov * 119027f6d22bSBorislav Petkov * Intel PEBS/LBR appear to typically provide the effective address, nothing 119127f6d22bSBorislav Petkov * much we can do about that but pray and treat it like a linear address. 119227f6d22bSBorislav Petkov */ 119327f6d22bSBorislav Petkov static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) 119427f6d22bSBorislav Petkov { 119527f6d22bSBorislav Petkov regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; 119627f6d22bSBorislav Petkov if (regs->flags & X86_VM_MASK) 119727f6d22bSBorislav Petkov regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); 119827f6d22bSBorislav Petkov regs->ip = ip; 119927f6d22bSBorislav Petkov } 120027f6d22bSBorislav Petkov 120127f6d22bSBorislav Petkov ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); 120227f6d22bSBorislav Petkov ssize_t intel_event_sysfs_show(char *page, u64 config); 120327f6d22bSBorislav Petkov 1204a49ac9f8SHuang Rui ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, 1205a49ac9f8SHuang Rui char *page); 1206fc07e9f9SAndi Kleen ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 1207fc07e9f9SAndi Kleen char *page); 1208a9c81ccdSKan Liang ssize_t events_hybrid_sysfs_show(struct device *dev, 1209a9c81ccdSKan Liang struct device_attribute *attr, 1210a9c81ccdSKan Liang char *page); 1211a49ac9f8SHuang Rui 1212fc4b8fcaSKan Liang static inline bool fixed_counter_disabled(int i, struct pmu *pmu) 121332451614SKan Liang { 1214fc4b8fcaSKan Liang u64 intel_ctrl = hybrid(pmu, intel_ctrl); 1215fc4b8fcaSKan Liang 1216fc4b8fcaSKan Liang return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED)); 121732451614SKan Liang } 121832451614SKan Liang 121927f6d22bSBorislav Petkov #ifdef CONFIG_CPU_SUP_AMD 122027f6d22bSBorislav Petkov 122127f6d22bSBorislav Petkov int amd_pmu_init(void); 1222cc37e520SStephane Eranian 1223cc37e520SStephane Eranian #ifdef CONFIG_PERF_EVENTS_AMD_BRS 1224ada54345SStephane Eranian int amd_brs_init(void); 1225ada54345SStephane Eranian void amd_brs_disable(void); 1226ada54345SStephane Eranian void amd_brs_enable(void); 1227ada54345SStephane Eranian void amd_brs_enable_all(void); 1228ada54345SStephane Eranian void amd_brs_disable_all(void); 1229ada54345SStephane Eranian void amd_brs_drain(void); 1230d5616bacSStephane Eranian void amd_brs_lopwr_init(void); 1231ada54345SStephane Eranian void amd_brs_disable_all(void); 1232ada54345SStephane Eranian int amd_brs_setup_filter(struct perf_event *event); 1233ada54345SStephane Eranian void amd_brs_reset(void); 1234ada54345SStephane Eranian 1235ada54345SStephane Eranian static inline void amd_pmu_brs_add(struct perf_event *event) 1236ada54345SStephane Eranian { 1237ada54345SStephane Eranian struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1238ada54345SStephane Eranian 1239ada54345SStephane Eranian perf_sched_cb_inc(event->ctx->pmu); 1240ada54345SStephane Eranian cpuc->lbr_users++; 1241ada54345SStephane Eranian /* 1242ada54345SStephane Eranian * No need to reset BRS because it is reset 1243ada54345SStephane Eranian * on brs_enable() and it is saturating 1244ada54345SStephane Eranian */ 1245ada54345SStephane Eranian } 1246ada54345SStephane Eranian 1247ada54345SStephane Eranian static inline void amd_pmu_brs_del(struct perf_event *event) 1248ada54345SStephane Eranian { 1249ada54345SStephane Eranian struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1250ada54345SStephane Eranian 1251ada54345SStephane Eranian cpuc->lbr_users--; 1252ada54345SStephane Eranian WARN_ON_ONCE(cpuc->lbr_users < 0); 1253ada54345SStephane Eranian 1254ada54345SStephane Eranian perf_sched_cb_dec(event->ctx->pmu); 1255ada54345SStephane Eranian } 1256ada54345SStephane Eranian 1257ada54345SStephane Eranian void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool sched_in); 1258cc37e520SStephane Eranian #else 1259cc37e520SStephane Eranian static inline int amd_brs_init(void) 1260cc37e520SStephane Eranian { 1261cc37e520SStephane Eranian return 0; 1262cc37e520SStephane Eranian } 1263cc37e520SStephane Eranian static inline void amd_brs_disable(void) {} 1264cc37e520SStephane Eranian static inline void amd_brs_enable(void) {} 1265cc37e520SStephane Eranian static inline void amd_brs_drain(void) {} 1266cc37e520SStephane Eranian static inline void amd_brs_lopwr_init(void) {} 1267cc37e520SStephane Eranian static inline void amd_brs_disable_all(void) {} 1268cc37e520SStephane Eranian static inline int amd_brs_setup_filter(struct perf_event *event) 1269cc37e520SStephane Eranian { 1270cc37e520SStephane Eranian return 0; 1271cc37e520SStephane Eranian } 1272cc37e520SStephane Eranian static inline void amd_brs_reset(void) {} 1273cc37e520SStephane Eranian 1274cc37e520SStephane Eranian static inline void amd_pmu_brs_add(struct perf_event *event) 1275cc37e520SStephane Eranian { 1276cc37e520SStephane Eranian } 1277cc37e520SStephane Eranian 1278cc37e520SStephane Eranian static inline void amd_pmu_brs_del(struct perf_event *event) 1279cc37e520SStephane Eranian { 1280cc37e520SStephane Eranian } 1281cc37e520SStephane Eranian 1282cc37e520SStephane Eranian static inline void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool sched_in) 1283cc37e520SStephane Eranian { 1284cc37e520SStephane Eranian } 1285cc37e520SStephane Eranian 1286cc37e520SStephane Eranian static inline void amd_brs_enable_all(void) 1287cc37e520SStephane Eranian { 1288cc37e520SStephane Eranian } 1289cc37e520SStephane Eranian 1290cc37e520SStephane Eranian #endif 1291ba2fe750SStephane Eranian 129227f6d22bSBorislav Petkov #else /* CONFIG_CPU_SUP_AMD */ 129327f6d22bSBorislav Petkov 129427f6d22bSBorislav Petkov static inline int amd_pmu_init(void) 129527f6d22bSBorislav Petkov { 129627f6d22bSBorislav Petkov return 0; 129727f6d22bSBorislav Petkov } 129827f6d22bSBorislav Petkov 1299ada54345SStephane Eranian static inline int amd_brs_init(void) 1300ada54345SStephane Eranian { 1301ada54345SStephane Eranian return -EOPNOTSUPP; 1302ada54345SStephane Eranian } 1303ada54345SStephane Eranian 1304ada54345SStephane Eranian static inline void amd_brs_drain(void) 1305ada54345SStephane Eranian { 1306ada54345SStephane Eranian } 1307ada54345SStephane Eranian 1308ada54345SStephane Eranian static inline void amd_brs_enable_all(void) 1309ada54345SStephane Eranian { 1310ada54345SStephane Eranian } 1311ada54345SStephane Eranian 1312ada54345SStephane Eranian static inline void amd_brs_disable_all(void) 1313ada54345SStephane Eranian { 1314ada54345SStephane Eranian } 131527f6d22bSBorislav Petkov #endif /* CONFIG_CPU_SUP_AMD */ 131627f6d22bSBorislav Petkov 131742880f72SAlexander Shishkin static inline int is_pebs_pt(struct perf_event *event) 131842880f72SAlexander Shishkin { 131942880f72SAlexander Shishkin return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT); 132042880f72SAlexander Shishkin } 132142880f72SAlexander Shishkin 132227f6d22bSBorislav Petkov #ifdef CONFIG_CPU_SUP_INTEL 132327f6d22bSBorislav Petkov 132481ec3f3cSJiri Olsa static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period) 132527f6d22bSBorislav Petkov { 132667266c10SJiri Olsa struct hw_perf_event *hwc = &event->hw; 132767266c10SJiri Olsa unsigned int hw_event, bts_event; 132827f6d22bSBorislav Petkov 132967266c10SJiri Olsa if (event->attr.freq) 133027f6d22bSBorislav Petkov return false; 133167266c10SJiri Olsa 133267266c10SJiri Olsa hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 133367266c10SJiri Olsa bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 133467266c10SJiri Olsa 133581ec3f3cSJiri Olsa return hw_event == bts_event && period == 1; 133681ec3f3cSJiri Olsa } 133781ec3f3cSJiri Olsa 133881ec3f3cSJiri Olsa static inline bool intel_pmu_has_bts(struct perf_event *event) 133981ec3f3cSJiri Olsa { 134081ec3f3cSJiri Olsa struct hw_perf_event *hwc = &event->hw; 134181ec3f3cSJiri Olsa 134281ec3f3cSJiri Olsa return intel_pmu_has_bts_period(event, hwc->sample_period); 134327f6d22bSBorislav Petkov } 134427f6d22bSBorislav Petkov 1345c22ac2a3SSong Liu static __always_inline void __intel_pmu_pebs_disable_all(void) 1346c22ac2a3SSong Liu { 1347c22ac2a3SSong Liu wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 1348c22ac2a3SSong Liu } 1349c22ac2a3SSong Liu 1350c22ac2a3SSong Liu static __always_inline void __intel_pmu_arch_lbr_disable(void) 1351c22ac2a3SSong Liu { 1352c22ac2a3SSong Liu wrmsrl(MSR_ARCH_LBR_CTL, 0); 1353c22ac2a3SSong Liu } 1354c22ac2a3SSong Liu 1355c22ac2a3SSong Liu static __always_inline void __intel_pmu_lbr_disable(void) 1356c22ac2a3SSong Liu { 1357c22ac2a3SSong Liu u64 debugctl; 1358c22ac2a3SSong Liu 1359c22ac2a3SSong Liu rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1360c22ac2a3SSong Liu debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 1361c22ac2a3SSong Liu wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1362c22ac2a3SSong Liu } 1363c22ac2a3SSong Liu 136427f6d22bSBorislav Petkov int intel_pmu_save_and_restart(struct perf_event *event); 136527f6d22bSBorislav Petkov 136627f6d22bSBorislav Petkov struct event_constraint * 136727f6d22bSBorislav Petkov x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 136827f6d22bSBorislav Petkov struct perf_event *event); 136927f6d22bSBorislav Petkov 1370d01b1f96SPeter Zijlstra (Intel) extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu); 1371d01b1f96SPeter Zijlstra (Intel) extern void intel_cpuc_finish(struct cpu_hw_events *cpuc); 137227f6d22bSBorislav Petkov 137327f6d22bSBorislav Petkov int intel_pmu_init(void); 137427f6d22bSBorislav Petkov 137527f6d22bSBorislav Petkov void init_debug_store_on_cpu(int cpu); 137627f6d22bSBorislav Petkov 137727f6d22bSBorislav Petkov void fini_debug_store_on_cpu(int cpu); 137827f6d22bSBorislav Petkov 137927f6d22bSBorislav Petkov void release_ds_buffers(void); 138027f6d22bSBorislav Petkov 138127f6d22bSBorislav Petkov void reserve_ds_buffers(void); 138227f6d22bSBorislav Petkov 1383c085fb87SKan Liang void release_lbr_buffers(void); 1384c085fb87SKan Liang 1385488e13a4SLike Xu void reserve_lbr_buffers(void); 1386488e13a4SLike Xu 138727f6d22bSBorislav Petkov extern struct event_constraint bts_constraint; 1388097e4311SLike Xu extern struct event_constraint vlbr_constraint; 138927f6d22bSBorislav Petkov 139027f6d22bSBorislav Petkov void intel_pmu_enable_bts(u64 config); 139127f6d22bSBorislav Petkov 139227f6d22bSBorislav Petkov void intel_pmu_disable_bts(void); 139327f6d22bSBorislav Petkov 139427f6d22bSBorislav Petkov int intel_pmu_drain_bts_buffer(void); 139527f6d22bSBorislav Petkov 139627f6d22bSBorislav Petkov extern struct event_constraint intel_core2_pebs_event_constraints[]; 139727f6d22bSBorislav Petkov 139827f6d22bSBorislav Petkov extern struct event_constraint intel_atom_pebs_event_constraints[]; 139927f6d22bSBorislav Petkov 140027f6d22bSBorislav Petkov extern struct event_constraint intel_slm_pebs_event_constraints[]; 140127f6d22bSBorislav Petkov 14028b92c3a7SKan Liang extern struct event_constraint intel_glm_pebs_event_constraints[]; 14038b92c3a7SKan Liang 1404dd0b06b5SKan Liang extern struct event_constraint intel_glp_pebs_event_constraints[]; 1405dd0b06b5SKan Liang 1406f83d2f91SKan Liang extern struct event_constraint intel_grt_pebs_event_constraints[]; 1407f83d2f91SKan Liang 140827f6d22bSBorislav Petkov extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 140927f6d22bSBorislav Petkov 141027f6d22bSBorislav Petkov extern struct event_constraint intel_westmere_pebs_event_constraints[]; 141127f6d22bSBorislav Petkov 141227f6d22bSBorislav Petkov extern struct event_constraint intel_snb_pebs_event_constraints[]; 141327f6d22bSBorislav Petkov 141427f6d22bSBorislav Petkov extern struct event_constraint intel_ivb_pebs_event_constraints[]; 141527f6d22bSBorislav Petkov 141627f6d22bSBorislav Petkov extern struct event_constraint intel_hsw_pebs_event_constraints[]; 141727f6d22bSBorislav Petkov 1418b3e62463SStephane Eranian extern struct event_constraint intel_bdw_pebs_event_constraints[]; 1419b3e62463SStephane Eranian 142027f6d22bSBorislav Petkov extern struct event_constraint intel_skl_pebs_event_constraints[]; 142127f6d22bSBorislav Petkov 142260176089SKan Liang extern struct event_constraint intel_icl_pebs_event_constraints[]; 142360176089SKan Liang 142461b985e3SKan Liang extern struct event_constraint intel_spr_pebs_event_constraints[]; 142561b985e3SKan Liang 142627f6d22bSBorislav Petkov struct event_constraint *intel_pebs_constraints(struct perf_event *event); 142727f6d22bSBorislav Petkov 142868f7082fSPeter Zijlstra void intel_pmu_pebs_add(struct perf_event *event); 142968f7082fSPeter Zijlstra 143068f7082fSPeter Zijlstra void intel_pmu_pebs_del(struct perf_event *event); 143168f7082fSPeter Zijlstra 143227f6d22bSBorislav Petkov void intel_pmu_pebs_enable(struct perf_event *event); 143327f6d22bSBorislav Petkov 143427f6d22bSBorislav Petkov void intel_pmu_pebs_disable(struct perf_event *event); 143527f6d22bSBorislav Petkov 143627f6d22bSBorislav Petkov void intel_pmu_pebs_enable_all(void); 143727f6d22bSBorislav Petkov 143827f6d22bSBorislav Petkov void intel_pmu_pebs_disable_all(void); 143927f6d22bSBorislav Petkov 144027f6d22bSBorislav Petkov void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in); 144127f6d22bSBorislav Petkov 14425bee2cc6SKan Liang void intel_pmu_auto_reload_read(struct perf_event *event); 14435bee2cc6SKan Liang 14445624986dSKan Liang void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr); 1445c22497f5SKan Liang 144627f6d22bSBorislav Petkov void intel_ds_init(void); 144727f6d22bSBorislav Petkov 1448421ca868SAlexey Budankov void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev, 1449421ca868SAlexey Budankov struct perf_event_context *next); 1450421ca868SAlexey Budankov 145127f6d22bSBorislav Petkov void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in); 145227f6d22bSBorislav Petkov 145319fc9dddSDavid Carrillo-Cisneros u64 lbr_from_signext_quirk_wr(u64 val); 145419fc9dddSDavid Carrillo-Cisneros 145527f6d22bSBorislav Petkov void intel_pmu_lbr_reset(void); 145627f6d22bSBorislav Petkov 14579f354a72SKan Liang void intel_pmu_lbr_reset_32(void); 14589f354a72SKan Liang 14599f354a72SKan Liang void intel_pmu_lbr_reset_64(void); 14609f354a72SKan Liang 146168f7082fSPeter Zijlstra void intel_pmu_lbr_add(struct perf_event *event); 146227f6d22bSBorislav Petkov 146368f7082fSPeter Zijlstra void intel_pmu_lbr_del(struct perf_event *event); 146427f6d22bSBorislav Petkov 146527f6d22bSBorislav Petkov void intel_pmu_lbr_enable_all(bool pmi); 146627f6d22bSBorislav Petkov 146727f6d22bSBorislav Petkov void intel_pmu_lbr_disable_all(void); 146827f6d22bSBorislav Petkov 146927f6d22bSBorislav Petkov void intel_pmu_lbr_read(void); 147027f6d22bSBorislav Petkov 1471c301b1d8SKan Liang void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc); 1472c301b1d8SKan Liang 1473c301b1d8SKan Liang void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc); 1474c301b1d8SKan Liang 1475799571bfSKan Liang void intel_pmu_lbr_save(void *ctx); 1476799571bfSKan Liang 1477799571bfSKan Liang void intel_pmu_lbr_restore(void *ctx); 1478799571bfSKan Liang 147927f6d22bSBorislav Petkov void intel_pmu_lbr_init_core(void); 148027f6d22bSBorislav Petkov 148127f6d22bSBorislav Petkov void intel_pmu_lbr_init_nhm(void); 148227f6d22bSBorislav Petkov 148327f6d22bSBorislav Petkov void intel_pmu_lbr_init_atom(void); 148427f6d22bSBorislav Petkov 1485f21d5adcSKan Liang void intel_pmu_lbr_init_slm(void); 1486f21d5adcSKan Liang 148727f6d22bSBorislav Petkov void intel_pmu_lbr_init_snb(void); 148827f6d22bSBorislav Petkov 148927f6d22bSBorislav Petkov void intel_pmu_lbr_init_hsw(void); 149027f6d22bSBorislav Petkov 149127f6d22bSBorislav Petkov void intel_pmu_lbr_init_skl(void); 149227f6d22bSBorislav Petkov 149327f6d22bSBorislav Petkov void intel_pmu_lbr_init_knl(void); 149427f6d22bSBorislav Petkov 14951ac7fd81SPeter Zijlstra (Intel) void intel_pmu_lbr_init(void); 14961ac7fd81SPeter Zijlstra (Intel) 149747125db2SKan Liang void intel_pmu_arch_lbr_init(void); 149847125db2SKan Liang 1499e17dc653SAndi Kleen void intel_pmu_pebs_data_source_nhm(void); 1500e17dc653SAndi Kleen 15016ae5fa61SAndi Kleen void intel_pmu_pebs_data_source_skl(bool pmem); 15026ae5fa61SAndi Kleen 150327f6d22bSBorislav Petkov int intel_pmu_setup_lbr_filter(struct perf_event *event); 150427f6d22bSBorislav Petkov 150527f6d22bSBorislav Petkov void intel_pt_interrupt(void); 150627f6d22bSBorislav Petkov 150727f6d22bSBorislav Petkov int intel_bts_interrupt(void); 150827f6d22bSBorislav Petkov 150927f6d22bSBorislav Petkov void intel_bts_enable_local(void); 151027f6d22bSBorislav Petkov 151127f6d22bSBorislav Petkov void intel_bts_disable_local(void); 151227f6d22bSBorislav Petkov 151327f6d22bSBorislav Petkov int p4_pmu_init(void); 151427f6d22bSBorislav Petkov 151527f6d22bSBorislav Petkov int p6_pmu_init(void); 151627f6d22bSBorislav Petkov 151727f6d22bSBorislav Petkov int knc_pmu_init(void); 151827f6d22bSBorislav Petkov 151927f6d22bSBorislav Petkov static inline int is_ht_workaround_enabled(void) 152027f6d22bSBorislav Petkov { 152127f6d22bSBorislav Petkov return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); 152227f6d22bSBorislav Petkov } 152327f6d22bSBorislav Petkov 152427f6d22bSBorislav Petkov #else /* CONFIG_CPU_SUP_INTEL */ 152527f6d22bSBorislav Petkov 152627f6d22bSBorislav Petkov static inline void reserve_ds_buffers(void) 152727f6d22bSBorislav Petkov { 152827f6d22bSBorislav Petkov } 152927f6d22bSBorislav Petkov 153027f6d22bSBorislav Petkov static inline void release_ds_buffers(void) 153127f6d22bSBorislav Petkov { 153227f6d22bSBorislav Petkov } 153327f6d22bSBorislav Petkov 1534c085fb87SKan Liang static inline void release_lbr_buffers(void) 1535c085fb87SKan Liang { 1536c085fb87SKan Liang } 1537c085fb87SKan Liang 1538488e13a4SLike Xu static inline void reserve_lbr_buffers(void) 1539488e13a4SLike Xu { 1540488e13a4SLike Xu } 1541488e13a4SLike Xu 154227f6d22bSBorislav Petkov static inline int intel_pmu_init(void) 154327f6d22bSBorislav Petkov { 154427f6d22bSBorislav Petkov return 0; 154527f6d22bSBorislav Petkov } 154627f6d22bSBorislav Petkov 1547f764c58bSPeter Zijlstra static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 154827f6d22bSBorislav Petkov { 1549d01b1f96SPeter Zijlstra (Intel) return 0; 1550d01b1f96SPeter Zijlstra (Intel) } 1551d01b1f96SPeter Zijlstra (Intel) 1552f764c58bSPeter Zijlstra static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc) 1553d01b1f96SPeter Zijlstra (Intel) { 155427f6d22bSBorislav Petkov } 155527f6d22bSBorislav Petkov 155627f6d22bSBorislav Petkov static inline int is_ht_workaround_enabled(void) 155727f6d22bSBorislav Petkov { 155827f6d22bSBorislav Petkov return 0; 155927f6d22bSBorislav Petkov } 156027f6d22bSBorislav Petkov #endif /* CONFIG_CPU_SUP_INTEL */ 15613a4ac121SCodyYao-oc 15623a4ac121SCodyYao-oc #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN)) 15633a4ac121SCodyYao-oc int zhaoxin_pmu_init(void); 15643a4ac121SCodyYao-oc #else 15653a4ac121SCodyYao-oc static inline int zhaoxin_pmu_init(void) 15663a4ac121SCodyYao-oc { 15673a4ac121SCodyYao-oc return 0; 15683a4ac121SCodyYao-oc } 15693a4ac121SCodyYao-oc #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/ 1570