127f6d22bSBorislav Petkov /* 227f6d22bSBorislav Petkov * Performance events x86 architecture header 327f6d22bSBorislav Petkov * 427f6d22bSBorislav Petkov * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 527f6d22bSBorislav Petkov * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 627f6d22bSBorislav Petkov * Copyright (C) 2009 Jaswinder Singh Rajput 727f6d22bSBorislav Petkov * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 827f6d22bSBorislav Petkov * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 927f6d22bSBorislav Petkov * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 1027f6d22bSBorislav Petkov * Copyright (C) 2009 Google, Inc., Stephane Eranian 1127f6d22bSBorislav Petkov * 1227f6d22bSBorislav Petkov * For licencing details see kernel-base/COPYING 1327f6d22bSBorislav Petkov */ 1427f6d22bSBorislav Petkov 1527f6d22bSBorislav Petkov #include <linux/perf_event.h> 1627f6d22bSBorislav Petkov 1710043e02SThomas Gleixner #include <asm/intel_ds.h> 1810043e02SThomas Gleixner 1927f6d22bSBorislav Petkov /* To enable MSR tracing please use the generic trace points. */ 2027f6d22bSBorislav Petkov 2127f6d22bSBorislav Petkov /* 2227f6d22bSBorislav Petkov * | NHM/WSM | SNB | 2327f6d22bSBorislav Petkov * register ------------------------------- 2427f6d22bSBorislav Petkov * | HT | no HT | HT | no HT | 2527f6d22bSBorislav Petkov *----------------------------------------- 2627f6d22bSBorislav Petkov * offcore | core | core | cpu | core | 2727f6d22bSBorislav Petkov * lbr_sel | core | core | cpu | core | 2827f6d22bSBorislav Petkov * ld_lat | cpu | core | cpu | core | 2927f6d22bSBorislav Petkov *----------------------------------------- 3027f6d22bSBorislav Petkov * 3127f6d22bSBorislav Petkov * Given that there is a small number of shared regs, 3227f6d22bSBorislav Petkov * we can pre-allocate their slot in the per-cpu 3327f6d22bSBorislav Petkov * per-core reg tables. 3427f6d22bSBorislav Petkov */ 3527f6d22bSBorislav Petkov enum extra_reg_type { 3627f6d22bSBorislav Petkov EXTRA_REG_NONE = -1, /* not used */ 3727f6d22bSBorislav Petkov 3827f6d22bSBorislav Petkov EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ 3927f6d22bSBorislav Petkov EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ 4027f6d22bSBorislav Petkov EXTRA_REG_LBR = 2, /* lbr_select */ 4127f6d22bSBorislav Petkov EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ 4227f6d22bSBorislav Petkov EXTRA_REG_FE = 4, /* fe_* */ 4327f6d22bSBorislav Petkov 4427f6d22bSBorislav Petkov EXTRA_REG_MAX /* number of entries needed */ 4527f6d22bSBorislav Petkov }; 4627f6d22bSBorislav Petkov 4727f6d22bSBorislav Petkov struct event_constraint { 4827f6d22bSBorislav Petkov union { 4927f6d22bSBorislav Petkov unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 5027f6d22bSBorislav Petkov u64 idxmsk64; 5127f6d22bSBorislav Petkov }; 5227f6d22bSBorislav Petkov u64 code; 5327f6d22bSBorislav Petkov u64 cmask; 5427f6d22bSBorislav Petkov int weight; 5527f6d22bSBorislav Petkov int overlap; 5627f6d22bSBorislav Petkov int flags; 5763b79f6eSPeter Zijlstra unsigned int size; 5827f6d22bSBorislav Petkov }; 591f6a1e2dSPeter Zijlstra 6063b79f6eSPeter Zijlstra static inline bool constraint_match(struct event_constraint *c, u64 ecode) 6163b79f6eSPeter Zijlstra { 6263b79f6eSPeter Zijlstra return ((ecode & c->cmask) - c->code) <= (u64)c->size; 6363b79f6eSPeter Zijlstra } 6463b79f6eSPeter Zijlstra 6527f6d22bSBorislav Petkov /* 6627f6d22bSBorislav Petkov * struct hw_perf_event.flags flags 6727f6d22bSBorislav Petkov */ 6827f6d22bSBorislav Petkov #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */ 6927f6d22bSBorislav Petkov #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */ 7027f6d22bSBorislav Petkov #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */ 711f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_PEBS_LD_HSW 0x0008 /* haswell style datala, load */ 721f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_PEBS_NA_HSW 0x0010 /* haswell style datala, unknown */ 731f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_EXCL 0x0020 /* HT exclusivity on counter */ 741f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_DYNAMIC 0x0040 /* dynamic alloc'd constraint */ 751f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0080 /* grant rdpmc permission */ 761f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_EXCL_ACCT 0x0100 /* accounted EXCL event */ 771f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_AUTO_RELOAD 0x0200 /* use PEBS auto-reload */ 781f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_LARGE_PEBS 0x0400 /* use large PEBS */ 7942880f72SAlexander Shishkin #define PERF_X86_EVENT_PEBS_VIA_PT 0x0800 /* use PT buffer for PEBS */ 80471af006SKim Phillips #define PERF_X86_EVENT_PAIR 0x1000 /* Large Increment per Cycle */ 81e1ad1ac2SLike Xu #define PERF_X86_EVENT_LBR_SELECT 0x2000 /* Save/Restore MSR_LBR_SELECT */ 827b2c05a1SKan Liang #define PERF_X86_EVENT_TOPDOWN 0x4000 /* Count Topdown slots/metrics events */ 837b2c05a1SKan Liang 847b2c05a1SKan Liang static inline bool is_topdown_count(struct perf_event *event) 857b2c05a1SKan Liang { 867b2c05a1SKan Liang return event->hw.flags & PERF_X86_EVENT_TOPDOWN; 877b2c05a1SKan Liang } 887b2c05a1SKan Liang 897b2c05a1SKan Liang static inline bool is_metric_event(struct perf_event *event) 907b2c05a1SKan Liang { 917b2c05a1SKan Liang u64 config = event->attr.config; 927b2c05a1SKan Liang 937b2c05a1SKan Liang return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) && 947b2c05a1SKan Liang ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) && 957b2c05a1SKan Liang ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX); 967b2c05a1SKan Liang } 977b2c05a1SKan Liang 987b2c05a1SKan Liang static inline bool is_slots_event(struct perf_event *event) 997b2c05a1SKan Liang { 1007b2c05a1SKan Liang return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS; 1017b2c05a1SKan Liang } 1027b2c05a1SKan Liang 1037b2c05a1SKan Liang static inline bool is_topdown_event(struct perf_event *event) 1047b2c05a1SKan Liang { 1057b2c05a1SKan Liang return is_metric_event(event) || is_slots_event(event); 1067b2c05a1SKan Liang } 10727f6d22bSBorislav Petkov 10827f6d22bSBorislav Petkov struct amd_nb { 10927f6d22bSBorislav Petkov int nb_id; /* NorthBridge id */ 11027f6d22bSBorislav Petkov int refcnt; /* reference count */ 11127f6d22bSBorislav Petkov struct perf_event *owners[X86_PMC_IDX_MAX]; 11227f6d22bSBorislav Petkov struct event_constraint event_constraints[X86_PMC_IDX_MAX]; 11327f6d22bSBorislav Petkov }; 11427f6d22bSBorislav Petkov 115fd583ad1SKan Liang #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) 11642880f72SAlexander Shishkin #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60) 11742880f72SAlexander Shishkin #define PEBS_OUTPUT_OFFSET 61 11842880f72SAlexander Shishkin #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET) 11942880f72SAlexander Shishkin #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET) 12042880f72SAlexander Shishkin #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD) 12127f6d22bSBorislav Petkov 12227f6d22bSBorislav Petkov /* 12327f6d22bSBorislav Petkov * Flags PEBS can handle without an PMI. 12427f6d22bSBorislav Petkov * 12527f6d22bSBorislav Petkov * TID can only be handled by flushing at context switch. 1262fe1bc1fSAndi Kleen * REGS_USER can be handled for events limited to ring 3. 12727f6d22bSBorislav Petkov * 12827f6d22bSBorislav Petkov */ 129174afc3eSKan Liang #define LARGE_PEBS_FLAGS \ 13027f6d22bSBorislav Petkov (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 13127f6d22bSBorislav Petkov PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 13227f6d22bSBorislav Petkov PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 1332fe1bc1fSAndi Kleen PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ 13411974914SJiri Olsa PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \ 13511974914SJiri Olsa PERF_SAMPLE_PERIOD) 13627f6d22bSBorislav Petkov 1379d5dcc93SKan Liang #define PEBS_GP_REGS \ 1389d5dcc93SKan Liang ((1ULL << PERF_REG_X86_AX) | \ 1399d5dcc93SKan Liang (1ULL << PERF_REG_X86_BX) | \ 1409d5dcc93SKan Liang (1ULL << PERF_REG_X86_CX) | \ 1419d5dcc93SKan Liang (1ULL << PERF_REG_X86_DX) | \ 1429d5dcc93SKan Liang (1ULL << PERF_REG_X86_DI) | \ 1439d5dcc93SKan Liang (1ULL << PERF_REG_X86_SI) | \ 1449d5dcc93SKan Liang (1ULL << PERF_REG_X86_SP) | \ 1459d5dcc93SKan Liang (1ULL << PERF_REG_X86_BP) | \ 1469d5dcc93SKan Liang (1ULL << PERF_REG_X86_IP) | \ 1479d5dcc93SKan Liang (1ULL << PERF_REG_X86_FLAGS) | \ 1489d5dcc93SKan Liang (1ULL << PERF_REG_X86_R8) | \ 1499d5dcc93SKan Liang (1ULL << PERF_REG_X86_R9) | \ 1509d5dcc93SKan Liang (1ULL << PERF_REG_X86_R10) | \ 1519d5dcc93SKan Liang (1ULL << PERF_REG_X86_R11) | \ 1529d5dcc93SKan Liang (1ULL << PERF_REG_X86_R12) | \ 1539d5dcc93SKan Liang (1ULL << PERF_REG_X86_R13) | \ 1549d5dcc93SKan Liang (1ULL << PERF_REG_X86_R14) | \ 1559d5dcc93SKan Liang (1ULL << PERF_REG_X86_R15)) 1562fe1bc1fSAndi Kleen 15727f6d22bSBorislav Petkov /* 15827f6d22bSBorislav Petkov * Per register state. 15927f6d22bSBorislav Petkov */ 16027f6d22bSBorislav Petkov struct er_account { 16127f6d22bSBorislav Petkov raw_spinlock_t lock; /* per-core: protect structure */ 16227f6d22bSBorislav Petkov u64 config; /* extra MSR config */ 16327f6d22bSBorislav Petkov u64 reg; /* extra MSR number */ 16427f6d22bSBorislav Petkov atomic_t ref; /* reference count */ 16527f6d22bSBorislav Petkov }; 16627f6d22bSBorislav Petkov 16727f6d22bSBorislav Petkov /* 16827f6d22bSBorislav Petkov * Per core/cpu state 16927f6d22bSBorislav Petkov * 17027f6d22bSBorislav Petkov * Used to coordinate shared registers between HT threads or 17127f6d22bSBorislav Petkov * among events on a single PMU. 17227f6d22bSBorislav Petkov */ 17327f6d22bSBorislav Petkov struct intel_shared_regs { 17427f6d22bSBorislav Petkov struct er_account regs[EXTRA_REG_MAX]; 17527f6d22bSBorislav Petkov int refcnt; /* per-core: #HT threads */ 17627f6d22bSBorislav Petkov unsigned core_id; /* per-core: core id */ 17727f6d22bSBorislav Petkov }; 17827f6d22bSBorislav Petkov 17927f6d22bSBorislav Petkov enum intel_excl_state_type { 18027f6d22bSBorislav Petkov INTEL_EXCL_UNUSED = 0, /* counter is unused */ 18127f6d22bSBorislav Petkov INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ 18227f6d22bSBorislav Petkov INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ 18327f6d22bSBorislav Petkov }; 18427f6d22bSBorislav Petkov 18527f6d22bSBorislav Petkov struct intel_excl_states { 18627f6d22bSBorislav Petkov enum intel_excl_state_type state[X86_PMC_IDX_MAX]; 18727f6d22bSBorislav Petkov bool sched_started; /* true if scheduling has started */ 18827f6d22bSBorislav Petkov }; 18927f6d22bSBorislav Petkov 19027f6d22bSBorislav Petkov struct intel_excl_cntrs { 19127f6d22bSBorislav Petkov raw_spinlock_t lock; 19227f6d22bSBorislav Petkov 19327f6d22bSBorislav Petkov struct intel_excl_states states[2]; 19427f6d22bSBorislav Petkov 19527f6d22bSBorislav Petkov union { 19627f6d22bSBorislav Petkov u16 has_exclusive[2]; 19727f6d22bSBorislav Petkov u32 exclusive_present; 19827f6d22bSBorislav Petkov }; 19927f6d22bSBorislav Petkov 20027f6d22bSBorislav Petkov int refcnt; /* per-core: #HT threads */ 20127f6d22bSBorislav Petkov unsigned core_id; /* per-core: core id */ 20227f6d22bSBorislav Petkov }; 20327f6d22bSBorislav Petkov 2048b077e4aSKan Liang struct x86_perf_task_context; 20527f6d22bSBorislav Petkov #define MAX_LBR_ENTRIES 32 20627f6d22bSBorislav Petkov 20727f6d22bSBorislav Petkov enum { 2089f354a72SKan Liang LBR_FORMAT_32 = 0x00, 2099f354a72SKan Liang LBR_FORMAT_LIP = 0x01, 2109f354a72SKan Liang LBR_FORMAT_EIP = 0x02, 2119f354a72SKan Liang LBR_FORMAT_EIP_FLAGS = 0x03, 2129f354a72SKan Liang LBR_FORMAT_EIP_FLAGS2 = 0x04, 2139f354a72SKan Liang LBR_FORMAT_INFO = 0x05, 2149f354a72SKan Liang LBR_FORMAT_TIME = 0x06, 2159f354a72SKan Liang LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME, 2169f354a72SKan Liang }; 2179f354a72SKan Liang 2189f354a72SKan Liang enum { 21927f6d22bSBorislav Petkov X86_PERF_KFREE_SHARED = 0, 22027f6d22bSBorislav Petkov X86_PERF_KFREE_EXCL = 1, 22127f6d22bSBorislav Petkov X86_PERF_KFREE_MAX 22227f6d22bSBorislav Petkov }; 22327f6d22bSBorislav Petkov 22427f6d22bSBorislav Petkov struct cpu_hw_events { 22527f6d22bSBorislav Petkov /* 22627f6d22bSBorislav Petkov * Generic x86 PMC bits 22727f6d22bSBorislav Petkov */ 22827f6d22bSBorislav Petkov struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ 22927f6d22bSBorislav Petkov unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 23027f6d22bSBorislav Petkov unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 23127f6d22bSBorislav Petkov int enabled; 23227f6d22bSBorislav Petkov 23327f6d22bSBorislav Petkov int n_events; /* the # of events in the below arrays */ 23427f6d22bSBorislav Petkov int n_added; /* the # last events in the below arrays; 23527f6d22bSBorislav Petkov they've never been enabled yet */ 23627f6d22bSBorislav Petkov int n_txn; /* the # last events in the below arrays; 23727f6d22bSBorislav Petkov added in the current transaction */ 238871a93b0SPeter Zijlstra int n_txn_pair; 2393dbde695SPeter Zijlstra int n_txn_metric; 24027f6d22bSBorislav Petkov int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ 24127f6d22bSBorislav Petkov u64 tags[X86_PMC_IDX_MAX]; 24227f6d22bSBorislav Petkov 24327f6d22bSBorislav Petkov struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ 24427f6d22bSBorislav Petkov struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; 24527f6d22bSBorislav Petkov 24627f6d22bSBorislav Petkov int n_excl; /* the number of exclusive events */ 24727f6d22bSBorislav Petkov 24827f6d22bSBorislav Petkov unsigned int txn_flags; 24927f6d22bSBorislav Petkov int is_fake; 25027f6d22bSBorislav Petkov 25127f6d22bSBorislav Petkov /* 25227f6d22bSBorislav Petkov * Intel DebugStore bits 25327f6d22bSBorislav Petkov */ 25427f6d22bSBorislav Petkov struct debug_store *ds; 255c1961a46SHugh Dickins void *ds_pebs_vaddr; 256c1961a46SHugh Dickins void *ds_bts_vaddr; 25727f6d22bSBorislav Petkov u64 pebs_enabled; 25809e61b4fSPeter Zijlstra int n_pebs; 25909e61b4fSPeter Zijlstra int n_large_pebs; 26042880f72SAlexander Shishkin int n_pebs_via_pt; 26142880f72SAlexander Shishkin int pebs_output; 26227f6d22bSBorislav Petkov 263c22497f5SKan Liang /* Current super set of events hardware configuration */ 264c22497f5SKan Liang u64 pebs_data_cfg; 265c22497f5SKan Liang u64 active_pebs_data_cfg; 266c22497f5SKan Liang int pebs_record_size; 267c22497f5SKan Liang 26827f6d22bSBorislav Petkov /* 26927f6d22bSBorislav Petkov * Intel LBR bits 27027f6d22bSBorislav Petkov */ 27127f6d22bSBorislav Petkov int lbr_users; 272d3617b98SAndi Kleen int lbr_pebs_users; 27327f6d22bSBorislav Petkov struct perf_branch_stack lbr_stack; 27427f6d22bSBorislav Petkov struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; 27549d8184fSKan Liang union { 27627f6d22bSBorislav Petkov struct er_account *lbr_sel; 27749d8184fSKan Liang struct er_account *lbr_ctl; 27849d8184fSKan Liang }; 27927f6d22bSBorislav Petkov u64 br_sel; 280f42be865SKan Liang void *last_task_ctx; 2818b077e4aSKan Liang int last_log_id; 282e1ad1ac2SLike Xu int lbr_select; 283c085fb87SKan Liang void *lbr_xsave; 28427f6d22bSBorislav Petkov 28527f6d22bSBorislav Petkov /* 28627f6d22bSBorislav Petkov * Intel host/guest exclude bits 28727f6d22bSBorislav Petkov */ 28827f6d22bSBorislav Petkov u64 intel_ctrl_guest_mask; 28927f6d22bSBorislav Petkov u64 intel_ctrl_host_mask; 29027f6d22bSBorislav Petkov struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; 29127f6d22bSBorislav Petkov 29227f6d22bSBorislav Petkov /* 29327f6d22bSBorislav Petkov * Intel checkpoint mask 29427f6d22bSBorislav Petkov */ 29527f6d22bSBorislav Petkov u64 intel_cp_status; 29627f6d22bSBorislav Petkov 29727f6d22bSBorislav Petkov /* 29827f6d22bSBorislav Petkov * manage shared (per-core, per-cpu) registers 29927f6d22bSBorislav Petkov * used on Intel NHM/WSM/SNB 30027f6d22bSBorislav Petkov */ 30127f6d22bSBorislav Petkov struct intel_shared_regs *shared_regs; 30227f6d22bSBorislav Petkov /* 30327f6d22bSBorislav Petkov * manage exclusive counter access between hyperthread 30427f6d22bSBorislav Petkov */ 30527f6d22bSBorislav Petkov struct event_constraint *constraint_list; /* in enable order */ 30627f6d22bSBorislav Petkov struct intel_excl_cntrs *excl_cntrs; 30727f6d22bSBorislav Petkov int excl_thread_id; /* 0 or 1 */ 30827f6d22bSBorislav Petkov 30927f6d22bSBorislav Petkov /* 310400816f6SPeter Zijlstra (Intel) * SKL TSX_FORCE_ABORT shadow 311400816f6SPeter Zijlstra (Intel) */ 312400816f6SPeter Zijlstra (Intel) u64 tfa_shadow; 313400816f6SPeter Zijlstra (Intel) 314400816f6SPeter Zijlstra (Intel) /* 3157b2c05a1SKan Liang * Perf Metrics 3167b2c05a1SKan Liang */ 3177b2c05a1SKan Liang /* number of accepted metrics events */ 3187b2c05a1SKan Liang int n_metric; 3197b2c05a1SKan Liang 3207b2c05a1SKan Liang /* 32127f6d22bSBorislav Petkov * AMD specific bits 32227f6d22bSBorislav Petkov */ 32327f6d22bSBorislav Petkov struct amd_nb *amd_nb; 32427f6d22bSBorislav Petkov /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ 32527f6d22bSBorislav Petkov u64 perf_ctr_virt_mask; 32657388912SKim Phillips int n_pair; /* Large increment events */ 32727f6d22bSBorislav Petkov 32827f6d22bSBorislav Petkov void *kfree_on_online[X86_PERF_KFREE_MAX]; 32927f6d22bSBorislav Petkov }; 33027f6d22bSBorislav Petkov 33163b79f6eSPeter Zijlstra #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \ 33227f6d22bSBorislav Petkov { .idxmsk64 = (n) }, \ 33327f6d22bSBorislav Petkov .code = (c), \ 33463b79f6eSPeter Zijlstra .size = (e) - (c), \ 33527f6d22bSBorislav Petkov .cmask = (m), \ 33627f6d22bSBorislav Petkov .weight = (w), \ 33727f6d22bSBorislav Petkov .overlap = (o), \ 33827f6d22bSBorislav Petkov .flags = f, \ 33927f6d22bSBorislav Petkov } 34027f6d22bSBorislav Petkov 34163b79f6eSPeter Zijlstra #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ 34263b79f6eSPeter Zijlstra __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f) 34363b79f6eSPeter Zijlstra 34427f6d22bSBorislav Petkov #define EVENT_CONSTRAINT(c, n, m) \ 34527f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) 34627f6d22bSBorislav Petkov 34763b79f6eSPeter Zijlstra /* 34863b79f6eSPeter Zijlstra * The constraint_match() function only works for 'simple' event codes 34963b79f6eSPeter Zijlstra * and not for extended (AMD64_EVENTSEL_EVENT) events codes. 35063b79f6eSPeter Zijlstra */ 35163b79f6eSPeter Zijlstra #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \ 35263b79f6eSPeter Zijlstra __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0) 35363b79f6eSPeter Zijlstra 35427f6d22bSBorislav Petkov #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ 35527f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ 35627f6d22bSBorislav Petkov 0, PERF_X86_EVENT_EXCL) 35727f6d22bSBorislav Petkov 35827f6d22bSBorislav Petkov /* 35927f6d22bSBorislav Petkov * The overlap flag marks event constraints with overlapping counter 36027f6d22bSBorislav Petkov * masks. This is the case if the counter mask of such an event is not 36127f6d22bSBorislav Petkov * a subset of any other counter mask of a constraint with an equal or 36227f6d22bSBorislav Petkov * higher weight, e.g.: 36327f6d22bSBorislav Petkov * 36427f6d22bSBorislav Petkov * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); 36527f6d22bSBorislav Petkov * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); 36627f6d22bSBorislav Petkov * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); 36727f6d22bSBorislav Petkov * 36827f6d22bSBorislav Petkov * The event scheduler may not select the correct counter in the first 36927f6d22bSBorislav Petkov * cycle because it needs to know which subsequent events will be 37027f6d22bSBorislav Petkov * scheduled. It may fail to schedule the events then. So we set the 37127f6d22bSBorislav Petkov * overlap flag for such constraints to give the scheduler a hint which 37227f6d22bSBorislav Petkov * events to select for counter rescheduling. 37327f6d22bSBorislav Petkov * 37427f6d22bSBorislav Petkov * Care must be taken as the rescheduling algorithm is O(n!) which 37500f52685SIngo Molnar * will increase scheduling cycles for an over-committed system 37627f6d22bSBorislav Petkov * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros 37727f6d22bSBorislav Petkov * and its counter masks must be kept at a minimum. 37827f6d22bSBorislav Petkov */ 37927f6d22bSBorislav Petkov #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ 38027f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) 38127f6d22bSBorislav Petkov 38227f6d22bSBorislav Petkov /* 38327f6d22bSBorislav Petkov * Constraint on the Event code. 38427f6d22bSBorislav Petkov */ 38527f6d22bSBorislav Petkov #define INTEL_EVENT_CONSTRAINT(c, n) \ 38627f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) 38727f6d22bSBorislav Petkov 38827f6d22bSBorislav Petkov /* 38963b79f6eSPeter Zijlstra * Constraint on a range of Event codes 39063b79f6eSPeter Zijlstra */ 39163b79f6eSPeter Zijlstra #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \ 39263b79f6eSPeter Zijlstra EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT) 39363b79f6eSPeter Zijlstra 39463b79f6eSPeter Zijlstra /* 39527f6d22bSBorislav Petkov * Constraint on the Event code + UMask + fixed-mask 39627f6d22bSBorislav Petkov * 39727f6d22bSBorislav Petkov * filter mask to validate fixed counter events. 39827f6d22bSBorislav Petkov * the following filters disqualify for fixed counters: 39927f6d22bSBorislav Petkov * - inv 40027f6d22bSBorislav Petkov * - edge 40127f6d22bSBorislav Petkov * - cnt-mask 40227f6d22bSBorislav Petkov * - in_tx 40327f6d22bSBorislav Petkov * - in_tx_checkpointed 40427f6d22bSBorislav Petkov * The other filters are supported by fixed counters. 40527f6d22bSBorislav Petkov * The any-thread option is supported starting with v3. 40627f6d22bSBorislav Petkov */ 40727f6d22bSBorislav Petkov #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) 40827f6d22bSBorislav Petkov #define FIXED_EVENT_CONSTRAINT(c, n) \ 40927f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) 41027f6d22bSBorislav Petkov 41127f6d22bSBorislav Petkov /* 41259a854e2SKan Liang * The special metric counters do not actually exist. They are calculated from 41359a854e2SKan Liang * the combination of the FxCtr3 + MSR_PERF_METRICS. 41459a854e2SKan Liang * 41559a854e2SKan Liang * The special metric counters are mapped to a dummy offset for the scheduler. 41659a854e2SKan Liang * The sharing between multiple users of the same metric without multiplexing 41759a854e2SKan Liang * is not allowed, even though the hardware supports that in principle. 41859a854e2SKan Liang */ 41959a854e2SKan Liang 42059a854e2SKan Liang #define METRIC_EVENT_CONSTRAINT(c, n) \ 42159a854e2SKan Liang EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \ 42259a854e2SKan Liang INTEL_ARCH_EVENT_MASK) 42359a854e2SKan Liang 42459a854e2SKan Liang /* 42527f6d22bSBorislav Petkov * Constraint on the Event code + UMask 42627f6d22bSBorislav Petkov */ 42727f6d22bSBorislav Petkov #define INTEL_UEVENT_CONSTRAINT(c, n) \ 42827f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) 42927f6d22bSBorislav Petkov 43027f6d22bSBorislav Petkov /* Constraint on specific umask bit only + event */ 43127f6d22bSBorislav Petkov #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \ 43227f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c)) 43327f6d22bSBorislav Petkov 43427f6d22bSBorislav Petkov /* Like UEVENT_CONSTRAINT, but match flags too */ 43527f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ 43627f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) 43727f6d22bSBorislav Petkov 43827f6d22bSBorislav Petkov #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ 43927f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ 44027f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) 44127f6d22bSBorislav Petkov 44227f6d22bSBorislav Petkov #define INTEL_PLD_CONSTRAINT(c, n) \ 44327f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 44427f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) 44527f6d22bSBorislav Petkov 44627f6d22bSBorislav Petkov #define INTEL_PST_CONSTRAINT(c, n) \ 44727f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 44827f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) 44927f6d22bSBorislav Petkov 45027f6d22bSBorislav Petkov /* Event constraint, but match on all event flags too. */ 45127f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ 4526b89d4c1SStephane Eranian EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 45327f6d22bSBorislav Petkov 45463b79f6eSPeter Zijlstra #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ 4556b89d4c1SStephane Eranian EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 45663b79f6eSPeter Zijlstra 45727f6d22bSBorislav Petkov /* Check only flags, but allow all event/umask */ 45827f6d22bSBorislav Petkov #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ 45927f6d22bSBorislav Petkov EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) 46027f6d22bSBorislav Petkov 46127f6d22bSBorislav Petkov /* Check flags and event code, and set the HSW store flag */ 46227f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ 46327f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 46427f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 46527f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 46627f6d22bSBorislav Petkov 46727f6d22bSBorislav Petkov /* Check flags and event code, and set the HSW load flag */ 46827f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ 46927f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 47027f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 47127f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 47227f6d22bSBorislav Petkov 47363b79f6eSPeter Zijlstra #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \ 47463b79f6eSPeter Zijlstra __EVENT_CONSTRAINT_RANGE(code, end, n, \ 47563b79f6eSPeter Zijlstra ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 47663b79f6eSPeter Zijlstra HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 47763b79f6eSPeter Zijlstra 47827f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ 47927f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 48027f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 48127f6d22bSBorislav Petkov HWEIGHT(n), 0, \ 48227f6d22bSBorislav Petkov PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 48327f6d22bSBorislav Petkov 48427f6d22bSBorislav Petkov /* Check flags and event code/umask, and set the HSW store flag */ 48527f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ 48627f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 48727f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 48827f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 48927f6d22bSBorislav Petkov 49027f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ 49127f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 49227f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 49327f6d22bSBorislav Petkov HWEIGHT(n), 0, \ 49427f6d22bSBorislav Petkov PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) 49527f6d22bSBorislav Petkov 49627f6d22bSBorislav Petkov /* Check flags and event code/umask, and set the HSW load flag */ 49727f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ 49827f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 49927f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 50027f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 50127f6d22bSBorislav Petkov 50227f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ 50327f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 50427f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 50527f6d22bSBorislav Petkov HWEIGHT(n), 0, \ 50627f6d22bSBorislav Petkov PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 50727f6d22bSBorislav Petkov 50827f6d22bSBorislav Petkov /* Check flags and event code/umask, and set the HSW N/A flag */ 50927f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ 51027f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 51127f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 51227f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) 51327f6d22bSBorislav Petkov 51427f6d22bSBorislav Petkov 51527f6d22bSBorislav Petkov /* 51627f6d22bSBorislav Petkov * We define the end marker as having a weight of -1 51727f6d22bSBorislav Petkov * to enable blacklisting of events using a counter bitmask 51827f6d22bSBorislav Petkov * of zero and thus a weight of zero. 51927f6d22bSBorislav Petkov * The end marker has a weight that cannot possibly be 52027f6d22bSBorislav Petkov * obtained from counting the bits in the bitmask. 52127f6d22bSBorislav Petkov */ 52227f6d22bSBorislav Petkov #define EVENT_CONSTRAINT_END { .weight = -1 } 52327f6d22bSBorislav Petkov 52427f6d22bSBorislav Petkov /* 52527f6d22bSBorislav Petkov * Check for end marker with weight == -1 52627f6d22bSBorislav Petkov */ 52727f6d22bSBorislav Petkov #define for_each_event_constraint(e, c) \ 52827f6d22bSBorislav Petkov for ((e) = (c); (e)->weight != -1; (e)++) 52927f6d22bSBorislav Petkov 53027f6d22bSBorislav Petkov /* 53127f6d22bSBorislav Petkov * Extra registers for specific events. 53227f6d22bSBorislav Petkov * 53327f6d22bSBorislav Petkov * Some events need large masks and require external MSRs. 53427f6d22bSBorislav Petkov * Those extra MSRs end up being shared for all events on 53527f6d22bSBorislav Petkov * a PMU and sometimes between PMU of sibling HT threads. 53627f6d22bSBorislav Petkov * In either case, the kernel needs to handle conflicting 53727f6d22bSBorislav Petkov * accesses to those extra, shared, regs. The data structure 53827f6d22bSBorislav Petkov * to manage those registers is stored in cpu_hw_event. 53927f6d22bSBorislav Petkov */ 54027f6d22bSBorislav Petkov struct extra_reg { 54127f6d22bSBorislav Petkov unsigned int event; 54227f6d22bSBorislav Petkov unsigned int msr; 54327f6d22bSBorislav Petkov u64 config_mask; 54427f6d22bSBorislav Petkov u64 valid_mask; 54527f6d22bSBorislav Petkov int idx; /* per_xxx->regs[] reg index */ 54627f6d22bSBorislav Petkov bool extra_msr_access; 54727f6d22bSBorislav Petkov }; 54827f6d22bSBorislav Petkov 54927f6d22bSBorislav Petkov #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ 55027f6d22bSBorislav Petkov .event = (e), \ 55127f6d22bSBorislav Petkov .msr = (ms), \ 55227f6d22bSBorislav Petkov .config_mask = (m), \ 55327f6d22bSBorislav Petkov .valid_mask = (vm), \ 55427f6d22bSBorislav Petkov .idx = EXTRA_REG_##i, \ 55527f6d22bSBorislav Petkov .extra_msr_access = true, \ 55627f6d22bSBorislav Petkov } 55727f6d22bSBorislav Petkov 55827f6d22bSBorislav Petkov #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ 55927f6d22bSBorislav Petkov EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) 56027f6d22bSBorislav Petkov 56127f6d22bSBorislav Petkov #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ 56227f6d22bSBorislav Petkov EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ 56327f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) 56427f6d22bSBorislav Petkov 56527f6d22bSBorislav Petkov #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ 56627f6d22bSBorislav Petkov INTEL_UEVENT_EXTRA_REG(c, \ 56727f6d22bSBorislav Petkov MSR_PEBS_LD_LAT_THRESHOLD, \ 56827f6d22bSBorislav Petkov 0xffff, \ 56927f6d22bSBorislav Petkov LDLAT) 57027f6d22bSBorislav Petkov 57127f6d22bSBorislav Petkov #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) 57227f6d22bSBorislav Petkov 57327f6d22bSBorislav Petkov union perf_capabilities { 57427f6d22bSBorislav Petkov struct { 57527f6d22bSBorislav Petkov u64 lbr_format:6; 57627f6d22bSBorislav Petkov u64 pebs_trap:1; 57727f6d22bSBorislav Petkov u64 pebs_arch_reg:1; 57827f6d22bSBorislav Petkov u64 pebs_format:4; 57927f6d22bSBorislav Petkov u64 smm_freeze:1; 58027f6d22bSBorislav Petkov /* 58127f6d22bSBorislav Petkov * PMU supports separate counter range for writing 58227f6d22bSBorislav Petkov * values > 32bit. 58327f6d22bSBorislav Petkov */ 58427f6d22bSBorislav Petkov u64 full_width_write:1; 585c22497f5SKan Liang u64 pebs_baseline:1; 586bbdbde2aSKan Liang u64 perf_metrics:1; 58742880f72SAlexander Shishkin u64 pebs_output_pt_available:1; 588*cadbaa03SStephane Eranian u64 anythread_deprecated:1; 58927f6d22bSBorislav Petkov }; 59027f6d22bSBorislav Petkov u64 capabilities; 59127f6d22bSBorislav Petkov }; 59227f6d22bSBorislav Petkov 59327f6d22bSBorislav Petkov struct x86_pmu_quirk { 59427f6d22bSBorislav Petkov struct x86_pmu_quirk *next; 59527f6d22bSBorislav Petkov void (*func)(void); 59627f6d22bSBorislav Petkov }; 59727f6d22bSBorislav Petkov 59827f6d22bSBorislav Petkov union x86_pmu_config { 59927f6d22bSBorislav Petkov struct { 60027f6d22bSBorislav Petkov u64 event:8, 60127f6d22bSBorislav Petkov umask:8, 60227f6d22bSBorislav Petkov usr:1, 60327f6d22bSBorislav Petkov os:1, 60427f6d22bSBorislav Petkov edge:1, 60527f6d22bSBorislav Petkov pc:1, 60627f6d22bSBorislav Petkov interrupt:1, 60727f6d22bSBorislav Petkov __reserved1:1, 60827f6d22bSBorislav Petkov en:1, 60927f6d22bSBorislav Petkov inv:1, 61027f6d22bSBorislav Petkov cmask:8, 61127f6d22bSBorislav Petkov event2:4, 61227f6d22bSBorislav Petkov __reserved2:4, 61327f6d22bSBorislav Petkov go:1, 61427f6d22bSBorislav Petkov ho:1; 61527f6d22bSBorislav Petkov } bits; 61627f6d22bSBorislav Petkov u64 value; 61727f6d22bSBorislav Petkov }; 61827f6d22bSBorislav Petkov 61927f6d22bSBorislav Petkov #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value 62027f6d22bSBorislav Petkov 62127f6d22bSBorislav Petkov enum { 62227f6d22bSBorislav Petkov x86_lbr_exclusive_lbr, 62327f6d22bSBorislav Petkov x86_lbr_exclusive_bts, 62427f6d22bSBorislav Petkov x86_lbr_exclusive_pt, 62527f6d22bSBorislav Petkov x86_lbr_exclusive_max, 62627f6d22bSBorislav Petkov }; 62727f6d22bSBorislav Petkov 62827f6d22bSBorislav Petkov /* 62927f6d22bSBorislav Petkov * struct x86_pmu - generic x86 pmu 63027f6d22bSBorislav Petkov */ 63127f6d22bSBorislav Petkov struct x86_pmu { 63227f6d22bSBorislav Petkov /* 63327f6d22bSBorislav Petkov * Generic x86 PMC bits 63427f6d22bSBorislav Petkov */ 63527f6d22bSBorislav Petkov const char *name; 63627f6d22bSBorislav Petkov int version; 63727f6d22bSBorislav Petkov int (*handle_irq)(struct pt_regs *); 63827f6d22bSBorislav Petkov void (*disable_all)(void); 63927f6d22bSBorislav Petkov void (*enable_all)(int added); 64027f6d22bSBorislav Petkov void (*enable)(struct perf_event *); 64127f6d22bSBorislav Petkov void (*disable)(struct perf_event *); 64268f7082fSPeter Zijlstra void (*add)(struct perf_event *); 64368f7082fSPeter Zijlstra void (*del)(struct perf_event *); 644bcfbe5c4SKan Liang void (*read)(struct perf_event *event); 64527f6d22bSBorislav Petkov int (*hw_config)(struct perf_event *event); 64627f6d22bSBorislav Petkov int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); 64727f6d22bSBorislav Petkov unsigned eventsel; 64827f6d22bSBorislav Petkov unsigned perfctr; 64927f6d22bSBorislav Petkov int (*addr_offset)(int index, bool eventsel); 65027f6d22bSBorislav Petkov int (*rdpmc_index)(int index); 65127f6d22bSBorislav Petkov u64 (*event_map)(int); 65227f6d22bSBorislav Petkov int max_events; 65327f6d22bSBorislav Petkov int num_counters; 65427f6d22bSBorislav Petkov int num_counters_fixed; 65527f6d22bSBorislav Petkov int cntval_bits; 65627f6d22bSBorislav Petkov u64 cntval_mask; 65727f6d22bSBorislav Petkov union { 65827f6d22bSBorislav Petkov unsigned long events_maskl; 65927f6d22bSBorislav Petkov unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; 66027f6d22bSBorislav Petkov }; 66127f6d22bSBorislav Petkov int events_mask_len; 66227f6d22bSBorislav Petkov int apic; 66327f6d22bSBorislav Petkov u64 max_period; 66427f6d22bSBorislav Petkov struct event_constraint * 66527f6d22bSBorislav Petkov (*get_event_constraints)(struct cpu_hw_events *cpuc, 66627f6d22bSBorislav Petkov int idx, 66727f6d22bSBorislav Petkov struct perf_event *event); 66827f6d22bSBorislav Petkov 66927f6d22bSBorislav Petkov void (*put_event_constraints)(struct cpu_hw_events *cpuc, 67027f6d22bSBorislav Petkov struct perf_event *event); 67127f6d22bSBorislav Petkov 67227f6d22bSBorislav Petkov void (*start_scheduling)(struct cpu_hw_events *cpuc); 67327f6d22bSBorislav Petkov 67427f6d22bSBorislav Petkov void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); 67527f6d22bSBorislav Petkov 67627f6d22bSBorislav Petkov void (*stop_scheduling)(struct cpu_hw_events *cpuc); 67727f6d22bSBorislav Petkov 67827f6d22bSBorislav Petkov struct event_constraint *event_constraints; 67927f6d22bSBorislav Petkov struct x86_pmu_quirk *quirks; 68027f6d22bSBorislav Petkov int perfctr_second_write; 681f605cfcaSKan Liang u64 (*limit_period)(struct perf_event *event, u64 l); 68227f6d22bSBorislav Petkov 683af3bdb99SAndi Kleen /* PMI handler bits */ 684af3bdb99SAndi Kleen unsigned int late_ack :1, 6853a4ac121SCodyYao-oc enabled_ack :1, 686af3bdb99SAndi Kleen counter_freezing :1; 68727f6d22bSBorislav Petkov /* 68827f6d22bSBorislav Petkov * sysfs attrs 68927f6d22bSBorislav Petkov */ 69027f6d22bSBorislav Petkov int attr_rdpmc_broken; 69127f6d22bSBorislav Petkov int attr_rdpmc; 69227f6d22bSBorislav Petkov struct attribute **format_attrs; 69327f6d22bSBorislav Petkov 69427f6d22bSBorislav Petkov ssize_t (*events_sysfs_show)(char *page, u64 config); 695baa0c833SJiri Olsa const struct attribute_group **attr_update; 69627f6d22bSBorislav Petkov 6976089327fSKan Liang unsigned long attr_freeze_on_smi; 6986089327fSKan Liang 69927f6d22bSBorislav Petkov /* 70027f6d22bSBorislav Petkov * CPU Hotplug hooks 70127f6d22bSBorislav Petkov */ 70227f6d22bSBorislav Petkov int (*cpu_prepare)(int cpu); 70327f6d22bSBorislav Petkov void (*cpu_starting)(int cpu); 70427f6d22bSBorislav Petkov void (*cpu_dying)(int cpu); 70527f6d22bSBorislav Petkov void (*cpu_dead)(int cpu); 70627f6d22bSBorislav Petkov 70727f6d22bSBorislav Petkov void (*check_microcode)(void); 70827f6d22bSBorislav Petkov void (*sched_task)(struct perf_event_context *ctx, 70927f6d22bSBorislav Petkov bool sched_in); 71027f6d22bSBorislav Petkov 71127f6d22bSBorislav Petkov /* 71227f6d22bSBorislav Petkov * Intel Arch Perfmon v2+ 71327f6d22bSBorislav Petkov */ 71427f6d22bSBorislav Petkov u64 intel_ctrl; 71527f6d22bSBorislav Petkov union perf_capabilities intel_cap; 71627f6d22bSBorislav Petkov 71727f6d22bSBorislav Petkov /* 71827f6d22bSBorislav Petkov * Intel DebugStore bits 71927f6d22bSBorislav Petkov */ 72027f6d22bSBorislav Petkov unsigned int bts :1, 72127f6d22bSBorislav Petkov bts_active :1, 72227f6d22bSBorislav Petkov pebs :1, 72327f6d22bSBorislav Petkov pebs_active :1, 72427f6d22bSBorislav Petkov pebs_broken :1, 72595298355SAndi Kleen pebs_prec_dist :1, 7269b545c04SAndi Kleen pebs_no_tlb :1, 727cd6b984fSKan Liang pebs_no_isolation :1; 72827f6d22bSBorislav Petkov int pebs_record_size; 729e72daf3fSJiri Olsa int pebs_buffer_size; 730c22497f5SKan Liang int max_pebs_events; 7319dfa9a5cSPeter Zijlstra void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data); 73227f6d22bSBorislav Petkov struct event_constraint *pebs_constraints; 73327f6d22bSBorislav Petkov void (*pebs_aliases)(struct perf_event *event); 734174afc3eSKan Liang unsigned long large_pebs_flags; 735c22497f5SKan Liang u64 rtm_abort_event; 73627f6d22bSBorislav Petkov 73727f6d22bSBorislav Petkov /* 73827f6d22bSBorislav Petkov * Intel LBR 73927f6d22bSBorislav Petkov */ 7403cb9d546SWei Wang unsigned int lbr_tos, lbr_from, lbr_to, 741fda1f99fSKan Liang lbr_info, lbr_nr; /* LBR base regs and size */ 74249d8184fSKan Liang union { 74327f6d22bSBorislav Petkov u64 lbr_sel_mask; /* LBR_SELECT valid bits */ 74449d8184fSKan Liang u64 lbr_ctl_mask; /* LBR_CTL valid bits */ 74549d8184fSKan Liang }; 74649d8184fSKan Liang union { 74727f6d22bSBorislav Petkov const int *lbr_sel_map; /* lbr_select mappings */ 74849d8184fSKan Liang int *lbr_ctl_map; /* LBR_CTL mappings */ 74949d8184fSKan Liang }; 75027f6d22bSBorislav Petkov bool lbr_double_abort; /* duplicated lbr aborts */ 751b0c1ef52SAndi Kleen bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ 75227f6d22bSBorislav Petkov 753af6cf129SKan Liang /* 754af6cf129SKan Liang * Intel Architectural LBR CPUID Enumeration 755af6cf129SKan Liang */ 756af6cf129SKan Liang unsigned int lbr_depth_mask:8; 757af6cf129SKan Liang unsigned int lbr_deep_c_reset:1; 758af6cf129SKan Liang unsigned int lbr_lip:1; 759af6cf129SKan Liang unsigned int lbr_cpl:1; 760af6cf129SKan Liang unsigned int lbr_filter:1; 761af6cf129SKan Liang unsigned int lbr_call_stack:1; 762af6cf129SKan Liang unsigned int lbr_mispred:1; 763af6cf129SKan Liang unsigned int lbr_timed_lbr:1; 764af6cf129SKan Liang unsigned int lbr_br_type:1; 765af6cf129SKan Liang 7669f354a72SKan Liang void (*lbr_reset)(void); 767c301b1d8SKan Liang void (*lbr_read)(struct cpu_hw_events *cpuc); 768799571bfSKan Liang void (*lbr_save)(void *ctx); 769799571bfSKan Liang void (*lbr_restore)(void *ctx); 7709f354a72SKan Liang 77127f6d22bSBorislav Petkov /* 77227f6d22bSBorislav Petkov * Intel PT/LBR/BTS are exclusive 77327f6d22bSBorislav Petkov */ 77427f6d22bSBorislav Petkov atomic_t lbr_exclusive[x86_lbr_exclusive_max]; 77527f6d22bSBorislav Petkov 77627f6d22bSBorislav Petkov /* 7777b2c05a1SKan Liang * Intel perf metrics 7787b2c05a1SKan Liang */ 7797b2c05a1SKan Liang u64 (*update_topdown_event)(struct perf_event *event); 7807b2c05a1SKan Liang int (*set_topdown_event_period)(struct perf_event *event); 7817b2c05a1SKan Liang 7827b2c05a1SKan Liang /* 783fc1adfe3SAlexey Budankov * perf task context (i.e. struct perf_event_context::task_ctx_data) 784fc1adfe3SAlexey Budankov * switch helper to bridge calls from perf/core to perf/x86. 785fc1adfe3SAlexey Budankov * See struct pmu::swap_task_ctx() usage for examples; 786fc1adfe3SAlexey Budankov */ 787fc1adfe3SAlexey Budankov void (*swap_task_ctx)(struct perf_event_context *prev, 788fc1adfe3SAlexey Budankov struct perf_event_context *next); 789fc1adfe3SAlexey Budankov 790fc1adfe3SAlexey Budankov /* 79132b62f44SPeter Zijlstra * AMD bits 79232b62f44SPeter Zijlstra */ 79332b62f44SPeter Zijlstra unsigned int amd_nb_constraints : 1; 79457388912SKim Phillips u64 perf_ctr_pair_en; 79532b62f44SPeter Zijlstra 79632b62f44SPeter Zijlstra /* 79727f6d22bSBorislav Petkov * Extra registers for events 79827f6d22bSBorislav Petkov */ 79927f6d22bSBorislav Petkov struct extra_reg *extra_regs; 80027f6d22bSBorislav Petkov unsigned int flags; 80127f6d22bSBorislav Petkov 80227f6d22bSBorislav Petkov /* 80327f6d22bSBorislav Petkov * Intel host/guest support (KVM) 80427f6d22bSBorislav Petkov */ 80527f6d22bSBorislav Petkov struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr); 80681ec3f3cSJiri Olsa 80781ec3f3cSJiri Olsa /* 80881ec3f3cSJiri Olsa * Check period value for PERF_EVENT_IOC_PERIOD ioctl. 80981ec3f3cSJiri Olsa */ 81081ec3f3cSJiri Olsa int (*check_period) (struct perf_event *event, u64 period); 81142880f72SAlexander Shishkin 81242880f72SAlexander Shishkin int (*aux_output_match) (struct perf_event *event); 81327f6d22bSBorislav Petkov }; 81427f6d22bSBorislav Petkov 815530bfff6SKan Liang struct x86_perf_task_context_opt { 816530bfff6SKan Liang int lbr_callstack_users; 817530bfff6SKan Liang int lbr_stack_state; 818530bfff6SKan Liang int log_id; 819530bfff6SKan Liang }; 820530bfff6SKan Liang 82127f6d22bSBorislav Petkov struct x86_perf_task_context { 822e1ad1ac2SLike Xu u64 lbr_sel; 82327f6d22bSBorislav Petkov int tos; 8240592e57bSKan Liang int valid_lbrs; 825530bfff6SKan Liang struct x86_perf_task_context_opt opt; 8265624986dSKan Liang struct lbr_entry lbr[MAX_LBR_ENTRIES]; 82727f6d22bSBorislav Petkov }; 82827f6d22bSBorislav Petkov 82947125db2SKan Liang struct x86_perf_task_context_arch_lbr { 83047125db2SKan Liang struct x86_perf_task_context_opt opt; 83147125db2SKan Liang struct lbr_entry entries[]; 83247125db2SKan Liang }; 83347125db2SKan Liang 834ce711ea3SKan Liang /* 835ce711ea3SKan Liang * Add padding to guarantee the 64-byte alignment of the state buffer. 836ce711ea3SKan Liang * 837ce711ea3SKan Liang * The structure is dynamically allocated. The size of the LBR state may vary 838ce711ea3SKan Liang * based on the number of LBR registers. 839ce711ea3SKan Liang * 840ce711ea3SKan Liang * Do not put anything after the LBR state. 841ce711ea3SKan Liang */ 842ce711ea3SKan Liang struct x86_perf_task_context_arch_lbr_xsave { 843ce711ea3SKan Liang struct x86_perf_task_context_opt opt; 844ce711ea3SKan Liang 845ce711ea3SKan Liang union { 846ce711ea3SKan Liang struct xregs_state xsave; 847ce711ea3SKan Liang struct { 848ce711ea3SKan Liang struct fxregs_state i387; 849ce711ea3SKan Liang struct xstate_header header; 850ce711ea3SKan Liang struct arch_lbr_state lbr; 851ce711ea3SKan Liang } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT))); 852ce711ea3SKan Liang }; 853ce711ea3SKan Liang }; 854ce711ea3SKan Liang 85527f6d22bSBorislav Petkov #define x86_add_quirk(func_) \ 85627f6d22bSBorislav Petkov do { \ 85727f6d22bSBorislav Petkov static struct x86_pmu_quirk __quirk __initdata = { \ 85827f6d22bSBorislav Petkov .func = func_, \ 85927f6d22bSBorislav Petkov }; \ 86027f6d22bSBorislav Petkov __quirk.next = x86_pmu.quirks; \ 86127f6d22bSBorislav Petkov x86_pmu.quirks = &__quirk; \ 86227f6d22bSBorislav Petkov } while (0) 86327f6d22bSBorislav Petkov 86427f6d22bSBorislav Petkov /* 86527f6d22bSBorislav Petkov * x86_pmu flags 86627f6d22bSBorislav Petkov */ 86727f6d22bSBorislav Petkov #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ 86827f6d22bSBorislav Petkov #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ 86927f6d22bSBorislav Petkov #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ 87027f6d22bSBorislav Petkov #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ 87131962340SKan Liang #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */ 872400816f6SPeter Zijlstra (Intel) #define PMU_FL_TFA 0x20 /* deal with TSX force abort */ 873471af006SKim Phillips #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */ 87427f6d22bSBorislav Petkov 87527f6d22bSBorislav Petkov #define EVENT_VAR(_id) event_attr_##_id 87627f6d22bSBorislav Petkov #define EVENT_PTR(_id) &event_attr_##_id.attr.attr 87727f6d22bSBorislav Petkov 87827f6d22bSBorislav Petkov #define EVENT_ATTR(_name, _id) \ 87927f6d22bSBorislav Petkov static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ 88027f6d22bSBorislav Petkov .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 88127f6d22bSBorislav Petkov .id = PERF_COUNT_HW_##_id, \ 88227f6d22bSBorislav Petkov .event_str = NULL, \ 88327f6d22bSBorislav Petkov }; 88427f6d22bSBorislav Petkov 88527f6d22bSBorislav Petkov #define EVENT_ATTR_STR(_name, v, str) \ 88627f6d22bSBorislav Petkov static struct perf_pmu_events_attr event_attr_##v = { \ 88727f6d22bSBorislav Petkov .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 88827f6d22bSBorislav Petkov .id = 0, \ 88927f6d22bSBorislav Petkov .event_str = str, \ 89027f6d22bSBorislav Petkov }; 89127f6d22bSBorislav Petkov 892fc07e9f9SAndi Kleen #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \ 893fc07e9f9SAndi Kleen static struct perf_pmu_events_ht_attr event_attr_##v = { \ 894fc07e9f9SAndi Kleen .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\ 895fc07e9f9SAndi Kleen .id = 0, \ 896fc07e9f9SAndi Kleen .event_str_noht = noht, \ 897fc07e9f9SAndi Kleen .event_str_ht = ht, \ 898fc07e9f9SAndi Kleen } 899fc07e9f9SAndi Kleen 900f447e4ebSStephane Eranian struct pmu *x86_get_pmu(void); 90127f6d22bSBorislav Petkov extern struct x86_pmu x86_pmu __read_mostly; 90227f6d22bSBorislav Petkov 903f42be865SKan Liang static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx) 904f42be865SKan Liang { 90547125db2SKan Liang if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 90647125db2SKan Liang return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt; 90747125db2SKan Liang 908f42be865SKan Liang return &((struct x86_perf_task_context *)ctx)->opt; 909f42be865SKan Liang } 910f42be865SKan Liang 91127f6d22bSBorislav Petkov static inline bool x86_pmu_has_lbr_callstack(void) 91227f6d22bSBorislav Petkov { 91327f6d22bSBorislav Petkov return x86_pmu.lbr_sel_map && 91427f6d22bSBorislav Petkov x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; 91527f6d22bSBorislav Petkov } 91627f6d22bSBorislav Petkov 91727f6d22bSBorislav Petkov DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 91827f6d22bSBorislav Petkov 91927f6d22bSBorislav Petkov int x86_perf_event_set_period(struct perf_event *event); 92027f6d22bSBorislav Petkov 92127f6d22bSBorislav Petkov /* 92227f6d22bSBorislav Petkov * Generalized hw caching related hw_event table, filled 92327f6d22bSBorislav Petkov * in on a per model basis. A value of 0 means 92427f6d22bSBorislav Petkov * 'not supported', -1 means 'hw_event makes no sense on 92527f6d22bSBorislav Petkov * this CPU', any other value means the raw hw_event 92627f6d22bSBorislav Petkov * ID. 92727f6d22bSBorislav Petkov */ 92827f6d22bSBorislav Petkov 92927f6d22bSBorislav Petkov #define C(x) PERF_COUNT_HW_CACHE_##x 93027f6d22bSBorislav Petkov 93127f6d22bSBorislav Petkov extern u64 __read_mostly hw_cache_event_ids 93227f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 93327f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 93427f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX]; 93527f6d22bSBorislav Petkov extern u64 __read_mostly hw_cache_extra_regs 93627f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 93727f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 93827f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX]; 93927f6d22bSBorislav Petkov 94027f6d22bSBorislav Petkov u64 x86_perf_event_update(struct perf_event *event); 94127f6d22bSBorislav Petkov 94227f6d22bSBorislav Petkov static inline unsigned int x86_pmu_config_addr(int index) 94327f6d22bSBorislav Petkov { 94427f6d22bSBorislav Petkov return x86_pmu.eventsel + (x86_pmu.addr_offset ? 94527f6d22bSBorislav Petkov x86_pmu.addr_offset(index, true) : index); 94627f6d22bSBorislav Petkov } 94727f6d22bSBorislav Petkov 94827f6d22bSBorislav Petkov static inline unsigned int x86_pmu_event_addr(int index) 94927f6d22bSBorislav Petkov { 95027f6d22bSBorislav Petkov return x86_pmu.perfctr + (x86_pmu.addr_offset ? 95127f6d22bSBorislav Petkov x86_pmu.addr_offset(index, false) : index); 95227f6d22bSBorislav Petkov } 95327f6d22bSBorislav Petkov 95427f6d22bSBorislav Petkov static inline int x86_pmu_rdpmc_index(int index) 95527f6d22bSBorislav Petkov { 95627f6d22bSBorislav Petkov return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; 95727f6d22bSBorislav Petkov } 95827f6d22bSBorislav Petkov 95927f6d22bSBorislav Petkov int x86_add_exclusive(unsigned int what); 96027f6d22bSBorislav Petkov 96127f6d22bSBorislav Petkov void x86_del_exclusive(unsigned int what); 96227f6d22bSBorislav Petkov 96327f6d22bSBorislav Petkov int x86_reserve_hardware(void); 96427f6d22bSBorislav Petkov 96527f6d22bSBorislav Petkov void x86_release_hardware(void); 96627f6d22bSBorislav Petkov 967b00233b5SAndi Kleen int x86_pmu_max_precise(void); 968b00233b5SAndi Kleen 96927f6d22bSBorislav Petkov void hw_perf_lbr_event_destroy(struct perf_event *event); 97027f6d22bSBorislav Petkov 97127f6d22bSBorislav Petkov int x86_setup_perfctr(struct perf_event *event); 97227f6d22bSBorislav Petkov 97327f6d22bSBorislav Petkov int x86_pmu_hw_config(struct perf_event *event); 97427f6d22bSBorislav Petkov 97527f6d22bSBorislav Petkov void x86_pmu_disable_all(void); 97627f6d22bSBorislav Petkov 97757388912SKim Phillips static inline bool is_counter_pair(struct hw_perf_event *hwc) 97857388912SKim Phillips { 97957388912SKim Phillips return hwc->flags & PERF_X86_EVENT_PAIR; 98057388912SKim Phillips } 98157388912SKim Phillips 98227f6d22bSBorislav Petkov static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, 98327f6d22bSBorislav Petkov u64 enable_mask) 98427f6d22bSBorislav Petkov { 98527f6d22bSBorislav Petkov u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 98627f6d22bSBorislav Petkov 98727f6d22bSBorislav Petkov if (hwc->extra_reg.reg) 98827f6d22bSBorislav Petkov wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); 98957388912SKim Phillips 99057388912SKim Phillips /* 99157388912SKim Phillips * Add enabled Merge event on next counter 99257388912SKim Phillips * if large increment event being enabled on this counter 99357388912SKim Phillips */ 99457388912SKim Phillips if (is_counter_pair(hwc)) 99557388912SKim Phillips wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); 99657388912SKim Phillips 99727f6d22bSBorislav Petkov wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 99827f6d22bSBorislav Petkov } 99927f6d22bSBorislav Petkov 100027f6d22bSBorislav Petkov void x86_pmu_enable_all(int added); 100127f6d22bSBorislav Petkov 100227f6d22bSBorislav Petkov int perf_assign_events(struct event_constraint **constraints, int n, 100327f6d22bSBorislav Petkov int wmin, int wmax, int gpmax, int *assign); 100427f6d22bSBorislav Petkov int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); 100527f6d22bSBorislav Petkov 100627f6d22bSBorislav Petkov void x86_pmu_stop(struct perf_event *event, int flags); 100727f6d22bSBorislav Petkov 100827f6d22bSBorislav Petkov static inline void x86_pmu_disable_event(struct perf_event *event) 100927f6d22bSBorislav Petkov { 101027f6d22bSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 101127f6d22bSBorislav Petkov 101227f6d22bSBorislav Petkov wrmsrl(hwc->config_base, hwc->config); 101357388912SKim Phillips 101457388912SKim Phillips if (is_counter_pair(hwc)) 101557388912SKim Phillips wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0); 101627f6d22bSBorislav Petkov } 101727f6d22bSBorislav Petkov 101827f6d22bSBorislav Petkov void x86_pmu_enable_event(struct perf_event *event); 101927f6d22bSBorislav Petkov 102027f6d22bSBorislav Petkov int x86_pmu_handle_irq(struct pt_regs *regs); 102127f6d22bSBorislav Petkov 102227f6d22bSBorislav Petkov extern struct event_constraint emptyconstraint; 102327f6d22bSBorislav Petkov 102427f6d22bSBorislav Petkov extern struct event_constraint unconstrained; 102527f6d22bSBorislav Petkov 102627f6d22bSBorislav Petkov static inline bool kernel_ip(unsigned long ip) 102727f6d22bSBorislav Petkov { 102827f6d22bSBorislav Petkov #ifdef CONFIG_X86_32 102927f6d22bSBorislav Petkov return ip > PAGE_OFFSET; 103027f6d22bSBorislav Petkov #else 103127f6d22bSBorislav Petkov return (long)ip < 0; 103227f6d22bSBorislav Petkov #endif 103327f6d22bSBorislav Petkov } 103427f6d22bSBorislav Petkov 103527f6d22bSBorislav Petkov /* 103627f6d22bSBorislav Petkov * Not all PMUs provide the right context information to place the reported IP 103727f6d22bSBorislav Petkov * into full context. Specifically segment registers are typically not 103827f6d22bSBorislav Petkov * supplied. 103927f6d22bSBorislav Petkov * 104027f6d22bSBorislav Petkov * Assuming the address is a linear address (it is for IBS), we fake the CS and 104127f6d22bSBorislav Petkov * vm86 mode using the known zero-based code segment and 'fix up' the registers 104227f6d22bSBorislav Petkov * to reflect this. 104327f6d22bSBorislav Petkov * 104427f6d22bSBorislav Petkov * Intel PEBS/LBR appear to typically provide the effective address, nothing 104527f6d22bSBorislav Petkov * much we can do about that but pray and treat it like a linear address. 104627f6d22bSBorislav Petkov */ 104727f6d22bSBorislav Petkov static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) 104827f6d22bSBorislav Petkov { 104927f6d22bSBorislav Petkov regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; 105027f6d22bSBorislav Petkov if (regs->flags & X86_VM_MASK) 105127f6d22bSBorislav Petkov regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); 105227f6d22bSBorislav Petkov regs->ip = ip; 105327f6d22bSBorislav Petkov } 105427f6d22bSBorislav Petkov 105527f6d22bSBorislav Petkov ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); 105627f6d22bSBorislav Petkov ssize_t intel_event_sysfs_show(char *page, u64 config); 105727f6d22bSBorislav Petkov 1058a49ac9f8SHuang Rui ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, 1059a49ac9f8SHuang Rui char *page); 1060fc07e9f9SAndi Kleen ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 1061fc07e9f9SAndi Kleen char *page); 1062a49ac9f8SHuang Rui 106327f6d22bSBorislav Petkov #ifdef CONFIG_CPU_SUP_AMD 106427f6d22bSBorislav Petkov 106527f6d22bSBorislav Petkov int amd_pmu_init(void); 106627f6d22bSBorislav Petkov 106727f6d22bSBorislav Petkov #else /* CONFIG_CPU_SUP_AMD */ 106827f6d22bSBorislav Petkov 106927f6d22bSBorislav Petkov static inline int amd_pmu_init(void) 107027f6d22bSBorislav Petkov { 107127f6d22bSBorislav Petkov return 0; 107227f6d22bSBorislav Petkov } 107327f6d22bSBorislav Petkov 107427f6d22bSBorislav Petkov #endif /* CONFIG_CPU_SUP_AMD */ 107527f6d22bSBorislav Petkov 107642880f72SAlexander Shishkin static inline int is_pebs_pt(struct perf_event *event) 107742880f72SAlexander Shishkin { 107842880f72SAlexander Shishkin return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT); 107942880f72SAlexander Shishkin } 108042880f72SAlexander Shishkin 108127f6d22bSBorislav Petkov #ifdef CONFIG_CPU_SUP_INTEL 108227f6d22bSBorislav Petkov 108381ec3f3cSJiri Olsa static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period) 108427f6d22bSBorislav Petkov { 108567266c10SJiri Olsa struct hw_perf_event *hwc = &event->hw; 108667266c10SJiri Olsa unsigned int hw_event, bts_event; 108727f6d22bSBorislav Petkov 108867266c10SJiri Olsa if (event->attr.freq) 108927f6d22bSBorislav Petkov return false; 109067266c10SJiri Olsa 109167266c10SJiri Olsa hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 109267266c10SJiri Olsa bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 109367266c10SJiri Olsa 109481ec3f3cSJiri Olsa return hw_event == bts_event && period == 1; 109581ec3f3cSJiri Olsa } 109681ec3f3cSJiri Olsa 109781ec3f3cSJiri Olsa static inline bool intel_pmu_has_bts(struct perf_event *event) 109881ec3f3cSJiri Olsa { 109981ec3f3cSJiri Olsa struct hw_perf_event *hwc = &event->hw; 110081ec3f3cSJiri Olsa 110181ec3f3cSJiri Olsa return intel_pmu_has_bts_period(event, hwc->sample_period); 110227f6d22bSBorislav Petkov } 110327f6d22bSBorislav Petkov 110427f6d22bSBorislav Petkov int intel_pmu_save_and_restart(struct perf_event *event); 110527f6d22bSBorislav Petkov 110627f6d22bSBorislav Petkov struct event_constraint * 110727f6d22bSBorislav Petkov x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 110827f6d22bSBorislav Petkov struct perf_event *event); 110927f6d22bSBorislav Petkov 1110d01b1f96SPeter Zijlstra (Intel) extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu); 1111d01b1f96SPeter Zijlstra (Intel) extern void intel_cpuc_finish(struct cpu_hw_events *cpuc); 111227f6d22bSBorislav Petkov 111327f6d22bSBorislav Petkov int intel_pmu_init(void); 111427f6d22bSBorislav Petkov 111527f6d22bSBorislav Petkov void init_debug_store_on_cpu(int cpu); 111627f6d22bSBorislav Petkov 111727f6d22bSBorislav Petkov void fini_debug_store_on_cpu(int cpu); 111827f6d22bSBorislav Petkov 111927f6d22bSBorislav Petkov void release_ds_buffers(void); 112027f6d22bSBorislav Petkov 112127f6d22bSBorislav Petkov void reserve_ds_buffers(void); 112227f6d22bSBorislav Petkov 1123c085fb87SKan Liang void release_lbr_buffers(void); 1124c085fb87SKan Liang 112527f6d22bSBorislav Petkov extern struct event_constraint bts_constraint; 1126097e4311SLike Xu extern struct event_constraint vlbr_constraint; 112727f6d22bSBorislav Petkov 112827f6d22bSBorislav Petkov void intel_pmu_enable_bts(u64 config); 112927f6d22bSBorislav Petkov 113027f6d22bSBorislav Petkov void intel_pmu_disable_bts(void); 113127f6d22bSBorislav Petkov 113227f6d22bSBorislav Petkov int intel_pmu_drain_bts_buffer(void); 113327f6d22bSBorislav Petkov 113427f6d22bSBorislav Petkov extern struct event_constraint intel_core2_pebs_event_constraints[]; 113527f6d22bSBorislav Petkov 113627f6d22bSBorislav Petkov extern struct event_constraint intel_atom_pebs_event_constraints[]; 113727f6d22bSBorislav Petkov 113827f6d22bSBorislav Petkov extern struct event_constraint intel_slm_pebs_event_constraints[]; 113927f6d22bSBorislav Petkov 11408b92c3a7SKan Liang extern struct event_constraint intel_glm_pebs_event_constraints[]; 11418b92c3a7SKan Liang 1142dd0b06b5SKan Liang extern struct event_constraint intel_glp_pebs_event_constraints[]; 1143dd0b06b5SKan Liang 114427f6d22bSBorislav Petkov extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 114527f6d22bSBorislav Petkov 114627f6d22bSBorislav Petkov extern struct event_constraint intel_westmere_pebs_event_constraints[]; 114727f6d22bSBorislav Petkov 114827f6d22bSBorislav Petkov extern struct event_constraint intel_snb_pebs_event_constraints[]; 114927f6d22bSBorislav Petkov 115027f6d22bSBorislav Petkov extern struct event_constraint intel_ivb_pebs_event_constraints[]; 115127f6d22bSBorislav Petkov 115227f6d22bSBorislav Petkov extern struct event_constraint intel_hsw_pebs_event_constraints[]; 115327f6d22bSBorislav Petkov 1154b3e62463SStephane Eranian extern struct event_constraint intel_bdw_pebs_event_constraints[]; 1155b3e62463SStephane Eranian 115627f6d22bSBorislav Petkov extern struct event_constraint intel_skl_pebs_event_constraints[]; 115727f6d22bSBorislav Petkov 115860176089SKan Liang extern struct event_constraint intel_icl_pebs_event_constraints[]; 115960176089SKan Liang 116027f6d22bSBorislav Petkov struct event_constraint *intel_pebs_constraints(struct perf_event *event); 116127f6d22bSBorislav Petkov 116268f7082fSPeter Zijlstra void intel_pmu_pebs_add(struct perf_event *event); 116368f7082fSPeter Zijlstra 116468f7082fSPeter Zijlstra void intel_pmu_pebs_del(struct perf_event *event); 116568f7082fSPeter Zijlstra 116627f6d22bSBorislav Petkov void intel_pmu_pebs_enable(struct perf_event *event); 116727f6d22bSBorislav Petkov 116827f6d22bSBorislav Petkov void intel_pmu_pebs_disable(struct perf_event *event); 116927f6d22bSBorislav Petkov 117027f6d22bSBorislav Petkov void intel_pmu_pebs_enable_all(void); 117127f6d22bSBorislav Petkov 117227f6d22bSBorislav Petkov void intel_pmu_pebs_disable_all(void); 117327f6d22bSBorislav Petkov 117427f6d22bSBorislav Petkov void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in); 117527f6d22bSBorislav Petkov 11765bee2cc6SKan Liang void intel_pmu_auto_reload_read(struct perf_event *event); 11775bee2cc6SKan Liang 11785624986dSKan Liang void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr); 1179c22497f5SKan Liang 118027f6d22bSBorislav Petkov void intel_ds_init(void); 118127f6d22bSBorislav Petkov 1182421ca868SAlexey Budankov void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev, 1183421ca868SAlexey Budankov struct perf_event_context *next); 1184421ca868SAlexey Budankov 118527f6d22bSBorislav Petkov void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in); 118627f6d22bSBorislav Petkov 118719fc9dddSDavid Carrillo-Cisneros u64 lbr_from_signext_quirk_wr(u64 val); 118819fc9dddSDavid Carrillo-Cisneros 118927f6d22bSBorislav Petkov void intel_pmu_lbr_reset(void); 119027f6d22bSBorislav Petkov 11919f354a72SKan Liang void intel_pmu_lbr_reset_32(void); 11929f354a72SKan Liang 11939f354a72SKan Liang void intel_pmu_lbr_reset_64(void); 11949f354a72SKan Liang 119568f7082fSPeter Zijlstra void intel_pmu_lbr_add(struct perf_event *event); 119627f6d22bSBorislav Petkov 119768f7082fSPeter Zijlstra void intel_pmu_lbr_del(struct perf_event *event); 119827f6d22bSBorislav Petkov 119927f6d22bSBorislav Petkov void intel_pmu_lbr_enable_all(bool pmi); 120027f6d22bSBorislav Petkov 120127f6d22bSBorislav Petkov void intel_pmu_lbr_disable_all(void); 120227f6d22bSBorislav Petkov 120327f6d22bSBorislav Petkov void intel_pmu_lbr_read(void); 120427f6d22bSBorislav Petkov 1205c301b1d8SKan Liang void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc); 1206c301b1d8SKan Liang 1207c301b1d8SKan Liang void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc); 1208c301b1d8SKan Liang 1209799571bfSKan Liang void intel_pmu_lbr_save(void *ctx); 1210799571bfSKan Liang 1211799571bfSKan Liang void intel_pmu_lbr_restore(void *ctx); 1212799571bfSKan Liang 121327f6d22bSBorislav Petkov void intel_pmu_lbr_init_core(void); 121427f6d22bSBorislav Petkov 121527f6d22bSBorislav Petkov void intel_pmu_lbr_init_nhm(void); 121627f6d22bSBorislav Petkov 121727f6d22bSBorislav Petkov void intel_pmu_lbr_init_atom(void); 121827f6d22bSBorislav Petkov 1219f21d5adcSKan Liang void intel_pmu_lbr_init_slm(void); 1220f21d5adcSKan Liang 122127f6d22bSBorislav Petkov void intel_pmu_lbr_init_snb(void); 122227f6d22bSBorislav Petkov 122327f6d22bSBorislav Petkov void intel_pmu_lbr_init_hsw(void); 122427f6d22bSBorislav Petkov 122527f6d22bSBorislav Petkov void intel_pmu_lbr_init_skl(void); 122627f6d22bSBorislav Petkov 122727f6d22bSBorislav Petkov void intel_pmu_lbr_init_knl(void); 122827f6d22bSBorislav Petkov 122947125db2SKan Liang void intel_pmu_arch_lbr_init(void); 123047125db2SKan Liang 1231e17dc653SAndi Kleen void intel_pmu_pebs_data_source_nhm(void); 1232e17dc653SAndi Kleen 12336ae5fa61SAndi Kleen void intel_pmu_pebs_data_source_skl(bool pmem); 12346ae5fa61SAndi Kleen 123527f6d22bSBorislav Petkov int intel_pmu_setup_lbr_filter(struct perf_event *event); 123627f6d22bSBorislav Petkov 123727f6d22bSBorislav Petkov void intel_pt_interrupt(void); 123827f6d22bSBorislav Petkov 123927f6d22bSBorislav Petkov int intel_bts_interrupt(void); 124027f6d22bSBorislav Petkov 124127f6d22bSBorislav Petkov void intel_bts_enable_local(void); 124227f6d22bSBorislav Petkov 124327f6d22bSBorislav Petkov void intel_bts_disable_local(void); 124427f6d22bSBorislav Petkov 124527f6d22bSBorislav Petkov int p4_pmu_init(void); 124627f6d22bSBorislav Petkov 124727f6d22bSBorislav Petkov int p6_pmu_init(void); 124827f6d22bSBorislav Petkov 124927f6d22bSBorislav Petkov int knc_pmu_init(void); 125027f6d22bSBorislav Petkov 125127f6d22bSBorislav Petkov static inline int is_ht_workaround_enabled(void) 125227f6d22bSBorislav Petkov { 125327f6d22bSBorislav Petkov return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); 125427f6d22bSBorislav Petkov } 125527f6d22bSBorislav Petkov 125627f6d22bSBorislav Petkov #else /* CONFIG_CPU_SUP_INTEL */ 125727f6d22bSBorislav Petkov 125827f6d22bSBorislav Petkov static inline void reserve_ds_buffers(void) 125927f6d22bSBorislav Petkov { 126027f6d22bSBorislav Petkov } 126127f6d22bSBorislav Petkov 126227f6d22bSBorislav Petkov static inline void release_ds_buffers(void) 126327f6d22bSBorislav Petkov { 126427f6d22bSBorislav Petkov } 126527f6d22bSBorislav Petkov 1266c085fb87SKan Liang static inline void release_lbr_buffers(void) 1267c085fb87SKan Liang { 1268c085fb87SKan Liang } 1269c085fb87SKan Liang 127027f6d22bSBorislav Petkov static inline int intel_pmu_init(void) 127127f6d22bSBorislav Petkov { 127227f6d22bSBorislav Petkov return 0; 127327f6d22bSBorislav Petkov } 127427f6d22bSBorislav Petkov 1275f764c58bSPeter Zijlstra static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 127627f6d22bSBorislav Petkov { 1277d01b1f96SPeter Zijlstra (Intel) return 0; 1278d01b1f96SPeter Zijlstra (Intel) } 1279d01b1f96SPeter Zijlstra (Intel) 1280f764c58bSPeter Zijlstra static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc) 1281d01b1f96SPeter Zijlstra (Intel) { 128227f6d22bSBorislav Petkov } 128327f6d22bSBorislav Petkov 128427f6d22bSBorislav Petkov static inline int is_ht_workaround_enabled(void) 128527f6d22bSBorislav Petkov { 128627f6d22bSBorislav Petkov return 0; 128727f6d22bSBorislav Petkov } 128827f6d22bSBorislav Petkov #endif /* CONFIG_CPU_SUP_INTEL */ 12893a4ac121SCodyYao-oc 12903a4ac121SCodyYao-oc #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN)) 12913a4ac121SCodyYao-oc int zhaoxin_pmu_init(void); 12923a4ac121SCodyYao-oc #else 12933a4ac121SCodyYao-oc static inline int zhaoxin_pmu_init(void) 12943a4ac121SCodyYao-oc { 12953a4ac121SCodyYao-oc return 0; 12963a4ac121SCodyYao-oc } 12973a4ac121SCodyYao-oc #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/ 1298