127f6d22bSBorislav Petkov /* 227f6d22bSBorislav Petkov * Performance events x86 architecture header 327f6d22bSBorislav Petkov * 427f6d22bSBorislav Petkov * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 527f6d22bSBorislav Petkov * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 627f6d22bSBorislav Petkov * Copyright (C) 2009 Jaswinder Singh Rajput 727f6d22bSBorislav Petkov * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 827f6d22bSBorislav Petkov * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 927f6d22bSBorislav Petkov * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 1027f6d22bSBorislav Petkov * Copyright (C) 2009 Google, Inc., Stephane Eranian 1127f6d22bSBorislav Petkov * 1227f6d22bSBorislav Petkov * For licencing details see kernel-base/COPYING 1327f6d22bSBorislav Petkov */ 1427f6d22bSBorislav Petkov 1527f6d22bSBorislav Petkov #include <linux/perf_event.h> 1627f6d22bSBorislav Petkov 1710043e02SThomas Gleixner #include <asm/intel_ds.h> 18d9977c43SKan Liang #include <asm/cpu.h> 1910043e02SThomas Gleixner 2027f6d22bSBorislav Petkov /* To enable MSR tracing please use the generic trace points. */ 2127f6d22bSBorislav Petkov 2227f6d22bSBorislav Petkov /* 2327f6d22bSBorislav Petkov * | NHM/WSM | SNB | 2427f6d22bSBorislav Petkov * register ------------------------------- 2527f6d22bSBorislav Petkov * | HT | no HT | HT | no HT | 2627f6d22bSBorislav Petkov *----------------------------------------- 2727f6d22bSBorislav Petkov * offcore | core | core | cpu | core | 2827f6d22bSBorislav Petkov * lbr_sel | core | core | cpu | core | 2927f6d22bSBorislav Petkov * ld_lat | cpu | core | cpu | core | 3027f6d22bSBorislav Petkov *----------------------------------------- 3127f6d22bSBorislav Petkov * 3227f6d22bSBorislav Petkov * Given that there is a small number of shared regs, 3327f6d22bSBorislav Petkov * we can pre-allocate their slot in the per-cpu 3427f6d22bSBorislav Petkov * per-core reg tables. 3527f6d22bSBorislav Petkov */ 3627f6d22bSBorislav Petkov enum extra_reg_type { 3727f6d22bSBorislav Petkov EXTRA_REG_NONE = -1, /* not used */ 3827f6d22bSBorislav Petkov 3927f6d22bSBorislav Petkov EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ 4027f6d22bSBorislav Petkov EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ 4127f6d22bSBorislav Petkov EXTRA_REG_LBR = 2, /* lbr_select */ 4227f6d22bSBorislav Petkov EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ 4327f6d22bSBorislav Petkov EXTRA_REG_FE = 4, /* fe_* */ 4427f6d22bSBorislav Petkov 4527f6d22bSBorislav Petkov EXTRA_REG_MAX /* number of entries needed */ 4627f6d22bSBorislav Petkov }; 4727f6d22bSBorislav Petkov 4827f6d22bSBorislav Petkov struct event_constraint { 4927f6d22bSBorislav Petkov union { 5027f6d22bSBorislav Petkov unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 5127f6d22bSBorislav Petkov u64 idxmsk64; 5227f6d22bSBorislav Petkov }; 5327f6d22bSBorislav Petkov u64 code; 5427f6d22bSBorislav Petkov u64 cmask; 5527f6d22bSBorislav Petkov int weight; 5627f6d22bSBorislav Petkov int overlap; 5727f6d22bSBorislav Petkov int flags; 5863b79f6eSPeter Zijlstra unsigned int size; 5927f6d22bSBorislav Petkov }; 601f6a1e2dSPeter Zijlstra 6163b79f6eSPeter Zijlstra static inline bool constraint_match(struct event_constraint *c, u64 ecode) 6263b79f6eSPeter Zijlstra { 6363b79f6eSPeter Zijlstra return ((ecode & c->cmask) - c->code) <= (u64)c->size; 6463b79f6eSPeter Zijlstra } 6563b79f6eSPeter Zijlstra 6627f6d22bSBorislav Petkov /* 6727f6d22bSBorislav Petkov * struct hw_perf_event.flags flags 6827f6d22bSBorislav Petkov */ 6927f6d22bSBorislav Petkov #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */ 7027f6d22bSBorislav Petkov #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */ 7127f6d22bSBorislav Petkov #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */ 721f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_PEBS_LD_HSW 0x0008 /* haswell style datala, load */ 731f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_PEBS_NA_HSW 0x0010 /* haswell style datala, unknown */ 741f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_EXCL 0x0020 /* HT exclusivity on counter */ 751f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_DYNAMIC 0x0040 /* dynamic alloc'd constraint */ 761f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0080 /* grant rdpmc permission */ 771f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_EXCL_ACCT 0x0100 /* accounted EXCL event */ 781f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_AUTO_RELOAD 0x0200 /* use PEBS auto-reload */ 791f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_LARGE_PEBS 0x0400 /* use large PEBS */ 8042880f72SAlexander Shishkin #define PERF_X86_EVENT_PEBS_VIA_PT 0x0800 /* use PT buffer for PEBS */ 81471af006SKim Phillips #define PERF_X86_EVENT_PAIR 0x1000 /* Large Increment per Cycle */ 82e1ad1ac2SLike Xu #define PERF_X86_EVENT_LBR_SELECT 0x2000 /* Save/Restore MSR_LBR_SELECT */ 837b2c05a1SKan Liang #define PERF_X86_EVENT_TOPDOWN 0x4000 /* Count Topdown slots/metrics events */ 8461b985e3SKan Liang #define PERF_X86_EVENT_PEBS_STLAT 0x8000 /* st+stlat data address sampling */ 857b2c05a1SKan Liang 867b2c05a1SKan Liang static inline bool is_topdown_count(struct perf_event *event) 877b2c05a1SKan Liang { 887b2c05a1SKan Liang return event->hw.flags & PERF_X86_EVENT_TOPDOWN; 897b2c05a1SKan Liang } 907b2c05a1SKan Liang 917b2c05a1SKan Liang static inline bool is_metric_event(struct perf_event *event) 927b2c05a1SKan Liang { 937b2c05a1SKan Liang u64 config = event->attr.config; 947b2c05a1SKan Liang 957b2c05a1SKan Liang return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) && 967b2c05a1SKan Liang ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) && 977b2c05a1SKan Liang ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX); 987b2c05a1SKan Liang } 997b2c05a1SKan Liang 1007b2c05a1SKan Liang static inline bool is_slots_event(struct perf_event *event) 1017b2c05a1SKan Liang { 1027b2c05a1SKan Liang return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS; 1037b2c05a1SKan Liang } 1047b2c05a1SKan Liang 1057b2c05a1SKan Liang static inline bool is_topdown_event(struct perf_event *event) 1067b2c05a1SKan Liang { 1077b2c05a1SKan Liang return is_metric_event(event) || is_slots_event(event); 1087b2c05a1SKan Liang } 10927f6d22bSBorislav Petkov 11027f6d22bSBorislav Petkov struct amd_nb { 11127f6d22bSBorislav Petkov int nb_id; /* NorthBridge id */ 11227f6d22bSBorislav Petkov int refcnt; /* reference count */ 11327f6d22bSBorislav Petkov struct perf_event *owners[X86_PMC_IDX_MAX]; 11427f6d22bSBorislav Petkov struct event_constraint event_constraints[X86_PMC_IDX_MAX]; 11527f6d22bSBorislav Petkov }; 11627f6d22bSBorislav Petkov 117fd583ad1SKan Liang #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) 11842880f72SAlexander Shishkin #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60) 11942880f72SAlexander Shishkin #define PEBS_OUTPUT_OFFSET 61 12042880f72SAlexander Shishkin #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET) 12142880f72SAlexander Shishkin #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET) 12242880f72SAlexander Shishkin #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD) 12327f6d22bSBorislav Petkov 12427f6d22bSBorislav Petkov /* 12527f6d22bSBorislav Petkov * Flags PEBS can handle without an PMI. 12627f6d22bSBorislav Petkov * 12727f6d22bSBorislav Petkov * TID can only be handled by flushing at context switch. 1282fe1bc1fSAndi Kleen * REGS_USER can be handled for events limited to ring 3. 12927f6d22bSBorislav Petkov * 13027f6d22bSBorislav Petkov */ 131174afc3eSKan Liang #define LARGE_PEBS_FLAGS \ 13227f6d22bSBorislav Petkov (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 13327f6d22bSBorislav Petkov PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 13427f6d22bSBorislav Petkov PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 1352fe1bc1fSAndi Kleen PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ 13611974914SJiri Olsa PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \ 137995f088eSStephane Eranian PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE) 13827f6d22bSBorislav Petkov 1399d5dcc93SKan Liang #define PEBS_GP_REGS \ 1409d5dcc93SKan Liang ((1ULL << PERF_REG_X86_AX) | \ 1419d5dcc93SKan Liang (1ULL << PERF_REG_X86_BX) | \ 1429d5dcc93SKan Liang (1ULL << PERF_REG_X86_CX) | \ 1439d5dcc93SKan Liang (1ULL << PERF_REG_X86_DX) | \ 1449d5dcc93SKan Liang (1ULL << PERF_REG_X86_DI) | \ 1459d5dcc93SKan Liang (1ULL << PERF_REG_X86_SI) | \ 1469d5dcc93SKan Liang (1ULL << PERF_REG_X86_SP) | \ 1479d5dcc93SKan Liang (1ULL << PERF_REG_X86_BP) | \ 1489d5dcc93SKan Liang (1ULL << PERF_REG_X86_IP) | \ 1499d5dcc93SKan Liang (1ULL << PERF_REG_X86_FLAGS) | \ 1509d5dcc93SKan Liang (1ULL << PERF_REG_X86_R8) | \ 1519d5dcc93SKan Liang (1ULL << PERF_REG_X86_R9) | \ 1529d5dcc93SKan Liang (1ULL << PERF_REG_X86_R10) | \ 1539d5dcc93SKan Liang (1ULL << PERF_REG_X86_R11) | \ 1549d5dcc93SKan Liang (1ULL << PERF_REG_X86_R12) | \ 1559d5dcc93SKan Liang (1ULL << PERF_REG_X86_R13) | \ 1569d5dcc93SKan Liang (1ULL << PERF_REG_X86_R14) | \ 1579d5dcc93SKan Liang (1ULL << PERF_REG_X86_R15)) 1582fe1bc1fSAndi Kleen 15927f6d22bSBorislav Petkov /* 16027f6d22bSBorislav Petkov * Per register state. 16127f6d22bSBorislav Petkov */ 16227f6d22bSBorislav Petkov struct er_account { 16327f6d22bSBorislav Petkov raw_spinlock_t lock; /* per-core: protect structure */ 16427f6d22bSBorislav Petkov u64 config; /* extra MSR config */ 16527f6d22bSBorislav Petkov u64 reg; /* extra MSR number */ 16627f6d22bSBorislav Petkov atomic_t ref; /* reference count */ 16727f6d22bSBorislav Petkov }; 16827f6d22bSBorislav Petkov 16927f6d22bSBorislav Petkov /* 17027f6d22bSBorislav Petkov * Per core/cpu state 17127f6d22bSBorislav Petkov * 17227f6d22bSBorislav Petkov * Used to coordinate shared registers between HT threads or 17327f6d22bSBorislav Petkov * among events on a single PMU. 17427f6d22bSBorislav Petkov */ 17527f6d22bSBorislav Petkov struct intel_shared_regs { 17627f6d22bSBorislav Petkov struct er_account regs[EXTRA_REG_MAX]; 17727f6d22bSBorislav Petkov int refcnt; /* per-core: #HT threads */ 17827f6d22bSBorislav Petkov unsigned core_id; /* per-core: core id */ 17927f6d22bSBorislav Petkov }; 18027f6d22bSBorislav Petkov 18127f6d22bSBorislav Petkov enum intel_excl_state_type { 18227f6d22bSBorislav Petkov INTEL_EXCL_UNUSED = 0, /* counter is unused */ 18327f6d22bSBorislav Petkov INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ 18427f6d22bSBorislav Petkov INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ 18527f6d22bSBorislav Petkov }; 18627f6d22bSBorislav Petkov 18727f6d22bSBorislav Petkov struct intel_excl_states { 18827f6d22bSBorislav Petkov enum intel_excl_state_type state[X86_PMC_IDX_MAX]; 18927f6d22bSBorislav Petkov bool sched_started; /* true if scheduling has started */ 19027f6d22bSBorislav Petkov }; 19127f6d22bSBorislav Petkov 19227f6d22bSBorislav Petkov struct intel_excl_cntrs { 19327f6d22bSBorislav Petkov raw_spinlock_t lock; 19427f6d22bSBorislav Petkov 19527f6d22bSBorislav Petkov struct intel_excl_states states[2]; 19627f6d22bSBorislav Petkov 19727f6d22bSBorislav Petkov union { 19827f6d22bSBorislav Petkov u16 has_exclusive[2]; 19927f6d22bSBorislav Petkov u32 exclusive_present; 20027f6d22bSBorislav Petkov }; 20127f6d22bSBorislav Petkov 20227f6d22bSBorislav Petkov int refcnt; /* per-core: #HT threads */ 20327f6d22bSBorislav Petkov unsigned core_id; /* per-core: core id */ 20427f6d22bSBorislav Petkov }; 20527f6d22bSBorislav Petkov 2068b077e4aSKan Liang struct x86_perf_task_context; 20727f6d22bSBorislav Petkov #define MAX_LBR_ENTRIES 32 20827f6d22bSBorislav Petkov 20927f6d22bSBorislav Petkov enum { 2109f354a72SKan Liang LBR_FORMAT_32 = 0x00, 2119f354a72SKan Liang LBR_FORMAT_LIP = 0x01, 2129f354a72SKan Liang LBR_FORMAT_EIP = 0x02, 2139f354a72SKan Liang LBR_FORMAT_EIP_FLAGS = 0x03, 2149f354a72SKan Liang LBR_FORMAT_EIP_FLAGS2 = 0x04, 2159f354a72SKan Liang LBR_FORMAT_INFO = 0x05, 2169f354a72SKan Liang LBR_FORMAT_TIME = 0x06, 2179f354a72SKan Liang LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME, 2189f354a72SKan Liang }; 2199f354a72SKan Liang 2209f354a72SKan Liang enum { 22127f6d22bSBorislav Petkov X86_PERF_KFREE_SHARED = 0, 22227f6d22bSBorislav Petkov X86_PERF_KFREE_EXCL = 1, 22327f6d22bSBorislav Petkov X86_PERF_KFREE_MAX 22427f6d22bSBorislav Petkov }; 22527f6d22bSBorislav Petkov 22627f6d22bSBorislav Petkov struct cpu_hw_events { 22727f6d22bSBorislav Petkov /* 22827f6d22bSBorislav Petkov * Generic x86 PMC bits 22927f6d22bSBorislav Petkov */ 23027f6d22bSBorislav Petkov struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ 23127f6d22bSBorislav Petkov unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 2325471eea5SKan Liang unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 23327f6d22bSBorislav Petkov int enabled; 23427f6d22bSBorislav Petkov 23527f6d22bSBorislav Petkov int n_events; /* the # of events in the below arrays */ 23627f6d22bSBorislav Petkov int n_added; /* the # last events in the below arrays; 23727f6d22bSBorislav Petkov they've never been enabled yet */ 23827f6d22bSBorislav Petkov int n_txn; /* the # last events in the below arrays; 23927f6d22bSBorislav Petkov added in the current transaction */ 240871a93b0SPeter Zijlstra int n_txn_pair; 2413dbde695SPeter Zijlstra int n_txn_metric; 24227f6d22bSBorislav Petkov int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ 24327f6d22bSBorislav Petkov u64 tags[X86_PMC_IDX_MAX]; 24427f6d22bSBorislav Petkov 24527f6d22bSBorislav Petkov struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ 24627f6d22bSBorislav Petkov struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; 24727f6d22bSBorislav Petkov 24827f6d22bSBorislav Petkov int n_excl; /* the number of exclusive events */ 24927f6d22bSBorislav Petkov 25027f6d22bSBorislav Petkov unsigned int txn_flags; 25127f6d22bSBorislav Petkov int is_fake; 25227f6d22bSBorislav Petkov 25327f6d22bSBorislav Petkov /* 25427f6d22bSBorislav Petkov * Intel DebugStore bits 25527f6d22bSBorislav Petkov */ 25627f6d22bSBorislav Petkov struct debug_store *ds; 257c1961a46SHugh Dickins void *ds_pebs_vaddr; 258c1961a46SHugh Dickins void *ds_bts_vaddr; 25927f6d22bSBorislav Petkov u64 pebs_enabled; 26009e61b4fSPeter Zijlstra int n_pebs; 26109e61b4fSPeter Zijlstra int n_large_pebs; 26242880f72SAlexander Shishkin int n_pebs_via_pt; 26342880f72SAlexander Shishkin int pebs_output; 26427f6d22bSBorislav Petkov 265c22497f5SKan Liang /* Current super set of events hardware configuration */ 266c22497f5SKan Liang u64 pebs_data_cfg; 267c22497f5SKan Liang u64 active_pebs_data_cfg; 268c22497f5SKan Liang int pebs_record_size; 269c22497f5SKan Liang 27027f6d22bSBorislav Petkov /* 27127f6d22bSBorislav Petkov * Intel LBR bits 27227f6d22bSBorislav Petkov */ 27327f6d22bSBorislav Petkov int lbr_users; 274d3617b98SAndi Kleen int lbr_pebs_users; 27527f6d22bSBorislav Petkov struct perf_branch_stack lbr_stack; 27627f6d22bSBorislav Petkov struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; 27749d8184fSKan Liang union { 27827f6d22bSBorislav Petkov struct er_account *lbr_sel; 27949d8184fSKan Liang struct er_account *lbr_ctl; 28049d8184fSKan Liang }; 28127f6d22bSBorislav Petkov u64 br_sel; 282f42be865SKan Liang void *last_task_ctx; 2838b077e4aSKan Liang int last_log_id; 284e1ad1ac2SLike Xu int lbr_select; 285c085fb87SKan Liang void *lbr_xsave; 28627f6d22bSBorislav Petkov 28727f6d22bSBorislav Petkov /* 28827f6d22bSBorislav Petkov * Intel host/guest exclude bits 28927f6d22bSBorislav Petkov */ 29027f6d22bSBorislav Petkov u64 intel_ctrl_guest_mask; 29127f6d22bSBorislav Petkov u64 intel_ctrl_host_mask; 29227f6d22bSBorislav Petkov struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; 29327f6d22bSBorislav Petkov 29427f6d22bSBorislav Petkov /* 29527f6d22bSBorislav Petkov * Intel checkpoint mask 29627f6d22bSBorislav Petkov */ 29727f6d22bSBorislav Petkov u64 intel_cp_status; 29827f6d22bSBorislav Petkov 29927f6d22bSBorislav Petkov /* 30027f6d22bSBorislav Petkov * manage shared (per-core, per-cpu) registers 30127f6d22bSBorislav Petkov * used on Intel NHM/WSM/SNB 30227f6d22bSBorislav Petkov */ 30327f6d22bSBorislav Petkov struct intel_shared_regs *shared_regs; 30427f6d22bSBorislav Petkov /* 30527f6d22bSBorislav Petkov * manage exclusive counter access between hyperthread 30627f6d22bSBorislav Petkov */ 30727f6d22bSBorislav Petkov struct event_constraint *constraint_list; /* in enable order */ 30827f6d22bSBorislav Petkov struct intel_excl_cntrs *excl_cntrs; 30927f6d22bSBorislav Petkov int excl_thread_id; /* 0 or 1 */ 31027f6d22bSBorislav Petkov 31127f6d22bSBorislav Petkov /* 312400816f6SPeter Zijlstra (Intel) * SKL TSX_FORCE_ABORT shadow 313400816f6SPeter Zijlstra (Intel) */ 314400816f6SPeter Zijlstra (Intel) u64 tfa_shadow; 315400816f6SPeter Zijlstra (Intel) 316400816f6SPeter Zijlstra (Intel) /* 3177b2c05a1SKan Liang * Perf Metrics 3187b2c05a1SKan Liang */ 3197b2c05a1SKan Liang /* number of accepted metrics events */ 3207b2c05a1SKan Liang int n_metric; 3217b2c05a1SKan Liang 3227b2c05a1SKan Liang /* 32327f6d22bSBorislav Petkov * AMD specific bits 32427f6d22bSBorislav Petkov */ 32527f6d22bSBorislav Petkov struct amd_nb *amd_nb; 32627f6d22bSBorislav Petkov /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ 32727f6d22bSBorislav Petkov u64 perf_ctr_virt_mask; 32857388912SKim Phillips int n_pair; /* Large increment events */ 32927f6d22bSBorislav Petkov 33027f6d22bSBorislav Petkov void *kfree_on_online[X86_PERF_KFREE_MAX]; 33161e76d53SKan Liang 33261e76d53SKan Liang struct pmu *pmu; 33327f6d22bSBorislav Petkov }; 33427f6d22bSBorislav Petkov 33563b79f6eSPeter Zijlstra #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \ 33627f6d22bSBorislav Petkov { .idxmsk64 = (n) }, \ 33727f6d22bSBorislav Petkov .code = (c), \ 33863b79f6eSPeter Zijlstra .size = (e) - (c), \ 33927f6d22bSBorislav Petkov .cmask = (m), \ 34027f6d22bSBorislav Petkov .weight = (w), \ 34127f6d22bSBorislav Petkov .overlap = (o), \ 34227f6d22bSBorislav Petkov .flags = f, \ 34327f6d22bSBorislav Petkov } 34427f6d22bSBorislav Petkov 34563b79f6eSPeter Zijlstra #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ 34663b79f6eSPeter Zijlstra __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f) 34763b79f6eSPeter Zijlstra 34827f6d22bSBorislav Petkov #define EVENT_CONSTRAINT(c, n, m) \ 34927f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) 35027f6d22bSBorislav Petkov 35163b79f6eSPeter Zijlstra /* 35263b79f6eSPeter Zijlstra * The constraint_match() function only works for 'simple' event codes 35363b79f6eSPeter Zijlstra * and not for extended (AMD64_EVENTSEL_EVENT) events codes. 35463b79f6eSPeter Zijlstra */ 35563b79f6eSPeter Zijlstra #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \ 35663b79f6eSPeter Zijlstra __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0) 35763b79f6eSPeter Zijlstra 35827f6d22bSBorislav Petkov #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ 35927f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ 36027f6d22bSBorislav Petkov 0, PERF_X86_EVENT_EXCL) 36127f6d22bSBorislav Petkov 36227f6d22bSBorislav Petkov /* 36327f6d22bSBorislav Petkov * The overlap flag marks event constraints with overlapping counter 36427f6d22bSBorislav Petkov * masks. This is the case if the counter mask of such an event is not 36527f6d22bSBorislav Petkov * a subset of any other counter mask of a constraint with an equal or 36627f6d22bSBorislav Petkov * higher weight, e.g.: 36727f6d22bSBorislav Petkov * 36827f6d22bSBorislav Petkov * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); 36927f6d22bSBorislav Petkov * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); 37027f6d22bSBorislav Petkov * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); 37127f6d22bSBorislav Petkov * 37227f6d22bSBorislav Petkov * The event scheduler may not select the correct counter in the first 37327f6d22bSBorislav Petkov * cycle because it needs to know which subsequent events will be 37427f6d22bSBorislav Petkov * scheduled. It may fail to schedule the events then. So we set the 37527f6d22bSBorislav Petkov * overlap flag for such constraints to give the scheduler a hint which 37627f6d22bSBorislav Petkov * events to select for counter rescheduling. 37727f6d22bSBorislav Petkov * 37827f6d22bSBorislav Petkov * Care must be taken as the rescheduling algorithm is O(n!) which 37900f52685SIngo Molnar * will increase scheduling cycles for an over-committed system 38027f6d22bSBorislav Petkov * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros 38127f6d22bSBorislav Petkov * and its counter masks must be kept at a minimum. 38227f6d22bSBorislav Petkov */ 38327f6d22bSBorislav Petkov #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ 38427f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) 38527f6d22bSBorislav Petkov 38627f6d22bSBorislav Petkov /* 38727f6d22bSBorislav Petkov * Constraint on the Event code. 38827f6d22bSBorislav Petkov */ 38927f6d22bSBorislav Petkov #define INTEL_EVENT_CONSTRAINT(c, n) \ 39027f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) 39127f6d22bSBorislav Petkov 39227f6d22bSBorislav Petkov /* 39363b79f6eSPeter Zijlstra * Constraint on a range of Event codes 39463b79f6eSPeter Zijlstra */ 39563b79f6eSPeter Zijlstra #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \ 39663b79f6eSPeter Zijlstra EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT) 39763b79f6eSPeter Zijlstra 39863b79f6eSPeter Zijlstra /* 39927f6d22bSBorislav Petkov * Constraint on the Event code + UMask + fixed-mask 40027f6d22bSBorislav Petkov * 40127f6d22bSBorislav Petkov * filter mask to validate fixed counter events. 40227f6d22bSBorislav Petkov * the following filters disqualify for fixed counters: 40327f6d22bSBorislav Petkov * - inv 40427f6d22bSBorislav Petkov * - edge 40527f6d22bSBorislav Petkov * - cnt-mask 40627f6d22bSBorislav Petkov * - in_tx 40727f6d22bSBorislav Petkov * - in_tx_checkpointed 40827f6d22bSBorislav Petkov * The other filters are supported by fixed counters. 40927f6d22bSBorislav Petkov * The any-thread option is supported starting with v3. 41027f6d22bSBorislav Petkov */ 41127f6d22bSBorislav Petkov #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) 41227f6d22bSBorislav Petkov #define FIXED_EVENT_CONSTRAINT(c, n) \ 41327f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) 41427f6d22bSBorislav Petkov 41527f6d22bSBorislav Petkov /* 41659a854e2SKan Liang * The special metric counters do not actually exist. They are calculated from 41759a854e2SKan Liang * the combination of the FxCtr3 + MSR_PERF_METRICS. 41859a854e2SKan Liang * 41959a854e2SKan Liang * The special metric counters are mapped to a dummy offset for the scheduler. 42059a854e2SKan Liang * The sharing between multiple users of the same metric without multiplexing 42159a854e2SKan Liang * is not allowed, even though the hardware supports that in principle. 42259a854e2SKan Liang */ 42359a854e2SKan Liang 42459a854e2SKan Liang #define METRIC_EVENT_CONSTRAINT(c, n) \ 42559a854e2SKan Liang EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \ 42659a854e2SKan Liang INTEL_ARCH_EVENT_MASK) 42759a854e2SKan Liang 42859a854e2SKan Liang /* 42927f6d22bSBorislav Petkov * Constraint on the Event code + UMask 43027f6d22bSBorislav Petkov */ 43127f6d22bSBorislav Petkov #define INTEL_UEVENT_CONSTRAINT(c, n) \ 43227f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) 43327f6d22bSBorislav Petkov 43427f6d22bSBorislav Petkov /* Constraint on specific umask bit only + event */ 43527f6d22bSBorislav Petkov #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \ 43627f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c)) 43727f6d22bSBorislav Petkov 43827f6d22bSBorislav Petkov /* Like UEVENT_CONSTRAINT, but match flags too */ 43927f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ 44027f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) 44127f6d22bSBorislav Petkov 44227f6d22bSBorislav Petkov #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ 44327f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ 44427f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) 44527f6d22bSBorislav Petkov 44627f6d22bSBorislav Petkov #define INTEL_PLD_CONSTRAINT(c, n) \ 44727f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 44827f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) 44927f6d22bSBorislav Petkov 45061b985e3SKan Liang #define INTEL_PSD_CONSTRAINT(c, n) \ 45161b985e3SKan Liang __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 45261b985e3SKan Liang HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT) 45361b985e3SKan Liang 45427f6d22bSBorislav Petkov #define INTEL_PST_CONSTRAINT(c, n) \ 45527f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 45627f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) 45727f6d22bSBorislav Petkov 45827f6d22bSBorislav Petkov /* Event constraint, but match on all event flags too. */ 45927f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ 4606b89d4c1SStephane Eranian EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 46127f6d22bSBorislav Petkov 46263b79f6eSPeter Zijlstra #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ 4636b89d4c1SStephane Eranian EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 46463b79f6eSPeter Zijlstra 46527f6d22bSBorislav Petkov /* Check only flags, but allow all event/umask */ 46627f6d22bSBorislav Petkov #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ 46727f6d22bSBorislav Petkov EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) 46827f6d22bSBorislav Petkov 46927f6d22bSBorislav Petkov /* Check flags and event code, and set the HSW store flag */ 47027f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ 47127f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 47227f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 47327f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 47427f6d22bSBorislav Petkov 47527f6d22bSBorislav Petkov /* Check flags and event code, and set the HSW load flag */ 47627f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ 47727f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 47827f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 47927f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 48027f6d22bSBorislav Petkov 48163b79f6eSPeter Zijlstra #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \ 48263b79f6eSPeter Zijlstra __EVENT_CONSTRAINT_RANGE(code, end, n, \ 48363b79f6eSPeter Zijlstra ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 48463b79f6eSPeter Zijlstra HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 48563b79f6eSPeter Zijlstra 48627f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ 48727f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 48827f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 48927f6d22bSBorislav Petkov HWEIGHT(n), 0, \ 49027f6d22bSBorislav Petkov PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 49127f6d22bSBorislav Petkov 49227f6d22bSBorislav Petkov /* Check flags and event code/umask, and set the HSW store flag */ 49327f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ 49427f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 49527f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 49627f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 49727f6d22bSBorislav Petkov 49827f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ 49927f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 50027f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 50127f6d22bSBorislav Petkov HWEIGHT(n), 0, \ 50227f6d22bSBorislav Petkov PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) 50327f6d22bSBorislav Petkov 50427f6d22bSBorislav Petkov /* Check flags and event code/umask, and set the HSW load flag */ 50527f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ 50627f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 50727f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 50827f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 50927f6d22bSBorislav Petkov 51027f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ 51127f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 51227f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 51327f6d22bSBorislav Petkov HWEIGHT(n), 0, \ 51427f6d22bSBorislav Petkov PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 51527f6d22bSBorislav Petkov 51627f6d22bSBorislav Petkov /* Check flags and event code/umask, and set the HSW N/A flag */ 51727f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ 51827f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 51927f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 52027f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) 52127f6d22bSBorislav Petkov 52227f6d22bSBorislav Petkov 52327f6d22bSBorislav Petkov /* 52427f6d22bSBorislav Petkov * We define the end marker as having a weight of -1 52527f6d22bSBorislav Petkov * to enable blacklisting of events using a counter bitmask 52627f6d22bSBorislav Petkov * of zero and thus a weight of zero. 52727f6d22bSBorislav Petkov * The end marker has a weight that cannot possibly be 52827f6d22bSBorislav Petkov * obtained from counting the bits in the bitmask. 52927f6d22bSBorislav Petkov */ 53027f6d22bSBorislav Petkov #define EVENT_CONSTRAINT_END { .weight = -1 } 53127f6d22bSBorislav Petkov 53227f6d22bSBorislav Petkov /* 53327f6d22bSBorislav Petkov * Check for end marker with weight == -1 53427f6d22bSBorislav Petkov */ 53527f6d22bSBorislav Petkov #define for_each_event_constraint(e, c) \ 53627f6d22bSBorislav Petkov for ((e) = (c); (e)->weight != -1; (e)++) 53727f6d22bSBorislav Petkov 53827f6d22bSBorislav Petkov /* 53927f6d22bSBorislav Petkov * Extra registers for specific events. 54027f6d22bSBorislav Petkov * 54127f6d22bSBorislav Petkov * Some events need large masks and require external MSRs. 54227f6d22bSBorislav Petkov * Those extra MSRs end up being shared for all events on 54327f6d22bSBorislav Petkov * a PMU and sometimes between PMU of sibling HT threads. 54427f6d22bSBorislav Petkov * In either case, the kernel needs to handle conflicting 54527f6d22bSBorislav Petkov * accesses to those extra, shared, regs. The data structure 54627f6d22bSBorislav Petkov * to manage those registers is stored in cpu_hw_event. 54727f6d22bSBorislav Petkov */ 54827f6d22bSBorislav Petkov struct extra_reg { 54927f6d22bSBorislav Petkov unsigned int event; 55027f6d22bSBorislav Petkov unsigned int msr; 55127f6d22bSBorislav Petkov u64 config_mask; 55227f6d22bSBorislav Petkov u64 valid_mask; 55327f6d22bSBorislav Petkov int idx; /* per_xxx->regs[] reg index */ 55427f6d22bSBorislav Petkov bool extra_msr_access; 55527f6d22bSBorislav Petkov }; 55627f6d22bSBorislav Petkov 55727f6d22bSBorislav Petkov #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ 55827f6d22bSBorislav Petkov .event = (e), \ 55927f6d22bSBorislav Petkov .msr = (ms), \ 56027f6d22bSBorislav Petkov .config_mask = (m), \ 56127f6d22bSBorislav Petkov .valid_mask = (vm), \ 56227f6d22bSBorislav Petkov .idx = EXTRA_REG_##i, \ 56327f6d22bSBorislav Petkov .extra_msr_access = true, \ 56427f6d22bSBorislav Petkov } 56527f6d22bSBorislav Petkov 56627f6d22bSBorislav Petkov #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ 56727f6d22bSBorislav Petkov EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) 56827f6d22bSBorislav Petkov 56927f6d22bSBorislav Petkov #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ 57027f6d22bSBorislav Petkov EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ 57127f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) 57227f6d22bSBorislav Petkov 57327f6d22bSBorislav Petkov #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ 57427f6d22bSBorislav Petkov INTEL_UEVENT_EXTRA_REG(c, \ 57527f6d22bSBorislav Petkov MSR_PEBS_LD_LAT_THRESHOLD, \ 57627f6d22bSBorislav Petkov 0xffff, \ 57727f6d22bSBorislav Petkov LDLAT) 57827f6d22bSBorislav Petkov 57927f6d22bSBorislav Petkov #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) 58027f6d22bSBorislav Petkov 58127f6d22bSBorislav Petkov union perf_capabilities { 58227f6d22bSBorislav Petkov struct { 58327f6d22bSBorislav Petkov u64 lbr_format:6; 58427f6d22bSBorislav Petkov u64 pebs_trap:1; 58527f6d22bSBorislav Petkov u64 pebs_arch_reg:1; 58627f6d22bSBorislav Petkov u64 pebs_format:4; 58727f6d22bSBorislav Petkov u64 smm_freeze:1; 58827f6d22bSBorislav Petkov /* 58927f6d22bSBorislav Petkov * PMU supports separate counter range for writing 59027f6d22bSBorislav Petkov * values > 32bit. 59127f6d22bSBorislav Petkov */ 59227f6d22bSBorislav Petkov u64 full_width_write:1; 593c22497f5SKan Liang u64 pebs_baseline:1; 594bbdbde2aSKan Liang u64 perf_metrics:1; 59542880f72SAlexander Shishkin u64 pebs_output_pt_available:1; 596cadbaa03SStephane Eranian u64 anythread_deprecated:1; 59727f6d22bSBorislav Petkov }; 59827f6d22bSBorislav Petkov u64 capabilities; 59927f6d22bSBorislav Petkov }; 60027f6d22bSBorislav Petkov 60127f6d22bSBorislav Petkov struct x86_pmu_quirk { 60227f6d22bSBorislav Petkov struct x86_pmu_quirk *next; 60327f6d22bSBorislav Petkov void (*func)(void); 60427f6d22bSBorislav Petkov }; 60527f6d22bSBorislav Petkov 60627f6d22bSBorislav Petkov union x86_pmu_config { 60727f6d22bSBorislav Petkov struct { 60827f6d22bSBorislav Petkov u64 event:8, 60927f6d22bSBorislav Petkov umask:8, 61027f6d22bSBorislav Petkov usr:1, 61127f6d22bSBorislav Petkov os:1, 61227f6d22bSBorislav Petkov edge:1, 61327f6d22bSBorislav Petkov pc:1, 61427f6d22bSBorislav Petkov interrupt:1, 61527f6d22bSBorislav Petkov __reserved1:1, 61627f6d22bSBorislav Petkov en:1, 61727f6d22bSBorislav Petkov inv:1, 61827f6d22bSBorislav Petkov cmask:8, 61927f6d22bSBorislav Petkov event2:4, 62027f6d22bSBorislav Petkov __reserved2:4, 62127f6d22bSBorislav Petkov go:1, 62227f6d22bSBorislav Petkov ho:1; 62327f6d22bSBorislav Petkov } bits; 62427f6d22bSBorislav Petkov u64 value; 62527f6d22bSBorislav Petkov }; 62627f6d22bSBorislav Petkov 62727f6d22bSBorislav Petkov #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value 62827f6d22bSBorislav Petkov 62927f6d22bSBorislav Petkov enum { 63027f6d22bSBorislav Petkov x86_lbr_exclusive_lbr, 63127f6d22bSBorislav Petkov x86_lbr_exclusive_bts, 63227f6d22bSBorislav Petkov x86_lbr_exclusive_pt, 63327f6d22bSBorislav Petkov x86_lbr_exclusive_max, 63427f6d22bSBorislav Petkov }; 63527f6d22bSBorislav Petkov 636d0946a88SKan Liang struct x86_hybrid_pmu { 637d0946a88SKan Liang struct pmu pmu; 638d9977c43SKan Liang const char *name; 639d9977c43SKan Liang u8 cpu_type; 640d9977c43SKan Liang cpumask_t supported_cpus; 641d0946a88SKan Liang union perf_capabilities intel_cap; 642fc4b8fcaSKan Liang u64 intel_ctrl; 643d4b294bfSKan Liang int max_pebs_events; 644d4b294bfSKan Liang int num_counters; 645d4b294bfSKan Liang int num_counters_fixed; 646eaacf07dSKan Liang struct event_constraint unconstrained; 6470d18f2dfSKan Liang 6480d18f2dfSKan Liang u64 hw_cache_event_ids 6490d18f2dfSKan Liang [PERF_COUNT_HW_CACHE_MAX] 6500d18f2dfSKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 6510d18f2dfSKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX]; 6520d18f2dfSKan Liang u64 hw_cache_extra_regs 6530d18f2dfSKan Liang [PERF_COUNT_HW_CACHE_MAX] 6540d18f2dfSKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 6550d18f2dfSKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX]; 65624ee38ffSKan Liang struct event_constraint *event_constraints; 65724ee38ffSKan Liang struct event_constraint *pebs_constraints; 658183af736SKan Liang struct extra_reg *extra_regs; 659acade637SKan Liang 660acade637SKan Liang unsigned int late_ack :1, 661acade637SKan Liang mid_ack :1, 662acade637SKan Liang enabled_ack :1; 663d0946a88SKan Liang }; 664d0946a88SKan Liang 665d0946a88SKan Liang static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu) 666d0946a88SKan Liang { 667d0946a88SKan Liang return container_of(pmu, struct x86_hybrid_pmu, pmu); 668d0946a88SKan Liang } 669d0946a88SKan Liang 670d0946a88SKan Liang extern struct static_key_false perf_is_hybrid; 671d0946a88SKan Liang #define is_hybrid() static_branch_unlikely(&perf_is_hybrid) 672d0946a88SKan Liang 673d0946a88SKan Liang #define hybrid(_pmu, _field) \ 674d0946a88SKan Liang (*({ \ 675d0946a88SKan Liang typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \ 676d0946a88SKan Liang \ 677d0946a88SKan Liang if (is_hybrid() && (_pmu)) \ 678d0946a88SKan Liang __Fp = &hybrid_pmu(_pmu)->_field; \ 679d0946a88SKan Liang \ 680d0946a88SKan Liang __Fp; \ 681d0946a88SKan Liang })) 682d0946a88SKan Liang 683eaacf07dSKan Liang #define hybrid_var(_pmu, _var) \ 684eaacf07dSKan Liang (*({ \ 685eaacf07dSKan Liang typeof(&_var) __Fp = &_var; \ 686eaacf07dSKan Liang \ 687eaacf07dSKan Liang if (is_hybrid() && (_pmu)) \ 688eaacf07dSKan Liang __Fp = &hybrid_pmu(_pmu)->_var; \ 689eaacf07dSKan Liang \ 690eaacf07dSKan Liang __Fp; \ 691eaacf07dSKan Liang })) 692eaacf07dSKan Liang 693acade637SKan Liang #define hybrid_bit(_pmu, _field) \ 694acade637SKan Liang ({ \ 695acade637SKan Liang bool __Fp = x86_pmu._field; \ 696acade637SKan Liang \ 697acade637SKan Liang if (is_hybrid() && (_pmu)) \ 698acade637SKan Liang __Fp = hybrid_pmu(_pmu)->_field; \ 699acade637SKan Liang \ 700acade637SKan Liang __Fp; \ 701acade637SKan Liang }) 702acade637SKan Liang 703d9977c43SKan Liang enum hybrid_pmu_type { 704d9977c43SKan Liang hybrid_big = 0x40, 705d9977c43SKan Liang hybrid_small = 0x20, 706d9977c43SKan Liang 707d9977c43SKan Liang hybrid_big_small = hybrid_big | hybrid_small, 708d9977c43SKan Liang }; 709d9977c43SKan Liang 710f83d2f91SKan Liang #define X86_HYBRID_PMU_ATOM_IDX 0 711f83d2f91SKan Liang #define X86_HYBRID_PMU_CORE_IDX 1 712f83d2f91SKan Liang 713f83d2f91SKan Liang #define X86_HYBRID_NUM_PMUS 2 714f83d2f91SKan Liang 71527f6d22bSBorislav Petkov /* 71627f6d22bSBorislav Petkov * struct x86_pmu - generic x86 pmu 71727f6d22bSBorislav Petkov */ 71827f6d22bSBorislav Petkov struct x86_pmu { 71927f6d22bSBorislav Petkov /* 72027f6d22bSBorislav Petkov * Generic x86 PMC bits 72127f6d22bSBorislav Petkov */ 72227f6d22bSBorislav Petkov const char *name; 72327f6d22bSBorislav Petkov int version; 72427f6d22bSBorislav Petkov int (*handle_irq)(struct pt_regs *); 72527f6d22bSBorislav Petkov void (*disable_all)(void); 72627f6d22bSBorislav Petkov void (*enable_all)(int added); 72727f6d22bSBorislav Petkov void (*enable)(struct perf_event *); 72827f6d22bSBorislav Petkov void (*disable)(struct perf_event *); 729*8b8ff8ccSAdrian Hunter void (*assign)(struct perf_event *event, int idx); 73068f7082fSPeter Zijlstra void (*add)(struct perf_event *); 73168f7082fSPeter Zijlstra void (*del)(struct perf_event *); 732bcfbe5c4SKan Liang void (*read)(struct perf_event *event); 73327f6d22bSBorislav Petkov int (*hw_config)(struct perf_event *event); 73427f6d22bSBorislav Petkov int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); 73527f6d22bSBorislav Petkov unsigned eventsel; 73627f6d22bSBorislav Petkov unsigned perfctr; 73727f6d22bSBorislav Petkov int (*addr_offset)(int index, bool eventsel); 73827f6d22bSBorislav Petkov int (*rdpmc_index)(int index); 73927f6d22bSBorislav Petkov u64 (*event_map)(int); 74027f6d22bSBorislav Petkov int max_events; 74127f6d22bSBorislav Petkov int num_counters; 74227f6d22bSBorislav Petkov int num_counters_fixed; 74327f6d22bSBorislav Petkov int cntval_bits; 74427f6d22bSBorislav Petkov u64 cntval_mask; 74527f6d22bSBorislav Petkov union { 74627f6d22bSBorislav Petkov unsigned long events_maskl; 74727f6d22bSBorislav Petkov unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; 74827f6d22bSBorislav Petkov }; 74927f6d22bSBorislav Petkov int events_mask_len; 75027f6d22bSBorislav Petkov int apic; 75127f6d22bSBorislav Petkov u64 max_period; 75227f6d22bSBorislav Petkov struct event_constraint * 75327f6d22bSBorislav Petkov (*get_event_constraints)(struct cpu_hw_events *cpuc, 75427f6d22bSBorislav Petkov int idx, 75527f6d22bSBorislav Petkov struct perf_event *event); 75627f6d22bSBorislav Petkov 75727f6d22bSBorislav Petkov void (*put_event_constraints)(struct cpu_hw_events *cpuc, 75827f6d22bSBorislav Petkov struct perf_event *event); 75927f6d22bSBorislav Petkov 76027f6d22bSBorislav Petkov void (*start_scheduling)(struct cpu_hw_events *cpuc); 76127f6d22bSBorislav Petkov 76227f6d22bSBorislav Petkov void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); 76327f6d22bSBorislav Petkov 76427f6d22bSBorislav Petkov void (*stop_scheduling)(struct cpu_hw_events *cpuc); 76527f6d22bSBorislav Petkov 76627f6d22bSBorislav Petkov struct event_constraint *event_constraints; 76727f6d22bSBorislav Petkov struct x86_pmu_quirk *quirks; 76827f6d22bSBorislav Petkov int perfctr_second_write; 769f605cfcaSKan Liang u64 (*limit_period)(struct perf_event *event, u64 l); 77027f6d22bSBorislav Petkov 771af3bdb99SAndi Kleen /* PMI handler bits */ 772af3bdb99SAndi Kleen unsigned int late_ack :1, 773acade637SKan Liang mid_ack :1, 7743daa96d6SPeter Zijlstra enabled_ack :1; 77527f6d22bSBorislav Petkov /* 77627f6d22bSBorislav Petkov * sysfs attrs 77727f6d22bSBorislav Petkov */ 77827f6d22bSBorislav Petkov int attr_rdpmc_broken; 77927f6d22bSBorislav Petkov int attr_rdpmc; 78027f6d22bSBorislav Petkov struct attribute **format_attrs; 78127f6d22bSBorislav Petkov 78227f6d22bSBorislav Petkov ssize_t (*events_sysfs_show)(char *page, u64 config); 783baa0c833SJiri Olsa const struct attribute_group **attr_update; 78427f6d22bSBorislav Petkov 7856089327fSKan Liang unsigned long attr_freeze_on_smi; 7866089327fSKan Liang 78727f6d22bSBorislav Petkov /* 78827f6d22bSBorislav Petkov * CPU Hotplug hooks 78927f6d22bSBorislav Petkov */ 79027f6d22bSBorislav Petkov int (*cpu_prepare)(int cpu); 79127f6d22bSBorislav Petkov void (*cpu_starting)(int cpu); 79227f6d22bSBorislav Petkov void (*cpu_dying)(int cpu); 79327f6d22bSBorislav Petkov void (*cpu_dead)(int cpu); 79427f6d22bSBorislav Petkov 79527f6d22bSBorislav Petkov void (*check_microcode)(void); 79627f6d22bSBorislav Petkov void (*sched_task)(struct perf_event_context *ctx, 79727f6d22bSBorislav Petkov bool sched_in); 79827f6d22bSBorislav Petkov 79927f6d22bSBorislav Petkov /* 80027f6d22bSBorislav Petkov * Intel Arch Perfmon v2+ 80127f6d22bSBorislav Petkov */ 80227f6d22bSBorislav Petkov u64 intel_ctrl; 80327f6d22bSBorislav Petkov union perf_capabilities intel_cap; 80427f6d22bSBorislav Petkov 80527f6d22bSBorislav Petkov /* 80627f6d22bSBorislav Petkov * Intel DebugStore bits 80727f6d22bSBorislav Petkov */ 80827f6d22bSBorislav Petkov unsigned int bts :1, 80927f6d22bSBorislav Petkov bts_active :1, 81027f6d22bSBorislav Petkov pebs :1, 81127f6d22bSBorislav Petkov pebs_active :1, 81227f6d22bSBorislav Petkov pebs_broken :1, 81395298355SAndi Kleen pebs_prec_dist :1, 8149b545c04SAndi Kleen pebs_no_tlb :1, 81561b985e3SKan Liang pebs_no_isolation :1, 81661b985e3SKan Liang pebs_block :1; 81727f6d22bSBorislav Petkov int pebs_record_size; 818e72daf3fSJiri Olsa int pebs_buffer_size; 819c22497f5SKan Liang int max_pebs_events; 8209dfa9a5cSPeter Zijlstra void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data); 82127f6d22bSBorislav Petkov struct event_constraint *pebs_constraints; 82227f6d22bSBorislav Petkov void (*pebs_aliases)(struct perf_event *event); 823174afc3eSKan Liang unsigned long large_pebs_flags; 824c22497f5SKan Liang u64 rtm_abort_event; 82527f6d22bSBorislav Petkov 82627f6d22bSBorislav Petkov /* 82727f6d22bSBorislav Petkov * Intel LBR 82827f6d22bSBorislav Petkov */ 8293cb9d546SWei Wang unsigned int lbr_tos, lbr_from, lbr_to, 830fda1f99fSKan Liang lbr_info, lbr_nr; /* LBR base regs and size */ 83149d8184fSKan Liang union { 83227f6d22bSBorislav Petkov u64 lbr_sel_mask; /* LBR_SELECT valid bits */ 83349d8184fSKan Liang u64 lbr_ctl_mask; /* LBR_CTL valid bits */ 83449d8184fSKan Liang }; 83549d8184fSKan Liang union { 83627f6d22bSBorislav Petkov const int *lbr_sel_map; /* lbr_select mappings */ 83749d8184fSKan Liang int *lbr_ctl_map; /* LBR_CTL mappings */ 83849d8184fSKan Liang }; 83927f6d22bSBorislav Petkov bool lbr_double_abort; /* duplicated lbr aborts */ 840b0c1ef52SAndi Kleen bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ 84127f6d22bSBorislav Petkov 842af6cf129SKan Liang /* 843af6cf129SKan Liang * Intel Architectural LBR CPUID Enumeration 844af6cf129SKan Liang */ 845af6cf129SKan Liang unsigned int lbr_depth_mask:8; 846af6cf129SKan Liang unsigned int lbr_deep_c_reset:1; 847af6cf129SKan Liang unsigned int lbr_lip:1; 848af6cf129SKan Liang unsigned int lbr_cpl:1; 849af6cf129SKan Liang unsigned int lbr_filter:1; 850af6cf129SKan Liang unsigned int lbr_call_stack:1; 851af6cf129SKan Liang unsigned int lbr_mispred:1; 852af6cf129SKan Liang unsigned int lbr_timed_lbr:1; 853af6cf129SKan Liang unsigned int lbr_br_type:1; 854af6cf129SKan Liang 8559f354a72SKan Liang void (*lbr_reset)(void); 856c301b1d8SKan Liang void (*lbr_read)(struct cpu_hw_events *cpuc); 857799571bfSKan Liang void (*lbr_save)(void *ctx); 858799571bfSKan Liang void (*lbr_restore)(void *ctx); 8599f354a72SKan Liang 86027f6d22bSBorislav Petkov /* 86127f6d22bSBorislav Petkov * Intel PT/LBR/BTS are exclusive 86227f6d22bSBorislav Petkov */ 86327f6d22bSBorislav Petkov atomic_t lbr_exclusive[x86_lbr_exclusive_max]; 86427f6d22bSBorislav Petkov 86527f6d22bSBorislav Petkov /* 8667b2c05a1SKan Liang * Intel perf metrics 8677b2c05a1SKan Liang */ 8681ab5f235SKan Liang int num_topdown_events; 8697b2c05a1SKan Liang u64 (*update_topdown_event)(struct perf_event *event); 8707b2c05a1SKan Liang int (*set_topdown_event_period)(struct perf_event *event); 8717b2c05a1SKan Liang 8727b2c05a1SKan Liang /* 873fc1adfe3SAlexey Budankov * perf task context (i.e. struct perf_event_context::task_ctx_data) 874fc1adfe3SAlexey Budankov * switch helper to bridge calls from perf/core to perf/x86. 875fc1adfe3SAlexey Budankov * See struct pmu::swap_task_ctx() usage for examples; 876fc1adfe3SAlexey Budankov */ 877fc1adfe3SAlexey Budankov void (*swap_task_ctx)(struct perf_event_context *prev, 878fc1adfe3SAlexey Budankov struct perf_event_context *next); 879fc1adfe3SAlexey Budankov 880fc1adfe3SAlexey Budankov /* 88132b62f44SPeter Zijlstra * AMD bits 88232b62f44SPeter Zijlstra */ 88332b62f44SPeter Zijlstra unsigned int amd_nb_constraints : 1; 88457388912SKim Phillips u64 perf_ctr_pair_en; 88532b62f44SPeter Zijlstra 88632b62f44SPeter Zijlstra /* 88727f6d22bSBorislav Petkov * Extra registers for events 88827f6d22bSBorislav Petkov */ 88927f6d22bSBorislav Petkov struct extra_reg *extra_regs; 89027f6d22bSBorislav Petkov unsigned int flags; 89127f6d22bSBorislav Petkov 89227f6d22bSBorislav Petkov /* 89327f6d22bSBorislav Petkov * Intel host/guest support (KVM) 89427f6d22bSBorislav Petkov */ 89527f6d22bSBorislav Petkov struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr); 89681ec3f3cSJiri Olsa 89781ec3f3cSJiri Olsa /* 89881ec3f3cSJiri Olsa * Check period value for PERF_EVENT_IOC_PERIOD ioctl. 89981ec3f3cSJiri Olsa */ 90081ec3f3cSJiri Olsa int (*check_period) (struct perf_event *event, u64 period); 90142880f72SAlexander Shishkin 90242880f72SAlexander Shishkin int (*aux_output_match) (struct perf_event *event); 903d0946a88SKan Liang 9043e9a8b21SKan Liang int (*filter_match)(struct perf_event *event); 905d0946a88SKan Liang /* 906d0946a88SKan Liang * Hybrid support 907d0946a88SKan Liang * 908d0946a88SKan Liang * Most PMU capabilities are the same among different hybrid PMUs. 909d0946a88SKan Liang * The global x86_pmu saves the architecture capabilities, which 910d0946a88SKan Liang * are available for all PMUs. The hybrid_pmu only includes the 911d0946a88SKan Liang * unique capabilities. 912d0946a88SKan Liang */ 913d4b294bfSKan Liang int num_hybrid_pmus; 914d0946a88SKan Liang struct x86_hybrid_pmu *hybrid_pmu; 915d9977c43SKan Liang u8 (*get_hybrid_cpu_type) (void); 91627f6d22bSBorislav Petkov }; 91727f6d22bSBorislav Petkov 918530bfff6SKan Liang struct x86_perf_task_context_opt { 919530bfff6SKan Liang int lbr_callstack_users; 920530bfff6SKan Liang int lbr_stack_state; 921530bfff6SKan Liang int log_id; 922530bfff6SKan Liang }; 923530bfff6SKan Liang 92427f6d22bSBorislav Petkov struct x86_perf_task_context { 925e1ad1ac2SLike Xu u64 lbr_sel; 92627f6d22bSBorislav Petkov int tos; 9270592e57bSKan Liang int valid_lbrs; 928530bfff6SKan Liang struct x86_perf_task_context_opt opt; 9295624986dSKan Liang struct lbr_entry lbr[MAX_LBR_ENTRIES]; 93027f6d22bSBorislav Petkov }; 93127f6d22bSBorislav Petkov 93247125db2SKan Liang struct x86_perf_task_context_arch_lbr { 93347125db2SKan Liang struct x86_perf_task_context_opt opt; 93447125db2SKan Liang struct lbr_entry entries[]; 93547125db2SKan Liang }; 93647125db2SKan Liang 937ce711ea3SKan Liang /* 938ce711ea3SKan Liang * Add padding to guarantee the 64-byte alignment of the state buffer. 939ce711ea3SKan Liang * 940ce711ea3SKan Liang * The structure is dynamically allocated. The size of the LBR state may vary 941ce711ea3SKan Liang * based on the number of LBR registers. 942ce711ea3SKan Liang * 943ce711ea3SKan Liang * Do not put anything after the LBR state. 944ce711ea3SKan Liang */ 945ce711ea3SKan Liang struct x86_perf_task_context_arch_lbr_xsave { 946ce711ea3SKan Liang struct x86_perf_task_context_opt opt; 947ce711ea3SKan Liang 948ce711ea3SKan Liang union { 949ce711ea3SKan Liang struct xregs_state xsave; 950ce711ea3SKan Liang struct { 951ce711ea3SKan Liang struct fxregs_state i387; 952ce711ea3SKan Liang struct xstate_header header; 953ce711ea3SKan Liang struct arch_lbr_state lbr; 954ce711ea3SKan Liang } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT))); 955ce711ea3SKan Liang }; 956ce711ea3SKan Liang }; 957ce711ea3SKan Liang 95827f6d22bSBorislav Petkov #define x86_add_quirk(func_) \ 95927f6d22bSBorislav Petkov do { \ 96027f6d22bSBorislav Petkov static struct x86_pmu_quirk __quirk __initdata = { \ 96127f6d22bSBorislav Petkov .func = func_, \ 96227f6d22bSBorislav Petkov }; \ 96327f6d22bSBorislav Petkov __quirk.next = x86_pmu.quirks; \ 96427f6d22bSBorislav Petkov x86_pmu.quirks = &__quirk; \ 96527f6d22bSBorislav Petkov } while (0) 96627f6d22bSBorislav Petkov 96727f6d22bSBorislav Petkov /* 96827f6d22bSBorislav Petkov * x86_pmu flags 96927f6d22bSBorislav Petkov */ 97027f6d22bSBorislav Petkov #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ 97127f6d22bSBorislav Petkov #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ 97227f6d22bSBorislav Petkov #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ 97327f6d22bSBorislav Petkov #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ 97431962340SKan Liang #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */ 975400816f6SPeter Zijlstra (Intel) #define PMU_FL_TFA 0x20 /* deal with TSX force abort */ 976471af006SKim Phillips #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */ 97761b985e3SKan Liang #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */ 97861b985e3SKan Liang #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */ 97927f6d22bSBorislav Petkov 98027f6d22bSBorislav Petkov #define EVENT_VAR(_id) event_attr_##_id 98127f6d22bSBorislav Petkov #define EVENT_PTR(_id) &event_attr_##_id.attr.attr 98227f6d22bSBorislav Petkov 98327f6d22bSBorislav Petkov #define EVENT_ATTR(_name, _id) \ 98427f6d22bSBorislav Petkov static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ 98527f6d22bSBorislav Petkov .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 98627f6d22bSBorislav Petkov .id = PERF_COUNT_HW_##_id, \ 98727f6d22bSBorislav Petkov .event_str = NULL, \ 98827f6d22bSBorislav Petkov }; 98927f6d22bSBorislav Petkov 99027f6d22bSBorislav Petkov #define EVENT_ATTR_STR(_name, v, str) \ 99127f6d22bSBorislav Petkov static struct perf_pmu_events_attr event_attr_##v = { \ 99227f6d22bSBorislav Petkov .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 99327f6d22bSBorislav Petkov .id = 0, \ 99427f6d22bSBorislav Petkov .event_str = str, \ 99527f6d22bSBorislav Petkov }; 99627f6d22bSBorislav Petkov 997fc07e9f9SAndi Kleen #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \ 998fc07e9f9SAndi Kleen static struct perf_pmu_events_ht_attr event_attr_##v = { \ 999fc07e9f9SAndi Kleen .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\ 1000fc07e9f9SAndi Kleen .id = 0, \ 1001fc07e9f9SAndi Kleen .event_str_noht = noht, \ 1002fc07e9f9SAndi Kleen .event_str_ht = ht, \ 1003fc07e9f9SAndi Kleen } 1004fc07e9f9SAndi Kleen 1005a9c81ccdSKan Liang #define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \ 1006a9c81ccdSKan Liang static struct perf_pmu_events_hybrid_attr event_attr_##v = { \ 1007a9c81ccdSKan Liang .attr = __ATTR(_name, 0444, events_hybrid_sysfs_show, NULL),\ 1008a9c81ccdSKan Liang .id = 0, \ 1009a9c81ccdSKan Liang .event_str = str, \ 1010a9c81ccdSKan Liang .pmu_type = _pmu, \ 1011a9c81ccdSKan Liang } 1012a9c81ccdSKan Liang 1013a9c81ccdSKan Liang #define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr) 1014a9c81ccdSKan Liang 1015a9c81ccdSKan Liang #define FORMAT_ATTR_HYBRID(_name, _pmu) \ 1016a9c81ccdSKan Liang static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\ 1017a9c81ccdSKan Liang .attr = __ATTR_RO(_name), \ 1018a9c81ccdSKan Liang .pmu_type = _pmu, \ 1019a9c81ccdSKan Liang } 1020a9c81ccdSKan Liang 102161e76d53SKan Liang struct pmu *x86_get_pmu(unsigned int cpu); 102227f6d22bSBorislav Petkov extern struct x86_pmu x86_pmu __read_mostly; 102327f6d22bSBorislav Petkov 1024f42be865SKan Liang static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx) 1025f42be865SKan Liang { 102647125db2SKan Liang if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 102747125db2SKan Liang return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt; 102847125db2SKan Liang 1029f42be865SKan Liang return &((struct x86_perf_task_context *)ctx)->opt; 1030f42be865SKan Liang } 1031f42be865SKan Liang 103227f6d22bSBorislav Petkov static inline bool x86_pmu_has_lbr_callstack(void) 103327f6d22bSBorislav Petkov { 103427f6d22bSBorislav Petkov return x86_pmu.lbr_sel_map && 103527f6d22bSBorislav Petkov x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; 103627f6d22bSBorislav Petkov } 103727f6d22bSBorislav Petkov 103827f6d22bSBorislav Petkov DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 103927f6d22bSBorislav Petkov 104027f6d22bSBorislav Petkov int x86_perf_event_set_period(struct perf_event *event); 104127f6d22bSBorislav Petkov 104227f6d22bSBorislav Petkov /* 104327f6d22bSBorislav Petkov * Generalized hw caching related hw_event table, filled 104427f6d22bSBorislav Petkov * in on a per model basis. A value of 0 means 104527f6d22bSBorislav Petkov * 'not supported', -1 means 'hw_event makes no sense on 104627f6d22bSBorislav Petkov * this CPU', any other value means the raw hw_event 104727f6d22bSBorislav Petkov * ID. 104827f6d22bSBorislav Petkov */ 104927f6d22bSBorislav Petkov 105027f6d22bSBorislav Petkov #define C(x) PERF_COUNT_HW_CACHE_##x 105127f6d22bSBorislav Petkov 105227f6d22bSBorislav Petkov extern u64 __read_mostly hw_cache_event_ids 105327f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 105427f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 105527f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX]; 105627f6d22bSBorislav Petkov extern u64 __read_mostly hw_cache_extra_regs 105727f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 105827f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 105927f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX]; 106027f6d22bSBorislav Petkov 106127f6d22bSBorislav Petkov u64 x86_perf_event_update(struct perf_event *event); 106227f6d22bSBorislav Petkov 106327f6d22bSBorislav Petkov static inline unsigned int x86_pmu_config_addr(int index) 106427f6d22bSBorislav Petkov { 106527f6d22bSBorislav Petkov return x86_pmu.eventsel + (x86_pmu.addr_offset ? 106627f6d22bSBorislav Petkov x86_pmu.addr_offset(index, true) : index); 106727f6d22bSBorislav Petkov } 106827f6d22bSBorislav Petkov 106927f6d22bSBorislav Petkov static inline unsigned int x86_pmu_event_addr(int index) 107027f6d22bSBorislav Petkov { 107127f6d22bSBorislav Petkov return x86_pmu.perfctr + (x86_pmu.addr_offset ? 107227f6d22bSBorislav Petkov x86_pmu.addr_offset(index, false) : index); 107327f6d22bSBorislav Petkov } 107427f6d22bSBorislav Petkov 107527f6d22bSBorislav Petkov static inline int x86_pmu_rdpmc_index(int index) 107627f6d22bSBorislav Petkov { 107727f6d22bSBorislav Petkov return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; 107827f6d22bSBorislav Petkov } 107927f6d22bSBorislav Petkov 1080fc4b8fcaSKan Liang bool check_hw_exists(struct pmu *pmu, int num_counters, 1081fc4b8fcaSKan Liang int num_counters_fixed); 1082fc4b8fcaSKan Liang 108327f6d22bSBorislav Petkov int x86_add_exclusive(unsigned int what); 108427f6d22bSBorislav Petkov 108527f6d22bSBorislav Petkov void x86_del_exclusive(unsigned int what); 108627f6d22bSBorislav Petkov 108727f6d22bSBorislav Petkov int x86_reserve_hardware(void); 108827f6d22bSBorislav Petkov 108927f6d22bSBorislav Petkov void x86_release_hardware(void); 109027f6d22bSBorislav Petkov 1091b00233b5SAndi Kleen int x86_pmu_max_precise(void); 1092b00233b5SAndi Kleen 109327f6d22bSBorislav Petkov void hw_perf_lbr_event_destroy(struct perf_event *event); 109427f6d22bSBorislav Petkov 109527f6d22bSBorislav Petkov int x86_setup_perfctr(struct perf_event *event); 109627f6d22bSBorislav Petkov 109727f6d22bSBorislav Petkov int x86_pmu_hw_config(struct perf_event *event); 109827f6d22bSBorislav Petkov 109927f6d22bSBorislav Petkov void x86_pmu_disable_all(void); 110027f6d22bSBorislav Petkov 110157388912SKim Phillips static inline bool is_counter_pair(struct hw_perf_event *hwc) 110257388912SKim Phillips { 110357388912SKim Phillips return hwc->flags & PERF_X86_EVENT_PAIR; 110457388912SKim Phillips } 110557388912SKim Phillips 110627f6d22bSBorislav Petkov static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, 110727f6d22bSBorislav Petkov u64 enable_mask) 110827f6d22bSBorislav Petkov { 110927f6d22bSBorislav Petkov u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 111027f6d22bSBorislav Petkov 111127f6d22bSBorislav Petkov if (hwc->extra_reg.reg) 111227f6d22bSBorislav Petkov wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); 111357388912SKim Phillips 111457388912SKim Phillips /* 111557388912SKim Phillips * Add enabled Merge event on next counter 111657388912SKim Phillips * if large increment event being enabled on this counter 111757388912SKim Phillips */ 111857388912SKim Phillips if (is_counter_pair(hwc)) 111957388912SKim Phillips wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); 112057388912SKim Phillips 112127f6d22bSBorislav Petkov wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 112227f6d22bSBorislav Petkov } 112327f6d22bSBorislav Petkov 112427f6d22bSBorislav Petkov void x86_pmu_enable_all(int added); 112527f6d22bSBorislav Petkov 112627f6d22bSBorislav Petkov int perf_assign_events(struct event_constraint **constraints, int n, 112727f6d22bSBorislav Petkov int wmin, int wmax, int gpmax, int *assign); 112827f6d22bSBorislav Petkov int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); 112927f6d22bSBorislav Petkov 113027f6d22bSBorislav Petkov void x86_pmu_stop(struct perf_event *event, int flags); 113127f6d22bSBorislav Petkov 113227f6d22bSBorislav Petkov static inline void x86_pmu_disable_event(struct perf_event *event) 113327f6d22bSBorislav Petkov { 1134df51fe7eSLike Xu u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 113527f6d22bSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 113627f6d22bSBorislav Petkov 1137df51fe7eSLike Xu wrmsrl(hwc->config_base, hwc->config & ~disable_mask); 113857388912SKim Phillips 113957388912SKim Phillips if (is_counter_pair(hwc)) 114057388912SKim Phillips wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0); 114127f6d22bSBorislav Petkov } 114227f6d22bSBorislav Petkov 114327f6d22bSBorislav Petkov void x86_pmu_enable_event(struct perf_event *event); 114427f6d22bSBorislav Petkov 114527f6d22bSBorislav Petkov int x86_pmu_handle_irq(struct pt_regs *regs); 114627f6d22bSBorislav Petkov 1147e11c1a7eSKan Liang void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed, 1148e11c1a7eSKan Liang u64 intel_ctrl); 1149e11c1a7eSKan Liang 1150d9977c43SKan Liang void x86_pmu_update_cpu_context(struct pmu *pmu, int cpu); 1151d9977c43SKan Liang 115227f6d22bSBorislav Petkov extern struct event_constraint emptyconstraint; 115327f6d22bSBorislav Petkov 115427f6d22bSBorislav Petkov extern struct event_constraint unconstrained; 115527f6d22bSBorislav Petkov 115627f6d22bSBorislav Petkov static inline bool kernel_ip(unsigned long ip) 115727f6d22bSBorislav Petkov { 115827f6d22bSBorislav Petkov #ifdef CONFIG_X86_32 115927f6d22bSBorislav Petkov return ip > PAGE_OFFSET; 116027f6d22bSBorislav Petkov #else 116127f6d22bSBorislav Petkov return (long)ip < 0; 116227f6d22bSBorislav Petkov #endif 116327f6d22bSBorislav Petkov } 116427f6d22bSBorislav Petkov 116527f6d22bSBorislav Petkov /* 116627f6d22bSBorislav Petkov * Not all PMUs provide the right context information to place the reported IP 116727f6d22bSBorislav Petkov * into full context. Specifically segment registers are typically not 116827f6d22bSBorislav Petkov * supplied. 116927f6d22bSBorislav Petkov * 117027f6d22bSBorislav Petkov * Assuming the address is a linear address (it is for IBS), we fake the CS and 117127f6d22bSBorislav Petkov * vm86 mode using the known zero-based code segment and 'fix up' the registers 117227f6d22bSBorislav Petkov * to reflect this. 117327f6d22bSBorislav Petkov * 117427f6d22bSBorislav Petkov * Intel PEBS/LBR appear to typically provide the effective address, nothing 117527f6d22bSBorislav Petkov * much we can do about that but pray and treat it like a linear address. 117627f6d22bSBorislav Petkov */ 117727f6d22bSBorislav Petkov static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) 117827f6d22bSBorislav Petkov { 117927f6d22bSBorislav Petkov regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; 118027f6d22bSBorislav Petkov if (regs->flags & X86_VM_MASK) 118127f6d22bSBorislav Petkov regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); 118227f6d22bSBorislav Petkov regs->ip = ip; 118327f6d22bSBorislav Petkov } 118427f6d22bSBorislav Petkov 118527f6d22bSBorislav Petkov ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); 118627f6d22bSBorislav Petkov ssize_t intel_event_sysfs_show(char *page, u64 config); 118727f6d22bSBorislav Petkov 1188a49ac9f8SHuang Rui ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, 1189a49ac9f8SHuang Rui char *page); 1190fc07e9f9SAndi Kleen ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 1191fc07e9f9SAndi Kleen char *page); 1192a9c81ccdSKan Liang ssize_t events_hybrid_sysfs_show(struct device *dev, 1193a9c81ccdSKan Liang struct device_attribute *attr, 1194a9c81ccdSKan Liang char *page); 1195a49ac9f8SHuang Rui 1196fc4b8fcaSKan Liang static inline bool fixed_counter_disabled(int i, struct pmu *pmu) 119732451614SKan Liang { 1198fc4b8fcaSKan Liang u64 intel_ctrl = hybrid(pmu, intel_ctrl); 1199fc4b8fcaSKan Liang 1200fc4b8fcaSKan Liang return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED)); 120132451614SKan Liang } 120232451614SKan Liang 120327f6d22bSBorislav Petkov #ifdef CONFIG_CPU_SUP_AMD 120427f6d22bSBorislav Petkov 120527f6d22bSBorislav Petkov int amd_pmu_init(void); 120627f6d22bSBorislav Petkov 120727f6d22bSBorislav Petkov #else /* CONFIG_CPU_SUP_AMD */ 120827f6d22bSBorislav Petkov 120927f6d22bSBorislav Petkov static inline int amd_pmu_init(void) 121027f6d22bSBorislav Petkov { 121127f6d22bSBorislav Petkov return 0; 121227f6d22bSBorislav Petkov } 121327f6d22bSBorislav Petkov 121427f6d22bSBorislav Petkov #endif /* CONFIG_CPU_SUP_AMD */ 121527f6d22bSBorislav Petkov 121642880f72SAlexander Shishkin static inline int is_pebs_pt(struct perf_event *event) 121742880f72SAlexander Shishkin { 121842880f72SAlexander Shishkin return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT); 121942880f72SAlexander Shishkin } 122042880f72SAlexander Shishkin 122127f6d22bSBorislav Petkov #ifdef CONFIG_CPU_SUP_INTEL 122227f6d22bSBorislav Petkov 122381ec3f3cSJiri Olsa static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period) 122427f6d22bSBorislav Petkov { 122567266c10SJiri Olsa struct hw_perf_event *hwc = &event->hw; 122667266c10SJiri Olsa unsigned int hw_event, bts_event; 122727f6d22bSBorislav Petkov 122867266c10SJiri Olsa if (event->attr.freq) 122927f6d22bSBorislav Petkov return false; 123067266c10SJiri Olsa 123167266c10SJiri Olsa hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 123267266c10SJiri Olsa bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 123367266c10SJiri Olsa 123481ec3f3cSJiri Olsa return hw_event == bts_event && period == 1; 123581ec3f3cSJiri Olsa } 123681ec3f3cSJiri Olsa 123781ec3f3cSJiri Olsa static inline bool intel_pmu_has_bts(struct perf_event *event) 123881ec3f3cSJiri Olsa { 123981ec3f3cSJiri Olsa struct hw_perf_event *hwc = &event->hw; 124081ec3f3cSJiri Olsa 124181ec3f3cSJiri Olsa return intel_pmu_has_bts_period(event, hwc->sample_period); 124227f6d22bSBorislav Petkov } 124327f6d22bSBorislav Petkov 124427f6d22bSBorislav Petkov int intel_pmu_save_and_restart(struct perf_event *event); 124527f6d22bSBorislav Petkov 124627f6d22bSBorislav Petkov struct event_constraint * 124727f6d22bSBorislav Petkov x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 124827f6d22bSBorislav Petkov struct perf_event *event); 124927f6d22bSBorislav Petkov 1250d01b1f96SPeter Zijlstra (Intel) extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu); 1251d01b1f96SPeter Zijlstra (Intel) extern void intel_cpuc_finish(struct cpu_hw_events *cpuc); 125227f6d22bSBorislav Petkov 125327f6d22bSBorislav Petkov int intel_pmu_init(void); 125427f6d22bSBorislav Petkov 125527f6d22bSBorislav Petkov void init_debug_store_on_cpu(int cpu); 125627f6d22bSBorislav Petkov 125727f6d22bSBorislav Petkov void fini_debug_store_on_cpu(int cpu); 125827f6d22bSBorislav Petkov 125927f6d22bSBorislav Petkov void release_ds_buffers(void); 126027f6d22bSBorislav Petkov 126127f6d22bSBorislav Petkov void reserve_ds_buffers(void); 126227f6d22bSBorislav Petkov 1263c085fb87SKan Liang void release_lbr_buffers(void); 1264c085fb87SKan Liang 1265488e13a4SLike Xu void reserve_lbr_buffers(void); 1266488e13a4SLike Xu 126727f6d22bSBorislav Petkov extern struct event_constraint bts_constraint; 1268097e4311SLike Xu extern struct event_constraint vlbr_constraint; 126927f6d22bSBorislav Petkov 127027f6d22bSBorislav Petkov void intel_pmu_enable_bts(u64 config); 127127f6d22bSBorislav Petkov 127227f6d22bSBorislav Petkov void intel_pmu_disable_bts(void); 127327f6d22bSBorislav Petkov 127427f6d22bSBorislav Petkov int intel_pmu_drain_bts_buffer(void); 127527f6d22bSBorislav Petkov 127627f6d22bSBorislav Petkov extern struct event_constraint intel_core2_pebs_event_constraints[]; 127727f6d22bSBorislav Petkov 127827f6d22bSBorislav Petkov extern struct event_constraint intel_atom_pebs_event_constraints[]; 127927f6d22bSBorislav Petkov 128027f6d22bSBorislav Petkov extern struct event_constraint intel_slm_pebs_event_constraints[]; 128127f6d22bSBorislav Petkov 12828b92c3a7SKan Liang extern struct event_constraint intel_glm_pebs_event_constraints[]; 12838b92c3a7SKan Liang 1284dd0b06b5SKan Liang extern struct event_constraint intel_glp_pebs_event_constraints[]; 1285dd0b06b5SKan Liang 1286f83d2f91SKan Liang extern struct event_constraint intel_grt_pebs_event_constraints[]; 1287f83d2f91SKan Liang 128827f6d22bSBorislav Petkov extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 128927f6d22bSBorislav Petkov 129027f6d22bSBorislav Petkov extern struct event_constraint intel_westmere_pebs_event_constraints[]; 129127f6d22bSBorislav Petkov 129227f6d22bSBorislav Petkov extern struct event_constraint intel_snb_pebs_event_constraints[]; 129327f6d22bSBorislav Petkov 129427f6d22bSBorislav Petkov extern struct event_constraint intel_ivb_pebs_event_constraints[]; 129527f6d22bSBorislav Petkov 129627f6d22bSBorislav Petkov extern struct event_constraint intel_hsw_pebs_event_constraints[]; 129727f6d22bSBorislav Petkov 1298b3e62463SStephane Eranian extern struct event_constraint intel_bdw_pebs_event_constraints[]; 1299b3e62463SStephane Eranian 130027f6d22bSBorislav Petkov extern struct event_constraint intel_skl_pebs_event_constraints[]; 130127f6d22bSBorislav Petkov 130260176089SKan Liang extern struct event_constraint intel_icl_pebs_event_constraints[]; 130360176089SKan Liang 130461b985e3SKan Liang extern struct event_constraint intel_spr_pebs_event_constraints[]; 130561b985e3SKan Liang 130627f6d22bSBorislav Petkov struct event_constraint *intel_pebs_constraints(struct perf_event *event); 130727f6d22bSBorislav Petkov 130868f7082fSPeter Zijlstra void intel_pmu_pebs_add(struct perf_event *event); 130968f7082fSPeter Zijlstra 131068f7082fSPeter Zijlstra void intel_pmu_pebs_del(struct perf_event *event); 131168f7082fSPeter Zijlstra 131227f6d22bSBorislav Petkov void intel_pmu_pebs_enable(struct perf_event *event); 131327f6d22bSBorislav Petkov 131427f6d22bSBorislav Petkov void intel_pmu_pebs_disable(struct perf_event *event); 131527f6d22bSBorislav Petkov 131627f6d22bSBorislav Petkov void intel_pmu_pebs_enable_all(void); 131727f6d22bSBorislav Petkov 131827f6d22bSBorislav Petkov void intel_pmu_pebs_disable_all(void); 131927f6d22bSBorislav Petkov 132027f6d22bSBorislav Petkov void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in); 132127f6d22bSBorislav Petkov 13225bee2cc6SKan Liang void intel_pmu_auto_reload_read(struct perf_event *event); 13235bee2cc6SKan Liang 13245624986dSKan Liang void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr); 1325c22497f5SKan Liang 132627f6d22bSBorislav Petkov void intel_ds_init(void); 132727f6d22bSBorislav Petkov 1328421ca868SAlexey Budankov void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev, 1329421ca868SAlexey Budankov struct perf_event_context *next); 1330421ca868SAlexey Budankov 133127f6d22bSBorislav Petkov void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in); 133227f6d22bSBorislav Petkov 133319fc9dddSDavid Carrillo-Cisneros u64 lbr_from_signext_quirk_wr(u64 val); 133419fc9dddSDavid Carrillo-Cisneros 133527f6d22bSBorislav Petkov void intel_pmu_lbr_reset(void); 133627f6d22bSBorislav Petkov 13379f354a72SKan Liang void intel_pmu_lbr_reset_32(void); 13389f354a72SKan Liang 13399f354a72SKan Liang void intel_pmu_lbr_reset_64(void); 13409f354a72SKan Liang 134168f7082fSPeter Zijlstra void intel_pmu_lbr_add(struct perf_event *event); 134227f6d22bSBorislav Petkov 134368f7082fSPeter Zijlstra void intel_pmu_lbr_del(struct perf_event *event); 134427f6d22bSBorislav Petkov 134527f6d22bSBorislav Petkov void intel_pmu_lbr_enable_all(bool pmi); 134627f6d22bSBorislav Petkov 134727f6d22bSBorislav Petkov void intel_pmu_lbr_disable_all(void); 134827f6d22bSBorislav Petkov 134927f6d22bSBorislav Petkov void intel_pmu_lbr_read(void); 135027f6d22bSBorislav Petkov 1351c301b1d8SKan Liang void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc); 1352c301b1d8SKan Liang 1353c301b1d8SKan Liang void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc); 1354c301b1d8SKan Liang 1355799571bfSKan Liang void intel_pmu_lbr_save(void *ctx); 1356799571bfSKan Liang 1357799571bfSKan Liang void intel_pmu_lbr_restore(void *ctx); 1358799571bfSKan Liang 135927f6d22bSBorislav Petkov void intel_pmu_lbr_init_core(void); 136027f6d22bSBorislav Petkov 136127f6d22bSBorislav Petkov void intel_pmu_lbr_init_nhm(void); 136227f6d22bSBorislav Petkov 136327f6d22bSBorislav Petkov void intel_pmu_lbr_init_atom(void); 136427f6d22bSBorislav Petkov 1365f21d5adcSKan Liang void intel_pmu_lbr_init_slm(void); 1366f21d5adcSKan Liang 136727f6d22bSBorislav Petkov void intel_pmu_lbr_init_snb(void); 136827f6d22bSBorislav Petkov 136927f6d22bSBorislav Petkov void intel_pmu_lbr_init_hsw(void); 137027f6d22bSBorislav Petkov 137127f6d22bSBorislav Petkov void intel_pmu_lbr_init_skl(void); 137227f6d22bSBorislav Petkov 137327f6d22bSBorislav Petkov void intel_pmu_lbr_init_knl(void); 137427f6d22bSBorislav Petkov 137547125db2SKan Liang void intel_pmu_arch_lbr_init(void); 137647125db2SKan Liang 1377e17dc653SAndi Kleen void intel_pmu_pebs_data_source_nhm(void); 1378e17dc653SAndi Kleen 13796ae5fa61SAndi Kleen void intel_pmu_pebs_data_source_skl(bool pmem); 13806ae5fa61SAndi Kleen 138127f6d22bSBorislav Petkov int intel_pmu_setup_lbr_filter(struct perf_event *event); 138227f6d22bSBorislav Petkov 138327f6d22bSBorislav Petkov void intel_pt_interrupt(void); 138427f6d22bSBorislav Petkov 138527f6d22bSBorislav Petkov int intel_bts_interrupt(void); 138627f6d22bSBorislav Petkov 138727f6d22bSBorislav Petkov void intel_bts_enable_local(void); 138827f6d22bSBorislav Petkov 138927f6d22bSBorislav Petkov void intel_bts_disable_local(void); 139027f6d22bSBorislav Petkov 139127f6d22bSBorislav Petkov int p4_pmu_init(void); 139227f6d22bSBorislav Petkov 139327f6d22bSBorislav Petkov int p6_pmu_init(void); 139427f6d22bSBorislav Petkov 139527f6d22bSBorislav Petkov int knc_pmu_init(void); 139627f6d22bSBorislav Petkov 139727f6d22bSBorislav Petkov static inline int is_ht_workaround_enabled(void) 139827f6d22bSBorislav Petkov { 139927f6d22bSBorislav Petkov return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); 140027f6d22bSBorislav Petkov } 140127f6d22bSBorislav Petkov 140227f6d22bSBorislav Petkov #else /* CONFIG_CPU_SUP_INTEL */ 140327f6d22bSBorislav Petkov 140427f6d22bSBorislav Petkov static inline void reserve_ds_buffers(void) 140527f6d22bSBorislav Petkov { 140627f6d22bSBorislav Petkov } 140727f6d22bSBorislav Petkov 140827f6d22bSBorislav Petkov static inline void release_ds_buffers(void) 140927f6d22bSBorislav Petkov { 141027f6d22bSBorislav Petkov } 141127f6d22bSBorislav Petkov 1412c085fb87SKan Liang static inline void release_lbr_buffers(void) 1413c085fb87SKan Liang { 1414c085fb87SKan Liang } 1415c085fb87SKan Liang 1416488e13a4SLike Xu static inline void reserve_lbr_buffers(void) 1417488e13a4SLike Xu { 1418488e13a4SLike Xu } 1419488e13a4SLike Xu 142027f6d22bSBorislav Petkov static inline int intel_pmu_init(void) 142127f6d22bSBorislav Petkov { 142227f6d22bSBorislav Petkov return 0; 142327f6d22bSBorislav Petkov } 142427f6d22bSBorislav Petkov 1425f764c58bSPeter Zijlstra static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 142627f6d22bSBorislav Petkov { 1427d01b1f96SPeter Zijlstra (Intel) return 0; 1428d01b1f96SPeter Zijlstra (Intel) } 1429d01b1f96SPeter Zijlstra (Intel) 1430f764c58bSPeter Zijlstra static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc) 1431d01b1f96SPeter Zijlstra (Intel) { 143227f6d22bSBorislav Petkov } 143327f6d22bSBorislav Petkov 143427f6d22bSBorislav Petkov static inline int is_ht_workaround_enabled(void) 143527f6d22bSBorislav Petkov { 143627f6d22bSBorislav Petkov return 0; 143727f6d22bSBorislav Petkov } 143827f6d22bSBorislav Petkov #endif /* CONFIG_CPU_SUP_INTEL */ 14393a4ac121SCodyYao-oc 14403a4ac121SCodyYao-oc #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN)) 14413a4ac121SCodyYao-oc int zhaoxin_pmu_init(void); 14423a4ac121SCodyYao-oc #else 14433a4ac121SCodyYao-oc static inline int zhaoxin_pmu_init(void) 14443a4ac121SCodyYao-oc { 14453a4ac121SCodyYao-oc return 0; 14463a4ac121SCodyYao-oc } 14473a4ac121SCodyYao-oc #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/ 1448