127f6d22bSBorislav Petkov /* 227f6d22bSBorislav Petkov * Performance events x86 architecture header 327f6d22bSBorislav Petkov * 427f6d22bSBorislav Petkov * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 527f6d22bSBorislav Petkov * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 627f6d22bSBorislav Petkov * Copyright (C) 2009 Jaswinder Singh Rajput 727f6d22bSBorislav Petkov * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 827f6d22bSBorislav Petkov * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 927f6d22bSBorislav Petkov * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 1027f6d22bSBorislav Petkov * Copyright (C) 2009 Google, Inc., Stephane Eranian 1127f6d22bSBorislav Petkov * 1227f6d22bSBorislav Petkov * For licencing details see kernel-base/COPYING 1327f6d22bSBorislav Petkov */ 1427f6d22bSBorislav Petkov 1527f6d22bSBorislav Petkov #include <linux/perf_event.h> 1627f6d22bSBorislav Petkov 1710043e02SThomas Gleixner #include <asm/intel_ds.h> 1810043e02SThomas Gleixner 1927f6d22bSBorislav Petkov /* To enable MSR tracing please use the generic trace points. */ 2027f6d22bSBorislav Petkov 2127f6d22bSBorislav Petkov /* 2227f6d22bSBorislav Petkov * | NHM/WSM | SNB | 2327f6d22bSBorislav Petkov * register ------------------------------- 2427f6d22bSBorislav Petkov * | HT | no HT | HT | no HT | 2527f6d22bSBorislav Petkov *----------------------------------------- 2627f6d22bSBorislav Petkov * offcore | core | core | cpu | core | 2727f6d22bSBorislav Petkov * lbr_sel | core | core | cpu | core | 2827f6d22bSBorislav Petkov * ld_lat | cpu | core | cpu | core | 2927f6d22bSBorislav Petkov *----------------------------------------- 3027f6d22bSBorislav Petkov * 3127f6d22bSBorislav Petkov * Given that there is a small number of shared regs, 3227f6d22bSBorislav Petkov * we can pre-allocate their slot in the per-cpu 3327f6d22bSBorislav Petkov * per-core reg tables. 3427f6d22bSBorislav Petkov */ 3527f6d22bSBorislav Petkov enum extra_reg_type { 3627f6d22bSBorislav Petkov EXTRA_REG_NONE = -1, /* not used */ 3727f6d22bSBorislav Petkov 3827f6d22bSBorislav Petkov EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ 3927f6d22bSBorislav Petkov EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ 4027f6d22bSBorislav Petkov EXTRA_REG_LBR = 2, /* lbr_select */ 4127f6d22bSBorislav Petkov EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ 4227f6d22bSBorislav Petkov EXTRA_REG_FE = 4, /* fe_* */ 4327f6d22bSBorislav Petkov 4427f6d22bSBorislav Petkov EXTRA_REG_MAX /* number of entries needed */ 4527f6d22bSBorislav Petkov }; 4627f6d22bSBorislav Petkov 4727f6d22bSBorislav Petkov struct event_constraint { 4827f6d22bSBorislav Petkov union { 4927f6d22bSBorislav Petkov unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 5027f6d22bSBorislav Petkov u64 idxmsk64; 5127f6d22bSBorislav Petkov }; 5227f6d22bSBorislav Petkov u64 code; 5327f6d22bSBorislav Petkov u64 cmask; 5427f6d22bSBorislav Petkov int weight; 5527f6d22bSBorislav Petkov int overlap; 5627f6d22bSBorislav Petkov int flags; 5763b79f6eSPeter Zijlstra unsigned int size; 5827f6d22bSBorislav Petkov }; 591f6a1e2dSPeter Zijlstra 6063b79f6eSPeter Zijlstra static inline bool constraint_match(struct event_constraint *c, u64 ecode) 6163b79f6eSPeter Zijlstra { 6263b79f6eSPeter Zijlstra return ((ecode & c->cmask) - c->code) <= (u64)c->size; 6363b79f6eSPeter Zijlstra } 6463b79f6eSPeter Zijlstra 6527f6d22bSBorislav Petkov /* 6627f6d22bSBorislav Petkov * struct hw_perf_event.flags flags 6727f6d22bSBorislav Petkov */ 6827f6d22bSBorislav Petkov #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */ 6927f6d22bSBorislav Petkov #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */ 7027f6d22bSBorislav Petkov #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */ 711f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_PEBS_LD_HSW 0x0008 /* haswell style datala, load */ 721f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_PEBS_NA_HSW 0x0010 /* haswell style datala, unknown */ 731f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_EXCL 0x0020 /* HT exclusivity on counter */ 741f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_DYNAMIC 0x0040 /* dynamic alloc'd constraint */ 751f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0080 /* grant rdpmc permission */ 761f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_EXCL_ACCT 0x0100 /* accounted EXCL event */ 771f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_AUTO_RELOAD 0x0200 /* use PEBS auto-reload */ 781f6a1e2dSPeter Zijlstra #define PERF_X86_EVENT_LARGE_PEBS 0x0400 /* use large PEBS */ 7927f6d22bSBorislav Petkov 8027f6d22bSBorislav Petkov struct amd_nb { 8127f6d22bSBorislav Petkov int nb_id; /* NorthBridge id */ 8227f6d22bSBorislav Petkov int refcnt; /* reference count */ 8327f6d22bSBorislav Petkov struct perf_event *owners[X86_PMC_IDX_MAX]; 8427f6d22bSBorislav Petkov struct event_constraint event_constraints[X86_PMC_IDX_MAX]; 8527f6d22bSBorislav Petkov }; 8627f6d22bSBorislav Petkov 87fd583ad1SKan Liang #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) 8827f6d22bSBorislav Petkov 8927f6d22bSBorislav Petkov /* 9027f6d22bSBorislav Petkov * Flags PEBS can handle without an PMI. 9127f6d22bSBorislav Petkov * 9227f6d22bSBorislav Petkov * TID can only be handled by flushing at context switch. 932fe1bc1fSAndi Kleen * REGS_USER can be handled for events limited to ring 3. 9427f6d22bSBorislav Petkov * 9527f6d22bSBorislav Petkov */ 96174afc3eSKan Liang #define LARGE_PEBS_FLAGS \ 9727f6d22bSBorislav Petkov (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 9827f6d22bSBorislav Petkov PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 9927f6d22bSBorislav Petkov PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 1002fe1bc1fSAndi Kleen PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ 10111974914SJiri Olsa PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \ 10211974914SJiri Olsa PERF_SAMPLE_PERIOD) 10327f6d22bSBorislav Petkov 1049d5dcc93SKan Liang #define PEBS_GP_REGS \ 1059d5dcc93SKan Liang ((1ULL << PERF_REG_X86_AX) | \ 1069d5dcc93SKan Liang (1ULL << PERF_REG_X86_BX) | \ 1079d5dcc93SKan Liang (1ULL << PERF_REG_X86_CX) | \ 1089d5dcc93SKan Liang (1ULL << PERF_REG_X86_DX) | \ 1099d5dcc93SKan Liang (1ULL << PERF_REG_X86_DI) | \ 1109d5dcc93SKan Liang (1ULL << PERF_REG_X86_SI) | \ 1119d5dcc93SKan Liang (1ULL << PERF_REG_X86_SP) | \ 1129d5dcc93SKan Liang (1ULL << PERF_REG_X86_BP) | \ 1139d5dcc93SKan Liang (1ULL << PERF_REG_X86_IP) | \ 1149d5dcc93SKan Liang (1ULL << PERF_REG_X86_FLAGS) | \ 1159d5dcc93SKan Liang (1ULL << PERF_REG_X86_R8) | \ 1169d5dcc93SKan Liang (1ULL << PERF_REG_X86_R9) | \ 1179d5dcc93SKan Liang (1ULL << PERF_REG_X86_R10) | \ 1189d5dcc93SKan Liang (1ULL << PERF_REG_X86_R11) | \ 1199d5dcc93SKan Liang (1ULL << PERF_REG_X86_R12) | \ 1209d5dcc93SKan Liang (1ULL << PERF_REG_X86_R13) | \ 1219d5dcc93SKan Liang (1ULL << PERF_REG_X86_R14) | \ 1229d5dcc93SKan Liang (1ULL << PERF_REG_X86_R15)) 1232fe1bc1fSAndi Kleen 124878068eaSKan Liang #define PEBS_XMM_REGS \ 125878068eaSKan Liang ((1ULL << PERF_REG_X86_XMM0) | \ 126878068eaSKan Liang (1ULL << PERF_REG_X86_XMM1) | \ 127878068eaSKan Liang (1ULL << PERF_REG_X86_XMM2) | \ 128878068eaSKan Liang (1ULL << PERF_REG_X86_XMM3) | \ 129878068eaSKan Liang (1ULL << PERF_REG_X86_XMM4) | \ 130878068eaSKan Liang (1ULL << PERF_REG_X86_XMM5) | \ 131878068eaSKan Liang (1ULL << PERF_REG_X86_XMM6) | \ 132878068eaSKan Liang (1ULL << PERF_REG_X86_XMM7) | \ 133878068eaSKan Liang (1ULL << PERF_REG_X86_XMM8) | \ 134878068eaSKan Liang (1ULL << PERF_REG_X86_XMM9) | \ 135878068eaSKan Liang (1ULL << PERF_REG_X86_XMM10) | \ 136878068eaSKan Liang (1ULL << PERF_REG_X86_XMM11) | \ 137878068eaSKan Liang (1ULL << PERF_REG_X86_XMM12) | \ 138878068eaSKan Liang (1ULL << PERF_REG_X86_XMM13) | \ 139878068eaSKan Liang (1ULL << PERF_REG_X86_XMM14) | \ 140878068eaSKan Liang (1ULL << PERF_REG_X86_XMM15)) 141878068eaSKan Liang 14227f6d22bSBorislav Petkov /* 14327f6d22bSBorislav Petkov * Per register state. 14427f6d22bSBorislav Petkov */ 14527f6d22bSBorislav Petkov struct er_account { 14627f6d22bSBorislav Petkov raw_spinlock_t lock; /* per-core: protect structure */ 14727f6d22bSBorislav Petkov u64 config; /* extra MSR config */ 14827f6d22bSBorislav Petkov u64 reg; /* extra MSR number */ 14927f6d22bSBorislav Petkov atomic_t ref; /* reference count */ 15027f6d22bSBorislav Petkov }; 15127f6d22bSBorislav Petkov 15227f6d22bSBorislav Petkov /* 15327f6d22bSBorislav Petkov * Per core/cpu state 15427f6d22bSBorislav Petkov * 15527f6d22bSBorislav Petkov * Used to coordinate shared registers between HT threads or 15627f6d22bSBorislav Petkov * among events on a single PMU. 15727f6d22bSBorislav Petkov */ 15827f6d22bSBorislav Petkov struct intel_shared_regs { 15927f6d22bSBorislav Petkov struct er_account regs[EXTRA_REG_MAX]; 16027f6d22bSBorislav Petkov int refcnt; /* per-core: #HT threads */ 16127f6d22bSBorislav Petkov unsigned core_id; /* per-core: core id */ 16227f6d22bSBorislav Petkov }; 16327f6d22bSBorislav Petkov 16427f6d22bSBorislav Petkov enum intel_excl_state_type { 16527f6d22bSBorislav Petkov INTEL_EXCL_UNUSED = 0, /* counter is unused */ 16627f6d22bSBorislav Petkov INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ 16727f6d22bSBorislav Petkov INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ 16827f6d22bSBorislav Petkov }; 16927f6d22bSBorislav Petkov 17027f6d22bSBorislav Petkov struct intel_excl_states { 17127f6d22bSBorislav Petkov enum intel_excl_state_type state[X86_PMC_IDX_MAX]; 17227f6d22bSBorislav Petkov bool sched_started; /* true if scheduling has started */ 17327f6d22bSBorislav Petkov }; 17427f6d22bSBorislav Petkov 17527f6d22bSBorislav Petkov struct intel_excl_cntrs { 17627f6d22bSBorislav Petkov raw_spinlock_t lock; 17727f6d22bSBorislav Petkov 17827f6d22bSBorislav Petkov struct intel_excl_states states[2]; 17927f6d22bSBorislav Petkov 18027f6d22bSBorislav Petkov union { 18127f6d22bSBorislav Petkov u16 has_exclusive[2]; 18227f6d22bSBorislav Petkov u32 exclusive_present; 18327f6d22bSBorislav Petkov }; 18427f6d22bSBorislav Petkov 18527f6d22bSBorislav Petkov int refcnt; /* per-core: #HT threads */ 18627f6d22bSBorislav Petkov unsigned core_id; /* per-core: core id */ 18727f6d22bSBorislav Petkov }; 18827f6d22bSBorislav Petkov 1898b077e4aSKan Liang struct x86_perf_task_context; 19027f6d22bSBorislav Petkov #define MAX_LBR_ENTRIES 32 19127f6d22bSBorislav Petkov 19227f6d22bSBorislav Petkov enum { 19327f6d22bSBorislav Petkov X86_PERF_KFREE_SHARED = 0, 19427f6d22bSBorislav Petkov X86_PERF_KFREE_EXCL = 1, 19527f6d22bSBorislav Petkov X86_PERF_KFREE_MAX 19627f6d22bSBorislav Petkov }; 19727f6d22bSBorislav Petkov 19827f6d22bSBorislav Petkov struct cpu_hw_events { 19927f6d22bSBorislav Petkov /* 20027f6d22bSBorislav Petkov * Generic x86 PMC bits 20127f6d22bSBorislav Petkov */ 20227f6d22bSBorislav Petkov struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ 20327f6d22bSBorislav Petkov unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 20427f6d22bSBorislav Petkov unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 20527f6d22bSBorislav Petkov int enabled; 20627f6d22bSBorislav Petkov 20727f6d22bSBorislav Petkov int n_events; /* the # of events in the below arrays */ 20827f6d22bSBorislav Petkov int n_added; /* the # last events in the below arrays; 20927f6d22bSBorislav Petkov they've never been enabled yet */ 21027f6d22bSBorislav Petkov int n_txn; /* the # last events in the below arrays; 21127f6d22bSBorislav Petkov added in the current transaction */ 21227f6d22bSBorislav Petkov int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ 21327f6d22bSBorislav Petkov u64 tags[X86_PMC_IDX_MAX]; 21427f6d22bSBorislav Petkov 21527f6d22bSBorislav Petkov struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ 21627f6d22bSBorislav Petkov struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; 21727f6d22bSBorislav Petkov 21827f6d22bSBorislav Petkov int n_excl; /* the number of exclusive events */ 21927f6d22bSBorislav Petkov 22027f6d22bSBorislav Petkov unsigned int txn_flags; 22127f6d22bSBorislav Petkov int is_fake; 22227f6d22bSBorislav Petkov 22327f6d22bSBorislav Petkov /* 22427f6d22bSBorislav Petkov * Intel DebugStore bits 22527f6d22bSBorislav Petkov */ 22627f6d22bSBorislav Petkov struct debug_store *ds; 227c1961a46SHugh Dickins void *ds_pebs_vaddr; 228c1961a46SHugh Dickins void *ds_bts_vaddr; 22927f6d22bSBorislav Petkov u64 pebs_enabled; 23009e61b4fSPeter Zijlstra int n_pebs; 23109e61b4fSPeter Zijlstra int n_large_pebs; 23227f6d22bSBorislav Petkov 233c22497f5SKan Liang /* Current super set of events hardware configuration */ 234c22497f5SKan Liang u64 pebs_data_cfg; 235c22497f5SKan Liang u64 active_pebs_data_cfg; 236c22497f5SKan Liang int pebs_record_size; 237c22497f5SKan Liang 23827f6d22bSBorislav Petkov /* 23927f6d22bSBorislav Petkov * Intel LBR bits 24027f6d22bSBorislav Petkov */ 24127f6d22bSBorislav Petkov int lbr_users; 242d3617b98SAndi Kleen int lbr_pebs_users; 24327f6d22bSBorislav Petkov struct perf_branch_stack lbr_stack; 24427f6d22bSBorislav Petkov struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; 24527f6d22bSBorislav Petkov struct er_account *lbr_sel; 24627f6d22bSBorislav Petkov u64 br_sel; 2478b077e4aSKan Liang struct x86_perf_task_context *last_task_ctx; 2488b077e4aSKan Liang int last_log_id; 24927f6d22bSBorislav Petkov 25027f6d22bSBorislav Petkov /* 25127f6d22bSBorislav Petkov * Intel host/guest exclude bits 25227f6d22bSBorislav Petkov */ 25327f6d22bSBorislav Petkov u64 intel_ctrl_guest_mask; 25427f6d22bSBorislav Petkov u64 intel_ctrl_host_mask; 25527f6d22bSBorislav Petkov struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; 25627f6d22bSBorislav Petkov 25727f6d22bSBorislav Petkov /* 25827f6d22bSBorislav Petkov * Intel checkpoint mask 25927f6d22bSBorislav Petkov */ 26027f6d22bSBorislav Petkov u64 intel_cp_status; 26127f6d22bSBorislav Petkov 26227f6d22bSBorislav Petkov /* 26327f6d22bSBorislav Petkov * manage shared (per-core, per-cpu) registers 26427f6d22bSBorislav Petkov * used on Intel NHM/WSM/SNB 26527f6d22bSBorislav Petkov */ 26627f6d22bSBorislav Petkov struct intel_shared_regs *shared_regs; 26727f6d22bSBorislav Petkov /* 26827f6d22bSBorislav Petkov * manage exclusive counter access between hyperthread 26927f6d22bSBorislav Petkov */ 27027f6d22bSBorislav Petkov struct event_constraint *constraint_list; /* in enable order */ 27127f6d22bSBorislav Petkov struct intel_excl_cntrs *excl_cntrs; 27227f6d22bSBorislav Petkov int excl_thread_id; /* 0 or 1 */ 27327f6d22bSBorislav Petkov 27427f6d22bSBorislav Petkov /* 275400816f6SPeter Zijlstra (Intel) * SKL TSX_FORCE_ABORT shadow 276400816f6SPeter Zijlstra (Intel) */ 277400816f6SPeter Zijlstra (Intel) u64 tfa_shadow; 278400816f6SPeter Zijlstra (Intel) 279400816f6SPeter Zijlstra (Intel) /* 28027f6d22bSBorislav Petkov * AMD specific bits 28127f6d22bSBorislav Petkov */ 28227f6d22bSBorislav Petkov struct amd_nb *amd_nb; 28327f6d22bSBorislav Petkov /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ 28427f6d22bSBorislav Petkov u64 perf_ctr_virt_mask; 28527f6d22bSBorislav Petkov 28627f6d22bSBorislav Petkov void *kfree_on_online[X86_PERF_KFREE_MAX]; 28727f6d22bSBorislav Petkov }; 28827f6d22bSBorislav Petkov 28963b79f6eSPeter Zijlstra #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \ 29027f6d22bSBorislav Petkov { .idxmsk64 = (n) }, \ 29127f6d22bSBorislav Petkov .code = (c), \ 29263b79f6eSPeter Zijlstra .size = (e) - (c), \ 29327f6d22bSBorislav Petkov .cmask = (m), \ 29427f6d22bSBorislav Petkov .weight = (w), \ 29527f6d22bSBorislav Petkov .overlap = (o), \ 29627f6d22bSBorislav Petkov .flags = f, \ 29727f6d22bSBorislav Petkov } 29827f6d22bSBorislav Petkov 29963b79f6eSPeter Zijlstra #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ 30063b79f6eSPeter Zijlstra __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f) 30163b79f6eSPeter Zijlstra 30227f6d22bSBorislav Petkov #define EVENT_CONSTRAINT(c, n, m) \ 30327f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) 30427f6d22bSBorislav Petkov 30563b79f6eSPeter Zijlstra /* 30663b79f6eSPeter Zijlstra * The constraint_match() function only works for 'simple' event codes 30763b79f6eSPeter Zijlstra * and not for extended (AMD64_EVENTSEL_EVENT) events codes. 30863b79f6eSPeter Zijlstra */ 30963b79f6eSPeter Zijlstra #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \ 31063b79f6eSPeter Zijlstra __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0) 31163b79f6eSPeter Zijlstra 31227f6d22bSBorislav Petkov #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ 31327f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ 31427f6d22bSBorislav Petkov 0, PERF_X86_EVENT_EXCL) 31527f6d22bSBorislav Petkov 31627f6d22bSBorislav Petkov /* 31727f6d22bSBorislav Petkov * The overlap flag marks event constraints with overlapping counter 31827f6d22bSBorislav Petkov * masks. This is the case if the counter mask of such an event is not 31927f6d22bSBorislav Petkov * a subset of any other counter mask of a constraint with an equal or 32027f6d22bSBorislav Petkov * higher weight, e.g.: 32127f6d22bSBorislav Petkov * 32227f6d22bSBorislav Petkov * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); 32327f6d22bSBorislav Petkov * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); 32427f6d22bSBorislav Petkov * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); 32527f6d22bSBorislav Petkov * 32627f6d22bSBorislav Petkov * The event scheduler may not select the correct counter in the first 32727f6d22bSBorislav Petkov * cycle because it needs to know which subsequent events will be 32827f6d22bSBorislav Petkov * scheduled. It may fail to schedule the events then. So we set the 32927f6d22bSBorislav Petkov * overlap flag for such constraints to give the scheduler a hint which 33027f6d22bSBorislav Petkov * events to select for counter rescheduling. 33127f6d22bSBorislav Petkov * 33227f6d22bSBorislav Petkov * Care must be taken as the rescheduling algorithm is O(n!) which 33300f52685SIngo Molnar * will increase scheduling cycles for an over-committed system 33427f6d22bSBorislav Petkov * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros 33527f6d22bSBorislav Petkov * and its counter masks must be kept at a minimum. 33627f6d22bSBorislav Petkov */ 33727f6d22bSBorislav Petkov #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ 33827f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) 33927f6d22bSBorislav Petkov 34027f6d22bSBorislav Petkov /* 34127f6d22bSBorislav Petkov * Constraint on the Event code. 34227f6d22bSBorislav Petkov */ 34327f6d22bSBorislav Petkov #define INTEL_EVENT_CONSTRAINT(c, n) \ 34427f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) 34527f6d22bSBorislav Petkov 34627f6d22bSBorislav Petkov /* 34763b79f6eSPeter Zijlstra * Constraint on a range of Event codes 34863b79f6eSPeter Zijlstra */ 34963b79f6eSPeter Zijlstra #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \ 35063b79f6eSPeter Zijlstra EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT) 35163b79f6eSPeter Zijlstra 35263b79f6eSPeter Zijlstra /* 35327f6d22bSBorislav Petkov * Constraint on the Event code + UMask + fixed-mask 35427f6d22bSBorislav Petkov * 35527f6d22bSBorislav Petkov * filter mask to validate fixed counter events. 35627f6d22bSBorislav Petkov * the following filters disqualify for fixed counters: 35727f6d22bSBorislav Petkov * - inv 35827f6d22bSBorislav Petkov * - edge 35927f6d22bSBorislav Petkov * - cnt-mask 36027f6d22bSBorislav Petkov * - in_tx 36127f6d22bSBorislav Petkov * - in_tx_checkpointed 36227f6d22bSBorislav Petkov * The other filters are supported by fixed counters. 36327f6d22bSBorislav Petkov * The any-thread option is supported starting with v3. 36427f6d22bSBorislav Petkov */ 36527f6d22bSBorislav Petkov #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) 36627f6d22bSBorislav Petkov #define FIXED_EVENT_CONSTRAINT(c, n) \ 36727f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) 36827f6d22bSBorislav Petkov 36927f6d22bSBorislav Petkov /* 37027f6d22bSBorislav Petkov * Constraint on the Event code + UMask 37127f6d22bSBorislav Petkov */ 37227f6d22bSBorislav Petkov #define INTEL_UEVENT_CONSTRAINT(c, n) \ 37327f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) 37427f6d22bSBorislav Petkov 37527f6d22bSBorislav Petkov /* Constraint on specific umask bit only + event */ 37627f6d22bSBorislav Petkov #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \ 37727f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c)) 37827f6d22bSBorislav Petkov 37927f6d22bSBorislav Petkov /* Like UEVENT_CONSTRAINT, but match flags too */ 38027f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ 38127f6d22bSBorislav Petkov EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) 38227f6d22bSBorislav Petkov 38327f6d22bSBorislav Petkov #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ 38427f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ 38527f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) 38627f6d22bSBorislav Petkov 38727f6d22bSBorislav Petkov #define INTEL_PLD_CONSTRAINT(c, n) \ 38827f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 38927f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) 39027f6d22bSBorislav Petkov 39127f6d22bSBorislav Petkov #define INTEL_PST_CONSTRAINT(c, n) \ 39227f6d22bSBorislav Petkov __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 39327f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) 39427f6d22bSBorislav Petkov 39527f6d22bSBorislav Petkov /* Event constraint, but match on all event flags too. */ 39627f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ 397*6b89d4c1SStephane Eranian EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 39827f6d22bSBorislav Petkov 39963b79f6eSPeter Zijlstra #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ 400*6b89d4c1SStephane Eranian EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 40163b79f6eSPeter Zijlstra 40227f6d22bSBorislav Petkov /* Check only flags, but allow all event/umask */ 40327f6d22bSBorislav Petkov #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ 40427f6d22bSBorislav Petkov EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) 40527f6d22bSBorislav Petkov 40627f6d22bSBorislav Petkov /* Check flags and event code, and set the HSW store flag */ 40727f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ 40827f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 40927f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 41027f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 41127f6d22bSBorislav Petkov 41227f6d22bSBorislav Petkov /* Check flags and event code, and set the HSW load flag */ 41327f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ 41427f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 41527f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 41627f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 41727f6d22bSBorislav Petkov 41863b79f6eSPeter Zijlstra #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \ 41963b79f6eSPeter Zijlstra __EVENT_CONSTRAINT_RANGE(code, end, n, \ 42063b79f6eSPeter Zijlstra ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 42163b79f6eSPeter Zijlstra HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 42263b79f6eSPeter Zijlstra 42327f6d22bSBorislav Petkov #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ 42427f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 42527f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 42627f6d22bSBorislav Petkov HWEIGHT(n), 0, \ 42727f6d22bSBorislav Petkov PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 42827f6d22bSBorislav Petkov 42927f6d22bSBorislav Petkov /* Check flags and event code/umask, and set the HSW store flag */ 43027f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ 43127f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 43227f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 43327f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 43427f6d22bSBorislav Petkov 43527f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ 43627f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 43727f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 43827f6d22bSBorislav Petkov HWEIGHT(n), 0, \ 43927f6d22bSBorislav Petkov PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) 44027f6d22bSBorislav Petkov 44127f6d22bSBorislav Petkov /* Check flags and event code/umask, and set the HSW load flag */ 44227f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ 44327f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 44427f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 44527f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 44627f6d22bSBorislav Petkov 44727f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ 44827f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 44927f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 45027f6d22bSBorislav Petkov HWEIGHT(n), 0, \ 45127f6d22bSBorislav Petkov PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 45227f6d22bSBorislav Petkov 45327f6d22bSBorislav Petkov /* Check flags and event code/umask, and set the HSW N/A flag */ 45427f6d22bSBorislav Petkov #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ 45527f6d22bSBorislav Petkov __EVENT_CONSTRAINT(code, n, \ 45627f6d22bSBorislav Petkov INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 45727f6d22bSBorislav Petkov HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) 45827f6d22bSBorislav Petkov 45927f6d22bSBorislav Petkov 46027f6d22bSBorislav Petkov /* 46127f6d22bSBorislav Petkov * We define the end marker as having a weight of -1 46227f6d22bSBorislav Petkov * to enable blacklisting of events using a counter bitmask 46327f6d22bSBorislav Petkov * of zero and thus a weight of zero. 46427f6d22bSBorislav Petkov * The end marker has a weight that cannot possibly be 46527f6d22bSBorislav Petkov * obtained from counting the bits in the bitmask. 46627f6d22bSBorislav Petkov */ 46727f6d22bSBorislav Petkov #define EVENT_CONSTRAINT_END { .weight = -1 } 46827f6d22bSBorislav Petkov 46927f6d22bSBorislav Petkov /* 47027f6d22bSBorislav Petkov * Check for end marker with weight == -1 47127f6d22bSBorislav Petkov */ 47227f6d22bSBorislav Petkov #define for_each_event_constraint(e, c) \ 47327f6d22bSBorislav Petkov for ((e) = (c); (e)->weight != -1; (e)++) 47427f6d22bSBorislav Petkov 47527f6d22bSBorislav Petkov /* 47627f6d22bSBorislav Petkov * Extra registers for specific events. 47727f6d22bSBorislav Petkov * 47827f6d22bSBorislav Petkov * Some events need large masks and require external MSRs. 47927f6d22bSBorislav Petkov * Those extra MSRs end up being shared for all events on 48027f6d22bSBorislav Petkov * a PMU and sometimes between PMU of sibling HT threads. 48127f6d22bSBorislav Petkov * In either case, the kernel needs to handle conflicting 48227f6d22bSBorislav Petkov * accesses to those extra, shared, regs. The data structure 48327f6d22bSBorislav Petkov * to manage those registers is stored in cpu_hw_event. 48427f6d22bSBorislav Petkov */ 48527f6d22bSBorislav Petkov struct extra_reg { 48627f6d22bSBorislav Petkov unsigned int event; 48727f6d22bSBorislav Petkov unsigned int msr; 48827f6d22bSBorislav Petkov u64 config_mask; 48927f6d22bSBorislav Petkov u64 valid_mask; 49027f6d22bSBorislav Petkov int idx; /* per_xxx->regs[] reg index */ 49127f6d22bSBorislav Petkov bool extra_msr_access; 49227f6d22bSBorislav Petkov }; 49327f6d22bSBorislav Petkov 49427f6d22bSBorislav Petkov #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ 49527f6d22bSBorislav Petkov .event = (e), \ 49627f6d22bSBorislav Petkov .msr = (ms), \ 49727f6d22bSBorislav Petkov .config_mask = (m), \ 49827f6d22bSBorislav Petkov .valid_mask = (vm), \ 49927f6d22bSBorislav Petkov .idx = EXTRA_REG_##i, \ 50027f6d22bSBorislav Petkov .extra_msr_access = true, \ 50127f6d22bSBorislav Petkov } 50227f6d22bSBorislav Petkov 50327f6d22bSBorislav Petkov #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ 50427f6d22bSBorislav Petkov EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) 50527f6d22bSBorislav Petkov 50627f6d22bSBorislav Petkov #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ 50727f6d22bSBorislav Petkov EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ 50827f6d22bSBorislav Petkov ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) 50927f6d22bSBorislav Petkov 51027f6d22bSBorislav Petkov #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ 51127f6d22bSBorislav Petkov INTEL_UEVENT_EXTRA_REG(c, \ 51227f6d22bSBorislav Petkov MSR_PEBS_LD_LAT_THRESHOLD, \ 51327f6d22bSBorislav Petkov 0xffff, \ 51427f6d22bSBorislav Petkov LDLAT) 51527f6d22bSBorislav Petkov 51627f6d22bSBorislav Petkov #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) 51727f6d22bSBorislav Petkov 51827f6d22bSBorislav Petkov union perf_capabilities { 51927f6d22bSBorislav Petkov struct { 52027f6d22bSBorislav Petkov u64 lbr_format:6; 52127f6d22bSBorislav Petkov u64 pebs_trap:1; 52227f6d22bSBorislav Petkov u64 pebs_arch_reg:1; 52327f6d22bSBorislav Petkov u64 pebs_format:4; 52427f6d22bSBorislav Petkov u64 smm_freeze:1; 52527f6d22bSBorislav Petkov /* 52627f6d22bSBorislav Petkov * PMU supports separate counter range for writing 52727f6d22bSBorislav Petkov * values > 32bit. 52827f6d22bSBorislav Petkov */ 52927f6d22bSBorislav Petkov u64 full_width_write:1; 530c22497f5SKan Liang u64 pebs_baseline:1; 53127f6d22bSBorislav Petkov }; 53227f6d22bSBorislav Petkov u64 capabilities; 53327f6d22bSBorislav Petkov }; 53427f6d22bSBorislav Petkov 53527f6d22bSBorislav Petkov struct x86_pmu_quirk { 53627f6d22bSBorislav Petkov struct x86_pmu_quirk *next; 53727f6d22bSBorislav Petkov void (*func)(void); 53827f6d22bSBorislav Petkov }; 53927f6d22bSBorislav Petkov 54027f6d22bSBorislav Petkov union x86_pmu_config { 54127f6d22bSBorislav Petkov struct { 54227f6d22bSBorislav Petkov u64 event:8, 54327f6d22bSBorislav Petkov umask:8, 54427f6d22bSBorislav Petkov usr:1, 54527f6d22bSBorislav Petkov os:1, 54627f6d22bSBorislav Petkov edge:1, 54727f6d22bSBorislav Petkov pc:1, 54827f6d22bSBorislav Petkov interrupt:1, 54927f6d22bSBorislav Petkov __reserved1:1, 55027f6d22bSBorislav Petkov en:1, 55127f6d22bSBorislav Petkov inv:1, 55227f6d22bSBorislav Petkov cmask:8, 55327f6d22bSBorislav Petkov event2:4, 55427f6d22bSBorislav Petkov __reserved2:4, 55527f6d22bSBorislav Petkov go:1, 55627f6d22bSBorislav Petkov ho:1; 55727f6d22bSBorislav Petkov } bits; 55827f6d22bSBorislav Petkov u64 value; 55927f6d22bSBorislav Petkov }; 56027f6d22bSBorislav Petkov 56127f6d22bSBorislav Petkov #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value 56227f6d22bSBorislav Petkov 56327f6d22bSBorislav Petkov enum { 56427f6d22bSBorislav Petkov x86_lbr_exclusive_lbr, 56527f6d22bSBorislav Petkov x86_lbr_exclusive_bts, 56627f6d22bSBorislav Petkov x86_lbr_exclusive_pt, 56727f6d22bSBorislav Petkov x86_lbr_exclusive_max, 56827f6d22bSBorislav Petkov }; 56927f6d22bSBorislav Petkov 57027f6d22bSBorislav Petkov /* 57127f6d22bSBorislav Petkov * struct x86_pmu - generic x86 pmu 57227f6d22bSBorislav Petkov */ 57327f6d22bSBorislav Petkov struct x86_pmu { 57427f6d22bSBorislav Petkov /* 57527f6d22bSBorislav Petkov * Generic x86 PMC bits 57627f6d22bSBorislav Petkov */ 57727f6d22bSBorislav Petkov const char *name; 57827f6d22bSBorislav Petkov int version; 57927f6d22bSBorislav Petkov int (*handle_irq)(struct pt_regs *); 58027f6d22bSBorislav Petkov void (*disable_all)(void); 58127f6d22bSBorislav Petkov void (*enable_all)(int added); 58227f6d22bSBorislav Petkov void (*enable)(struct perf_event *); 58327f6d22bSBorislav Petkov void (*disable)(struct perf_event *); 58468f7082fSPeter Zijlstra void (*add)(struct perf_event *); 58568f7082fSPeter Zijlstra void (*del)(struct perf_event *); 586bcfbe5c4SKan Liang void (*read)(struct perf_event *event); 58727f6d22bSBorislav Petkov int (*hw_config)(struct perf_event *event); 58827f6d22bSBorislav Petkov int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); 58927f6d22bSBorislav Petkov unsigned eventsel; 59027f6d22bSBorislav Petkov unsigned perfctr; 59127f6d22bSBorislav Petkov int (*addr_offset)(int index, bool eventsel); 59227f6d22bSBorislav Petkov int (*rdpmc_index)(int index); 59327f6d22bSBorislav Petkov u64 (*event_map)(int); 59427f6d22bSBorislav Petkov int max_events; 59527f6d22bSBorislav Petkov int num_counters; 59627f6d22bSBorislav Petkov int num_counters_fixed; 59727f6d22bSBorislav Petkov int cntval_bits; 59827f6d22bSBorislav Petkov u64 cntval_mask; 59927f6d22bSBorislav Petkov union { 60027f6d22bSBorislav Petkov unsigned long events_maskl; 60127f6d22bSBorislav Petkov unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; 60227f6d22bSBorislav Petkov }; 60327f6d22bSBorislav Petkov int events_mask_len; 60427f6d22bSBorislav Petkov int apic; 60527f6d22bSBorislav Petkov u64 max_period; 60627f6d22bSBorislav Petkov struct event_constraint * 60727f6d22bSBorislav Petkov (*get_event_constraints)(struct cpu_hw_events *cpuc, 60827f6d22bSBorislav Petkov int idx, 60927f6d22bSBorislav Petkov struct perf_event *event); 61027f6d22bSBorislav Petkov 61127f6d22bSBorislav Petkov void (*put_event_constraints)(struct cpu_hw_events *cpuc, 61227f6d22bSBorislav Petkov struct perf_event *event); 61327f6d22bSBorislav Petkov 61427f6d22bSBorislav Petkov void (*start_scheduling)(struct cpu_hw_events *cpuc); 61527f6d22bSBorislav Petkov 61627f6d22bSBorislav Petkov void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); 61727f6d22bSBorislav Petkov 61827f6d22bSBorislav Petkov void (*stop_scheduling)(struct cpu_hw_events *cpuc); 61927f6d22bSBorislav Petkov 62027f6d22bSBorislav Petkov struct event_constraint *event_constraints; 62127f6d22bSBorislav Petkov struct x86_pmu_quirk *quirks; 62227f6d22bSBorislav Petkov int perfctr_second_write; 623f605cfcaSKan Liang u64 (*limit_period)(struct perf_event *event, u64 l); 62427f6d22bSBorislav Petkov 625af3bdb99SAndi Kleen /* PMI handler bits */ 626af3bdb99SAndi Kleen unsigned int late_ack :1, 627af3bdb99SAndi Kleen counter_freezing :1; 62827f6d22bSBorislav Petkov /* 62927f6d22bSBorislav Petkov * sysfs attrs 63027f6d22bSBorislav Petkov */ 63127f6d22bSBorislav Petkov int attr_rdpmc_broken; 63227f6d22bSBorislav Petkov int attr_rdpmc; 63327f6d22bSBorislav Petkov struct attribute **format_attrs; 63427f6d22bSBorislav Petkov struct attribute **event_attrs; 635b00233b5SAndi Kleen struct attribute **caps_attrs; 63627f6d22bSBorislav Petkov 63727f6d22bSBorislav Petkov ssize_t (*events_sysfs_show)(char *page, u64 config); 63827f6d22bSBorislav Petkov struct attribute **cpu_events; 63927f6d22bSBorislav Petkov 6406089327fSKan Liang unsigned long attr_freeze_on_smi; 6416089327fSKan Liang struct attribute **attrs; 6426089327fSKan Liang 64327f6d22bSBorislav Petkov /* 64427f6d22bSBorislav Petkov * CPU Hotplug hooks 64527f6d22bSBorislav Petkov */ 64627f6d22bSBorislav Petkov int (*cpu_prepare)(int cpu); 64727f6d22bSBorislav Petkov void (*cpu_starting)(int cpu); 64827f6d22bSBorislav Petkov void (*cpu_dying)(int cpu); 64927f6d22bSBorislav Petkov void (*cpu_dead)(int cpu); 65027f6d22bSBorislav Petkov 65127f6d22bSBorislav Petkov void (*check_microcode)(void); 65227f6d22bSBorislav Petkov void (*sched_task)(struct perf_event_context *ctx, 65327f6d22bSBorislav Petkov bool sched_in); 65427f6d22bSBorislav Petkov 65527f6d22bSBorislav Petkov /* 65627f6d22bSBorislav Petkov * Intel Arch Perfmon v2+ 65727f6d22bSBorislav Petkov */ 65827f6d22bSBorislav Petkov u64 intel_ctrl; 65927f6d22bSBorislav Petkov union perf_capabilities intel_cap; 66027f6d22bSBorislav Petkov 66127f6d22bSBorislav Petkov /* 66227f6d22bSBorislav Petkov * Intel DebugStore bits 66327f6d22bSBorislav Petkov */ 66427f6d22bSBorislav Petkov unsigned int bts :1, 66527f6d22bSBorislav Petkov bts_active :1, 66627f6d22bSBorislav Petkov pebs :1, 66727f6d22bSBorislav Petkov pebs_active :1, 66827f6d22bSBorislav Petkov pebs_broken :1, 66995298355SAndi Kleen pebs_prec_dist :1, 6709b545c04SAndi Kleen pebs_no_tlb :1, 671878068eaSKan Liang pebs_no_isolation :1, 672878068eaSKan Liang pebs_no_xmm_regs :1; 67327f6d22bSBorislav Petkov int pebs_record_size; 674e72daf3fSJiri Olsa int pebs_buffer_size; 675c22497f5SKan Liang int max_pebs_events; 67627f6d22bSBorislav Petkov void (*drain_pebs)(struct pt_regs *regs); 67727f6d22bSBorislav Petkov struct event_constraint *pebs_constraints; 67827f6d22bSBorislav Petkov void (*pebs_aliases)(struct perf_event *event); 679174afc3eSKan Liang unsigned long large_pebs_flags; 680c22497f5SKan Liang u64 rtm_abort_event; 68127f6d22bSBorislav Petkov 68227f6d22bSBorislav Petkov /* 68327f6d22bSBorislav Petkov * Intel LBR 68427f6d22bSBorislav Petkov */ 68527f6d22bSBorislav Petkov unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ 68627f6d22bSBorislav Petkov int lbr_nr; /* hardware stack size */ 68727f6d22bSBorislav Petkov u64 lbr_sel_mask; /* LBR_SELECT valid bits */ 68827f6d22bSBorislav Petkov const int *lbr_sel_map; /* lbr_select mappings */ 68927f6d22bSBorislav Petkov bool lbr_double_abort; /* duplicated lbr aborts */ 690b0c1ef52SAndi Kleen bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ 69127f6d22bSBorislav Petkov 69227f6d22bSBorislav Petkov /* 69327f6d22bSBorislav Petkov * Intel PT/LBR/BTS are exclusive 69427f6d22bSBorislav Petkov */ 69527f6d22bSBorislav Petkov atomic_t lbr_exclusive[x86_lbr_exclusive_max]; 69627f6d22bSBorislav Petkov 69727f6d22bSBorislav Petkov /* 69832b62f44SPeter Zijlstra * AMD bits 69932b62f44SPeter Zijlstra */ 70032b62f44SPeter Zijlstra unsigned int amd_nb_constraints : 1; 70132b62f44SPeter Zijlstra 70232b62f44SPeter Zijlstra /* 70327f6d22bSBorislav Petkov * Extra registers for events 70427f6d22bSBorislav Petkov */ 70527f6d22bSBorislav Petkov struct extra_reg *extra_regs; 70627f6d22bSBorislav Petkov unsigned int flags; 70727f6d22bSBorislav Petkov 70827f6d22bSBorislav Petkov /* 70927f6d22bSBorislav Petkov * Intel host/guest support (KVM) 71027f6d22bSBorislav Petkov */ 71127f6d22bSBorislav Petkov struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr); 71281ec3f3cSJiri Olsa 71381ec3f3cSJiri Olsa /* 71481ec3f3cSJiri Olsa * Check period value for PERF_EVENT_IOC_PERIOD ioctl. 71581ec3f3cSJiri Olsa */ 71681ec3f3cSJiri Olsa int (*check_period) (struct perf_event *event, u64 period); 71727f6d22bSBorislav Petkov }; 71827f6d22bSBorislav Petkov 71927f6d22bSBorislav Petkov struct x86_perf_task_context { 72027f6d22bSBorislav Petkov u64 lbr_from[MAX_LBR_ENTRIES]; 72127f6d22bSBorislav Petkov u64 lbr_to[MAX_LBR_ENTRIES]; 72227f6d22bSBorislav Petkov u64 lbr_info[MAX_LBR_ENTRIES]; 72327f6d22bSBorislav Petkov int tos; 7240592e57bSKan Liang int valid_lbrs; 72527f6d22bSBorislav Petkov int lbr_callstack_users; 72627f6d22bSBorislav Petkov int lbr_stack_state; 7278b077e4aSKan Liang int log_id; 72827f6d22bSBorislav Petkov }; 72927f6d22bSBorislav Petkov 73027f6d22bSBorislav Petkov #define x86_add_quirk(func_) \ 73127f6d22bSBorislav Petkov do { \ 73227f6d22bSBorislav Petkov static struct x86_pmu_quirk __quirk __initdata = { \ 73327f6d22bSBorislav Petkov .func = func_, \ 73427f6d22bSBorislav Petkov }; \ 73527f6d22bSBorislav Petkov __quirk.next = x86_pmu.quirks; \ 73627f6d22bSBorislav Petkov x86_pmu.quirks = &__quirk; \ 73727f6d22bSBorislav Petkov } while (0) 73827f6d22bSBorislav Petkov 73927f6d22bSBorislav Petkov /* 74027f6d22bSBorislav Petkov * x86_pmu flags 74127f6d22bSBorislav Petkov */ 74227f6d22bSBorislav Petkov #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ 74327f6d22bSBorislav Petkov #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ 74427f6d22bSBorislav Petkov #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ 74527f6d22bSBorislav Petkov #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ 74631962340SKan Liang #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */ 747400816f6SPeter Zijlstra (Intel) #define PMU_FL_TFA 0x20 /* deal with TSX force abort */ 74827f6d22bSBorislav Petkov 74927f6d22bSBorislav Petkov #define EVENT_VAR(_id) event_attr_##_id 75027f6d22bSBorislav Petkov #define EVENT_PTR(_id) &event_attr_##_id.attr.attr 75127f6d22bSBorislav Petkov 75227f6d22bSBorislav Petkov #define EVENT_ATTR(_name, _id) \ 75327f6d22bSBorislav Petkov static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ 75427f6d22bSBorislav Petkov .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 75527f6d22bSBorislav Petkov .id = PERF_COUNT_HW_##_id, \ 75627f6d22bSBorislav Petkov .event_str = NULL, \ 75727f6d22bSBorislav Petkov }; 75827f6d22bSBorislav Petkov 75927f6d22bSBorislav Petkov #define EVENT_ATTR_STR(_name, v, str) \ 76027f6d22bSBorislav Petkov static struct perf_pmu_events_attr event_attr_##v = { \ 76127f6d22bSBorislav Petkov .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 76227f6d22bSBorislav Petkov .id = 0, \ 76327f6d22bSBorislav Petkov .event_str = str, \ 76427f6d22bSBorislav Petkov }; 76527f6d22bSBorislav Petkov 766fc07e9f9SAndi Kleen #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \ 767fc07e9f9SAndi Kleen static struct perf_pmu_events_ht_attr event_attr_##v = { \ 768fc07e9f9SAndi Kleen .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\ 769fc07e9f9SAndi Kleen .id = 0, \ 770fc07e9f9SAndi Kleen .event_str_noht = noht, \ 771fc07e9f9SAndi Kleen .event_str_ht = ht, \ 772fc07e9f9SAndi Kleen } 773fc07e9f9SAndi Kleen 774f447e4ebSStephane Eranian struct pmu *x86_get_pmu(void); 77527f6d22bSBorislav Petkov extern struct x86_pmu x86_pmu __read_mostly; 77627f6d22bSBorislav Petkov 77727f6d22bSBorislav Petkov static inline bool x86_pmu_has_lbr_callstack(void) 77827f6d22bSBorislav Petkov { 77927f6d22bSBorislav Petkov return x86_pmu.lbr_sel_map && 78027f6d22bSBorislav Petkov x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; 78127f6d22bSBorislav Petkov } 78227f6d22bSBorislav Petkov 78327f6d22bSBorislav Petkov DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 78427f6d22bSBorislav Petkov 78527f6d22bSBorislav Petkov int x86_perf_event_set_period(struct perf_event *event); 78627f6d22bSBorislav Petkov 78727f6d22bSBorislav Petkov /* 78827f6d22bSBorislav Petkov * Generalized hw caching related hw_event table, filled 78927f6d22bSBorislav Petkov * in on a per model basis. A value of 0 means 79027f6d22bSBorislav Petkov * 'not supported', -1 means 'hw_event makes no sense on 79127f6d22bSBorislav Petkov * this CPU', any other value means the raw hw_event 79227f6d22bSBorislav Petkov * ID. 79327f6d22bSBorislav Petkov */ 79427f6d22bSBorislav Petkov 79527f6d22bSBorislav Petkov #define C(x) PERF_COUNT_HW_CACHE_##x 79627f6d22bSBorislav Petkov 79727f6d22bSBorislav Petkov extern u64 __read_mostly hw_cache_event_ids 79827f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 79927f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 80027f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX]; 80127f6d22bSBorislav Petkov extern u64 __read_mostly hw_cache_extra_regs 80227f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 80327f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 80427f6d22bSBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX]; 80527f6d22bSBorislav Petkov 80627f6d22bSBorislav Petkov u64 x86_perf_event_update(struct perf_event *event); 80727f6d22bSBorislav Petkov 80827f6d22bSBorislav Petkov static inline unsigned int x86_pmu_config_addr(int index) 80927f6d22bSBorislav Petkov { 81027f6d22bSBorislav Petkov return x86_pmu.eventsel + (x86_pmu.addr_offset ? 81127f6d22bSBorislav Petkov x86_pmu.addr_offset(index, true) : index); 81227f6d22bSBorislav Petkov } 81327f6d22bSBorislav Petkov 81427f6d22bSBorislav Petkov static inline unsigned int x86_pmu_event_addr(int index) 81527f6d22bSBorislav Petkov { 81627f6d22bSBorislav Petkov return x86_pmu.perfctr + (x86_pmu.addr_offset ? 81727f6d22bSBorislav Petkov x86_pmu.addr_offset(index, false) : index); 81827f6d22bSBorislav Petkov } 81927f6d22bSBorislav Petkov 82027f6d22bSBorislav Petkov static inline int x86_pmu_rdpmc_index(int index) 82127f6d22bSBorislav Petkov { 82227f6d22bSBorislav Petkov return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; 82327f6d22bSBorislav Petkov } 82427f6d22bSBorislav Petkov 82527f6d22bSBorislav Petkov int x86_add_exclusive(unsigned int what); 82627f6d22bSBorislav Petkov 82727f6d22bSBorislav Petkov void x86_del_exclusive(unsigned int what); 82827f6d22bSBorislav Petkov 82927f6d22bSBorislav Petkov int x86_reserve_hardware(void); 83027f6d22bSBorislav Petkov 83127f6d22bSBorislav Petkov void x86_release_hardware(void); 83227f6d22bSBorislav Petkov 833b00233b5SAndi Kleen int x86_pmu_max_precise(void); 834b00233b5SAndi Kleen 83527f6d22bSBorislav Petkov void hw_perf_lbr_event_destroy(struct perf_event *event); 83627f6d22bSBorislav Petkov 83727f6d22bSBorislav Petkov int x86_setup_perfctr(struct perf_event *event); 83827f6d22bSBorislav Petkov 83927f6d22bSBorislav Petkov int x86_pmu_hw_config(struct perf_event *event); 84027f6d22bSBorislav Petkov 84127f6d22bSBorislav Petkov void x86_pmu_disable_all(void); 84227f6d22bSBorislav Petkov 84327f6d22bSBorislav Petkov static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, 84427f6d22bSBorislav Petkov u64 enable_mask) 84527f6d22bSBorislav Petkov { 84627f6d22bSBorislav Petkov u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 84727f6d22bSBorislav Petkov 84827f6d22bSBorislav Petkov if (hwc->extra_reg.reg) 84927f6d22bSBorislav Petkov wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); 85027f6d22bSBorislav Petkov wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 85127f6d22bSBorislav Petkov } 85227f6d22bSBorislav Petkov 85327f6d22bSBorislav Petkov void x86_pmu_enable_all(int added); 85427f6d22bSBorislav Petkov 85527f6d22bSBorislav Petkov int perf_assign_events(struct event_constraint **constraints, int n, 85627f6d22bSBorislav Petkov int wmin, int wmax, int gpmax, int *assign); 85727f6d22bSBorislav Petkov int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); 85827f6d22bSBorislav Petkov 85927f6d22bSBorislav Petkov void x86_pmu_stop(struct perf_event *event, int flags); 86027f6d22bSBorislav Petkov 86127f6d22bSBorislav Petkov static inline void x86_pmu_disable_event(struct perf_event *event) 86227f6d22bSBorislav Petkov { 86327f6d22bSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 86427f6d22bSBorislav Petkov 86527f6d22bSBorislav Petkov wrmsrl(hwc->config_base, hwc->config); 86627f6d22bSBorislav Petkov } 86727f6d22bSBorislav Petkov 86827f6d22bSBorislav Petkov void x86_pmu_enable_event(struct perf_event *event); 86927f6d22bSBorislav Petkov 87027f6d22bSBorislav Petkov int x86_pmu_handle_irq(struct pt_regs *regs); 87127f6d22bSBorislav Petkov 87227f6d22bSBorislav Petkov extern struct event_constraint emptyconstraint; 87327f6d22bSBorislav Petkov 87427f6d22bSBorislav Petkov extern struct event_constraint unconstrained; 87527f6d22bSBorislav Petkov 87627f6d22bSBorislav Petkov static inline bool kernel_ip(unsigned long ip) 87727f6d22bSBorislav Petkov { 87827f6d22bSBorislav Petkov #ifdef CONFIG_X86_32 87927f6d22bSBorislav Petkov return ip > PAGE_OFFSET; 88027f6d22bSBorislav Petkov #else 88127f6d22bSBorislav Petkov return (long)ip < 0; 88227f6d22bSBorislav Petkov #endif 88327f6d22bSBorislav Petkov } 88427f6d22bSBorislav Petkov 88527f6d22bSBorislav Petkov /* 88627f6d22bSBorislav Petkov * Not all PMUs provide the right context information to place the reported IP 88727f6d22bSBorislav Petkov * into full context. Specifically segment registers are typically not 88827f6d22bSBorislav Petkov * supplied. 88927f6d22bSBorislav Petkov * 89027f6d22bSBorislav Petkov * Assuming the address is a linear address (it is for IBS), we fake the CS and 89127f6d22bSBorislav Petkov * vm86 mode using the known zero-based code segment and 'fix up' the registers 89227f6d22bSBorislav Petkov * to reflect this. 89327f6d22bSBorislav Petkov * 89427f6d22bSBorislav Petkov * Intel PEBS/LBR appear to typically provide the effective address, nothing 89527f6d22bSBorislav Petkov * much we can do about that but pray and treat it like a linear address. 89627f6d22bSBorislav Petkov */ 89727f6d22bSBorislav Petkov static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) 89827f6d22bSBorislav Petkov { 89927f6d22bSBorislav Petkov regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; 90027f6d22bSBorislav Petkov if (regs->flags & X86_VM_MASK) 90127f6d22bSBorislav Petkov regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); 90227f6d22bSBorislav Petkov regs->ip = ip; 90327f6d22bSBorislav Petkov } 90427f6d22bSBorislav Petkov 90527f6d22bSBorislav Petkov ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); 90627f6d22bSBorislav Petkov ssize_t intel_event_sysfs_show(char *page, u64 config); 90727f6d22bSBorislav Petkov 90827f6d22bSBorislav Petkov struct attribute **merge_attr(struct attribute **a, struct attribute **b); 90927f6d22bSBorislav Petkov 910a49ac9f8SHuang Rui ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, 911a49ac9f8SHuang Rui char *page); 912fc07e9f9SAndi Kleen ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 913fc07e9f9SAndi Kleen char *page); 914a49ac9f8SHuang Rui 91527f6d22bSBorislav Petkov #ifdef CONFIG_CPU_SUP_AMD 91627f6d22bSBorislav Petkov 91727f6d22bSBorislav Petkov int amd_pmu_init(void); 91827f6d22bSBorislav Petkov 91927f6d22bSBorislav Petkov #else /* CONFIG_CPU_SUP_AMD */ 92027f6d22bSBorislav Petkov 92127f6d22bSBorislav Petkov static inline int amd_pmu_init(void) 92227f6d22bSBorislav Petkov { 92327f6d22bSBorislav Petkov return 0; 92427f6d22bSBorislav Petkov } 92527f6d22bSBorislav Petkov 92627f6d22bSBorislav Petkov #endif /* CONFIG_CPU_SUP_AMD */ 92727f6d22bSBorislav Petkov 92827f6d22bSBorislav Petkov #ifdef CONFIG_CPU_SUP_INTEL 92927f6d22bSBorislav Petkov 93081ec3f3cSJiri Olsa static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period) 93127f6d22bSBorislav Petkov { 93267266c10SJiri Olsa struct hw_perf_event *hwc = &event->hw; 93367266c10SJiri Olsa unsigned int hw_event, bts_event; 93427f6d22bSBorislav Petkov 93567266c10SJiri Olsa if (event->attr.freq) 93627f6d22bSBorislav Petkov return false; 93767266c10SJiri Olsa 93867266c10SJiri Olsa hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 93967266c10SJiri Olsa bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 94067266c10SJiri Olsa 94181ec3f3cSJiri Olsa return hw_event == bts_event && period == 1; 94281ec3f3cSJiri Olsa } 94381ec3f3cSJiri Olsa 94481ec3f3cSJiri Olsa static inline bool intel_pmu_has_bts(struct perf_event *event) 94581ec3f3cSJiri Olsa { 94681ec3f3cSJiri Olsa struct hw_perf_event *hwc = &event->hw; 94781ec3f3cSJiri Olsa 94881ec3f3cSJiri Olsa return intel_pmu_has_bts_period(event, hwc->sample_period); 94927f6d22bSBorislav Petkov } 95027f6d22bSBorislav Petkov 95127f6d22bSBorislav Petkov int intel_pmu_save_and_restart(struct perf_event *event); 95227f6d22bSBorislav Petkov 95327f6d22bSBorislav Petkov struct event_constraint * 95427f6d22bSBorislav Petkov x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 95527f6d22bSBorislav Petkov struct perf_event *event); 95627f6d22bSBorislav Petkov 957d01b1f96SPeter Zijlstra (Intel) extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu); 958d01b1f96SPeter Zijlstra (Intel) extern void intel_cpuc_finish(struct cpu_hw_events *cpuc); 95927f6d22bSBorislav Petkov 96027f6d22bSBorislav Petkov int intel_pmu_init(void); 96127f6d22bSBorislav Petkov 96227f6d22bSBorislav Petkov void init_debug_store_on_cpu(int cpu); 96327f6d22bSBorislav Petkov 96427f6d22bSBorislav Petkov void fini_debug_store_on_cpu(int cpu); 96527f6d22bSBorislav Petkov 96627f6d22bSBorislav Petkov void release_ds_buffers(void); 96727f6d22bSBorislav Petkov 96827f6d22bSBorislav Petkov void reserve_ds_buffers(void); 96927f6d22bSBorislav Petkov 97027f6d22bSBorislav Petkov extern struct event_constraint bts_constraint; 97127f6d22bSBorislav Petkov 97227f6d22bSBorislav Petkov void intel_pmu_enable_bts(u64 config); 97327f6d22bSBorislav Petkov 97427f6d22bSBorislav Petkov void intel_pmu_disable_bts(void); 97527f6d22bSBorislav Petkov 97627f6d22bSBorislav Petkov int intel_pmu_drain_bts_buffer(void); 97727f6d22bSBorislav Petkov 97827f6d22bSBorislav Petkov extern struct event_constraint intel_core2_pebs_event_constraints[]; 97927f6d22bSBorislav Petkov 98027f6d22bSBorislav Petkov extern struct event_constraint intel_atom_pebs_event_constraints[]; 98127f6d22bSBorislav Petkov 98227f6d22bSBorislav Petkov extern struct event_constraint intel_slm_pebs_event_constraints[]; 98327f6d22bSBorislav Petkov 9848b92c3a7SKan Liang extern struct event_constraint intel_glm_pebs_event_constraints[]; 9858b92c3a7SKan Liang 986dd0b06b5SKan Liang extern struct event_constraint intel_glp_pebs_event_constraints[]; 987dd0b06b5SKan Liang 98827f6d22bSBorislav Petkov extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 98927f6d22bSBorislav Petkov 99027f6d22bSBorislav Petkov extern struct event_constraint intel_westmere_pebs_event_constraints[]; 99127f6d22bSBorislav Petkov 99227f6d22bSBorislav Petkov extern struct event_constraint intel_snb_pebs_event_constraints[]; 99327f6d22bSBorislav Petkov 99427f6d22bSBorislav Petkov extern struct event_constraint intel_ivb_pebs_event_constraints[]; 99527f6d22bSBorislav Petkov 99627f6d22bSBorislav Petkov extern struct event_constraint intel_hsw_pebs_event_constraints[]; 99727f6d22bSBorislav Petkov 998b3e62463SStephane Eranian extern struct event_constraint intel_bdw_pebs_event_constraints[]; 999b3e62463SStephane Eranian 100027f6d22bSBorislav Petkov extern struct event_constraint intel_skl_pebs_event_constraints[]; 100127f6d22bSBorislav Petkov 100260176089SKan Liang extern struct event_constraint intel_icl_pebs_event_constraints[]; 100360176089SKan Liang 100427f6d22bSBorislav Petkov struct event_constraint *intel_pebs_constraints(struct perf_event *event); 100527f6d22bSBorislav Petkov 100668f7082fSPeter Zijlstra void intel_pmu_pebs_add(struct perf_event *event); 100768f7082fSPeter Zijlstra 100868f7082fSPeter Zijlstra void intel_pmu_pebs_del(struct perf_event *event); 100968f7082fSPeter Zijlstra 101027f6d22bSBorislav Petkov void intel_pmu_pebs_enable(struct perf_event *event); 101127f6d22bSBorislav Petkov 101227f6d22bSBorislav Petkov void intel_pmu_pebs_disable(struct perf_event *event); 101327f6d22bSBorislav Petkov 101427f6d22bSBorislav Petkov void intel_pmu_pebs_enable_all(void); 101527f6d22bSBorislav Petkov 101627f6d22bSBorislav Petkov void intel_pmu_pebs_disable_all(void); 101727f6d22bSBorislav Petkov 101827f6d22bSBorislav Petkov void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in); 101927f6d22bSBorislav Petkov 10205bee2cc6SKan Liang void intel_pmu_auto_reload_read(struct perf_event *event); 10215bee2cc6SKan Liang 1022c22497f5SKan Liang void intel_pmu_store_pebs_lbrs(struct pebs_lbr *lbr); 1023c22497f5SKan Liang 102427f6d22bSBorislav Petkov void intel_ds_init(void); 102527f6d22bSBorislav Petkov 102627f6d22bSBorislav Petkov void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in); 102727f6d22bSBorislav Petkov 102819fc9dddSDavid Carrillo-Cisneros u64 lbr_from_signext_quirk_wr(u64 val); 102919fc9dddSDavid Carrillo-Cisneros 103027f6d22bSBorislav Petkov void intel_pmu_lbr_reset(void); 103127f6d22bSBorislav Petkov 103268f7082fSPeter Zijlstra void intel_pmu_lbr_add(struct perf_event *event); 103327f6d22bSBorislav Petkov 103468f7082fSPeter Zijlstra void intel_pmu_lbr_del(struct perf_event *event); 103527f6d22bSBorislav Petkov 103627f6d22bSBorislav Petkov void intel_pmu_lbr_enable_all(bool pmi); 103727f6d22bSBorislav Petkov 103827f6d22bSBorislav Petkov void intel_pmu_lbr_disable_all(void); 103927f6d22bSBorislav Petkov 104027f6d22bSBorislav Petkov void intel_pmu_lbr_read(void); 104127f6d22bSBorislav Petkov 104227f6d22bSBorislav Petkov void intel_pmu_lbr_init_core(void); 104327f6d22bSBorislav Petkov 104427f6d22bSBorislav Petkov void intel_pmu_lbr_init_nhm(void); 104527f6d22bSBorislav Petkov 104627f6d22bSBorislav Petkov void intel_pmu_lbr_init_atom(void); 104727f6d22bSBorislav Petkov 1048f21d5adcSKan Liang void intel_pmu_lbr_init_slm(void); 1049f21d5adcSKan Liang 105027f6d22bSBorislav Petkov void intel_pmu_lbr_init_snb(void); 105127f6d22bSBorislav Petkov 105227f6d22bSBorislav Petkov void intel_pmu_lbr_init_hsw(void); 105327f6d22bSBorislav Petkov 105427f6d22bSBorislav Petkov void intel_pmu_lbr_init_skl(void); 105527f6d22bSBorislav Petkov 105627f6d22bSBorislav Petkov void intel_pmu_lbr_init_knl(void); 105727f6d22bSBorislav Petkov 1058e17dc653SAndi Kleen void intel_pmu_pebs_data_source_nhm(void); 1059e17dc653SAndi Kleen 10606ae5fa61SAndi Kleen void intel_pmu_pebs_data_source_skl(bool pmem); 10616ae5fa61SAndi Kleen 106227f6d22bSBorislav Petkov int intel_pmu_setup_lbr_filter(struct perf_event *event); 106327f6d22bSBorislav Petkov 106427f6d22bSBorislav Petkov void intel_pt_interrupt(void); 106527f6d22bSBorislav Petkov 106627f6d22bSBorislav Petkov int intel_bts_interrupt(void); 106727f6d22bSBorislav Petkov 106827f6d22bSBorislav Petkov void intel_bts_enable_local(void); 106927f6d22bSBorislav Petkov 107027f6d22bSBorislav Petkov void intel_bts_disable_local(void); 107127f6d22bSBorislav Petkov 107227f6d22bSBorislav Petkov int p4_pmu_init(void); 107327f6d22bSBorislav Petkov 107427f6d22bSBorislav Petkov int p6_pmu_init(void); 107527f6d22bSBorislav Petkov 107627f6d22bSBorislav Petkov int knc_pmu_init(void); 107727f6d22bSBorislav Petkov 107827f6d22bSBorislav Petkov static inline int is_ht_workaround_enabled(void) 107927f6d22bSBorislav Petkov { 108027f6d22bSBorislav Petkov return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); 108127f6d22bSBorislav Petkov } 108227f6d22bSBorislav Petkov 108327f6d22bSBorislav Petkov #else /* CONFIG_CPU_SUP_INTEL */ 108427f6d22bSBorislav Petkov 108527f6d22bSBorislav Petkov static inline void reserve_ds_buffers(void) 108627f6d22bSBorislav Petkov { 108727f6d22bSBorislav Petkov } 108827f6d22bSBorislav Petkov 108927f6d22bSBorislav Petkov static inline void release_ds_buffers(void) 109027f6d22bSBorislav Petkov { 109127f6d22bSBorislav Petkov } 109227f6d22bSBorislav Petkov 109327f6d22bSBorislav Petkov static inline int intel_pmu_init(void) 109427f6d22bSBorislav Petkov { 109527f6d22bSBorislav Petkov return 0; 109627f6d22bSBorislav Petkov } 109727f6d22bSBorislav Petkov 1098f764c58bSPeter Zijlstra static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 109927f6d22bSBorislav Petkov { 1100d01b1f96SPeter Zijlstra (Intel) return 0; 1101d01b1f96SPeter Zijlstra (Intel) } 1102d01b1f96SPeter Zijlstra (Intel) 1103f764c58bSPeter Zijlstra static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc) 1104d01b1f96SPeter Zijlstra (Intel) { 110527f6d22bSBorislav Petkov } 110627f6d22bSBorislav Petkov 110727f6d22bSBorislav Petkov static inline int is_ht_workaround_enabled(void) 110827f6d22bSBorislav Petkov { 110927f6d22bSBorislav Petkov return 0; 111027f6d22bSBorislav Petkov } 111127f6d22bSBorislav Petkov #endif /* CONFIG_CPU_SUP_INTEL */ 1112