1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/perf_event.h> 3 #include <linux/sysfs.h> 4 #include <linux/nospec.h> 5 #include <asm/msr.h> 6 7 #include "probe.h" 8 9 enum perf_msr_id { 10 PERF_MSR_TSC = 0, 11 PERF_MSR_APERF = 1, 12 PERF_MSR_MPERF = 2, 13 PERF_MSR_PPERF = 3, 14 PERF_MSR_SMI = 4, 15 PERF_MSR_PTSC = 5, 16 PERF_MSR_IRPERF = 6, 17 PERF_MSR_THERM = 7, 18 PERF_MSR_EVENT_MAX, 19 }; 20 21 static bool test_aperfmperf(int idx, void *data) 22 { 23 return boot_cpu_has(X86_FEATURE_APERFMPERF); 24 } 25 26 static bool test_ptsc(int idx, void *data) 27 { 28 return boot_cpu_has(X86_FEATURE_PTSC); 29 } 30 31 static bool test_irperf(int idx, void *data) 32 { 33 return boot_cpu_has(X86_FEATURE_IRPERF); 34 } 35 36 static bool test_therm_status(int idx, void *data) 37 { 38 return boot_cpu_has(X86_FEATURE_DTHERM); 39 } 40 41 static bool test_intel(int idx, void *data) 42 { 43 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 44 return false; 45 46 /* Rely on perf_msr_probe() to check the availability */ 47 return true; 48 } 49 50 PMU_EVENT_ATTR_STRING(tsc, attr_tsc, "event=0x00" ); 51 PMU_EVENT_ATTR_STRING(aperf, attr_aperf, "event=0x01" ); 52 PMU_EVENT_ATTR_STRING(mperf, attr_mperf, "event=0x02" ); 53 PMU_EVENT_ATTR_STRING(pperf, attr_pperf, "event=0x03" ); 54 PMU_EVENT_ATTR_STRING(smi, attr_smi, "event=0x04" ); 55 PMU_EVENT_ATTR_STRING(ptsc, attr_ptsc, "event=0x05" ); 56 PMU_EVENT_ATTR_STRING(irperf, attr_irperf, "event=0x06" ); 57 PMU_EVENT_ATTR_STRING(cpu_thermal_margin, attr_therm, "event=0x07" ); 58 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot, attr_therm_snap, "1" ); 59 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit, attr_therm_unit, "C" ); 60 61 static unsigned long msr_mask; 62 63 PMU_EVENT_GROUP(events, aperf); 64 PMU_EVENT_GROUP(events, mperf); 65 PMU_EVENT_GROUP(events, pperf); 66 PMU_EVENT_GROUP(events, smi); 67 PMU_EVENT_GROUP(events, ptsc); 68 PMU_EVENT_GROUP(events, irperf); 69 70 static struct attribute *attrs_therm[] = { 71 &attr_therm.attr.attr, 72 &attr_therm_snap.attr.attr, 73 &attr_therm_unit.attr.attr, 74 NULL, 75 }; 76 77 static struct attribute_group group_therm = { 78 .name = "events", 79 .attrs = attrs_therm, 80 }; 81 82 static struct perf_msr msr[] = { 83 [PERF_MSR_TSC] = { .no_check = true, }, 84 [PERF_MSR_APERF] = { MSR_IA32_APERF, &group_aperf, test_aperfmperf, }, 85 [PERF_MSR_MPERF] = { MSR_IA32_MPERF, &group_mperf, test_aperfmperf, }, 86 [PERF_MSR_PPERF] = { MSR_PPERF, &group_pperf, test_intel, }, 87 [PERF_MSR_SMI] = { MSR_SMI_COUNT, &group_smi, test_intel, }, 88 [PERF_MSR_PTSC] = { MSR_F15H_PTSC, &group_ptsc, test_ptsc, }, 89 [PERF_MSR_IRPERF] = { MSR_F17H_IRPERF, &group_irperf, test_irperf, }, 90 [PERF_MSR_THERM] = { MSR_IA32_THERM_STATUS, &group_therm, test_therm_status, }, 91 }; 92 93 static struct attribute *events_attrs[] = { 94 &attr_tsc.attr.attr, 95 NULL, 96 }; 97 98 static struct attribute_group events_attr_group = { 99 .name = "events", 100 .attrs = events_attrs, 101 }; 102 103 PMU_FORMAT_ATTR(event, "config:0-63"); 104 static struct attribute *format_attrs[] = { 105 &format_attr_event.attr, 106 NULL, 107 }; 108 static struct attribute_group format_attr_group = { 109 .name = "format", 110 .attrs = format_attrs, 111 }; 112 113 static const struct attribute_group *attr_groups[] = { 114 &events_attr_group, 115 &format_attr_group, 116 NULL, 117 }; 118 119 static const struct attribute_group *attr_update[] = { 120 &group_aperf, 121 &group_mperf, 122 &group_pperf, 123 &group_smi, 124 &group_ptsc, 125 &group_irperf, 126 &group_therm, 127 NULL, 128 }; 129 130 static int msr_event_init(struct perf_event *event) 131 { 132 u64 cfg = event->attr.config; 133 134 if (event->attr.type != event->pmu->type) 135 return -ENOENT; 136 137 /* unsupported modes and filters */ 138 if (event->attr.sample_period) /* no sampling */ 139 return -EINVAL; 140 141 if (cfg >= PERF_MSR_EVENT_MAX) 142 return -EINVAL; 143 144 cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX); 145 146 if (!(msr_mask & (1 << cfg))) 147 return -EINVAL; 148 149 event->hw.idx = -1; 150 event->hw.event_base = msr[cfg].msr; 151 event->hw.config = cfg; 152 153 return 0; 154 } 155 156 static inline u64 msr_read_counter(struct perf_event *event) 157 { 158 u64 now; 159 160 if (event->hw.event_base) 161 rdmsrq(event->hw.event_base, now); 162 else 163 now = rdtsc_ordered(); 164 165 return now; 166 } 167 168 static void msr_event_update(struct perf_event *event) 169 { 170 u64 prev, now; 171 s64 delta; 172 173 /* Careful, an NMI might modify the previous event value: */ 174 prev = local64_read(&event->hw.prev_count); 175 do { 176 now = msr_read_counter(event); 177 } while (!local64_try_cmpxchg(&event->hw.prev_count, &prev, now)); 178 179 delta = now - prev; 180 if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) { 181 delta = sign_extend64(delta, 31); 182 local64_add(delta, &event->count); 183 } else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) { 184 /* If valid, extract digital readout, otherwise set to -1: */ 185 now = now & (1ULL << 31) ? (now >> 16) & 0x3f : -1; 186 local64_set(&event->count, now); 187 } else { 188 local64_add(delta, &event->count); 189 } 190 } 191 192 static void msr_event_start(struct perf_event *event, int flags) 193 { 194 u64 now = msr_read_counter(event); 195 196 local64_set(&event->hw.prev_count, now); 197 } 198 199 static void msr_event_stop(struct perf_event *event, int flags) 200 { 201 msr_event_update(event); 202 } 203 204 static void msr_event_del(struct perf_event *event, int flags) 205 { 206 msr_event_stop(event, PERF_EF_UPDATE); 207 } 208 209 static int msr_event_add(struct perf_event *event, int flags) 210 { 211 if (flags & PERF_EF_START) 212 msr_event_start(event, flags); 213 214 return 0; 215 } 216 217 static struct pmu pmu_msr = { 218 .task_ctx_nr = perf_sw_context, 219 .attr_groups = attr_groups, 220 .event_init = msr_event_init, 221 .add = msr_event_add, 222 .del = msr_event_del, 223 .start = msr_event_start, 224 .stop = msr_event_stop, 225 .read = msr_event_update, 226 .capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, 227 .attr_update = attr_update, 228 }; 229 230 static int __init msr_init(void) 231 { 232 if (!boot_cpu_has(X86_FEATURE_TSC)) { 233 pr_cont("no MSR PMU driver.\n"); 234 return 0; 235 } 236 237 msr_mask = perf_msr_probe(msr, PERF_MSR_EVENT_MAX, true, NULL); 238 239 perf_pmu_register(&pmu_msr, "msr", -1); 240 241 return 0; 242 } 243 device_initcall(msr_init); 244