1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #include <linux/slab.h> 3 #include <linux/pci.h> 4 #include <asm/apicdef.h> 5 #include <linux/io-64-nonatomic-lo-hi.h> 6 7 #include <linux/perf_event.h> 8 #include "../perf_event.h" 9 10 #define UNCORE_PMU_NAME_LEN 32 11 #define UNCORE_PMU_HRTIMER_INTERVAL (60LL * NSEC_PER_SEC) 12 #define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC) 13 14 #define UNCORE_FIXED_EVENT 0xff 15 #define UNCORE_PMC_IDX_MAX_GENERIC 8 16 #define UNCORE_PMC_IDX_MAX_FIXED 1 17 #define UNCORE_PMC_IDX_MAX_FREERUNNING 1 18 #define UNCORE_PMC_IDX_FIXED UNCORE_PMC_IDX_MAX_GENERIC 19 #define UNCORE_PMC_IDX_FREERUNNING (UNCORE_PMC_IDX_FIXED + \ 20 UNCORE_PMC_IDX_MAX_FIXED) 21 #define UNCORE_PMC_IDX_MAX (UNCORE_PMC_IDX_FREERUNNING + \ 22 UNCORE_PMC_IDX_MAX_FREERUNNING) 23 24 #define UNCORE_PCI_DEV_FULL_DATA(dev, func, type, idx) \ 25 ((dev << 24) | (func << 16) | (type << 8) | idx) 26 #define UNCORE_PCI_DEV_DATA(type, idx) ((type << 8) | idx) 27 #define UNCORE_PCI_DEV_DEV(data) ((data >> 24) & 0xff) 28 #define UNCORE_PCI_DEV_FUNC(data) ((data >> 16) & 0xff) 29 #define UNCORE_PCI_DEV_TYPE(data) ((data >> 8) & 0xff) 30 #define UNCORE_PCI_DEV_IDX(data) (data & 0xff) 31 #define UNCORE_EXTRA_PCI_DEV 0xff 32 #define UNCORE_EXTRA_PCI_DEV_MAX 4 33 34 #define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff) 35 36 struct pci_extra_dev { 37 struct pci_dev *dev[UNCORE_EXTRA_PCI_DEV_MAX]; 38 }; 39 40 struct intel_uncore_ops; 41 struct intel_uncore_pmu; 42 struct intel_uncore_box; 43 struct uncore_event_desc; 44 struct freerunning_counters; 45 struct intel_uncore_topology; 46 47 struct intel_uncore_type { 48 const char *name; 49 int num_counters; 50 int num_boxes; 51 int perf_ctr_bits; 52 int fixed_ctr_bits; 53 int num_freerunning_types; 54 int type_id; 55 unsigned perf_ctr; 56 unsigned event_ctl; 57 unsigned event_mask; 58 unsigned event_mask_ext; 59 unsigned fixed_ctr; 60 unsigned fixed_ctl; 61 unsigned box_ctl; 62 u64 *box_ctls; /* Unit ctrl addr of the first box of each die */ 63 union { 64 unsigned msr_offset; 65 unsigned mmio_offset; 66 }; 67 unsigned mmio_map_size; 68 unsigned num_shared_regs:8; 69 unsigned single_fixed:1; 70 unsigned pair_ctr_ctl:1; 71 union { 72 unsigned *msr_offsets; 73 unsigned *pci_offsets; 74 unsigned *mmio_offsets; 75 }; 76 unsigned *box_ids; 77 struct event_constraint unconstrainted; 78 struct event_constraint *constraints; 79 struct intel_uncore_pmu *pmus; 80 struct intel_uncore_ops *ops; 81 struct uncore_event_desc *event_descs; 82 struct freerunning_counters *freerunning; 83 const struct attribute_group *attr_groups[4]; 84 const struct attribute_group **attr_update; 85 struct pmu *pmu; /* for custom pmu ops */ 86 /* 87 * Uncore PMU would store relevant platform topology configuration here 88 * to identify which platform component each PMON block of that type is 89 * supposed to monitor. 90 */ 91 struct intel_uncore_topology *topology; 92 /* 93 * Optional callbacks for managing mapping of Uncore units to PMONs 94 */ 95 int (*set_mapping)(struct intel_uncore_type *type); 96 void (*cleanup_mapping)(struct intel_uncore_type *type); 97 }; 98 99 #define pmu_group attr_groups[0] 100 #define format_group attr_groups[1] 101 #define events_group attr_groups[2] 102 103 struct intel_uncore_ops { 104 void (*init_box)(struct intel_uncore_box *); 105 void (*exit_box)(struct intel_uncore_box *); 106 void (*disable_box)(struct intel_uncore_box *); 107 void (*enable_box)(struct intel_uncore_box *); 108 void (*disable_event)(struct intel_uncore_box *, struct perf_event *); 109 void (*enable_event)(struct intel_uncore_box *, struct perf_event *); 110 u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *); 111 int (*hw_config)(struct intel_uncore_box *, struct perf_event *); 112 struct event_constraint *(*get_constraint)(struct intel_uncore_box *, 113 struct perf_event *); 114 void (*put_constraint)(struct intel_uncore_box *, struct perf_event *); 115 }; 116 117 struct intel_uncore_pmu { 118 struct pmu pmu; 119 char name[UNCORE_PMU_NAME_LEN]; 120 int pmu_idx; 121 int func_id; 122 bool registered; 123 atomic_t activeboxes; 124 struct intel_uncore_type *type; 125 struct intel_uncore_box **boxes; 126 }; 127 128 struct intel_uncore_extra_reg { 129 raw_spinlock_t lock; 130 u64 config, config1, config2; 131 atomic_t ref; 132 }; 133 134 struct intel_uncore_box { 135 int dieid; /* Logical die ID */ 136 int n_active; /* number of active events */ 137 int n_events; 138 int cpu; /* cpu to collect events */ 139 unsigned long flags; 140 atomic_t refcnt; 141 struct perf_event *events[UNCORE_PMC_IDX_MAX]; 142 struct perf_event *event_list[UNCORE_PMC_IDX_MAX]; 143 struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX]; 144 unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)]; 145 u64 tags[UNCORE_PMC_IDX_MAX]; 146 struct pci_dev *pci_dev; 147 struct intel_uncore_pmu *pmu; 148 u64 hrtimer_duration; /* hrtimer timeout for this box */ 149 struct hrtimer hrtimer; 150 struct list_head list; 151 struct list_head active_list; 152 void __iomem *io_addr; 153 struct intel_uncore_extra_reg shared_regs[]; 154 }; 155 156 /* CFL uncore 8th cbox MSRs */ 157 #define CFL_UNC_CBO_7_PERFEVTSEL0 0xf70 158 #define CFL_UNC_CBO_7_PER_CTR0 0xf76 159 160 #define UNCORE_BOX_FLAG_INITIATED 0 161 /* event config registers are 8-byte apart */ 162 #define UNCORE_BOX_FLAG_CTL_OFFS8 1 163 /* CFL 8th CBOX has different MSR space */ 164 #define UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS 2 165 166 struct uncore_event_desc { 167 struct device_attribute attr; 168 const char *config; 169 }; 170 171 struct freerunning_counters { 172 unsigned int counter_base; 173 unsigned int counter_offset; 174 unsigned int box_offset; 175 unsigned int num_counters; 176 unsigned int bits; 177 unsigned *box_offsets; 178 }; 179 180 struct intel_uncore_topology { 181 u64 configuration; 182 int segment; 183 }; 184 185 struct pci2phy_map { 186 struct list_head list; 187 int segment; 188 int pbus_to_dieid[256]; 189 }; 190 191 struct pci2phy_map *__find_pci2phy_map(int segment); 192 int uncore_pcibus_to_dieid(struct pci_bus *bus); 193 int uncore_die_to_segment(int die); 194 195 ssize_t uncore_event_show(struct device *dev, 196 struct device_attribute *attr, char *buf); 197 198 static inline struct intel_uncore_pmu *dev_to_uncore_pmu(struct device *dev) 199 { 200 return container_of(dev_get_drvdata(dev), struct intel_uncore_pmu, pmu); 201 } 202 203 #define to_device_attribute(n) container_of(n, struct device_attribute, attr) 204 #define to_dev_ext_attribute(n) container_of(n, struct dev_ext_attribute, attr) 205 #define attr_to_ext_attr(n) to_dev_ext_attribute(to_device_attribute(n)) 206 207 extern int __uncore_max_dies; 208 #define uncore_max_dies() (__uncore_max_dies) 209 210 #define INTEL_UNCORE_EVENT_DESC(_name, _config) \ 211 { \ 212 .attr = __ATTR(_name, 0444, uncore_event_show, NULL), \ 213 .config = _config, \ 214 } 215 216 #define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format) \ 217 static ssize_t __uncore_##_var##_show(struct device *dev, \ 218 struct device_attribute *attr, \ 219 char *page) \ 220 { \ 221 BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \ 222 return sprintf(page, _format "\n"); \ 223 } \ 224 static struct device_attribute format_attr_##_var = \ 225 __ATTR(_name, 0444, __uncore_##_var##_show, NULL) 226 227 static inline bool uncore_pmc_fixed(int idx) 228 { 229 return idx == UNCORE_PMC_IDX_FIXED; 230 } 231 232 static inline bool uncore_pmc_freerunning(int idx) 233 { 234 return idx == UNCORE_PMC_IDX_FREERUNNING; 235 } 236 237 static inline bool uncore_mmio_is_valid_offset(struct intel_uncore_box *box, 238 unsigned long offset) 239 { 240 if (offset < box->pmu->type->mmio_map_size) 241 return true; 242 243 pr_warn_once("perf uncore: Invalid offset 0x%lx exceeds mapped area of %s.\n", 244 offset, box->pmu->type->name); 245 246 return false; 247 } 248 249 static inline 250 unsigned int uncore_mmio_box_ctl(struct intel_uncore_box *box) 251 { 252 return box->pmu->type->box_ctl + 253 box->pmu->type->mmio_offset * box->pmu->pmu_idx; 254 } 255 256 static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box) 257 { 258 return box->pmu->type->box_ctl; 259 } 260 261 static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box) 262 { 263 return box->pmu->type->fixed_ctl; 264 } 265 266 static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box) 267 { 268 return box->pmu->type->fixed_ctr; 269 } 270 271 static inline 272 unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx) 273 { 274 if (test_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags)) 275 return idx * 8 + box->pmu->type->event_ctl; 276 277 return idx * 4 + box->pmu->type->event_ctl; 278 } 279 280 static inline 281 unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx) 282 { 283 return idx * 8 + box->pmu->type->perf_ctr; 284 } 285 286 static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box) 287 { 288 struct intel_uncore_pmu *pmu = box->pmu; 289 return pmu->type->msr_offsets ? 290 pmu->type->msr_offsets[pmu->pmu_idx] : 291 pmu->type->msr_offset * pmu->pmu_idx; 292 } 293 294 static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box) 295 { 296 if (!box->pmu->type->box_ctl) 297 return 0; 298 return box->pmu->type->box_ctl + uncore_msr_box_offset(box); 299 } 300 301 static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box) 302 { 303 if (!box->pmu->type->fixed_ctl) 304 return 0; 305 return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box); 306 } 307 308 static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box) 309 { 310 return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box); 311 } 312 313 314 /* 315 * In the uncore document, there is no event-code assigned to free running 316 * counters. Some events need to be defined to indicate the free running 317 * counters. The events are encoded as event-code + umask-code. 318 * 319 * The event-code for all free running counters is 0xff, which is the same as 320 * the fixed counters. 321 * 322 * The umask-code is used to distinguish a fixed counter and a free running 323 * counter, and different types of free running counters. 324 * - For fixed counters, the umask-code is 0x0X. 325 * X indicates the index of the fixed counter, which starts from 0. 326 * - For free running counters, the umask-code uses the rest of the space. 327 * It would bare the format of 0xXY. 328 * X stands for the type of free running counters, which starts from 1. 329 * Y stands for the index of free running counters of same type, which 330 * starts from 0. 331 * 332 * For example, there are three types of IIO free running counters on Skylake 333 * server, IO CLOCKS counters, BANDWIDTH counters and UTILIZATION counters. 334 * The event-code for all the free running counters is 0xff. 335 * 'ioclk' is the first counter of IO CLOCKS. IO CLOCKS is the first type, 336 * which umask-code starts from 0x10. 337 * So 'ioclk' is encoded as event=0xff,umask=0x10 338 * 'bw_in_port2' is the third counter of BANDWIDTH counters. BANDWIDTH is 339 * the second type, which umask-code starts from 0x20. 340 * So 'bw_in_port2' is encoded as event=0xff,umask=0x22 341 */ 342 static inline unsigned int uncore_freerunning_idx(u64 config) 343 { 344 return ((config >> 8) & 0xf); 345 } 346 347 #define UNCORE_FREERUNNING_UMASK_START 0x10 348 349 static inline unsigned int uncore_freerunning_type(u64 config) 350 { 351 return ((((config >> 8) - UNCORE_FREERUNNING_UMASK_START) >> 4) & 0xf); 352 } 353 354 static inline 355 unsigned int uncore_freerunning_counter(struct intel_uncore_box *box, 356 struct perf_event *event) 357 { 358 unsigned int type = uncore_freerunning_type(event->hw.config); 359 unsigned int idx = uncore_freerunning_idx(event->hw.config); 360 struct intel_uncore_pmu *pmu = box->pmu; 361 362 return pmu->type->freerunning[type].counter_base + 363 pmu->type->freerunning[type].counter_offset * idx + 364 (pmu->type->freerunning[type].box_offsets ? 365 pmu->type->freerunning[type].box_offsets[pmu->pmu_idx] : 366 pmu->type->freerunning[type].box_offset * pmu->pmu_idx); 367 } 368 369 static inline 370 unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx) 371 { 372 if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) { 373 return CFL_UNC_CBO_7_PERFEVTSEL0 + 374 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx); 375 } else { 376 return box->pmu->type->event_ctl + 377 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) + 378 uncore_msr_box_offset(box); 379 } 380 } 381 382 static inline 383 unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx) 384 { 385 if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) { 386 return CFL_UNC_CBO_7_PER_CTR0 + 387 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx); 388 } else { 389 return box->pmu->type->perf_ctr + 390 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) + 391 uncore_msr_box_offset(box); 392 } 393 } 394 395 static inline 396 unsigned uncore_fixed_ctl(struct intel_uncore_box *box) 397 { 398 if (box->pci_dev || box->io_addr) 399 return uncore_pci_fixed_ctl(box); 400 else 401 return uncore_msr_fixed_ctl(box); 402 } 403 404 static inline 405 unsigned uncore_fixed_ctr(struct intel_uncore_box *box) 406 { 407 if (box->pci_dev || box->io_addr) 408 return uncore_pci_fixed_ctr(box); 409 else 410 return uncore_msr_fixed_ctr(box); 411 } 412 413 static inline 414 unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx) 415 { 416 if (box->pci_dev || box->io_addr) 417 return uncore_pci_event_ctl(box, idx); 418 else 419 return uncore_msr_event_ctl(box, idx); 420 } 421 422 static inline 423 unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx) 424 { 425 if (box->pci_dev || box->io_addr) 426 return uncore_pci_perf_ctr(box, idx); 427 else 428 return uncore_msr_perf_ctr(box, idx); 429 } 430 431 static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box) 432 { 433 return box->pmu->type->perf_ctr_bits; 434 } 435 436 static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box) 437 { 438 return box->pmu->type->fixed_ctr_bits; 439 } 440 441 static inline 442 unsigned int uncore_freerunning_bits(struct intel_uncore_box *box, 443 struct perf_event *event) 444 { 445 unsigned int type = uncore_freerunning_type(event->hw.config); 446 447 return box->pmu->type->freerunning[type].bits; 448 } 449 450 static inline int uncore_num_freerunning(struct intel_uncore_box *box, 451 struct perf_event *event) 452 { 453 unsigned int type = uncore_freerunning_type(event->hw.config); 454 455 return box->pmu->type->freerunning[type].num_counters; 456 } 457 458 static inline int uncore_num_freerunning_types(struct intel_uncore_box *box, 459 struct perf_event *event) 460 { 461 return box->pmu->type->num_freerunning_types; 462 } 463 464 static inline bool check_valid_freerunning_event(struct intel_uncore_box *box, 465 struct perf_event *event) 466 { 467 unsigned int type = uncore_freerunning_type(event->hw.config); 468 unsigned int idx = uncore_freerunning_idx(event->hw.config); 469 470 return (type < uncore_num_freerunning_types(box, event)) && 471 (idx < uncore_num_freerunning(box, event)); 472 } 473 474 static inline int uncore_num_counters(struct intel_uncore_box *box) 475 { 476 return box->pmu->type->num_counters; 477 } 478 479 static inline bool is_freerunning_event(struct perf_event *event) 480 { 481 u64 cfg = event->attr.config; 482 483 return ((cfg & UNCORE_FIXED_EVENT) == UNCORE_FIXED_EVENT) && 484 (((cfg >> 8) & 0xff) >= UNCORE_FREERUNNING_UMASK_START); 485 } 486 487 /* Check and reject invalid config */ 488 static inline int uncore_freerunning_hw_config(struct intel_uncore_box *box, 489 struct perf_event *event) 490 { 491 if (is_freerunning_event(event)) 492 return 0; 493 494 return -EINVAL; 495 } 496 497 static inline void uncore_disable_event(struct intel_uncore_box *box, 498 struct perf_event *event) 499 { 500 box->pmu->type->ops->disable_event(box, event); 501 } 502 503 static inline void uncore_enable_event(struct intel_uncore_box *box, 504 struct perf_event *event) 505 { 506 box->pmu->type->ops->enable_event(box, event); 507 } 508 509 static inline u64 uncore_read_counter(struct intel_uncore_box *box, 510 struct perf_event *event) 511 { 512 return box->pmu->type->ops->read_counter(box, event); 513 } 514 515 static inline void uncore_box_init(struct intel_uncore_box *box) 516 { 517 if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) { 518 if (box->pmu->type->ops->init_box) 519 box->pmu->type->ops->init_box(box); 520 } 521 } 522 523 static inline void uncore_box_exit(struct intel_uncore_box *box) 524 { 525 if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) { 526 if (box->pmu->type->ops->exit_box) 527 box->pmu->type->ops->exit_box(box); 528 } 529 } 530 531 static inline bool uncore_box_is_fake(struct intel_uncore_box *box) 532 { 533 return (box->dieid < 0); 534 } 535 536 static inline struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event) 537 { 538 return container_of(event->pmu, struct intel_uncore_pmu, pmu); 539 } 540 541 static inline struct intel_uncore_box *uncore_event_to_box(struct perf_event *event) 542 { 543 return event->pmu_private; 544 } 545 546 struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu); 547 u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event); 548 void uncore_mmio_exit_box(struct intel_uncore_box *box); 549 u64 uncore_mmio_read_counter(struct intel_uncore_box *box, 550 struct perf_event *event); 551 void uncore_pmu_start_hrtimer(struct intel_uncore_box *box); 552 void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box); 553 void uncore_pmu_event_start(struct perf_event *event, int flags); 554 void uncore_pmu_event_stop(struct perf_event *event, int flags); 555 int uncore_pmu_event_add(struct perf_event *event, int flags); 556 void uncore_pmu_event_del(struct perf_event *event, int flags); 557 void uncore_pmu_event_read(struct perf_event *event); 558 void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event); 559 struct event_constraint * 560 uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event); 561 void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event); 562 u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx); 563 564 extern struct intel_uncore_type *empty_uncore[]; 565 extern struct intel_uncore_type **uncore_msr_uncores; 566 extern struct intel_uncore_type **uncore_pci_uncores; 567 extern struct intel_uncore_type **uncore_mmio_uncores; 568 extern struct pci_driver *uncore_pci_driver; 569 extern struct pci_driver *uncore_pci_sub_driver; 570 extern raw_spinlock_t pci2phy_map_lock; 571 extern struct list_head pci2phy_map_head; 572 extern struct pci_extra_dev *uncore_extra_pci_dev; 573 extern struct event_constraint uncore_constraint_empty; 574 575 /* uncore_snb.c */ 576 int snb_uncore_pci_init(void); 577 int ivb_uncore_pci_init(void); 578 int hsw_uncore_pci_init(void); 579 int bdw_uncore_pci_init(void); 580 int skl_uncore_pci_init(void); 581 void snb_uncore_cpu_init(void); 582 void nhm_uncore_cpu_init(void); 583 void skl_uncore_cpu_init(void); 584 void icl_uncore_cpu_init(void); 585 void adl_uncore_cpu_init(void); 586 void tgl_uncore_cpu_init(void); 587 void tgl_uncore_mmio_init(void); 588 void tgl_l_uncore_mmio_init(void); 589 int snb_pci2phy_map_init(int devid); 590 591 /* uncore_snbep.c */ 592 int snbep_uncore_pci_init(void); 593 void snbep_uncore_cpu_init(void); 594 int ivbep_uncore_pci_init(void); 595 void ivbep_uncore_cpu_init(void); 596 int hswep_uncore_pci_init(void); 597 void hswep_uncore_cpu_init(void); 598 int bdx_uncore_pci_init(void); 599 void bdx_uncore_cpu_init(void); 600 int knl_uncore_pci_init(void); 601 void knl_uncore_cpu_init(void); 602 int skx_uncore_pci_init(void); 603 void skx_uncore_cpu_init(void); 604 int snr_uncore_pci_init(void); 605 void snr_uncore_cpu_init(void); 606 void snr_uncore_mmio_init(void); 607 int icx_uncore_pci_init(void); 608 void icx_uncore_cpu_init(void); 609 void icx_uncore_mmio_init(void); 610 611 /* uncore_nhmex.c */ 612 void nhmex_uncore_cpu_init(void); 613