1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Intel(R) Processor Trace PMU driver for perf 4 * Copyright (c) 2013-2014, Intel Corporation. 5 * 6 * Intel PT is specified in the Intel Architecture Instruction Set Extensions 7 * Programming Reference: 8 * http://software.intel.com/en-us/intel-isa-extensions 9 */ 10 11 #ifndef __INTEL_PT_H__ 12 #define __INTEL_PT_H__ 13 14 /* 15 * Single-entry ToPA: when this close to region boundary, switch 16 * buffers to avoid losing data. 17 */ 18 #define TOPA_PMI_MARGIN 512 19 20 #define TOPA_SHIFT 12 21 22 static inline unsigned int sizes(unsigned int tsz) 23 { 24 return 1 << (tsz + TOPA_SHIFT); 25 }; 26 27 struct topa_entry { 28 u64 end : 1; 29 u64 rsvd0 : 1; 30 u64 intr : 1; 31 u64 rsvd1 : 1; 32 u64 stop : 1; 33 u64 rsvd2 : 1; 34 u64 size : 4; 35 u64 rsvd3 : 2; 36 u64 base : 40; 37 u64 rsvd4 : 12; 38 }; 39 40 struct pt_pmu { 41 struct pmu pmu; 42 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; 43 bool vmx; 44 bool branch_en_always_on; 45 unsigned long max_nonturbo_ratio; 46 unsigned int tsc_art_num; 47 unsigned int tsc_art_den; 48 }; 49 50 /** 51 * struct pt_buffer - buffer configuration; one buffer per task_struct or 52 * cpu, depending on perf event configuration 53 * @tables: list of ToPA tables in this buffer 54 * @first: shorthand for first topa table 55 * @last: shorthand for last topa table 56 * @cur: current topa table 57 * @nr_pages: buffer size in pages 58 * @cur_idx: current output region's index within @cur table 59 * @output_off: offset within the current output region 60 * @data_size: running total of the amount of data in this buffer 61 * @lost: if data was lost/truncated 62 * @head: logical write offset inside the buffer 63 * @snapshot: if this is for a snapshot/overwrite counter 64 * @single: use Single Range Output instead of ToPA 65 * @wrapped: buffer advance wrapped back to the first topa table 66 * @stop_pos: STOP topa entry index 67 * @intr_pos: INT topa entry index 68 * @stop_te: STOP topa entry pointer 69 * @intr_te: INT topa entry pointer 70 * @data_pages: array of pages from perf 71 * @topa_index: table of topa entries indexed by page offset 72 */ 73 struct pt_buffer { 74 struct list_head tables; 75 struct topa *first, *last, *cur; 76 unsigned int cur_idx; 77 size_t output_off; 78 unsigned long nr_pages; 79 local_t data_size; 80 local64_t head; 81 bool snapshot; 82 bool single; 83 bool wrapped; 84 long stop_pos, intr_pos; 85 struct topa_entry *stop_te, *intr_te; 86 void **data_pages; 87 }; 88 89 #define PT_FILTERS_NUM 4 90 91 /** 92 * struct pt_filter - IP range filter configuration 93 * @msr_a: range start, goes to RTIT_ADDRn_A 94 * @msr_b: range end, goes to RTIT_ADDRn_B 95 * @config: 4-bit field in RTIT_CTL 96 */ 97 struct pt_filter { 98 unsigned long msr_a; 99 unsigned long msr_b; 100 unsigned long config; 101 }; 102 103 /** 104 * struct pt_filters - IP range filtering context 105 * @filter: filters defined for this context 106 * @nr_filters: number of defined filters in the @filter array 107 */ 108 struct pt_filters { 109 struct pt_filter filter[PT_FILTERS_NUM]; 110 unsigned int nr_filters; 111 }; 112 113 /** 114 * struct pt - per-cpu pt context 115 * @handle: perf output handle 116 * @filters: last configured filters 117 * @handle_nmi: do handle PT PMI on this cpu, there's an active event 118 * @vmx_on: 1 if VMX is ON on this cpu 119 * @pause_allowed: PERF_EF_PAUSE is allowed to stop tracing 120 * @resume_allowed: PERF_EF_RESUME is allowed to start tracing 121 * @output_base: cached RTIT_OUTPUT_BASE MSR value 122 * @output_mask: cached RTIT_OUTPUT_MASK MSR value 123 */ 124 struct pt { 125 struct perf_output_handle handle; 126 struct pt_filters filters; 127 int handle_nmi; 128 int vmx_on; 129 int pause_allowed; 130 int resume_allowed; 131 u64 output_base; 132 u64 output_mask; 133 }; 134 135 #endif /* __INTEL_PT_H__ */ 136