1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Intel(R) Processor Trace PMU driver for perf 4 * Copyright (c) 2013-2014, Intel Corporation. 5 * 6 * Intel PT is specified in the Intel Architecture Instruction Set Extensions 7 * Programming Reference: 8 * http://software.intel.com/en-us/intel-isa-extensions 9 */ 10 11 #ifndef __INTEL_PT_H__ 12 #define __INTEL_PT_H__ 13 14 /* 15 * Single-entry ToPA: when this close to region boundary, switch 16 * buffers to avoid losing data. 17 */ 18 #define TOPA_PMI_MARGIN 512 19 20 #define TOPA_SHIFT 12 21 22 static inline unsigned int sizes(unsigned int tsz) 23 { 24 return 1 << (tsz + TOPA_SHIFT); 25 }; 26 27 struct topa_entry { 28 u64 end : 1; 29 u64 rsvd0 : 1; 30 u64 intr : 1; 31 u64 rsvd1 : 1; 32 u64 stop : 1; 33 u64 rsvd2 : 1; 34 u64 size : 4; 35 u64 rsvd3 : 2; 36 u64 base : 40; 37 u64 rsvd4 : 12; 38 }; 39 40 struct pt_pmu { 41 struct pmu pmu; 42 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; 43 bool vmx; 44 bool branch_en_always_on; 45 unsigned long max_nonturbo_ratio; 46 unsigned int tsc_art_num; 47 unsigned int tsc_art_den; 48 }; 49 50 /** 51 * struct pt_buffer - buffer configuration; one buffer per task_struct or 52 * cpu, depending on perf event configuration 53 * @tables: list of ToPA tables in this buffer 54 * @first: shorthand for first topa table 55 * @last: shorthand for last topa table 56 * @cur: current topa table 57 * @nr_pages: buffer size in pages 58 * @cur_idx: current output region's index within @cur table 59 * @output_off: offset within the current output region 60 * @data_size: running total of the amount of data in this buffer 61 * @head: logical write offset inside the buffer 62 * @snapshot: if this is for a snapshot/overwrite counter 63 * @single: use Single Range Output instead of ToPA 64 * @wrapped: buffer advance wrapped back to the first topa table 65 * @stop_pos: STOP topa entry index 66 * @intr_pos: INT topa entry index 67 * @stop_te: STOP topa entry pointer 68 * @intr_te: INT topa entry pointer 69 * @data_pages: array of pages from perf 70 */ 71 struct pt_buffer { 72 struct list_head tables; 73 struct topa *first, *last, *cur; 74 unsigned int cur_idx; 75 size_t output_off; 76 unsigned long nr_pages; 77 local_t data_size; 78 local64_t head; 79 bool snapshot; 80 bool single; 81 bool wrapped; 82 long stop_pos, intr_pos; 83 struct topa_entry *stop_te, *intr_te; 84 void **data_pages; 85 }; 86 87 #define PT_FILTERS_NUM 4 88 89 /** 90 * struct pt_filter - IP range filter configuration 91 * @msr_a: range start, goes to RTIT_ADDRn_A 92 * @msr_b: range end, goes to RTIT_ADDRn_B 93 * @config: 4-bit field in RTIT_CTL 94 */ 95 struct pt_filter { 96 unsigned long msr_a; 97 unsigned long msr_b; 98 unsigned long config; 99 }; 100 101 /** 102 * struct pt_filters - IP range filtering context 103 * @filter: filters defined for this context 104 * @nr_filters: number of defined filters in the @filter array 105 */ 106 struct pt_filters { 107 struct pt_filter filter[PT_FILTERS_NUM]; 108 unsigned int nr_filters; 109 }; 110 111 /** 112 * struct pt - per-cpu pt context 113 * @handle: perf output handle 114 * @filters: last configured filters 115 * @handle_nmi: do handle PT PMI on this cpu, there's an active event 116 * @vmx_on: 1 if VMX is ON on this cpu 117 * @pause_allowed: PERF_EF_PAUSE is allowed to stop tracing 118 * @resume_allowed: PERF_EF_RESUME is allowed to start tracing 119 * @output_base: cached RTIT_OUTPUT_BASE MSR value 120 * @output_mask: cached RTIT_OUTPUT_MASK MSR value 121 */ 122 struct pt { 123 struct perf_output_handle handle; 124 struct pt_filters filters; 125 int handle_nmi; 126 int vmx_on; 127 int pause_allowed; 128 int resume_allowed; 129 u64 output_base; 130 u64 output_mask; 131 }; 132 133 #endif /* __INTEL_PT_H__ */ 134