1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel(R) Processor Trace PMU driver for perf 4 * Copyright (c) 2013-2014, Intel Corporation. 5 * 6 * Intel PT is specified in the Intel Architecture Instruction Set Extensions 7 * Programming Reference: 8 * http://software.intel.com/en-us/intel-isa-extensions 9 */ 10 11 #undef DEBUG 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/types.h> 16 #include <linux/bits.h> 17 #include <linux/limits.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/kvm_types.h> 21 22 #include <asm/cpuid/api.h> 23 #include <asm/perf_event.h> 24 #include <asm/insn.h> 25 #include <asm/io.h> 26 #include <asm/intel_pt.h> 27 #include <asm/cpu_device_id.h> 28 #include <asm/msr.h> 29 30 #include "../perf_event.h" 31 #include "pt.h" 32 33 static DEFINE_PER_CPU(struct pt, pt_ctx); 34 35 static struct pt_pmu pt_pmu; 36 37 /* 38 * Capabilities of Intel PT hardware, such as number of address bits or 39 * supported output schemes, are cached and exported to userspace as "caps" 40 * attribute group of pt pmu device 41 * (/sys/bus/event_source/devices/intel_pt/caps/) so that userspace can store 42 * relevant bits together with intel_pt traces. 43 * 44 * These are necessary for both trace decoding (payloads_lip, contains address 45 * width encoded in IP-related packets), and event configuration (bitmasks with 46 * permitted values for certain bit fields). 47 */ 48 #define PT_CAP(_n, _l, _r, _m) \ 49 [PT_CAP_ ## _n] = { .name = __stringify(_n), .leaf = _l, \ 50 .reg = _r, .mask = _m } 51 52 static struct pt_cap_desc { 53 const char *name; 54 u32 leaf; 55 u8 reg; 56 u32 mask; 57 } pt_caps[] = { 58 PT_CAP(max_subleaf, 0, CPUID_EAX, 0xffffffff), 59 PT_CAP(cr3_filtering, 0, CPUID_EBX, BIT(0)), 60 PT_CAP(psb_cyc, 0, CPUID_EBX, BIT(1)), 61 PT_CAP(ip_filtering, 0, CPUID_EBX, BIT(2)), 62 PT_CAP(mtc, 0, CPUID_EBX, BIT(3)), 63 PT_CAP(ptwrite, 0, CPUID_EBX, BIT(4)), 64 PT_CAP(power_event_trace, 0, CPUID_EBX, BIT(5)), 65 PT_CAP(event_trace, 0, CPUID_EBX, BIT(7)), 66 PT_CAP(tnt_disable, 0, CPUID_EBX, BIT(8)), 67 PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)), 68 PT_CAP(topa_multiple_entries, 0, CPUID_ECX, BIT(1)), 69 PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)), 70 PT_CAP(output_subsys, 0, CPUID_ECX, BIT(3)), 71 PT_CAP(payloads_lip, 0, CPUID_ECX, BIT(31)), 72 PT_CAP(num_address_ranges, 1, CPUID_EAX, 0x7), 73 PT_CAP(mtc_periods, 1, CPUID_EAX, 0xffff0000), 74 PT_CAP(cycle_thresholds, 1, CPUID_EBX, 0xffff), 75 PT_CAP(psb_periods, 1, CPUID_EBX, 0xffff0000), 76 }; 77 78 u32 intel_pt_validate_cap(u32 *caps, enum pt_capabilities capability) 79 { 80 struct pt_cap_desc *cd = &pt_caps[capability]; 81 u32 c = caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg]; 82 unsigned int shift = __ffs(cd->mask); 83 84 return (c & cd->mask) >> shift; 85 } 86 EXPORT_SYMBOL_FOR_KVM(intel_pt_validate_cap); 87 88 u32 intel_pt_validate_hw_cap(enum pt_capabilities cap) 89 { 90 return intel_pt_validate_cap(pt_pmu.caps, cap); 91 } 92 EXPORT_SYMBOL_FOR_KVM(intel_pt_validate_hw_cap); 93 94 static ssize_t pt_cap_show(struct device *cdev, 95 struct device_attribute *attr, 96 char *buf) 97 { 98 struct dev_ext_attribute *ea = 99 container_of(attr, struct dev_ext_attribute, attr); 100 enum pt_capabilities cap = (long)ea->var; 101 102 return snprintf(buf, PAGE_SIZE, "%x\n", intel_pt_validate_hw_cap(cap)); 103 } 104 105 static struct attribute_group pt_cap_group __ro_after_init = { 106 .name = "caps", 107 }; 108 109 PMU_FORMAT_ATTR(pt, "config:0" ); 110 PMU_FORMAT_ATTR(cyc, "config:1" ); 111 PMU_FORMAT_ATTR(pwr_evt, "config:4" ); 112 PMU_FORMAT_ATTR(fup_on_ptw, "config:5" ); 113 PMU_FORMAT_ATTR(mtc, "config:9" ); 114 PMU_FORMAT_ATTR(tsc, "config:10" ); 115 PMU_FORMAT_ATTR(noretcomp, "config:11" ); 116 PMU_FORMAT_ATTR(ptw, "config:12" ); 117 PMU_FORMAT_ATTR(branch, "config:13" ); 118 PMU_FORMAT_ATTR(event, "config:31" ); 119 PMU_FORMAT_ATTR(notnt, "config:55" ); 120 PMU_FORMAT_ATTR(mtc_period, "config:14-17" ); 121 PMU_FORMAT_ATTR(cyc_thresh, "config:19-22" ); 122 PMU_FORMAT_ATTR(psb_period, "config:24-27" ); 123 124 static struct attribute *pt_formats_attr[] = { 125 &format_attr_pt.attr, 126 &format_attr_cyc.attr, 127 &format_attr_pwr_evt.attr, 128 &format_attr_event.attr, 129 &format_attr_notnt.attr, 130 &format_attr_fup_on_ptw.attr, 131 &format_attr_mtc.attr, 132 &format_attr_tsc.attr, 133 &format_attr_noretcomp.attr, 134 &format_attr_ptw.attr, 135 &format_attr_branch.attr, 136 &format_attr_mtc_period.attr, 137 &format_attr_cyc_thresh.attr, 138 &format_attr_psb_period.attr, 139 NULL, 140 }; 141 142 static struct attribute_group pt_format_group = { 143 .name = "format", 144 .attrs = pt_formats_attr, 145 }; 146 147 static ssize_t 148 pt_timing_attr_show(struct device *dev, struct device_attribute *attr, 149 char *page) 150 { 151 struct perf_pmu_events_attr *pmu_attr = 152 container_of(attr, struct perf_pmu_events_attr, attr); 153 154 switch (pmu_attr->id) { 155 case 0: 156 return sprintf(page, "%lu\n", pt_pmu.max_nonturbo_ratio); 157 case 1: 158 return sprintf(page, "%u:%u\n", 159 pt_pmu.tsc_art_num, 160 pt_pmu.tsc_art_den); 161 default: 162 break; 163 } 164 165 return -EINVAL; 166 } 167 168 PMU_EVENT_ATTR(max_nonturbo_ratio, timing_attr_max_nonturbo_ratio, 0, 169 pt_timing_attr_show); 170 PMU_EVENT_ATTR(tsc_art_ratio, timing_attr_tsc_art_ratio, 1, 171 pt_timing_attr_show); 172 173 static struct attribute *pt_timing_attr[] = { 174 &timing_attr_max_nonturbo_ratio.attr.attr, 175 &timing_attr_tsc_art_ratio.attr.attr, 176 NULL, 177 }; 178 179 static struct attribute_group pt_timing_group = { 180 .attrs = pt_timing_attr, 181 }; 182 183 static const struct attribute_group *pt_attr_groups[] = { 184 &pt_cap_group, 185 &pt_format_group, 186 &pt_timing_group, 187 NULL, 188 }; 189 190 static int __init pt_pmu_hw_init(void) 191 { 192 struct dev_ext_attribute *de_attrs; 193 struct attribute **attrs; 194 size_t size; 195 u64 reg; 196 int ret; 197 long i; 198 199 rdmsrq(MSR_PLATFORM_INFO, reg); 200 pt_pmu.max_nonturbo_ratio = (reg & 0xff00) >> 8; 201 202 /* 203 * if available, read in TSC to core crystal clock ratio, 204 * otherwise, zero for numerator stands for "not enumerated" 205 * as per SDM 206 */ 207 if (boot_cpu_data.cpuid_level >= CPUID_LEAF_TSC) { 208 u32 eax, ebx, ecx, edx; 209 210 cpuid(CPUID_LEAF_TSC, &eax, &ebx, &ecx, &edx); 211 212 pt_pmu.tsc_art_num = ebx; 213 pt_pmu.tsc_art_den = eax; 214 } 215 216 /* model-specific quirks */ 217 switch (boot_cpu_data.x86_vfm) { 218 case INTEL_BROADWELL: 219 case INTEL_BROADWELL_D: 220 case INTEL_BROADWELL_G: 221 case INTEL_BROADWELL_X: 222 /* not setting BRANCH_EN will #GP, erratum BDM106 */ 223 pt_pmu.branch_en_always_on = true; 224 break; 225 default: 226 break; 227 } 228 229 if (boot_cpu_has(X86_FEATURE_VMX)) { 230 /* 231 * Intel SDM, 36.5 "Tracing post-VMXON" says that 232 * "IA32_VMX_MISC[bit 14]" being 1 means PT can trace 233 * post-VMXON. 234 */ 235 rdmsrq(MSR_IA32_VMX_MISC, reg); 236 if (reg & BIT(14)) 237 pt_pmu.vmx = true; 238 } 239 240 for (i = 0; i < PT_CPUID_LEAVES; i++) { 241 cpuid_count(20, i, 242 &pt_pmu.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM], 243 &pt_pmu.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM], 244 &pt_pmu.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM], 245 &pt_pmu.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM]); 246 } 247 248 ret = -ENOMEM; 249 size = sizeof(struct attribute *) * (ARRAY_SIZE(pt_caps)+1); 250 attrs = kzalloc(size, GFP_KERNEL); 251 if (!attrs) 252 goto fail; 253 254 size = sizeof(struct dev_ext_attribute) * (ARRAY_SIZE(pt_caps)+1); 255 de_attrs = kzalloc(size, GFP_KERNEL); 256 if (!de_attrs) 257 goto fail; 258 259 for (i = 0; i < ARRAY_SIZE(pt_caps); i++) { 260 struct dev_ext_attribute *de_attr = de_attrs + i; 261 262 de_attr->attr.attr.name = pt_caps[i].name; 263 264 sysfs_attr_init(&de_attr->attr.attr); 265 266 de_attr->attr.attr.mode = S_IRUGO; 267 de_attr->attr.show = pt_cap_show; 268 de_attr->var = (void *)i; 269 270 attrs[i] = &de_attr->attr.attr; 271 } 272 273 pt_cap_group.attrs = attrs; 274 275 return 0; 276 277 fail: 278 kfree(attrs); 279 280 return ret; 281 } 282 283 #define RTIT_CTL_CYC_PSB (RTIT_CTL_CYCLEACC | \ 284 RTIT_CTL_CYC_THRESH | \ 285 RTIT_CTL_PSB_FREQ) 286 287 #define RTIT_CTL_MTC (RTIT_CTL_MTC_EN | \ 288 RTIT_CTL_MTC_RANGE) 289 290 #define RTIT_CTL_PTW (RTIT_CTL_PTW_EN | \ 291 RTIT_CTL_FUP_ON_PTW) 292 293 /* 294 * Bit 0 (TraceEn) in the attr.config is meaningless as the 295 * corresponding bit in the RTIT_CTL can only be controlled 296 * by the driver; therefore, repurpose it to mean: pass 297 * through the bit that was previously assumed to be always 298 * on for PT, thereby allowing the user to *not* set it if 299 * they so wish. See also pt_event_valid() and pt_config(). 300 */ 301 #define RTIT_CTL_PASSTHROUGH RTIT_CTL_TRACEEN 302 303 #define PT_CONFIG_MASK (RTIT_CTL_TRACEEN | \ 304 RTIT_CTL_TSC_EN | \ 305 RTIT_CTL_DISRETC | \ 306 RTIT_CTL_BRANCH_EN | \ 307 RTIT_CTL_CYC_PSB | \ 308 RTIT_CTL_MTC | \ 309 RTIT_CTL_PWR_EVT_EN | \ 310 RTIT_CTL_EVENT_EN | \ 311 RTIT_CTL_NOTNT | \ 312 RTIT_CTL_FUP_ON_PTW | \ 313 RTIT_CTL_PTW_EN) 314 315 static bool pt_event_valid(struct perf_event *event) 316 { 317 u64 config = event->attr.config; 318 u64 allowed, requested; 319 320 if ((config & PT_CONFIG_MASK) != config) 321 return false; 322 323 if (config & RTIT_CTL_CYC_PSB) { 324 if (!intel_pt_validate_hw_cap(PT_CAP_psb_cyc)) 325 return false; 326 327 allowed = intel_pt_validate_hw_cap(PT_CAP_psb_periods); 328 requested = (config & RTIT_CTL_PSB_FREQ) >> 329 RTIT_CTL_PSB_FREQ_OFFSET; 330 if (requested && (!(allowed & BIT(requested)))) 331 return false; 332 333 allowed = intel_pt_validate_hw_cap(PT_CAP_cycle_thresholds); 334 requested = (config & RTIT_CTL_CYC_THRESH) >> 335 RTIT_CTL_CYC_THRESH_OFFSET; 336 if (requested && (!(allowed & BIT(requested)))) 337 return false; 338 } 339 340 if (config & RTIT_CTL_MTC) { 341 /* 342 * In the unlikely case that CPUID lists valid mtc periods, 343 * but not the mtc capability, drop out here. 344 * 345 * Spec says that setting mtc period bits while mtc bit in 346 * CPUID is 0 will #GP, so better safe than sorry. 347 */ 348 if (!intel_pt_validate_hw_cap(PT_CAP_mtc)) 349 return false; 350 351 allowed = intel_pt_validate_hw_cap(PT_CAP_mtc_periods); 352 if (!allowed) 353 return false; 354 355 requested = (config & RTIT_CTL_MTC_RANGE) >> 356 RTIT_CTL_MTC_RANGE_OFFSET; 357 358 if (!(allowed & BIT(requested))) 359 return false; 360 } 361 362 if (config & RTIT_CTL_PWR_EVT_EN && 363 !intel_pt_validate_hw_cap(PT_CAP_power_event_trace)) 364 return false; 365 366 if (config & RTIT_CTL_EVENT_EN && 367 !intel_pt_validate_hw_cap(PT_CAP_event_trace)) 368 return false; 369 370 if (config & RTIT_CTL_NOTNT && 371 !intel_pt_validate_hw_cap(PT_CAP_tnt_disable)) 372 return false; 373 374 if (config & RTIT_CTL_PTW) { 375 if (!intel_pt_validate_hw_cap(PT_CAP_ptwrite)) 376 return false; 377 378 /* FUPonPTW without PTW doesn't make sense */ 379 if ((config & RTIT_CTL_FUP_ON_PTW) && 380 !(config & RTIT_CTL_PTW_EN)) 381 return false; 382 } 383 384 /* 385 * Setting bit 0 (TraceEn in RTIT_CTL MSR) in the attr.config 386 * clears the assumption that BranchEn must always be enabled, 387 * as was the case with the first implementation of PT. 388 * If this bit is not set, the legacy behavior is preserved 389 * for compatibility with the older userspace. 390 * 391 * Re-using bit 0 for this purpose is fine because it is never 392 * directly set by the user; previous attempts at setting it in 393 * the attr.config resulted in -EINVAL. 394 */ 395 if (config & RTIT_CTL_PASSTHROUGH) { 396 /* 397 * Disallow not setting BRANCH_EN where BRANCH_EN is 398 * always required. 399 */ 400 if (pt_pmu.branch_en_always_on && 401 !(config & RTIT_CTL_BRANCH_EN)) 402 return false; 403 } else { 404 /* 405 * Disallow BRANCH_EN without the PASSTHROUGH. 406 */ 407 if (config & RTIT_CTL_BRANCH_EN) 408 return false; 409 } 410 411 return true; 412 } 413 414 /* 415 * PT configuration helpers 416 * These all are cpu affine and operate on a local PT 417 */ 418 419 static void pt_config_start(struct perf_event *event) 420 { 421 struct pt *pt = this_cpu_ptr(&pt_ctx); 422 u64 ctl = event->hw.aux_config; 423 424 if (READ_ONCE(event->hw.aux_paused)) 425 return; 426 427 ctl |= RTIT_CTL_TRACEEN; 428 if (READ_ONCE(pt->vmx_on)) 429 perf_aux_output_flag(&pt->handle, PERF_AUX_FLAG_PARTIAL); 430 else 431 wrmsrq(MSR_IA32_RTIT_CTL, ctl); 432 433 WRITE_ONCE(event->hw.aux_config, ctl); 434 } 435 436 /* Address ranges and their corresponding msr configuration registers */ 437 static const struct pt_address_range { 438 unsigned long msr_a; 439 unsigned long msr_b; 440 unsigned int reg_off; 441 } pt_address_ranges[] = { 442 { 443 .msr_a = MSR_IA32_RTIT_ADDR0_A, 444 .msr_b = MSR_IA32_RTIT_ADDR0_B, 445 .reg_off = RTIT_CTL_ADDR0_OFFSET, 446 }, 447 { 448 .msr_a = MSR_IA32_RTIT_ADDR1_A, 449 .msr_b = MSR_IA32_RTIT_ADDR1_B, 450 .reg_off = RTIT_CTL_ADDR1_OFFSET, 451 }, 452 { 453 .msr_a = MSR_IA32_RTIT_ADDR2_A, 454 .msr_b = MSR_IA32_RTIT_ADDR2_B, 455 .reg_off = RTIT_CTL_ADDR2_OFFSET, 456 }, 457 { 458 .msr_a = MSR_IA32_RTIT_ADDR3_A, 459 .msr_b = MSR_IA32_RTIT_ADDR3_B, 460 .reg_off = RTIT_CTL_ADDR3_OFFSET, 461 } 462 }; 463 464 static u64 pt_config_filters(struct perf_event *event) 465 { 466 struct pt_filters *filters = event->hw.addr_filters; 467 struct pt *pt = this_cpu_ptr(&pt_ctx); 468 unsigned int range = 0; 469 u64 rtit_ctl = 0; 470 471 if (!filters) 472 return 0; 473 474 perf_event_addr_filters_sync(event); 475 476 for (range = 0; range < filters->nr_filters; range++) { 477 struct pt_filter *filter = &filters->filter[range]; 478 479 /* 480 * Note, if the range has zero start/end addresses due 481 * to its dynamic object not being loaded yet, we just 482 * go ahead and program zeroed range, which will simply 483 * produce no data. Note^2: if executable code at 0x0 484 * is a concern, we can set up an "invalid" configuration 485 * such as msr_b < msr_a. 486 */ 487 488 /* avoid redundant msr writes */ 489 if (pt->filters.filter[range].msr_a != filter->msr_a) { 490 wrmsrq(pt_address_ranges[range].msr_a, filter->msr_a); 491 pt->filters.filter[range].msr_a = filter->msr_a; 492 } 493 494 if (pt->filters.filter[range].msr_b != filter->msr_b) { 495 wrmsrq(pt_address_ranges[range].msr_b, filter->msr_b); 496 pt->filters.filter[range].msr_b = filter->msr_b; 497 } 498 499 rtit_ctl |= (u64)filter->config << pt_address_ranges[range].reg_off; 500 } 501 502 return rtit_ctl; 503 } 504 505 static void pt_config_enable(struct perf_event *event) 506 { 507 struct pt *pt = this_cpu_ptr(&pt_ctx); 508 509 /* 510 * Allow resume before starting so as not to overwrite a value set by a 511 * PMI. 512 */ 513 barrier(); 514 WRITE_ONCE(pt->resume_allowed, 1); 515 /* Configuration is complete, it is now OK to handle an NMI */ 516 barrier(); 517 WRITE_ONCE(pt->handle_nmi, 1); 518 barrier(); 519 pt_config_start(event); 520 barrier(); 521 /* 522 * Allow pause after starting so its pt_config_stop() doesn't race with 523 * pt_config_start(). 524 */ 525 WRITE_ONCE(pt->pause_allowed, 1); 526 } 527 528 static void pt_config(struct perf_event *event) 529 { 530 struct pt *pt = this_cpu_ptr(&pt_ctx); 531 struct pt_buffer *buf = perf_get_aux(&pt->handle); 532 u64 reg; 533 534 /* First round: clear STATUS, in particular the PSB byte counter. */ 535 if (!event->hw.aux_config) { 536 perf_event_itrace_started(event); 537 wrmsrq(MSR_IA32_RTIT_STATUS, 0); 538 } 539 540 reg = pt_config_filters(event); 541 reg |= RTIT_CTL_TRACEEN; 542 if (!buf->single) 543 reg |= RTIT_CTL_TOPA; 544 545 /* 546 * Previously, we had BRANCH_EN on by default, but now that PT has 547 * grown features outside of branch tracing, it is useful to allow 548 * the user to disable it. Setting bit 0 in the event's attr.config 549 * allows BRANCH_EN to pass through instead of being always on. See 550 * also the comment in pt_event_valid(). 551 */ 552 if (event->attr.config & BIT(0)) { 553 reg |= event->attr.config & RTIT_CTL_BRANCH_EN; 554 } else { 555 reg |= RTIT_CTL_BRANCH_EN; 556 } 557 558 if (!event->attr.exclude_kernel) 559 reg |= RTIT_CTL_OS; 560 if (!event->attr.exclude_user) 561 reg |= RTIT_CTL_USR; 562 563 reg |= (event->attr.config & PT_CONFIG_MASK); 564 565 event->hw.aux_config = reg; 566 567 pt_config_enable(event); 568 } 569 570 static void pt_config_stop(struct perf_event *event) 571 { 572 struct pt *pt = this_cpu_ptr(&pt_ctx); 573 u64 ctl = READ_ONCE(event->hw.aux_config); 574 575 /* may be already stopped by a PMI */ 576 if (!(ctl & RTIT_CTL_TRACEEN)) 577 return; 578 579 ctl &= ~RTIT_CTL_TRACEEN; 580 if (!READ_ONCE(pt->vmx_on)) 581 wrmsrq(MSR_IA32_RTIT_CTL, ctl); 582 583 WRITE_ONCE(event->hw.aux_config, ctl); 584 585 /* 586 * A wrmsr that disables trace generation serializes other PT 587 * registers and causes all data packets to be written to memory, 588 * but a fence is required for the data to become globally visible. 589 * 590 * The below WMB, separating data store and aux_head store matches 591 * the consumer's RMB that separates aux_head load and data load. 592 */ 593 wmb(); 594 } 595 596 /** 597 * struct topa - ToPA metadata 598 * @list: linkage to struct pt_buffer's list of tables 599 * @offset: offset of the first entry in this table in the buffer 600 * @size: total size of all entries in this table 601 * @last: index of the last initialized entry in this table 602 * @z_count: how many times the first entry repeats 603 */ 604 struct topa { 605 struct list_head list; 606 u64 offset; 607 size_t size; 608 int last; 609 unsigned int z_count; 610 }; 611 612 /* 613 * Keep ToPA table-related metadata on the same page as the actual table, 614 * taking up a few words from the top 615 */ 616 617 #define TENTS_PER_PAGE \ 618 ((PAGE_SIZE - sizeof(struct topa)) / sizeof(struct topa_entry)) 619 620 /** 621 * struct topa_page - page-sized ToPA table with metadata at the top 622 * @table: actual ToPA table entries, as understood by PT hardware 623 * @topa: metadata 624 */ 625 struct topa_page { 626 struct topa_entry table[TENTS_PER_PAGE]; 627 struct topa topa; 628 }; 629 630 static inline struct topa_page *topa_to_page(struct topa *topa) 631 { 632 return container_of(topa, struct topa_page, topa); 633 } 634 635 static inline struct topa_page *topa_entry_to_page(struct topa_entry *te) 636 { 637 return (struct topa_page *)((unsigned long)te & PAGE_MASK); 638 } 639 640 static inline phys_addr_t topa_pfn(struct topa *topa) 641 { 642 return PFN_DOWN(virt_to_phys(topa_to_page(topa))); 643 } 644 645 /* make -1 stand for the last table entry */ 646 #define TOPA_ENTRY(t, i) \ 647 ((i) == -1 \ 648 ? &topa_to_page(t)->table[(t)->last] \ 649 : &topa_to_page(t)->table[(i)]) 650 #define TOPA_ENTRY_SIZE(t, i) (sizes(TOPA_ENTRY((t), (i))->size)) 651 #define TOPA_ENTRY_PAGES(t, i) (1 << TOPA_ENTRY((t), (i))->size) 652 653 static void pt_config_buffer(struct pt_buffer *buf) 654 { 655 struct pt *pt = this_cpu_ptr(&pt_ctx); 656 u64 reg, mask; 657 void *base; 658 659 if (buf->single) { 660 base = buf->data_pages[0]; 661 mask = (buf->nr_pages * PAGE_SIZE - 1) >> 7; 662 } else { 663 base = topa_to_page(buf->cur)->table; 664 mask = (u64)buf->cur_idx; 665 } 666 667 reg = virt_to_phys(base); 668 if (pt->output_base != reg) { 669 pt->output_base = reg; 670 wrmsrq(MSR_IA32_RTIT_OUTPUT_BASE, reg); 671 } 672 673 reg = 0x7f | (mask << 7) | ((u64)buf->output_off << 32); 674 if (pt->output_mask != reg) { 675 pt->output_mask = reg; 676 wrmsrq(MSR_IA32_RTIT_OUTPUT_MASK, reg); 677 } 678 } 679 680 /** 681 * topa_alloc() - allocate page-sized ToPA table 682 * @cpu: CPU on which to allocate. 683 * @gfp: Allocation flags. 684 * 685 * Return: On success, return the pointer to ToPA table page. 686 */ 687 static struct topa *topa_alloc(int cpu, gfp_t gfp) 688 { 689 int node = cpu_to_node(cpu); 690 struct topa_page *tp; 691 struct page *p; 692 693 p = alloc_pages_node(node, gfp | __GFP_ZERO, 0); 694 if (!p) 695 return NULL; 696 697 tp = page_address(p); 698 tp->topa.last = 0; 699 700 /* 701 * In case of singe-entry ToPA, always put the self-referencing END 702 * link as the 2nd entry in the table 703 */ 704 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) { 705 TOPA_ENTRY(&tp->topa, 1)->base = page_to_phys(p) >> TOPA_SHIFT; 706 TOPA_ENTRY(&tp->topa, 1)->end = 1; 707 } 708 709 return &tp->topa; 710 } 711 712 /** 713 * topa_free() - free a page-sized ToPA table 714 * @topa: Table to deallocate. 715 */ 716 static void topa_free(struct topa *topa) 717 { 718 free_page((unsigned long)topa); 719 } 720 721 /** 722 * topa_insert_table() - insert a ToPA table into a buffer 723 * @buf: PT buffer that's being extended. 724 * @topa: New topa table to be inserted. 725 * 726 * If it's the first table in this buffer, set up buffer's pointers 727 * accordingly; otherwise, add a END=1 link entry to @topa to the current 728 * "last" table and adjust the last table pointer to @topa. 729 */ 730 static void topa_insert_table(struct pt_buffer *buf, struct topa *topa) 731 { 732 struct topa *last = buf->last; 733 734 list_add_tail(&topa->list, &buf->tables); 735 736 if (!buf->first) { 737 buf->first = buf->last = buf->cur = topa; 738 return; 739 } 740 741 topa->offset = last->offset + last->size; 742 buf->last = topa; 743 744 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) 745 return; 746 747 BUG_ON(last->last != TENTS_PER_PAGE - 1); 748 749 TOPA_ENTRY(last, -1)->base = topa_pfn(topa); 750 TOPA_ENTRY(last, -1)->end = 1; 751 } 752 753 /** 754 * topa_table_full() - check if a ToPA table is filled up 755 * @topa: ToPA table. 756 */ 757 static bool topa_table_full(struct topa *topa) 758 { 759 /* single-entry ToPA is a special case */ 760 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) 761 return !!topa->last; 762 763 return topa->last == TENTS_PER_PAGE - 1; 764 } 765 766 /** 767 * topa_insert_pages() - create a list of ToPA tables 768 * @buf: PT buffer being initialized. 769 * @cpu: CPU on which to allocate. 770 * @gfp: Allocation flags. 771 * 772 * This initializes a list of ToPA tables with entries from 773 * the data_pages provided by rb_alloc_aux(). 774 * 775 * Return: 0 on success or error code. 776 */ 777 static int topa_insert_pages(struct pt_buffer *buf, int cpu, gfp_t gfp) 778 { 779 struct topa *topa = buf->last; 780 int order = 0; 781 struct page *p; 782 783 p = virt_to_page(buf->data_pages[buf->nr_pages]); 784 if (PagePrivate(p)) 785 order = page_private(p); 786 787 if (topa_table_full(topa)) { 788 topa = topa_alloc(cpu, gfp); 789 if (!topa) 790 return -ENOMEM; 791 792 topa_insert_table(buf, topa); 793 } 794 795 if (topa->z_count == topa->last - 1) { 796 if (order == TOPA_ENTRY(topa, topa->last - 1)->size) 797 topa->z_count++; 798 } 799 800 TOPA_ENTRY(topa, -1)->base = page_to_phys(p) >> TOPA_SHIFT; 801 TOPA_ENTRY(topa, -1)->size = order; 802 if (!buf->snapshot && 803 !intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) { 804 TOPA_ENTRY(topa, -1)->intr = 1; 805 TOPA_ENTRY(topa, -1)->stop = 1; 806 } 807 808 topa->last++; 809 topa->size += sizes(order); 810 811 buf->nr_pages += 1ul << order; 812 813 return 0; 814 } 815 816 /** 817 * pt_topa_dump() - print ToPA tables and their entries 818 * @buf: PT buffer. 819 */ 820 static void pt_topa_dump(struct pt_buffer *buf) 821 { 822 struct topa *topa; 823 824 list_for_each_entry(topa, &buf->tables, list) { 825 struct topa_page *tp = topa_to_page(topa); 826 int i; 827 828 pr_debug("# table @%p, off %llx size %zx\n", tp->table, 829 topa->offset, topa->size); 830 for (i = 0; i < TENTS_PER_PAGE; i++) { 831 pr_debug("# entry @%p (%lx sz %u %c%c%c) raw=%16llx\n", 832 &tp->table[i], 833 (unsigned long)tp->table[i].base << TOPA_SHIFT, 834 sizes(tp->table[i].size), 835 tp->table[i].end ? 'E' : ' ', 836 tp->table[i].intr ? 'I' : ' ', 837 tp->table[i].stop ? 'S' : ' ', 838 *(u64 *)&tp->table[i]); 839 if ((intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) && 840 tp->table[i].stop) || 841 tp->table[i].end) 842 break; 843 if (!i && topa->z_count) 844 i += topa->z_count; 845 } 846 } 847 } 848 849 /** 850 * pt_buffer_advance() - advance to the next output region 851 * @buf: PT buffer. 852 * 853 * Advance the current pointers in the buffer to the next ToPA entry. 854 */ 855 static void pt_buffer_advance(struct pt_buffer *buf) 856 { 857 buf->output_off = 0; 858 buf->cur_idx++; 859 860 if (buf->cur_idx == buf->cur->last) { 861 if (buf->cur == buf->last) { 862 buf->cur = buf->first; 863 buf->wrapped = true; 864 } else { 865 buf->cur = list_entry(buf->cur->list.next, struct topa, 866 list); 867 } 868 buf->cur_idx = 0; 869 } 870 } 871 872 /** 873 * pt_update_head() - calculate current offsets and sizes 874 * @pt: Per-cpu pt context. 875 * 876 * Update buffer's current write pointer position and data size. 877 */ 878 static void pt_update_head(struct pt *pt) 879 { 880 struct pt_buffer *buf = perf_get_aux(&pt->handle); 881 bool wrapped = buf->wrapped; 882 u64 topa_idx, base, old; 883 884 buf->wrapped = false; 885 886 if (buf->single) { 887 local_set(&buf->data_size, buf->output_off); 888 return; 889 } 890 891 /* offset of the first region in this table from the beginning of buf */ 892 base = buf->cur->offset + buf->output_off; 893 894 /* offset of the current output region within this table */ 895 for (topa_idx = 0; topa_idx < buf->cur_idx; topa_idx++) 896 base += TOPA_ENTRY_SIZE(buf->cur, topa_idx); 897 898 if (buf->snapshot) { 899 local_set(&buf->data_size, base); 900 } else { 901 old = (local64_xchg(&buf->head, base) & 902 ((buf->nr_pages << PAGE_SHIFT) - 1)); 903 if (base < old || (base == old && wrapped)) 904 base += buf->nr_pages << PAGE_SHIFT; 905 906 local_add(base - old, &buf->data_size); 907 } 908 } 909 910 /** 911 * pt_buffer_region() - obtain current output region's address 912 * @buf: PT buffer. 913 */ 914 static void *pt_buffer_region(struct pt_buffer *buf) 915 { 916 return phys_to_virt((phys_addr_t)TOPA_ENTRY(buf->cur, buf->cur_idx)->base << TOPA_SHIFT); 917 } 918 919 /** 920 * pt_buffer_region_size() - obtain current output region's size 921 * @buf: PT buffer. 922 */ 923 static size_t pt_buffer_region_size(struct pt_buffer *buf) 924 { 925 return TOPA_ENTRY_SIZE(buf->cur, buf->cur_idx); 926 } 927 928 /** 929 * pt_handle_status() - take care of possible status conditions 930 * @pt: Per-cpu pt context. 931 */ 932 static void pt_handle_status(struct pt *pt) 933 { 934 struct pt_buffer *buf = perf_get_aux(&pt->handle); 935 int advance = 0; 936 u64 status; 937 938 rdmsrq(MSR_IA32_RTIT_STATUS, status); 939 940 if (status & RTIT_STATUS_ERROR) { 941 pr_err_ratelimited("ToPA ERROR encountered, trying to recover\n"); 942 pt_topa_dump(buf); 943 status &= ~RTIT_STATUS_ERROR; 944 } 945 946 if (status & RTIT_STATUS_STOPPED) { 947 status &= ~RTIT_STATUS_STOPPED; 948 949 /* 950 * On systems that only do single-entry ToPA, hitting STOP 951 * means we are already losing data; need to let the decoder 952 * know. 953 */ 954 if (!buf->single && 955 (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) || 956 buf->output_off == pt_buffer_region_size(buf))) { 957 perf_aux_output_flag(&pt->handle, 958 PERF_AUX_FLAG_TRUNCATED); 959 advance++; 960 } 961 } 962 963 /* 964 * Also on single-entry ToPA implementations, interrupt will come 965 * before the output reaches its output region's boundary. 966 */ 967 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) && 968 !buf->snapshot && 969 pt_buffer_region_size(buf) - buf->output_off <= TOPA_PMI_MARGIN) { 970 void *head = pt_buffer_region(buf); 971 972 /* everything within this margin needs to be zeroed out */ 973 memset(head + buf->output_off, 0, 974 pt_buffer_region_size(buf) - 975 buf->output_off); 976 advance++; 977 } 978 979 if (advance) 980 pt_buffer_advance(buf); 981 982 wrmsrq(MSR_IA32_RTIT_STATUS, status); 983 } 984 985 /** 986 * pt_read_offset() - translate registers into buffer pointers 987 * @buf: PT buffer. 988 * 989 * Set buffer's output pointers from MSR values. 990 */ 991 static void pt_read_offset(struct pt_buffer *buf) 992 { 993 struct pt *pt = this_cpu_ptr(&pt_ctx); 994 struct topa_page *tp; 995 996 if (!buf->single) { 997 rdmsrq(MSR_IA32_RTIT_OUTPUT_BASE, pt->output_base); 998 tp = phys_to_virt(pt->output_base); 999 buf->cur = &tp->topa; 1000 } 1001 1002 rdmsrq(MSR_IA32_RTIT_OUTPUT_MASK, pt->output_mask); 1003 /* offset within current output region */ 1004 buf->output_off = pt->output_mask >> 32; 1005 /* index of current output region within this table */ 1006 if (!buf->single) 1007 buf->cur_idx = (pt->output_mask & 0xffffff80) >> 7; 1008 } 1009 1010 static struct topa_entry * 1011 pt_topa_entry_for_page(struct pt_buffer *buf, unsigned int pg) 1012 { 1013 struct topa_page *tp; 1014 struct topa *topa; 1015 unsigned int idx, cur_pg = 0, z_pg = 0, start_idx = 0; 1016 1017 /* 1018 * Indicates a bug in the caller. 1019 */ 1020 if (WARN_ON_ONCE(pg >= buf->nr_pages)) 1021 return NULL; 1022 1023 /* 1024 * First, find the ToPA table where @pg fits. With high 1025 * order allocations, there shouldn't be many of these. 1026 */ 1027 list_for_each_entry(topa, &buf->tables, list) { 1028 if (topa->offset + topa->size > (unsigned long)pg << PAGE_SHIFT) 1029 goto found; 1030 } 1031 1032 /* 1033 * Hitting this means we have a problem in the ToPA 1034 * allocation code. 1035 */ 1036 WARN_ON_ONCE(1); 1037 1038 return NULL; 1039 1040 found: 1041 /* 1042 * Indicates a problem in the ToPA allocation code. 1043 */ 1044 if (WARN_ON_ONCE(topa->last == -1)) 1045 return NULL; 1046 1047 tp = topa_to_page(topa); 1048 cur_pg = PFN_DOWN(topa->offset); 1049 if (topa->z_count) { 1050 z_pg = TOPA_ENTRY_PAGES(topa, 0) * (topa->z_count + 1); 1051 start_idx = topa->z_count + 1; 1052 } 1053 1054 /* 1055 * Multiple entries at the beginning of the table have the same size, 1056 * ideally all of them; if @pg falls there, the search is done. 1057 */ 1058 if (pg >= cur_pg && pg < cur_pg + z_pg) { 1059 idx = (pg - cur_pg) / TOPA_ENTRY_PAGES(topa, 0); 1060 return &tp->table[idx]; 1061 } 1062 1063 /* 1064 * Otherwise, slow path: iterate through the remaining entries. 1065 */ 1066 for (idx = start_idx, cur_pg += z_pg; idx < topa->last; idx++) { 1067 if (cur_pg + TOPA_ENTRY_PAGES(topa, idx) > pg) 1068 return &tp->table[idx]; 1069 1070 cur_pg += TOPA_ENTRY_PAGES(topa, idx); 1071 } 1072 1073 /* 1074 * Means we couldn't find a ToPA entry in the table that does match. 1075 */ 1076 WARN_ON_ONCE(1); 1077 1078 return NULL; 1079 } 1080 1081 static struct topa_entry * 1082 pt_topa_prev_entry(struct pt_buffer *buf, struct topa_entry *te) 1083 { 1084 unsigned long table = (unsigned long)te & ~(PAGE_SIZE - 1); 1085 struct topa_page *tp; 1086 struct topa *topa; 1087 1088 tp = (struct topa_page *)table; 1089 if (tp->table != te) 1090 return --te; 1091 1092 topa = &tp->topa; 1093 if (topa == buf->first) 1094 topa = buf->last; 1095 else 1096 topa = list_prev_entry(topa, list); 1097 1098 tp = topa_to_page(topa); 1099 1100 return &tp->table[topa->last - 1]; 1101 } 1102 1103 /** 1104 * pt_buffer_reset_markers() - place interrupt and stop bits in the buffer 1105 * @buf: PT buffer. 1106 * @handle: Current output handle. 1107 * 1108 * Place INT and STOP marks to prevent overwriting old data that the consumer 1109 * hasn't yet collected and waking up the consumer after a certain fraction of 1110 * the buffer has filled up. Only needed and sensible for non-snapshot counters. 1111 * 1112 * This obviously relies on buf::head to figure out buffer markers, so it has 1113 * to be called after pt_buffer_reset_offsets() and before the hardware tracing 1114 * is enabled. 1115 */ 1116 static int pt_buffer_reset_markers(struct pt_buffer *buf, 1117 struct perf_output_handle *handle) 1118 1119 { 1120 unsigned long head = local64_read(&buf->head); 1121 unsigned long idx, npages, wakeup; 1122 1123 if (buf->single) 1124 return 0; 1125 1126 /* can't stop in the middle of an output region */ 1127 if (buf->output_off + handle->size + 1 < pt_buffer_region_size(buf)) { 1128 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); 1129 return -EINVAL; 1130 } 1131 1132 1133 /* single entry ToPA is handled by marking all regions STOP=1 INT=1 */ 1134 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) 1135 return 0; 1136 1137 /* clear STOP and INT from current entry */ 1138 if (buf->stop_te) { 1139 buf->stop_te->stop = 0; 1140 buf->stop_te->intr = 0; 1141 } 1142 1143 if (buf->intr_te) 1144 buf->intr_te->intr = 0; 1145 1146 /* how many pages till the STOP marker */ 1147 npages = handle->size >> PAGE_SHIFT; 1148 1149 /* if it's on a page boundary, fill up one more page */ 1150 if (!offset_in_page(head + handle->size + 1)) 1151 npages++; 1152 1153 idx = (head >> PAGE_SHIFT) + npages; 1154 idx &= buf->nr_pages - 1; 1155 1156 if (idx != buf->stop_pos) { 1157 buf->stop_pos = idx; 1158 buf->stop_te = pt_topa_entry_for_page(buf, idx); 1159 buf->stop_te = pt_topa_prev_entry(buf, buf->stop_te); 1160 } 1161 1162 wakeup = handle->wakeup >> PAGE_SHIFT; 1163 1164 /* in the worst case, wake up the consumer one page before hard stop */ 1165 idx = (head >> PAGE_SHIFT) + npages - 1; 1166 if (idx > wakeup) 1167 idx = wakeup; 1168 1169 idx &= buf->nr_pages - 1; 1170 if (idx != buf->intr_pos) { 1171 buf->intr_pos = idx; 1172 buf->intr_te = pt_topa_entry_for_page(buf, idx); 1173 buf->intr_te = pt_topa_prev_entry(buf, buf->intr_te); 1174 } 1175 1176 buf->stop_te->stop = 1; 1177 buf->stop_te->intr = 1; 1178 buf->intr_te->intr = 1; 1179 1180 return 0; 1181 } 1182 1183 /** 1184 * pt_buffer_reset_offsets() - adjust buffer's write pointers from aux_head 1185 * @buf: PT buffer. 1186 * @head: Write pointer (aux_head) from AUX buffer. 1187 * 1188 * Find the ToPA table and entry corresponding to given @head and set buffer's 1189 * "current" pointers accordingly. This is done after we have obtained the 1190 * current aux_head position from a successful call to perf_aux_output_begin() 1191 * to make sure the hardware is writing to the right place. 1192 * 1193 * This function modifies buf::{cur,cur_idx,output_off} that will be programmed 1194 * into PT msrs when the tracing is enabled and buf::head and buf::data_size, 1195 * which are used to determine INT and STOP markers' locations by a subsequent 1196 * call to pt_buffer_reset_markers(). 1197 */ 1198 static void pt_buffer_reset_offsets(struct pt_buffer *buf, unsigned long head) 1199 { 1200 struct topa_page *cur_tp; 1201 struct topa_entry *te; 1202 int pg; 1203 1204 if (buf->snapshot) 1205 head &= (buf->nr_pages << PAGE_SHIFT) - 1; 1206 1207 if (!buf->single) { 1208 pg = (head >> PAGE_SHIFT) & (buf->nr_pages - 1); 1209 te = pt_topa_entry_for_page(buf, pg); 1210 1211 cur_tp = topa_entry_to_page(te); 1212 buf->cur = &cur_tp->topa; 1213 buf->cur_idx = te - TOPA_ENTRY(buf->cur, 0); 1214 buf->output_off = head & (pt_buffer_region_size(buf) - 1); 1215 } else { 1216 buf->output_off = head; 1217 } 1218 1219 local64_set(&buf->head, head); 1220 local_set(&buf->data_size, 0); 1221 } 1222 1223 /** 1224 * pt_buffer_fini_topa() - deallocate ToPA structure of a buffer 1225 * @buf: PT buffer. 1226 */ 1227 static void pt_buffer_fini_topa(struct pt_buffer *buf) 1228 { 1229 struct topa *topa, *iter; 1230 1231 if (buf->single) 1232 return; 1233 1234 list_for_each_entry_safe(topa, iter, &buf->tables, list) { 1235 /* 1236 * right now, this is in free_aux() path only, so 1237 * no need to unlink this table from the list 1238 */ 1239 topa_free(topa); 1240 } 1241 } 1242 1243 /** 1244 * pt_buffer_init_topa() - initialize ToPA table for pt buffer 1245 * @buf: PT buffer. 1246 * @cpu: CPU on which to allocate. 1247 * @nr_pages: No. of pages to allocate. 1248 * @gfp: Allocation flags. 1249 * 1250 * Return: 0 on success or error code. 1251 */ 1252 static int pt_buffer_init_topa(struct pt_buffer *buf, int cpu, 1253 unsigned long nr_pages, gfp_t gfp) 1254 { 1255 struct topa *topa; 1256 int err; 1257 1258 topa = topa_alloc(cpu, gfp); 1259 if (!topa) 1260 return -ENOMEM; 1261 1262 topa_insert_table(buf, topa); 1263 1264 while (buf->nr_pages < nr_pages) { 1265 err = topa_insert_pages(buf, cpu, gfp); 1266 if (err) { 1267 pt_buffer_fini_topa(buf); 1268 return -ENOMEM; 1269 } 1270 } 1271 1272 /* link last table to the first one, unless we're double buffering */ 1273 if (intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) { 1274 TOPA_ENTRY(buf->last, -1)->base = topa_pfn(buf->first); 1275 TOPA_ENTRY(buf->last, -1)->end = 1; 1276 } 1277 1278 pt_topa_dump(buf); 1279 return 0; 1280 } 1281 1282 static int pt_buffer_try_single(struct pt_buffer *buf, int nr_pages) 1283 { 1284 struct page *p = virt_to_page(buf->data_pages[0]); 1285 int ret = -ENOTSUPP, order = 0; 1286 1287 /* 1288 * We can use single range output mode 1289 * + in snapshot mode, where we don't need interrupts; 1290 * + if the hardware supports it; 1291 * + if the entire buffer is one contiguous allocation. 1292 */ 1293 if (!buf->snapshot) 1294 goto out; 1295 1296 if (!intel_pt_validate_hw_cap(PT_CAP_single_range_output)) 1297 goto out; 1298 1299 if (PagePrivate(p)) 1300 order = page_private(p); 1301 1302 if (1 << order != nr_pages) 1303 goto out; 1304 1305 /* 1306 * Some processors cannot always support single range for more than 1307 * 4KB - refer errata TGL052, ADL037 and RPL017. Future processors might 1308 * also be affected, so for now rather than trying to keep track of 1309 * which ones, just disable it for all. 1310 */ 1311 if (nr_pages > 1) 1312 goto out; 1313 1314 buf->single = true; 1315 buf->nr_pages = nr_pages; 1316 ret = 0; 1317 out: 1318 return ret; 1319 } 1320 1321 /** 1322 * pt_buffer_setup_aux() - set up topa tables for a PT buffer 1323 * @event: Performance event 1324 * @pages: Array of pointers to buffer pages passed from perf core. 1325 * @nr_pages: Number of pages in the buffer. 1326 * @snapshot: If this is a snapshot/overwrite counter. 1327 * 1328 * This is a pmu::setup_aux callback that sets up ToPA tables and all the 1329 * bookkeeping for an AUX buffer. 1330 * 1331 * Return: Our private PT buffer structure. 1332 */ 1333 static void * 1334 pt_buffer_setup_aux(struct perf_event *event, void **pages, 1335 int nr_pages, bool snapshot) 1336 { 1337 struct pt_buffer *buf; 1338 int node, ret, cpu = event->cpu; 1339 1340 if (!nr_pages) 1341 return NULL; 1342 1343 /* 1344 * Only support AUX sampling in snapshot mode, where we don't 1345 * generate NMIs. 1346 */ 1347 if (event->attr.aux_sample_size && !snapshot) 1348 return NULL; 1349 1350 if (cpu == -1) 1351 cpu = raw_smp_processor_id(); 1352 node = cpu_to_node(cpu); 1353 1354 buf = kzalloc_node(sizeof(struct pt_buffer), GFP_KERNEL, node); 1355 if (!buf) 1356 return NULL; 1357 1358 buf->snapshot = snapshot; 1359 buf->data_pages = pages; 1360 buf->stop_pos = -1; 1361 buf->intr_pos = -1; 1362 1363 INIT_LIST_HEAD(&buf->tables); 1364 1365 ret = pt_buffer_try_single(buf, nr_pages); 1366 if (!ret) 1367 return buf; 1368 1369 ret = pt_buffer_init_topa(buf, cpu, nr_pages, GFP_KERNEL); 1370 if (ret) { 1371 kfree(buf); 1372 return NULL; 1373 } 1374 1375 return buf; 1376 } 1377 1378 /** 1379 * pt_buffer_free_aux() - perf AUX deallocation path callback 1380 * @data: PT buffer. 1381 */ 1382 static void pt_buffer_free_aux(void *data) 1383 { 1384 struct pt_buffer *buf = data; 1385 1386 pt_buffer_fini_topa(buf); 1387 kfree(buf); 1388 } 1389 1390 static int pt_addr_filters_init(struct perf_event *event) 1391 { 1392 struct pt_filters *filters; 1393 int node = event->cpu == -1 ? -1 : cpu_to_node(event->cpu); 1394 1395 if (!intel_pt_validate_hw_cap(PT_CAP_num_address_ranges)) 1396 return 0; 1397 1398 filters = kzalloc_node(sizeof(struct pt_filters), GFP_KERNEL, node); 1399 if (!filters) 1400 return -ENOMEM; 1401 1402 if (event->parent) 1403 memcpy(filters, event->parent->hw.addr_filters, 1404 sizeof(*filters)); 1405 1406 event->hw.addr_filters = filters; 1407 1408 return 0; 1409 } 1410 1411 static void pt_addr_filters_fini(struct perf_event *event) 1412 { 1413 kfree(event->hw.addr_filters); 1414 event->hw.addr_filters = NULL; 1415 } 1416 1417 #ifdef CONFIG_X86_64 1418 /* Clamp to a canonical address greater-than-or-equal-to the address given */ 1419 static u64 clamp_to_ge_canonical_addr(u64 vaddr, u8 vaddr_bits) 1420 { 1421 return __is_canonical_address(vaddr, vaddr_bits) ? 1422 vaddr : 1423 -BIT_ULL(vaddr_bits - 1); 1424 } 1425 1426 /* Clamp to a canonical address less-than-or-equal-to the address given */ 1427 static u64 clamp_to_le_canonical_addr(u64 vaddr, u8 vaddr_bits) 1428 { 1429 return __is_canonical_address(vaddr, vaddr_bits) ? 1430 vaddr : 1431 BIT_ULL(vaddr_bits - 1) - 1; 1432 } 1433 #else 1434 #define clamp_to_ge_canonical_addr(x, y) (x) 1435 #define clamp_to_le_canonical_addr(x, y) (x) 1436 #endif 1437 1438 static int pt_event_addr_filters_validate(struct list_head *filters) 1439 { 1440 struct perf_addr_filter *filter; 1441 int range = 0; 1442 1443 list_for_each_entry(filter, filters, entry) { 1444 /* 1445 * PT doesn't support single address triggers and 1446 * 'start' filters. 1447 */ 1448 if (!filter->size || 1449 filter->action == PERF_ADDR_FILTER_ACTION_START) 1450 return -EOPNOTSUPP; 1451 1452 if (++range > intel_pt_validate_hw_cap(PT_CAP_num_address_ranges)) 1453 return -EOPNOTSUPP; 1454 } 1455 1456 return 0; 1457 } 1458 1459 static void pt_event_addr_filters_sync(struct perf_event *event) 1460 { 1461 struct perf_addr_filters_head *head = perf_event_addr_filters(event); 1462 unsigned long msr_a, msr_b; 1463 struct perf_addr_filter_range *fr = event->addr_filter_ranges; 1464 struct pt_filters *filters = event->hw.addr_filters; 1465 struct perf_addr_filter *filter; 1466 int range = 0; 1467 1468 if (!filters) 1469 return; 1470 1471 list_for_each_entry(filter, &head->list, entry) { 1472 if (filter->path.dentry && !fr[range].start) { 1473 msr_a = msr_b = 0; 1474 } else { 1475 unsigned long n = fr[range].size - 1; 1476 unsigned long a = fr[range].start; 1477 unsigned long b; 1478 1479 if (a > ULONG_MAX - n) 1480 b = ULONG_MAX; 1481 else 1482 b = a + n; 1483 /* 1484 * Apply the offset. 64-bit addresses written to the 1485 * MSRs must be canonical, but the range can encompass 1486 * non-canonical addresses. Since software cannot 1487 * execute at non-canonical addresses, adjusting to 1488 * canonical addresses does not affect the result of the 1489 * address filter. 1490 */ 1491 msr_a = clamp_to_ge_canonical_addr(a, boot_cpu_data.x86_virt_bits); 1492 msr_b = clamp_to_le_canonical_addr(b, boot_cpu_data.x86_virt_bits); 1493 if (msr_b < msr_a) 1494 msr_a = msr_b = 0; 1495 } 1496 1497 filters->filter[range].msr_a = msr_a; 1498 filters->filter[range].msr_b = msr_b; 1499 if (filter->action == PERF_ADDR_FILTER_ACTION_FILTER) 1500 filters->filter[range].config = 1; 1501 else 1502 filters->filter[range].config = 2; 1503 range++; 1504 } 1505 1506 filters->nr_filters = range; 1507 } 1508 1509 /** 1510 * intel_pt_interrupt() - PT PMI handler 1511 */ 1512 void intel_pt_interrupt(void) 1513 { 1514 struct pt *pt = this_cpu_ptr(&pt_ctx); 1515 struct pt_buffer *buf; 1516 struct perf_event *event = pt->handle.event; 1517 1518 /* 1519 * There may be a dangling PT bit in the interrupt status register 1520 * after PT has been disabled by pt_event_stop(). Make sure we don't 1521 * do anything (particularly, re-enable) for this event here. 1522 */ 1523 if (!READ_ONCE(pt->handle_nmi)) 1524 return; 1525 1526 if (!event) 1527 return; 1528 1529 pt_config_stop(event); 1530 1531 buf = perf_get_aux(&pt->handle); 1532 if (!buf) 1533 return; 1534 1535 pt_read_offset(buf); 1536 1537 pt_handle_status(pt); 1538 1539 pt_update_head(pt); 1540 1541 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0)); 1542 1543 event->hw.state |= PERF_HES_UPTODATE; 1544 1545 if (!(event->hw.state & PERF_HES_STOPPED)) { 1546 int ret; 1547 1548 buf = perf_aux_output_begin(&pt->handle, event); 1549 if (!buf) { 1550 event->hw.state |= PERF_HES_STOPPED; 1551 WRITE_ONCE(pt->resume_allowed, 0); 1552 return; 1553 } 1554 1555 pt_buffer_reset_offsets(buf, pt->handle.head); 1556 /* snapshot counters don't use PMI, so it's safe */ 1557 ret = pt_buffer_reset_markers(buf, &pt->handle); 1558 if (ret) { 1559 perf_aux_output_end(&pt->handle, 0); 1560 WRITE_ONCE(pt->resume_allowed, 0); 1561 return; 1562 } 1563 1564 pt_config_buffer(buf); 1565 pt_config_start(event); 1566 1567 event->hw.state &= ~PERF_HES_UPTODATE; 1568 } 1569 } 1570 1571 void intel_pt_handle_vmx(int on) 1572 { 1573 struct pt *pt = this_cpu_ptr(&pt_ctx); 1574 struct perf_event *event; 1575 unsigned long flags; 1576 1577 /* PT plays nice with VMX, do nothing */ 1578 if (pt_pmu.vmx) 1579 return; 1580 1581 /* 1582 * VMXON will clear RTIT_CTL.TraceEn; we need to make 1583 * sure to not try to set it while VMX is on. Disable 1584 * interrupts to avoid racing with pmu callbacks; 1585 * concurrent PMI should be handled fine. 1586 */ 1587 local_irq_save(flags); 1588 WRITE_ONCE(pt->vmx_on, on); 1589 1590 /* 1591 * If an AUX transaction is in progress, it will contain 1592 * gap(s), so flag it PARTIAL to inform the user. 1593 */ 1594 event = pt->handle.event; 1595 if (event) 1596 perf_aux_output_flag(&pt->handle, 1597 PERF_AUX_FLAG_PARTIAL); 1598 1599 /* Turn PTs back on */ 1600 if (!on && event) 1601 wrmsrq(MSR_IA32_RTIT_CTL, event->hw.aux_config); 1602 1603 local_irq_restore(flags); 1604 } 1605 1606 /* 1607 * PMU callbacks 1608 */ 1609 1610 static void pt_event_start(struct perf_event *event, int mode) 1611 { 1612 struct hw_perf_event *hwc = &event->hw; 1613 struct pt *pt = this_cpu_ptr(&pt_ctx); 1614 struct pt_buffer *buf; 1615 1616 if (mode & PERF_EF_RESUME) { 1617 if (READ_ONCE(pt->resume_allowed)) { 1618 u64 status; 1619 1620 /* 1621 * Only if the trace is not active and the error and 1622 * stopped bits are clear, is it safe to start, but a 1623 * PMI might have just cleared these, so resume_allowed 1624 * must be checked again also. 1625 */ 1626 rdmsrq(MSR_IA32_RTIT_STATUS, status); 1627 if (!(status & (RTIT_STATUS_TRIGGEREN | 1628 RTIT_STATUS_ERROR | 1629 RTIT_STATUS_STOPPED)) && 1630 READ_ONCE(pt->resume_allowed)) 1631 pt_config_start(event); 1632 } 1633 return; 1634 } 1635 1636 /* 1637 * Re-start subsequent to a call to pt_event_stop() without the 1638 * PERF_EF_UPDATE flag. Absence of PERF_HES_UPTODATE indicates that 1639 * perf_aux_output_begin() has already been called. This path can 1640 * come about only in snapshot/overwrite mode - see pt_event_stop(). 1641 */ 1642 if (!(hwc->state & PERF_HES_UPTODATE)) { 1643 hwc->state &= ~PERF_HES_STOPPED; 1644 pt_config_enable(event); 1645 return; 1646 } 1647 1648 buf = perf_aux_output_begin(&pt->handle, event); 1649 if (!buf) 1650 goto fail_stop; 1651 1652 pt_buffer_reset_offsets(buf, pt->handle.head); 1653 if (!buf->snapshot) { 1654 if (pt_buffer_reset_markers(buf, &pt->handle)) 1655 goto fail_end_stop; 1656 } 1657 1658 hwc->state &= ~(PERF_HES_STOPPED | PERF_HES_UPTODATE); 1659 1660 pt_config_buffer(buf); 1661 pt_config(event); 1662 1663 return; 1664 1665 fail_end_stop: 1666 perf_aux_output_end(&pt->handle, 0); 1667 fail_stop: 1668 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 1669 } 1670 1671 static void pt_event_stop(struct perf_event *event, int mode) 1672 { 1673 struct pt *pt = this_cpu_ptr(&pt_ctx); 1674 struct pt_buffer *buf; 1675 1676 if (mode & PERF_EF_PAUSE) { 1677 if (READ_ONCE(pt->pause_allowed)) 1678 pt_config_stop(event); 1679 return; 1680 } 1681 1682 /* 1683 * Protect against the PMI racing with disabling wrmsr, 1684 * see comment in intel_pt_interrupt(). 1685 */ 1686 WRITE_ONCE(pt->handle_nmi, 0); 1687 barrier(); 1688 1689 /* 1690 * Prevent a resume from attempting to restart tracing, or a pause 1691 * during a subsequent start. Do this after clearing handle_nmi so that 1692 * pt_event_snapshot_aux() will not re-allow them. 1693 */ 1694 WRITE_ONCE(pt->pause_allowed, 0); 1695 WRITE_ONCE(pt->resume_allowed, 0); 1696 barrier(); 1697 1698 pt_config_stop(event); 1699 1700 event->hw.state |= PERF_HES_STOPPED; 1701 1702 if (event->hw.state & PERF_HES_UPTODATE) 1703 return; 1704 1705 buf = perf_get_aux(&pt->handle); 1706 if (!buf) 1707 return; 1708 1709 /* 1710 * When not in snapshot/overwrite mode, there is a possibility that the 1711 * buffer has run out of space. The accounting for that is handled by 1712 * the update, so always update in that case. Snapshot/overwrite mode is 1713 * treated differently to allow for pt_event_snapshot_aux() which can 1714 * still get called if the AUX-sampling event is not stopped until after 1715 * PT is stopped. 1716 */ 1717 if ((mode & PERF_EF_UPDATE) || !buf->snapshot) { 1718 if (WARN_ON_ONCE(pt->handle.event != event)) 1719 return; 1720 1721 pt_read_offset(buf); 1722 1723 pt_handle_status(pt); 1724 1725 pt_update_head(pt); 1726 1727 if (buf->snapshot) 1728 pt->handle.head = 1729 local_xchg(&buf->data_size, 1730 buf->nr_pages << PAGE_SHIFT); 1731 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0)); 1732 event->hw.state |= PERF_HES_UPTODATE; 1733 } 1734 } 1735 1736 static long pt_event_snapshot_aux(struct perf_event *event, 1737 struct perf_output_handle *handle, 1738 unsigned long size) 1739 { 1740 struct pt *pt = this_cpu_ptr(&pt_ctx); 1741 struct pt_buffer *buf = perf_get_aux(&pt->handle); 1742 unsigned long from = 0, to; 1743 long ret; 1744 1745 if (WARN_ON_ONCE(!buf)) 1746 return 0; 1747 1748 /* 1749 * Sampling is only allowed on snapshot events; 1750 * see pt_buffer_setup_aux(). 1751 */ 1752 if (WARN_ON_ONCE(!buf->snapshot)) 1753 return 0; 1754 1755 /* Prevent pause/resume from attempting to start/stop tracing */ 1756 WRITE_ONCE(pt->pause_allowed, 0); 1757 WRITE_ONCE(pt->resume_allowed, 0); 1758 barrier(); 1759 /* 1760 * There is no PT interrupt in this mode, so stop the trace and it will 1761 * remain stopped while the buffer is copied. 1762 */ 1763 pt_config_stop(event); 1764 pt_read_offset(buf); 1765 pt_update_head(pt); 1766 1767 to = local_read(&buf->data_size); 1768 if (to < size) 1769 from = buf->nr_pages << PAGE_SHIFT; 1770 from += to - size; 1771 1772 ret = perf_output_copy_aux(&pt->handle, handle, from, to); 1773 1774 /* 1775 * Here, handle_nmi tells us if the tracing was on. 1776 * If the tracing was on, restart it. 1777 */ 1778 if (READ_ONCE(pt->handle_nmi)) { 1779 WRITE_ONCE(pt->resume_allowed, 1); 1780 barrier(); 1781 pt_config_start(event); 1782 barrier(); 1783 WRITE_ONCE(pt->pause_allowed, 1); 1784 } 1785 1786 return ret; 1787 } 1788 1789 static void pt_event_del(struct perf_event *event, int mode) 1790 { 1791 pt_event_stop(event, PERF_EF_UPDATE); 1792 } 1793 1794 static int pt_event_add(struct perf_event *event, int mode) 1795 { 1796 struct pt *pt = this_cpu_ptr(&pt_ctx); 1797 struct hw_perf_event *hwc = &event->hw; 1798 int ret = -EBUSY; 1799 1800 if (pt->handle.event) 1801 goto fail; 1802 1803 event->hw.state |= PERF_HES_UPTODATE; 1804 1805 if (mode & PERF_EF_START) { 1806 pt_event_start(event, 0); 1807 ret = -EINVAL; 1808 if (hwc->state & PERF_HES_STOPPED) 1809 goto fail; 1810 } else { 1811 hwc->state |= PERF_HES_STOPPED; 1812 } 1813 1814 ret = 0; 1815 fail: 1816 1817 return ret; 1818 } 1819 1820 static void pt_event_read(struct perf_event *event) 1821 { 1822 } 1823 1824 static void pt_event_destroy(struct perf_event *event) 1825 { 1826 pt_addr_filters_fini(event); 1827 x86_del_exclusive(x86_lbr_exclusive_pt); 1828 } 1829 1830 static int pt_event_init(struct perf_event *event) 1831 { 1832 if (event->attr.type != pt_pmu.pmu.type) 1833 return -ENOENT; 1834 1835 if (!pt_event_valid(event)) 1836 return -EINVAL; 1837 1838 if (x86_add_exclusive(x86_lbr_exclusive_pt)) 1839 return -EBUSY; 1840 1841 if (pt_addr_filters_init(event)) { 1842 x86_del_exclusive(x86_lbr_exclusive_pt); 1843 return -ENOMEM; 1844 } 1845 1846 event->destroy = pt_event_destroy; 1847 1848 return 0; 1849 } 1850 1851 void cpu_emergency_stop_pt(void) 1852 { 1853 struct pt *pt = this_cpu_ptr(&pt_ctx); 1854 1855 if (pt->handle.event) 1856 pt_event_stop(pt->handle.event, PERF_EF_UPDATE); 1857 } 1858 1859 int is_intel_pt_event(struct perf_event *event) 1860 { 1861 return event->pmu == &pt_pmu.pmu; 1862 } 1863 1864 static __init int pt_init(void) 1865 { 1866 int ret, cpu, prior_warn = 0; 1867 1868 BUILD_BUG_ON(sizeof(struct topa) > PAGE_SIZE); 1869 1870 if (!boot_cpu_has(X86_FEATURE_INTEL_PT)) 1871 return -ENODEV; 1872 1873 cpus_read_lock(); 1874 for_each_online_cpu(cpu) { 1875 u64 ctl; 1876 1877 ret = rdmsrq_safe_on_cpu(cpu, MSR_IA32_RTIT_CTL, &ctl); 1878 if (!ret && (ctl & RTIT_CTL_TRACEEN)) 1879 prior_warn++; 1880 } 1881 cpus_read_unlock(); 1882 1883 if (prior_warn) { 1884 x86_add_exclusive(x86_lbr_exclusive_pt); 1885 pr_warn("PT is enabled at boot time, doing nothing\n"); 1886 1887 return -EBUSY; 1888 } 1889 1890 ret = pt_pmu_hw_init(); 1891 if (ret) 1892 return ret; 1893 1894 if (!intel_pt_validate_hw_cap(PT_CAP_topa_output)) { 1895 pr_warn("ToPA output is not supported on this CPU\n"); 1896 return -ENODEV; 1897 } 1898 1899 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) 1900 pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG; 1901 else 1902 pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_PREFER_LARGE; 1903 1904 pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | 1905 PERF_PMU_CAP_ITRACE | 1906 PERF_PMU_CAP_AUX_PAUSE; 1907 pt_pmu.pmu.attr_groups = pt_attr_groups; 1908 pt_pmu.pmu.task_ctx_nr = perf_sw_context; 1909 pt_pmu.pmu.event_init = pt_event_init; 1910 pt_pmu.pmu.add = pt_event_add; 1911 pt_pmu.pmu.del = pt_event_del; 1912 pt_pmu.pmu.start = pt_event_start; 1913 pt_pmu.pmu.stop = pt_event_stop; 1914 pt_pmu.pmu.snapshot_aux = pt_event_snapshot_aux; 1915 pt_pmu.pmu.read = pt_event_read; 1916 pt_pmu.pmu.setup_aux = pt_buffer_setup_aux; 1917 pt_pmu.pmu.free_aux = pt_buffer_free_aux; 1918 pt_pmu.pmu.addr_filters_sync = pt_event_addr_filters_sync; 1919 pt_pmu.pmu.addr_filters_validate = pt_event_addr_filters_validate; 1920 pt_pmu.pmu.nr_addr_filters = 1921 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges); 1922 1923 ret = perf_pmu_register(&pt_pmu.pmu, "intel_pt", -1); 1924 1925 return ret; 1926 } 1927 arch_initcall(pt_init); 1928