1 /* 2 * Intel(R) Processor Trace PMU driver for perf 3 * Copyright (c) 2013-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * Intel PT is specified in the Intel Architecture Instruction Set Extensions 15 * Programming Reference: 16 * http://software.intel.com/en-us/intel-isa-extensions 17 */ 18 19 #undef DEBUG 20 21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 22 23 #include <linux/types.h> 24 #include <linux/slab.h> 25 #include <linux/device.h> 26 27 #include <asm/perf_event.h> 28 #include <asm/insn.h> 29 #include <asm/io.h> 30 #include <asm/intel_pt.h> 31 32 #include "../perf_event.h" 33 #include "pt.h" 34 35 static DEFINE_PER_CPU(struct pt, pt_ctx); 36 37 static struct pt_pmu pt_pmu; 38 39 enum cpuid_regs { 40 CR_EAX = 0, 41 CR_ECX, 42 CR_EDX, 43 CR_EBX 44 }; 45 46 /* 47 * Capabilities of Intel PT hardware, such as number of address bits or 48 * supported output schemes, are cached and exported to userspace as "caps" 49 * attribute group of pt pmu device 50 * (/sys/bus/event_source/devices/intel_pt/caps/) so that userspace can store 51 * relevant bits together with intel_pt traces. 52 * 53 * These are necessary for both trace decoding (payloads_lip, contains address 54 * width encoded in IP-related packets), and event configuration (bitmasks with 55 * permitted values for certain bit fields). 56 */ 57 #define PT_CAP(_n, _l, _r, _m) \ 58 [PT_CAP_ ## _n] = { .name = __stringify(_n), .leaf = _l, \ 59 .reg = _r, .mask = _m } 60 61 static struct pt_cap_desc { 62 const char *name; 63 u32 leaf; 64 u8 reg; 65 u32 mask; 66 } pt_caps[] = { 67 PT_CAP(max_subleaf, 0, CR_EAX, 0xffffffff), 68 PT_CAP(cr3_filtering, 0, CR_EBX, BIT(0)), 69 PT_CAP(psb_cyc, 0, CR_EBX, BIT(1)), 70 PT_CAP(mtc, 0, CR_EBX, BIT(3)), 71 PT_CAP(topa_output, 0, CR_ECX, BIT(0)), 72 PT_CAP(topa_multiple_entries, 0, CR_ECX, BIT(1)), 73 PT_CAP(single_range_output, 0, CR_ECX, BIT(2)), 74 PT_CAP(payloads_lip, 0, CR_ECX, BIT(31)), 75 PT_CAP(mtc_periods, 1, CR_EAX, 0xffff0000), 76 PT_CAP(cycle_thresholds, 1, CR_EBX, 0xffff), 77 PT_CAP(psb_periods, 1, CR_EBX, 0xffff0000), 78 }; 79 80 static u32 pt_cap_get(enum pt_capabilities cap) 81 { 82 struct pt_cap_desc *cd = &pt_caps[cap]; 83 u32 c = pt_pmu.caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg]; 84 unsigned int shift = __ffs(cd->mask); 85 86 return (c & cd->mask) >> shift; 87 } 88 89 static ssize_t pt_cap_show(struct device *cdev, 90 struct device_attribute *attr, 91 char *buf) 92 { 93 struct dev_ext_attribute *ea = 94 container_of(attr, struct dev_ext_attribute, attr); 95 enum pt_capabilities cap = (long)ea->var; 96 97 return snprintf(buf, PAGE_SIZE, "%x\n", pt_cap_get(cap)); 98 } 99 100 static struct attribute_group pt_cap_group = { 101 .name = "caps", 102 }; 103 104 PMU_FORMAT_ATTR(cyc, "config:1" ); 105 PMU_FORMAT_ATTR(mtc, "config:9" ); 106 PMU_FORMAT_ATTR(tsc, "config:10" ); 107 PMU_FORMAT_ATTR(noretcomp, "config:11" ); 108 PMU_FORMAT_ATTR(mtc_period, "config:14-17" ); 109 PMU_FORMAT_ATTR(cyc_thresh, "config:19-22" ); 110 PMU_FORMAT_ATTR(psb_period, "config:24-27" ); 111 112 static struct attribute *pt_formats_attr[] = { 113 &format_attr_cyc.attr, 114 &format_attr_mtc.attr, 115 &format_attr_tsc.attr, 116 &format_attr_noretcomp.attr, 117 &format_attr_mtc_period.attr, 118 &format_attr_cyc_thresh.attr, 119 &format_attr_psb_period.attr, 120 NULL, 121 }; 122 123 static struct attribute_group pt_format_group = { 124 .name = "format", 125 .attrs = pt_formats_attr, 126 }; 127 128 static const struct attribute_group *pt_attr_groups[] = { 129 &pt_cap_group, 130 &pt_format_group, 131 NULL, 132 }; 133 134 static int __init pt_pmu_hw_init(void) 135 { 136 struct dev_ext_attribute *de_attrs; 137 struct attribute **attrs; 138 size_t size; 139 int ret; 140 long i; 141 142 attrs = NULL; 143 144 for (i = 0; i < PT_CPUID_LEAVES; i++) { 145 cpuid_count(20, i, 146 &pt_pmu.caps[CR_EAX + i*PT_CPUID_REGS_NUM], 147 &pt_pmu.caps[CR_EBX + i*PT_CPUID_REGS_NUM], 148 &pt_pmu.caps[CR_ECX + i*PT_CPUID_REGS_NUM], 149 &pt_pmu.caps[CR_EDX + i*PT_CPUID_REGS_NUM]); 150 } 151 152 ret = -ENOMEM; 153 size = sizeof(struct attribute *) * (ARRAY_SIZE(pt_caps)+1); 154 attrs = kzalloc(size, GFP_KERNEL); 155 if (!attrs) 156 goto fail; 157 158 size = sizeof(struct dev_ext_attribute) * (ARRAY_SIZE(pt_caps)+1); 159 de_attrs = kzalloc(size, GFP_KERNEL); 160 if (!de_attrs) 161 goto fail; 162 163 for (i = 0; i < ARRAY_SIZE(pt_caps); i++) { 164 struct dev_ext_attribute *de_attr = de_attrs + i; 165 166 de_attr->attr.attr.name = pt_caps[i].name; 167 168 sysfs_attr_init(&de_attr->attr.attr); 169 170 de_attr->attr.attr.mode = S_IRUGO; 171 de_attr->attr.show = pt_cap_show; 172 de_attr->var = (void *)i; 173 174 attrs[i] = &de_attr->attr.attr; 175 } 176 177 pt_cap_group.attrs = attrs; 178 179 return 0; 180 181 fail: 182 kfree(attrs); 183 184 return ret; 185 } 186 187 #define RTIT_CTL_CYC_PSB (RTIT_CTL_CYCLEACC | \ 188 RTIT_CTL_CYC_THRESH | \ 189 RTIT_CTL_PSB_FREQ) 190 191 #define RTIT_CTL_MTC (RTIT_CTL_MTC_EN | \ 192 RTIT_CTL_MTC_RANGE) 193 194 #define PT_CONFIG_MASK (RTIT_CTL_TSC_EN | \ 195 RTIT_CTL_DISRETC | \ 196 RTIT_CTL_CYC_PSB | \ 197 RTIT_CTL_MTC) 198 199 static bool pt_event_valid(struct perf_event *event) 200 { 201 u64 config = event->attr.config; 202 u64 allowed, requested; 203 204 if ((config & PT_CONFIG_MASK) != config) 205 return false; 206 207 if (config & RTIT_CTL_CYC_PSB) { 208 if (!pt_cap_get(PT_CAP_psb_cyc)) 209 return false; 210 211 allowed = pt_cap_get(PT_CAP_psb_periods); 212 requested = (config & RTIT_CTL_PSB_FREQ) >> 213 RTIT_CTL_PSB_FREQ_OFFSET; 214 if (requested && (!(allowed & BIT(requested)))) 215 return false; 216 217 allowed = pt_cap_get(PT_CAP_cycle_thresholds); 218 requested = (config & RTIT_CTL_CYC_THRESH) >> 219 RTIT_CTL_CYC_THRESH_OFFSET; 220 if (requested && (!(allowed & BIT(requested)))) 221 return false; 222 } 223 224 if (config & RTIT_CTL_MTC) { 225 /* 226 * In the unlikely case that CPUID lists valid mtc periods, 227 * but not the mtc capability, drop out here. 228 * 229 * Spec says that setting mtc period bits while mtc bit in 230 * CPUID is 0 will #GP, so better safe than sorry. 231 */ 232 if (!pt_cap_get(PT_CAP_mtc)) 233 return false; 234 235 allowed = pt_cap_get(PT_CAP_mtc_periods); 236 if (!allowed) 237 return false; 238 239 requested = (config & RTIT_CTL_MTC_RANGE) >> 240 RTIT_CTL_MTC_RANGE_OFFSET; 241 242 if (!(allowed & BIT(requested))) 243 return false; 244 } 245 246 return true; 247 } 248 249 /* 250 * PT configuration helpers 251 * These all are cpu affine and operate on a local PT 252 */ 253 254 static void pt_config(struct perf_event *event) 255 { 256 u64 reg; 257 258 if (!event->hw.itrace_started) { 259 event->hw.itrace_started = 1; 260 wrmsrl(MSR_IA32_RTIT_STATUS, 0); 261 } 262 263 reg = RTIT_CTL_TOPA | RTIT_CTL_BRANCH_EN | RTIT_CTL_TRACEEN; 264 265 if (!event->attr.exclude_kernel) 266 reg |= RTIT_CTL_OS; 267 if (!event->attr.exclude_user) 268 reg |= RTIT_CTL_USR; 269 270 reg |= (event->attr.config & PT_CONFIG_MASK); 271 272 wrmsrl(MSR_IA32_RTIT_CTL, reg); 273 } 274 275 static void pt_config_start(bool start) 276 { 277 u64 ctl; 278 279 rdmsrl(MSR_IA32_RTIT_CTL, ctl); 280 if (start) 281 ctl |= RTIT_CTL_TRACEEN; 282 else 283 ctl &= ~RTIT_CTL_TRACEEN; 284 wrmsrl(MSR_IA32_RTIT_CTL, ctl); 285 286 /* 287 * A wrmsr that disables trace generation serializes other PT 288 * registers and causes all data packets to be written to memory, 289 * but a fence is required for the data to become globally visible. 290 * 291 * The below WMB, separating data store and aux_head store matches 292 * the consumer's RMB that separates aux_head load and data load. 293 */ 294 if (!start) 295 wmb(); 296 } 297 298 static void pt_config_buffer(void *buf, unsigned int topa_idx, 299 unsigned int output_off) 300 { 301 u64 reg; 302 303 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, virt_to_phys(buf)); 304 305 reg = 0x7f | ((u64)topa_idx << 7) | ((u64)output_off << 32); 306 307 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, reg); 308 } 309 310 /* 311 * Keep ToPA table-related metadata on the same page as the actual table, 312 * taking up a few words from the top 313 */ 314 315 #define TENTS_PER_PAGE (((PAGE_SIZE - 40) / sizeof(struct topa_entry)) - 1) 316 317 /** 318 * struct topa - page-sized ToPA table with metadata at the top 319 * @table: actual ToPA table entries, as understood by PT hardware 320 * @list: linkage to struct pt_buffer's list of tables 321 * @phys: physical address of this page 322 * @offset: offset of the first entry in this table in the buffer 323 * @size: total size of all entries in this table 324 * @last: index of the last initialized entry in this table 325 */ 326 struct topa { 327 struct topa_entry table[TENTS_PER_PAGE]; 328 struct list_head list; 329 u64 phys; 330 u64 offset; 331 size_t size; 332 int last; 333 }; 334 335 /* make -1 stand for the last table entry */ 336 #define TOPA_ENTRY(t, i) ((i) == -1 ? &(t)->table[(t)->last] : &(t)->table[(i)]) 337 338 /** 339 * topa_alloc() - allocate page-sized ToPA table 340 * @cpu: CPU on which to allocate. 341 * @gfp: Allocation flags. 342 * 343 * Return: On success, return the pointer to ToPA table page. 344 */ 345 static struct topa *topa_alloc(int cpu, gfp_t gfp) 346 { 347 int node = cpu_to_node(cpu); 348 struct topa *topa; 349 struct page *p; 350 351 p = alloc_pages_node(node, gfp | __GFP_ZERO, 0); 352 if (!p) 353 return NULL; 354 355 topa = page_address(p); 356 topa->last = 0; 357 topa->phys = page_to_phys(p); 358 359 /* 360 * In case of singe-entry ToPA, always put the self-referencing END 361 * link as the 2nd entry in the table 362 */ 363 if (!pt_cap_get(PT_CAP_topa_multiple_entries)) { 364 TOPA_ENTRY(topa, 1)->base = topa->phys >> TOPA_SHIFT; 365 TOPA_ENTRY(topa, 1)->end = 1; 366 } 367 368 return topa; 369 } 370 371 /** 372 * topa_free() - free a page-sized ToPA table 373 * @topa: Table to deallocate. 374 */ 375 static void topa_free(struct topa *topa) 376 { 377 free_page((unsigned long)topa); 378 } 379 380 /** 381 * topa_insert_table() - insert a ToPA table into a buffer 382 * @buf: PT buffer that's being extended. 383 * @topa: New topa table to be inserted. 384 * 385 * If it's the first table in this buffer, set up buffer's pointers 386 * accordingly; otherwise, add a END=1 link entry to @topa to the current 387 * "last" table and adjust the last table pointer to @topa. 388 */ 389 static void topa_insert_table(struct pt_buffer *buf, struct topa *topa) 390 { 391 struct topa *last = buf->last; 392 393 list_add_tail(&topa->list, &buf->tables); 394 395 if (!buf->first) { 396 buf->first = buf->last = buf->cur = topa; 397 return; 398 } 399 400 topa->offset = last->offset + last->size; 401 buf->last = topa; 402 403 if (!pt_cap_get(PT_CAP_topa_multiple_entries)) 404 return; 405 406 BUG_ON(last->last != TENTS_PER_PAGE - 1); 407 408 TOPA_ENTRY(last, -1)->base = topa->phys >> TOPA_SHIFT; 409 TOPA_ENTRY(last, -1)->end = 1; 410 } 411 412 /** 413 * topa_table_full() - check if a ToPA table is filled up 414 * @topa: ToPA table. 415 */ 416 static bool topa_table_full(struct topa *topa) 417 { 418 /* single-entry ToPA is a special case */ 419 if (!pt_cap_get(PT_CAP_topa_multiple_entries)) 420 return !!topa->last; 421 422 return topa->last == TENTS_PER_PAGE - 1; 423 } 424 425 /** 426 * topa_insert_pages() - create a list of ToPA tables 427 * @buf: PT buffer being initialized. 428 * @gfp: Allocation flags. 429 * 430 * This initializes a list of ToPA tables with entries from 431 * the data_pages provided by rb_alloc_aux(). 432 * 433 * Return: 0 on success or error code. 434 */ 435 static int topa_insert_pages(struct pt_buffer *buf, gfp_t gfp) 436 { 437 struct topa *topa = buf->last; 438 int order = 0; 439 struct page *p; 440 441 p = virt_to_page(buf->data_pages[buf->nr_pages]); 442 if (PagePrivate(p)) 443 order = page_private(p); 444 445 if (topa_table_full(topa)) { 446 topa = topa_alloc(buf->cpu, gfp); 447 if (!topa) 448 return -ENOMEM; 449 450 topa_insert_table(buf, topa); 451 } 452 453 TOPA_ENTRY(topa, -1)->base = page_to_phys(p) >> TOPA_SHIFT; 454 TOPA_ENTRY(topa, -1)->size = order; 455 if (!buf->snapshot && !pt_cap_get(PT_CAP_topa_multiple_entries)) { 456 TOPA_ENTRY(topa, -1)->intr = 1; 457 TOPA_ENTRY(topa, -1)->stop = 1; 458 } 459 460 topa->last++; 461 topa->size += sizes(order); 462 463 buf->nr_pages += 1ul << order; 464 465 return 0; 466 } 467 468 /** 469 * pt_topa_dump() - print ToPA tables and their entries 470 * @buf: PT buffer. 471 */ 472 static void pt_topa_dump(struct pt_buffer *buf) 473 { 474 struct topa *topa; 475 476 list_for_each_entry(topa, &buf->tables, list) { 477 int i; 478 479 pr_debug("# table @%p (%016Lx), off %llx size %zx\n", topa->table, 480 topa->phys, topa->offset, topa->size); 481 for (i = 0; i < TENTS_PER_PAGE; i++) { 482 pr_debug("# entry @%p (%lx sz %u %c%c%c) raw=%16llx\n", 483 &topa->table[i], 484 (unsigned long)topa->table[i].base << TOPA_SHIFT, 485 sizes(topa->table[i].size), 486 topa->table[i].end ? 'E' : ' ', 487 topa->table[i].intr ? 'I' : ' ', 488 topa->table[i].stop ? 'S' : ' ', 489 *(u64 *)&topa->table[i]); 490 if ((pt_cap_get(PT_CAP_topa_multiple_entries) && 491 topa->table[i].stop) || 492 topa->table[i].end) 493 break; 494 } 495 } 496 } 497 498 /** 499 * pt_buffer_advance() - advance to the next output region 500 * @buf: PT buffer. 501 * 502 * Advance the current pointers in the buffer to the next ToPA entry. 503 */ 504 static void pt_buffer_advance(struct pt_buffer *buf) 505 { 506 buf->output_off = 0; 507 buf->cur_idx++; 508 509 if (buf->cur_idx == buf->cur->last) { 510 if (buf->cur == buf->last) 511 buf->cur = buf->first; 512 else 513 buf->cur = list_entry(buf->cur->list.next, struct topa, 514 list); 515 buf->cur_idx = 0; 516 } 517 } 518 519 /** 520 * pt_update_head() - calculate current offsets and sizes 521 * @pt: Per-cpu pt context. 522 * 523 * Update buffer's current write pointer position and data size. 524 */ 525 static void pt_update_head(struct pt *pt) 526 { 527 struct pt_buffer *buf = perf_get_aux(&pt->handle); 528 u64 topa_idx, base, old; 529 530 /* offset of the first region in this table from the beginning of buf */ 531 base = buf->cur->offset + buf->output_off; 532 533 /* offset of the current output region within this table */ 534 for (topa_idx = 0; topa_idx < buf->cur_idx; topa_idx++) 535 base += sizes(buf->cur->table[topa_idx].size); 536 537 if (buf->snapshot) { 538 local_set(&buf->data_size, base); 539 } else { 540 old = (local64_xchg(&buf->head, base) & 541 ((buf->nr_pages << PAGE_SHIFT) - 1)); 542 if (base < old) 543 base += buf->nr_pages << PAGE_SHIFT; 544 545 local_add(base - old, &buf->data_size); 546 } 547 } 548 549 /** 550 * pt_buffer_region() - obtain current output region's address 551 * @buf: PT buffer. 552 */ 553 static void *pt_buffer_region(struct pt_buffer *buf) 554 { 555 return phys_to_virt(buf->cur->table[buf->cur_idx].base << TOPA_SHIFT); 556 } 557 558 /** 559 * pt_buffer_region_size() - obtain current output region's size 560 * @buf: PT buffer. 561 */ 562 static size_t pt_buffer_region_size(struct pt_buffer *buf) 563 { 564 return sizes(buf->cur->table[buf->cur_idx].size); 565 } 566 567 /** 568 * pt_handle_status() - take care of possible status conditions 569 * @pt: Per-cpu pt context. 570 */ 571 static void pt_handle_status(struct pt *pt) 572 { 573 struct pt_buffer *buf = perf_get_aux(&pt->handle); 574 int advance = 0; 575 u64 status; 576 577 rdmsrl(MSR_IA32_RTIT_STATUS, status); 578 579 if (status & RTIT_STATUS_ERROR) { 580 pr_err_ratelimited("ToPA ERROR encountered, trying to recover\n"); 581 pt_topa_dump(buf); 582 status &= ~RTIT_STATUS_ERROR; 583 } 584 585 if (status & RTIT_STATUS_STOPPED) { 586 status &= ~RTIT_STATUS_STOPPED; 587 588 /* 589 * On systems that only do single-entry ToPA, hitting STOP 590 * means we are already losing data; need to let the decoder 591 * know. 592 */ 593 if (!pt_cap_get(PT_CAP_topa_multiple_entries) || 594 buf->output_off == sizes(TOPA_ENTRY(buf->cur, buf->cur_idx)->size)) { 595 local_inc(&buf->lost); 596 advance++; 597 } 598 } 599 600 /* 601 * Also on single-entry ToPA implementations, interrupt will come 602 * before the output reaches its output region's boundary. 603 */ 604 if (!pt_cap_get(PT_CAP_topa_multiple_entries) && !buf->snapshot && 605 pt_buffer_region_size(buf) - buf->output_off <= TOPA_PMI_MARGIN) { 606 void *head = pt_buffer_region(buf); 607 608 /* everything within this margin needs to be zeroed out */ 609 memset(head + buf->output_off, 0, 610 pt_buffer_region_size(buf) - 611 buf->output_off); 612 advance++; 613 } 614 615 if (advance) 616 pt_buffer_advance(buf); 617 618 wrmsrl(MSR_IA32_RTIT_STATUS, status); 619 } 620 621 /** 622 * pt_read_offset() - translate registers into buffer pointers 623 * @buf: PT buffer. 624 * 625 * Set buffer's output pointers from MSR values. 626 */ 627 static void pt_read_offset(struct pt_buffer *buf) 628 { 629 u64 offset, base_topa; 630 631 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, base_topa); 632 buf->cur = phys_to_virt(base_topa); 633 634 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, offset); 635 /* offset within current output region */ 636 buf->output_off = offset >> 32; 637 /* index of current output region within this table */ 638 buf->cur_idx = (offset & 0xffffff80) >> 7; 639 } 640 641 /** 642 * pt_topa_next_entry() - obtain index of the first page in the next ToPA entry 643 * @buf: PT buffer. 644 * @pg: Page offset in the buffer. 645 * 646 * When advancing to the next output region (ToPA entry), given a page offset 647 * into the buffer, we need to find the offset of the first page in the next 648 * region. 649 */ 650 static unsigned int pt_topa_next_entry(struct pt_buffer *buf, unsigned int pg) 651 { 652 struct topa_entry *te = buf->topa_index[pg]; 653 654 /* one region */ 655 if (buf->first == buf->last && buf->first->last == 1) 656 return pg; 657 658 do { 659 pg++; 660 pg &= buf->nr_pages - 1; 661 } while (buf->topa_index[pg] == te); 662 663 return pg; 664 } 665 666 /** 667 * pt_buffer_reset_markers() - place interrupt and stop bits in the buffer 668 * @buf: PT buffer. 669 * @handle: Current output handle. 670 * 671 * Place INT and STOP marks to prevent overwriting old data that the consumer 672 * hasn't yet collected and waking up the consumer after a certain fraction of 673 * the buffer has filled up. Only needed and sensible for non-snapshot counters. 674 * 675 * This obviously relies on buf::head to figure out buffer markers, so it has 676 * to be called after pt_buffer_reset_offsets() and before the hardware tracing 677 * is enabled. 678 */ 679 static int pt_buffer_reset_markers(struct pt_buffer *buf, 680 struct perf_output_handle *handle) 681 682 { 683 unsigned long head = local64_read(&buf->head); 684 unsigned long idx, npages, wakeup; 685 686 /* can't stop in the middle of an output region */ 687 if (buf->output_off + handle->size + 1 < 688 sizes(TOPA_ENTRY(buf->cur, buf->cur_idx)->size)) 689 return -EINVAL; 690 691 692 /* single entry ToPA is handled by marking all regions STOP=1 INT=1 */ 693 if (!pt_cap_get(PT_CAP_topa_multiple_entries)) 694 return 0; 695 696 /* clear STOP and INT from current entry */ 697 buf->topa_index[buf->stop_pos]->stop = 0; 698 buf->topa_index[buf->intr_pos]->intr = 0; 699 700 /* how many pages till the STOP marker */ 701 npages = handle->size >> PAGE_SHIFT; 702 703 /* if it's on a page boundary, fill up one more page */ 704 if (!offset_in_page(head + handle->size + 1)) 705 npages++; 706 707 idx = (head >> PAGE_SHIFT) + npages; 708 idx &= buf->nr_pages - 1; 709 buf->stop_pos = idx; 710 711 wakeup = handle->wakeup >> PAGE_SHIFT; 712 713 /* in the worst case, wake up the consumer one page before hard stop */ 714 idx = (head >> PAGE_SHIFT) + npages - 1; 715 if (idx > wakeup) 716 idx = wakeup; 717 718 idx &= buf->nr_pages - 1; 719 buf->intr_pos = idx; 720 721 buf->topa_index[buf->stop_pos]->stop = 1; 722 buf->topa_index[buf->intr_pos]->intr = 1; 723 724 return 0; 725 } 726 727 /** 728 * pt_buffer_setup_topa_index() - build topa_index[] table of regions 729 * @buf: PT buffer. 730 * 731 * topa_index[] references output regions indexed by offset into the 732 * buffer for purposes of quick reverse lookup. 733 */ 734 static void pt_buffer_setup_topa_index(struct pt_buffer *buf) 735 { 736 struct topa *cur = buf->first, *prev = buf->last; 737 struct topa_entry *te_cur = TOPA_ENTRY(cur, 0), 738 *te_prev = TOPA_ENTRY(prev, prev->last - 1); 739 int pg = 0, idx = 0; 740 741 while (pg < buf->nr_pages) { 742 int tidx; 743 744 /* pages within one topa entry */ 745 for (tidx = 0; tidx < 1 << te_cur->size; tidx++, pg++) 746 buf->topa_index[pg] = te_prev; 747 748 te_prev = te_cur; 749 750 if (idx == cur->last - 1) { 751 /* advance to next topa table */ 752 idx = 0; 753 cur = list_entry(cur->list.next, struct topa, list); 754 } else { 755 idx++; 756 } 757 te_cur = TOPA_ENTRY(cur, idx); 758 } 759 760 } 761 762 /** 763 * pt_buffer_reset_offsets() - adjust buffer's write pointers from aux_head 764 * @buf: PT buffer. 765 * @head: Write pointer (aux_head) from AUX buffer. 766 * 767 * Find the ToPA table and entry corresponding to given @head and set buffer's 768 * "current" pointers accordingly. This is done after we have obtained the 769 * current aux_head position from a successful call to perf_aux_output_begin() 770 * to make sure the hardware is writing to the right place. 771 * 772 * This function modifies buf::{cur,cur_idx,output_off} that will be programmed 773 * into PT msrs when the tracing is enabled and buf::head and buf::data_size, 774 * which are used to determine INT and STOP markers' locations by a subsequent 775 * call to pt_buffer_reset_markers(). 776 */ 777 static void pt_buffer_reset_offsets(struct pt_buffer *buf, unsigned long head) 778 { 779 int pg; 780 781 if (buf->snapshot) 782 head &= (buf->nr_pages << PAGE_SHIFT) - 1; 783 784 pg = (head >> PAGE_SHIFT) & (buf->nr_pages - 1); 785 pg = pt_topa_next_entry(buf, pg); 786 787 buf->cur = (struct topa *)((unsigned long)buf->topa_index[pg] & PAGE_MASK); 788 buf->cur_idx = ((unsigned long)buf->topa_index[pg] - 789 (unsigned long)buf->cur) / sizeof(struct topa_entry); 790 buf->output_off = head & (sizes(buf->cur->table[buf->cur_idx].size) - 1); 791 792 local64_set(&buf->head, head); 793 local_set(&buf->data_size, 0); 794 } 795 796 /** 797 * pt_buffer_fini_topa() - deallocate ToPA structure of a buffer 798 * @buf: PT buffer. 799 */ 800 static void pt_buffer_fini_topa(struct pt_buffer *buf) 801 { 802 struct topa *topa, *iter; 803 804 list_for_each_entry_safe(topa, iter, &buf->tables, list) { 805 /* 806 * right now, this is in free_aux() path only, so 807 * no need to unlink this table from the list 808 */ 809 topa_free(topa); 810 } 811 } 812 813 /** 814 * pt_buffer_init_topa() - initialize ToPA table for pt buffer 815 * @buf: PT buffer. 816 * @size: Total size of all regions within this ToPA. 817 * @gfp: Allocation flags. 818 */ 819 static int pt_buffer_init_topa(struct pt_buffer *buf, unsigned long nr_pages, 820 gfp_t gfp) 821 { 822 struct topa *topa; 823 int err; 824 825 topa = topa_alloc(buf->cpu, gfp); 826 if (!topa) 827 return -ENOMEM; 828 829 topa_insert_table(buf, topa); 830 831 while (buf->nr_pages < nr_pages) { 832 err = topa_insert_pages(buf, gfp); 833 if (err) { 834 pt_buffer_fini_topa(buf); 835 return -ENOMEM; 836 } 837 } 838 839 pt_buffer_setup_topa_index(buf); 840 841 /* link last table to the first one, unless we're double buffering */ 842 if (pt_cap_get(PT_CAP_topa_multiple_entries)) { 843 TOPA_ENTRY(buf->last, -1)->base = buf->first->phys >> TOPA_SHIFT; 844 TOPA_ENTRY(buf->last, -1)->end = 1; 845 } 846 847 pt_topa_dump(buf); 848 return 0; 849 } 850 851 /** 852 * pt_buffer_setup_aux() - set up topa tables for a PT buffer 853 * @cpu: Cpu on which to allocate, -1 means current. 854 * @pages: Array of pointers to buffer pages passed from perf core. 855 * @nr_pages: Number of pages in the buffer. 856 * @snapshot: If this is a snapshot/overwrite counter. 857 * 858 * This is a pmu::setup_aux callback that sets up ToPA tables and all the 859 * bookkeeping for an AUX buffer. 860 * 861 * Return: Our private PT buffer structure. 862 */ 863 static void * 864 pt_buffer_setup_aux(int cpu, void **pages, int nr_pages, bool snapshot) 865 { 866 struct pt_buffer *buf; 867 int node, ret; 868 869 if (!nr_pages) 870 return NULL; 871 872 if (cpu == -1) 873 cpu = raw_smp_processor_id(); 874 node = cpu_to_node(cpu); 875 876 buf = kzalloc_node(offsetof(struct pt_buffer, topa_index[nr_pages]), 877 GFP_KERNEL, node); 878 if (!buf) 879 return NULL; 880 881 buf->cpu = cpu; 882 buf->snapshot = snapshot; 883 buf->data_pages = pages; 884 885 INIT_LIST_HEAD(&buf->tables); 886 887 ret = pt_buffer_init_topa(buf, nr_pages, GFP_KERNEL); 888 if (ret) { 889 kfree(buf); 890 return NULL; 891 } 892 893 return buf; 894 } 895 896 /** 897 * pt_buffer_free_aux() - perf AUX deallocation path callback 898 * @data: PT buffer. 899 */ 900 static void pt_buffer_free_aux(void *data) 901 { 902 struct pt_buffer *buf = data; 903 904 pt_buffer_fini_topa(buf); 905 kfree(buf); 906 } 907 908 /** 909 * pt_buffer_is_full() - check if the buffer is full 910 * @buf: PT buffer. 911 * @pt: Per-cpu pt handle. 912 * 913 * If the user hasn't read data from the output region that aux_head 914 * points to, the buffer is considered full: the user needs to read at 915 * least this region and update aux_tail to point past it. 916 */ 917 static bool pt_buffer_is_full(struct pt_buffer *buf, struct pt *pt) 918 { 919 if (buf->snapshot) 920 return false; 921 922 if (local_read(&buf->data_size) >= pt->handle.size) 923 return true; 924 925 return false; 926 } 927 928 /** 929 * intel_pt_interrupt() - PT PMI handler 930 */ 931 void intel_pt_interrupt(void) 932 { 933 struct pt *pt = this_cpu_ptr(&pt_ctx); 934 struct pt_buffer *buf; 935 struct perf_event *event = pt->handle.event; 936 937 /* 938 * There may be a dangling PT bit in the interrupt status register 939 * after PT has been disabled by pt_event_stop(). Make sure we don't 940 * do anything (particularly, re-enable) for this event here. 941 */ 942 if (!ACCESS_ONCE(pt->handle_nmi)) 943 return; 944 945 pt_config_start(false); 946 947 if (!event) 948 return; 949 950 buf = perf_get_aux(&pt->handle); 951 if (!buf) 952 return; 953 954 pt_read_offset(buf); 955 956 pt_handle_status(pt); 957 958 pt_update_head(pt); 959 960 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0), 961 local_xchg(&buf->lost, 0)); 962 963 if (!event->hw.state) { 964 int ret; 965 966 buf = perf_aux_output_begin(&pt->handle, event); 967 if (!buf) { 968 event->hw.state = PERF_HES_STOPPED; 969 return; 970 } 971 972 pt_buffer_reset_offsets(buf, pt->handle.head); 973 /* snapshot counters don't use PMI, so it's safe */ 974 ret = pt_buffer_reset_markers(buf, &pt->handle); 975 if (ret) { 976 perf_aux_output_end(&pt->handle, 0, true); 977 return; 978 } 979 980 pt_config_buffer(buf->cur->table, buf->cur_idx, 981 buf->output_off); 982 pt_config(event); 983 } 984 } 985 986 /* 987 * PMU callbacks 988 */ 989 990 static void pt_event_start(struct perf_event *event, int mode) 991 { 992 struct pt *pt = this_cpu_ptr(&pt_ctx); 993 struct pt_buffer *buf = perf_get_aux(&pt->handle); 994 995 if (!buf || pt_buffer_is_full(buf, pt)) { 996 event->hw.state = PERF_HES_STOPPED; 997 return; 998 } 999 1000 ACCESS_ONCE(pt->handle_nmi) = 1; 1001 event->hw.state = 0; 1002 1003 pt_config_buffer(buf->cur->table, buf->cur_idx, 1004 buf->output_off); 1005 pt_config(event); 1006 } 1007 1008 static void pt_event_stop(struct perf_event *event, int mode) 1009 { 1010 struct pt *pt = this_cpu_ptr(&pt_ctx); 1011 1012 /* 1013 * Protect against the PMI racing with disabling wrmsr, 1014 * see comment in intel_pt_interrupt(). 1015 */ 1016 ACCESS_ONCE(pt->handle_nmi) = 0; 1017 pt_config_start(false); 1018 1019 if (event->hw.state == PERF_HES_STOPPED) 1020 return; 1021 1022 event->hw.state = PERF_HES_STOPPED; 1023 1024 if (mode & PERF_EF_UPDATE) { 1025 struct pt_buffer *buf = perf_get_aux(&pt->handle); 1026 1027 if (!buf) 1028 return; 1029 1030 if (WARN_ON_ONCE(pt->handle.event != event)) 1031 return; 1032 1033 pt_read_offset(buf); 1034 1035 pt_handle_status(pt); 1036 1037 pt_update_head(pt); 1038 } 1039 } 1040 1041 static void pt_event_del(struct perf_event *event, int mode) 1042 { 1043 struct pt *pt = this_cpu_ptr(&pt_ctx); 1044 struct pt_buffer *buf; 1045 1046 pt_event_stop(event, PERF_EF_UPDATE); 1047 1048 buf = perf_get_aux(&pt->handle); 1049 1050 if (buf) { 1051 if (buf->snapshot) 1052 pt->handle.head = 1053 local_xchg(&buf->data_size, 1054 buf->nr_pages << PAGE_SHIFT); 1055 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0), 1056 local_xchg(&buf->lost, 0)); 1057 } 1058 } 1059 1060 static int pt_event_add(struct perf_event *event, int mode) 1061 { 1062 struct pt_buffer *buf; 1063 struct pt *pt = this_cpu_ptr(&pt_ctx); 1064 struct hw_perf_event *hwc = &event->hw; 1065 int ret = -EBUSY; 1066 1067 if (pt->handle.event) 1068 goto fail; 1069 1070 buf = perf_aux_output_begin(&pt->handle, event); 1071 ret = -EINVAL; 1072 if (!buf) 1073 goto fail_stop; 1074 1075 pt_buffer_reset_offsets(buf, pt->handle.head); 1076 if (!buf->snapshot) { 1077 ret = pt_buffer_reset_markers(buf, &pt->handle); 1078 if (ret) 1079 goto fail_end_stop; 1080 } 1081 1082 if (mode & PERF_EF_START) { 1083 pt_event_start(event, 0); 1084 ret = -EBUSY; 1085 if (hwc->state == PERF_HES_STOPPED) 1086 goto fail_end_stop; 1087 } else { 1088 hwc->state = PERF_HES_STOPPED; 1089 } 1090 1091 return 0; 1092 1093 fail_end_stop: 1094 perf_aux_output_end(&pt->handle, 0, true); 1095 fail_stop: 1096 hwc->state = PERF_HES_STOPPED; 1097 fail: 1098 return ret; 1099 } 1100 1101 static void pt_event_read(struct perf_event *event) 1102 { 1103 } 1104 1105 static void pt_event_destroy(struct perf_event *event) 1106 { 1107 x86_del_exclusive(x86_lbr_exclusive_pt); 1108 } 1109 1110 static int pt_event_init(struct perf_event *event) 1111 { 1112 if (event->attr.type != pt_pmu.pmu.type) 1113 return -ENOENT; 1114 1115 if (!pt_event_valid(event)) 1116 return -EINVAL; 1117 1118 if (x86_add_exclusive(x86_lbr_exclusive_pt)) 1119 return -EBUSY; 1120 1121 event->destroy = pt_event_destroy; 1122 1123 return 0; 1124 } 1125 1126 void cpu_emergency_stop_pt(void) 1127 { 1128 struct pt *pt = this_cpu_ptr(&pt_ctx); 1129 1130 if (pt->handle.event) 1131 pt_event_stop(pt->handle.event, PERF_EF_UPDATE); 1132 } 1133 1134 static __init int pt_init(void) 1135 { 1136 int ret, cpu, prior_warn = 0; 1137 1138 BUILD_BUG_ON(sizeof(struct topa) > PAGE_SIZE); 1139 1140 if (!test_cpu_cap(&boot_cpu_data, X86_FEATURE_INTEL_PT)) 1141 return -ENODEV; 1142 1143 get_online_cpus(); 1144 for_each_online_cpu(cpu) { 1145 u64 ctl; 1146 1147 ret = rdmsrl_safe_on_cpu(cpu, MSR_IA32_RTIT_CTL, &ctl); 1148 if (!ret && (ctl & RTIT_CTL_TRACEEN)) 1149 prior_warn++; 1150 } 1151 put_online_cpus(); 1152 1153 if (prior_warn) { 1154 x86_add_exclusive(x86_lbr_exclusive_pt); 1155 pr_warn("PT is enabled at boot time, doing nothing\n"); 1156 1157 return -EBUSY; 1158 } 1159 1160 ret = pt_pmu_hw_init(); 1161 if (ret) 1162 return ret; 1163 1164 if (!pt_cap_get(PT_CAP_topa_output)) { 1165 pr_warn("ToPA output is not supported on this CPU\n"); 1166 return -ENODEV; 1167 } 1168 1169 if (!pt_cap_get(PT_CAP_topa_multiple_entries)) 1170 pt_pmu.pmu.capabilities = 1171 PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_AUX_SW_DOUBLEBUF; 1172 1173 pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE; 1174 pt_pmu.pmu.attr_groups = pt_attr_groups; 1175 pt_pmu.pmu.task_ctx_nr = perf_sw_context; 1176 pt_pmu.pmu.event_init = pt_event_init; 1177 pt_pmu.pmu.add = pt_event_add; 1178 pt_pmu.pmu.del = pt_event_del; 1179 pt_pmu.pmu.start = pt_event_start; 1180 pt_pmu.pmu.stop = pt_event_stop; 1181 pt_pmu.pmu.read = pt_event_read; 1182 pt_pmu.pmu.setup_aux = pt_buffer_setup_aux; 1183 pt_pmu.pmu.free_aux = pt_buffer_free_aux; 1184 ret = perf_pmu_register(&pt_pmu.pmu, "intel_pt", -1); 1185 1186 return ret; 1187 } 1188 arch_initcall(pt_init); 1189