1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/bitops.h> 3 #include <linux/types.h> 4 #include <linux/slab.h> 5 6 #include <asm/cpu_entry_area.h> 7 #include <asm/perf_event.h> 8 #include <asm/tlbflush.h> 9 #include <asm/insn.h> 10 11 #include "../perf_event.h" 12 13 /* Waste a full page so it can be mapped into the cpu_entry_area */ 14 DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store); 15 16 /* The size of a BTS record in bytes: */ 17 #define BTS_RECORD_SIZE 24 18 19 #define PEBS_FIXUP_SIZE PAGE_SIZE 20 21 /* 22 * pebs_record_32 for p4 and core not supported 23 24 struct pebs_record_32 { 25 u32 flags, ip; 26 u32 ax, bc, cx, dx; 27 u32 si, di, bp, sp; 28 }; 29 30 */ 31 32 union intel_x86_pebs_dse { 33 u64 val; 34 struct { 35 unsigned int ld_dse:4; 36 unsigned int ld_stlb_miss:1; 37 unsigned int ld_locked:1; 38 unsigned int ld_reserved:26; 39 }; 40 struct { 41 unsigned int st_l1d_hit:1; 42 unsigned int st_reserved1:3; 43 unsigned int st_stlb_miss:1; 44 unsigned int st_locked:1; 45 unsigned int st_reserved2:26; 46 }; 47 }; 48 49 50 /* 51 * Map PEBS Load Latency Data Source encodings to generic 52 * memory data source information 53 */ 54 #define P(a, b) PERF_MEM_S(a, b) 55 #define OP_LH (P(OP, LOAD) | P(LVL, HIT)) 56 #define LEVEL(x) P(LVLNUM, x) 57 #define REM P(REMOTE, REMOTE) 58 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS)) 59 60 /* Version for Sandy Bridge and later */ 61 static u64 pebs_data_source[] = { 62 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */ 63 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */ 64 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */ 65 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */ 66 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */ 67 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */ 68 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */ 69 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */ 70 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */ 71 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/ 72 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */ 73 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */ 74 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */ 75 OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */ 76 OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */ 77 OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */ 78 }; 79 80 /* Patch up minor differences in the bits */ 81 void __init intel_pmu_pebs_data_source_nhm(void) 82 { 83 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); 84 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); 85 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); 86 } 87 88 void __init intel_pmu_pebs_data_source_skl(bool pmem) 89 { 90 u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4); 91 92 pebs_data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT); 93 pebs_data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT); 94 pebs_data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); 95 pebs_data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD); 96 pebs_data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM); 97 } 98 99 static u64 precise_store_data(u64 status) 100 { 101 union intel_x86_pebs_dse dse; 102 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); 103 104 dse.val = status; 105 106 /* 107 * bit 4: TLB access 108 * 1 = stored missed 2nd level TLB 109 * 110 * so it either hit the walker or the OS 111 * otherwise hit 2nd level TLB 112 */ 113 if (dse.st_stlb_miss) 114 val |= P(TLB, MISS); 115 else 116 val |= P(TLB, HIT); 117 118 /* 119 * bit 0: hit L1 data cache 120 * if not set, then all we know is that 121 * it missed L1D 122 */ 123 if (dse.st_l1d_hit) 124 val |= P(LVL, HIT); 125 else 126 val |= P(LVL, MISS); 127 128 /* 129 * bit 5: Locked prefix 130 */ 131 if (dse.st_locked) 132 val |= P(LOCK, LOCKED); 133 134 return val; 135 } 136 137 static u64 precise_datala_hsw(struct perf_event *event, u64 status) 138 { 139 union perf_mem_data_src dse; 140 141 dse.val = PERF_MEM_NA; 142 143 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) 144 dse.mem_op = PERF_MEM_OP_STORE; 145 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW) 146 dse.mem_op = PERF_MEM_OP_LOAD; 147 148 /* 149 * L1 info only valid for following events: 150 * 151 * MEM_UOPS_RETIRED.STLB_MISS_STORES 152 * MEM_UOPS_RETIRED.LOCK_STORES 153 * MEM_UOPS_RETIRED.SPLIT_STORES 154 * MEM_UOPS_RETIRED.ALL_STORES 155 */ 156 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) { 157 if (status & 1) 158 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT; 159 else 160 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS; 161 } 162 return dse.val; 163 } 164 165 static u64 load_latency_data(u64 status) 166 { 167 union intel_x86_pebs_dse dse; 168 u64 val; 169 170 dse.val = status; 171 172 /* 173 * use the mapping table for bit 0-3 174 */ 175 val = pebs_data_source[dse.ld_dse]; 176 177 /* 178 * Nehalem models do not support TLB, Lock infos 179 */ 180 if (x86_pmu.pebs_no_tlb) { 181 val |= P(TLB, NA) | P(LOCK, NA); 182 return val; 183 } 184 /* 185 * bit 4: TLB access 186 * 0 = did not miss 2nd level TLB 187 * 1 = missed 2nd level TLB 188 */ 189 if (dse.ld_stlb_miss) 190 val |= P(TLB, MISS) | P(TLB, L2); 191 else 192 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); 193 194 /* 195 * bit 5: locked prefix 196 */ 197 if (dse.ld_locked) 198 val |= P(LOCK, LOCKED); 199 200 return val; 201 } 202 203 struct pebs_record_core { 204 u64 flags, ip; 205 u64 ax, bx, cx, dx; 206 u64 si, di, bp, sp; 207 u64 r8, r9, r10, r11; 208 u64 r12, r13, r14, r15; 209 }; 210 211 struct pebs_record_nhm { 212 u64 flags, ip; 213 u64 ax, bx, cx, dx; 214 u64 si, di, bp, sp; 215 u64 r8, r9, r10, r11; 216 u64 r12, r13, r14, r15; 217 u64 status, dla, dse, lat; 218 }; 219 220 /* 221 * Same as pebs_record_nhm, with two additional fields. 222 */ 223 struct pebs_record_hsw { 224 u64 flags, ip; 225 u64 ax, bx, cx, dx; 226 u64 si, di, bp, sp; 227 u64 r8, r9, r10, r11; 228 u64 r12, r13, r14, r15; 229 u64 status, dla, dse, lat; 230 u64 real_ip, tsx_tuning; 231 }; 232 233 union hsw_tsx_tuning { 234 struct { 235 u32 cycles_last_block : 32, 236 hle_abort : 1, 237 rtm_abort : 1, 238 instruction_abort : 1, 239 non_instruction_abort : 1, 240 retry : 1, 241 data_conflict : 1, 242 capacity_writes : 1, 243 capacity_reads : 1; 244 }; 245 u64 value; 246 }; 247 248 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL 249 250 /* Same as HSW, plus TSC */ 251 252 struct pebs_record_skl { 253 u64 flags, ip; 254 u64 ax, bx, cx, dx; 255 u64 si, di, bp, sp; 256 u64 r8, r9, r10, r11; 257 u64 r12, r13, r14, r15; 258 u64 status, dla, dse, lat; 259 u64 real_ip, tsx_tuning; 260 u64 tsc; 261 }; 262 263 void init_debug_store_on_cpu(int cpu) 264 { 265 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; 266 267 if (!ds) 268 return; 269 270 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 271 (u32)((u64)(unsigned long)ds), 272 (u32)((u64)(unsigned long)ds >> 32)); 273 } 274 275 void fini_debug_store_on_cpu(int cpu) 276 { 277 if (!per_cpu(cpu_hw_events, cpu).ds) 278 return; 279 280 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); 281 } 282 283 static DEFINE_PER_CPU(void *, insn_buffer); 284 285 static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot) 286 { 287 unsigned long start = (unsigned long)cea; 288 phys_addr_t pa; 289 size_t msz = 0; 290 291 pa = virt_to_phys(addr); 292 293 preempt_disable(); 294 for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE) 295 cea_set_pte(cea, pa, prot); 296 297 /* 298 * This is a cross-CPU update of the cpu_entry_area, we must shoot down 299 * all TLB entries for it. 300 */ 301 flush_tlb_kernel_range(start, start + size); 302 preempt_enable(); 303 } 304 305 static void ds_clear_cea(void *cea, size_t size) 306 { 307 unsigned long start = (unsigned long)cea; 308 size_t msz = 0; 309 310 preempt_disable(); 311 for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE) 312 cea_set_pte(cea, 0, PAGE_NONE); 313 314 flush_tlb_kernel_range(start, start + size); 315 preempt_enable(); 316 } 317 318 static void *dsalloc_pages(size_t size, gfp_t flags, int cpu) 319 { 320 unsigned int order = get_order(size); 321 int node = cpu_to_node(cpu); 322 struct page *page; 323 324 page = __alloc_pages_node(node, flags | __GFP_ZERO, order); 325 return page ? page_address(page) : NULL; 326 } 327 328 static void dsfree_pages(const void *buffer, size_t size) 329 { 330 if (buffer) 331 free_pages((unsigned long)buffer, get_order(size)); 332 } 333 334 static int alloc_pebs_buffer(int cpu) 335 { 336 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 337 struct debug_store *ds = hwev->ds; 338 size_t bsiz = x86_pmu.pebs_buffer_size; 339 int max, node = cpu_to_node(cpu); 340 void *buffer, *ibuffer, *cea; 341 342 if (!x86_pmu.pebs) 343 return 0; 344 345 buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu); 346 if (unlikely(!buffer)) 347 return -ENOMEM; 348 349 /* 350 * HSW+ already provides us the eventing ip; no need to allocate this 351 * buffer then. 352 */ 353 if (x86_pmu.intel_cap.pebs_format < 2) { 354 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node); 355 if (!ibuffer) { 356 dsfree_pages(buffer, bsiz); 357 return -ENOMEM; 358 } 359 per_cpu(insn_buffer, cpu) = ibuffer; 360 } 361 hwev->ds_pebs_vaddr = buffer; 362 /* Update the cpu entry area mapping */ 363 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; 364 ds->pebs_buffer_base = (unsigned long) cea; 365 ds_update_cea(cea, buffer, bsiz, PAGE_KERNEL); 366 ds->pebs_index = ds->pebs_buffer_base; 367 max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size); 368 ds->pebs_absolute_maximum = ds->pebs_buffer_base + max; 369 return 0; 370 } 371 372 static void release_pebs_buffer(int cpu) 373 { 374 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 375 void *cea; 376 377 if (!x86_pmu.pebs) 378 return; 379 380 kfree(per_cpu(insn_buffer, cpu)); 381 per_cpu(insn_buffer, cpu) = NULL; 382 383 /* Clear the fixmap */ 384 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; 385 ds_clear_cea(cea, x86_pmu.pebs_buffer_size); 386 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size); 387 hwev->ds_pebs_vaddr = NULL; 388 } 389 390 static int alloc_bts_buffer(int cpu) 391 { 392 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 393 struct debug_store *ds = hwev->ds; 394 void *buffer, *cea; 395 int max; 396 397 if (!x86_pmu.bts) 398 return 0; 399 400 buffer = dsalloc_pages(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, cpu); 401 if (unlikely(!buffer)) { 402 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__); 403 return -ENOMEM; 404 } 405 hwev->ds_bts_vaddr = buffer; 406 /* Update the fixmap */ 407 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; 408 ds->bts_buffer_base = (unsigned long) cea; 409 ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL); 410 ds->bts_index = ds->bts_buffer_base; 411 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE; 412 ds->bts_absolute_maximum = ds->bts_buffer_base + 413 max * BTS_RECORD_SIZE; 414 ds->bts_interrupt_threshold = ds->bts_absolute_maximum - 415 (max / 16) * BTS_RECORD_SIZE; 416 return 0; 417 } 418 419 static void release_bts_buffer(int cpu) 420 { 421 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 422 void *cea; 423 424 if (!x86_pmu.bts) 425 return; 426 427 /* Clear the fixmap */ 428 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; 429 ds_clear_cea(cea, BTS_BUFFER_SIZE); 430 dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE); 431 hwev->ds_bts_vaddr = NULL; 432 } 433 434 static int alloc_ds_buffer(int cpu) 435 { 436 struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store; 437 438 memset(ds, 0, sizeof(*ds)); 439 per_cpu(cpu_hw_events, cpu).ds = ds; 440 return 0; 441 } 442 443 static void release_ds_buffer(int cpu) 444 { 445 per_cpu(cpu_hw_events, cpu).ds = NULL; 446 } 447 448 void release_ds_buffers(void) 449 { 450 int cpu; 451 452 if (!x86_pmu.bts && !x86_pmu.pebs) 453 return; 454 455 for_each_possible_cpu(cpu) 456 release_ds_buffer(cpu); 457 458 for_each_possible_cpu(cpu) { 459 /* 460 * Again, ignore errors from offline CPUs, they will no longer 461 * observe cpu_hw_events.ds and not program the DS_AREA when 462 * they come up. 463 */ 464 fini_debug_store_on_cpu(cpu); 465 } 466 467 for_each_possible_cpu(cpu) { 468 release_pebs_buffer(cpu); 469 release_bts_buffer(cpu); 470 } 471 } 472 473 void reserve_ds_buffers(void) 474 { 475 int bts_err = 0, pebs_err = 0; 476 int cpu; 477 478 x86_pmu.bts_active = 0; 479 x86_pmu.pebs_active = 0; 480 481 if (!x86_pmu.bts && !x86_pmu.pebs) 482 return; 483 484 if (!x86_pmu.bts) 485 bts_err = 1; 486 487 if (!x86_pmu.pebs) 488 pebs_err = 1; 489 490 for_each_possible_cpu(cpu) { 491 if (alloc_ds_buffer(cpu)) { 492 bts_err = 1; 493 pebs_err = 1; 494 } 495 496 if (!bts_err && alloc_bts_buffer(cpu)) 497 bts_err = 1; 498 499 if (!pebs_err && alloc_pebs_buffer(cpu)) 500 pebs_err = 1; 501 502 if (bts_err && pebs_err) 503 break; 504 } 505 506 if (bts_err) { 507 for_each_possible_cpu(cpu) 508 release_bts_buffer(cpu); 509 } 510 511 if (pebs_err) { 512 for_each_possible_cpu(cpu) 513 release_pebs_buffer(cpu); 514 } 515 516 if (bts_err && pebs_err) { 517 for_each_possible_cpu(cpu) 518 release_ds_buffer(cpu); 519 } else { 520 if (x86_pmu.bts && !bts_err) 521 x86_pmu.bts_active = 1; 522 523 if (x86_pmu.pebs && !pebs_err) 524 x86_pmu.pebs_active = 1; 525 526 for_each_possible_cpu(cpu) { 527 /* 528 * Ignores wrmsr_on_cpu() errors for offline CPUs they 529 * will get this call through intel_pmu_cpu_starting(). 530 */ 531 init_debug_store_on_cpu(cpu); 532 } 533 } 534 } 535 536 /* 537 * BTS 538 */ 539 540 struct event_constraint bts_constraint = 541 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0); 542 543 void intel_pmu_enable_bts(u64 config) 544 { 545 unsigned long debugctlmsr; 546 547 debugctlmsr = get_debugctlmsr(); 548 549 debugctlmsr |= DEBUGCTLMSR_TR; 550 debugctlmsr |= DEBUGCTLMSR_BTS; 551 if (config & ARCH_PERFMON_EVENTSEL_INT) 552 debugctlmsr |= DEBUGCTLMSR_BTINT; 553 554 if (!(config & ARCH_PERFMON_EVENTSEL_OS)) 555 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS; 556 557 if (!(config & ARCH_PERFMON_EVENTSEL_USR)) 558 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR; 559 560 update_debugctlmsr(debugctlmsr); 561 } 562 563 void intel_pmu_disable_bts(void) 564 { 565 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 566 unsigned long debugctlmsr; 567 568 if (!cpuc->ds) 569 return; 570 571 debugctlmsr = get_debugctlmsr(); 572 573 debugctlmsr &= 574 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT | 575 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR); 576 577 update_debugctlmsr(debugctlmsr); 578 } 579 580 int intel_pmu_drain_bts_buffer(void) 581 { 582 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 583 struct debug_store *ds = cpuc->ds; 584 struct bts_record { 585 u64 from; 586 u64 to; 587 u64 flags; 588 }; 589 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 590 struct bts_record *at, *base, *top; 591 struct perf_output_handle handle; 592 struct perf_event_header header; 593 struct perf_sample_data data; 594 unsigned long skip = 0; 595 struct pt_regs regs; 596 597 if (!event) 598 return 0; 599 600 if (!x86_pmu.bts_active) 601 return 0; 602 603 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base; 604 top = (struct bts_record *)(unsigned long)ds->bts_index; 605 606 if (top <= base) 607 return 0; 608 609 memset(®s, 0, sizeof(regs)); 610 611 ds->bts_index = ds->bts_buffer_base; 612 613 perf_sample_data_init(&data, 0, event->hw.last_period); 614 615 /* 616 * BTS leaks kernel addresses in branches across the cpl boundary, 617 * such as traps or system calls, so unless the user is asking for 618 * kernel tracing (and right now it's not possible), we'd need to 619 * filter them out. But first we need to count how many of those we 620 * have in the current batch. This is an extra O(n) pass, however, 621 * it's much faster than the other one especially considering that 622 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the 623 * alloc_bts_buffer()). 624 */ 625 for (at = base; at < top; at++) { 626 /* 627 * Note that right now *this* BTS code only works if 628 * attr::exclude_kernel is set, but let's keep this extra 629 * check here in case that changes. 630 */ 631 if (event->attr.exclude_kernel && 632 (kernel_ip(at->from) || kernel_ip(at->to))) 633 skip++; 634 } 635 636 /* 637 * Prepare a generic sample, i.e. fill in the invariant fields. 638 * We will overwrite the from and to address before we output 639 * the sample. 640 */ 641 rcu_read_lock(); 642 perf_prepare_sample(&header, &data, event, ®s); 643 644 if (perf_output_begin(&handle, event, header.size * 645 (top - base - skip))) 646 goto unlock; 647 648 for (at = base; at < top; at++) { 649 /* Filter out any records that contain kernel addresses. */ 650 if (event->attr.exclude_kernel && 651 (kernel_ip(at->from) || kernel_ip(at->to))) 652 continue; 653 654 data.ip = at->from; 655 data.addr = at->to; 656 657 perf_output_sample(&handle, &header, &data, event); 658 } 659 660 perf_output_end(&handle); 661 662 /* There's new data available. */ 663 event->hw.interrupts++; 664 event->pending_kill = POLL_IN; 665 unlock: 666 rcu_read_unlock(); 667 return 1; 668 } 669 670 static inline void intel_pmu_drain_pebs_buffer(void) 671 { 672 struct pt_regs regs; 673 674 x86_pmu.drain_pebs(®s); 675 } 676 677 /* 678 * PEBS 679 */ 680 struct event_constraint intel_core2_pebs_event_constraints[] = { 681 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ 682 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */ 683 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */ 684 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */ 685 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ 686 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 687 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01), 688 EVENT_CONSTRAINT_END 689 }; 690 691 struct event_constraint intel_atom_pebs_event_constraints[] = { 692 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ 693 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */ 694 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ 695 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 696 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01), 697 /* Allow all events as PEBS with no flags */ 698 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), 699 EVENT_CONSTRAINT_END 700 }; 701 702 struct event_constraint intel_slm_pebs_event_constraints[] = { 703 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 704 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1), 705 /* Allow all events as PEBS with no flags */ 706 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), 707 EVENT_CONSTRAINT_END 708 }; 709 710 struct event_constraint intel_glm_pebs_event_constraints[] = { 711 /* Allow all events as PEBS with no flags */ 712 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), 713 EVENT_CONSTRAINT_END 714 }; 715 716 struct event_constraint intel_nehalem_pebs_event_constraints[] = { 717 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ 718 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ 719 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ 720 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */ 721 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ 722 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ 723 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */ 724 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ 725 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ 726 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ 727 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ 728 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 729 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), 730 EVENT_CONSTRAINT_END 731 }; 732 733 struct event_constraint intel_westmere_pebs_event_constraints[] = { 734 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ 735 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ 736 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ 737 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */ 738 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ 739 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ 740 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */ 741 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ 742 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ 743 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ 744 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ 745 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 746 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), 747 EVENT_CONSTRAINT_END 748 }; 749 750 struct event_constraint intel_snb_pebs_event_constraints[] = { 751 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 752 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ 753 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ 754 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 755 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), 756 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ 757 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 758 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 759 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 760 /* Allow all events as PEBS with no flags */ 761 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 762 EVENT_CONSTRAINT_END 763 }; 764 765 struct event_constraint intel_ivb_pebs_event_constraints[] = { 766 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 767 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ 768 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ 769 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 770 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), 771 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 772 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), 773 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ 774 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 775 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 776 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 777 /* Allow all events as PEBS with no flags */ 778 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 779 EVENT_CONSTRAINT_END 780 }; 781 782 struct event_constraint intel_hsw_pebs_event_constraints[] = { 783 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 784 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ 785 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 786 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), 787 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 788 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), 789 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ 790 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ 791 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ 792 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ 793 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ 794 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ 795 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ 796 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ 797 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 798 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ 799 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ 800 /* Allow all events as PEBS with no flags */ 801 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 802 EVENT_CONSTRAINT_END 803 }; 804 805 struct event_constraint intel_bdw_pebs_event_constraints[] = { 806 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 807 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ 808 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 809 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), 810 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 811 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), 812 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ 813 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ 814 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ 815 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ 816 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ 817 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ 818 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ 819 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ 820 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 821 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ 822 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ 823 /* Allow all events as PEBS with no flags */ 824 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 825 EVENT_CONSTRAINT_END 826 }; 827 828 829 struct event_constraint intel_skl_pebs_event_constraints[] = { 830 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 831 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 832 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), 833 /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */ 834 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), 835 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */ 836 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */ 837 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */ 838 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */ 839 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */ 840 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */ 841 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */ 842 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */ 843 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */ 844 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 845 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 846 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */ 847 /* Allow all events as PEBS with no flags */ 848 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 849 EVENT_CONSTRAINT_END 850 }; 851 852 struct event_constraint *intel_pebs_constraints(struct perf_event *event) 853 { 854 struct event_constraint *c; 855 856 if (!event->attr.precise_ip) 857 return NULL; 858 859 if (x86_pmu.pebs_constraints) { 860 for_each_event_constraint(c, x86_pmu.pebs_constraints) { 861 if ((event->hw.config & c->cmask) == c->code) { 862 event->hw.flags |= c->flags; 863 return c; 864 } 865 } 866 } 867 868 /* 869 * Extended PEBS support 870 * Makes the PEBS code search the normal constraints. 871 */ 872 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 873 return NULL; 874 875 return &emptyconstraint; 876 } 877 878 /* 879 * We need the sched_task callback even for per-cpu events when we use 880 * the large interrupt threshold, such that we can provide PID and TID 881 * to PEBS samples. 882 */ 883 static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc) 884 { 885 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs); 886 } 887 888 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in) 889 { 890 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 891 892 if (!sched_in && pebs_needs_sched_cb(cpuc)) 893 intel_pmu_drain_pebs_buffer(); 894 } 895 896 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc) 897 { 898 struct debug_store *ds = cpuc->ds; 899 u64 threshold; 900 int reserved; 901 902 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 903 reserved = x86_pmu.max_pebs_events + x86_pmu.num_counters_fixed; 904 else 905 reserved = x86_pmu.max_pebs_events; 906 907 if (cpuc->n_pebs == cpuc->n_large_pebs) { 908 threshold = ds->pebs_absolute_maximum - 909 reserved * x86_pmu.pebs_record_size; 910 } else { 911 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size; 912 } 913 914 ds->pebs_interrupt_threshold = threshold; 915 } 916 917 static void 918 pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, struct pmu *pmu) 919 { 920 /* 921 * Make sure we get updated with the first PEBS 922 * event. It will trigger also during removal, but 923 * that does not hurt: 924 */ 925 bool update = cpuc->n_pebs == 1; 926 927 if (needed_cb != pebs_needs_sched_cb(cpuc)) { 928 if (!needed_cb) 929 perf_sched_cb_inc(pmu); 930 else 931 perf_sched_cb_dec(pmu); 932 933 update = true; 934 } 935 936 if (update) 937 pebs_update_threshold(cpuc); 938 } 939 940 void intel_pmu_pebs_add(struct perf_event *event) 941 { 942 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 943 struct hw_perf_event *hwc = &event->hw; 944 bool needed_cb = pebs_needs_sched_cb(cpuc); 945 946 cpuc->n_pebs++; 947 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) 948 cpuc->n_large_pebs++; 949 950 pebs_update_state(needed_cb, cpuc, event->ctx->pmu); 951 } 952 953 void intel_pmu_pebs_enable(struct perf_event *event) 954 { 955 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 956 struct hw_perf_event *hwc = &event->hw; 957 struct debug_store *ds = cpuc->ds; 958 959 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; 960 961 cpuc->pebs_enabled |= 1ULL << hwc->idx; 962 963 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) 964 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32); 965 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) 966 cpuc->pebs_enabled |= 1ULL << 63; 967 968 /* 969 * Use auto-reload if possible to save a MSR write in the PMI. 970 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD. 971 */ 972 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { 973 unsigned int idx = hwc->idx; 974 975 if (idx >= INTEL_PMC_IDX_FIXED) 976 idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED); 977 ds->pebs_event_reset[idx] = 978 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; 979 } else { 980 ds->pebs_event_reset[hwc->idx] = 0; 981 } 982 } 983 984 void intel_pmu_pebs_del(struct perf_event *event) 985 { 986 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 987 struct hw_perf_event *hwc = &event->hw; 988 bool needed_cb = pebs_needs_sched_cb(cpuc); 989 990 cpuc->n_pebs--; 991 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) 992 cpuc->n_large_pebs--; 993 994 pebs_update_state(needed_cb, cpuc, event->ctx->pmu); 995 } 996 997 void intel_pmu_pebs_disable(struct perf_event *event) 998 { 999 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1000 struct hw_perf_event *hwc = &event->hw; 1001 1002 if (cpuc->n_pebs == cpuc->n_large_pebs) 1003 intel_pmu_drain_pebs_buffer(); 1004 1005 cpuc->pebs_enabled &= ~(1ULL << hwc->idx); 1006 1007 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) 1008 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32)); 1009 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) 1010 cpuc->pebs_enabled &= ~(1ULL << 63); 1011 1012 if (cpuc->enabled) 1013 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 1014 1015 hwc->config |= ARCH_PERFMON_EVENTSEL_INT; 1016 } 1017 1018 void intel_pmu_pebs_enable_all(void) 1019 { 1020 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1021 1022 if (cpuc->pebs_enabled) 1023 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 1024 } 1025 1026 void intel_pmu_pebs_disable_all(void) 1027 { 1028 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1029 1030 if (cpuc->pebs_enabled) 1031 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 1032 } 1033 1034 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs) 1035 { 1036 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1037 unsigned long from = cpuc->lbr_entries[0].from; 1038 unsigned long old_to, to = cpuc->lbr_entries[0].to; 1039 unsigned long ip = regs->ip; 1040 int is_64bit = 0; 1041 void *kaddr; 1042 int size; 1043 1044 /* 1045 * We don't need to fixup if the PEBS assist is fault like 1046 */ 1047 if (!x86_pmu.intel_cap.pebs_trap) 1048 return 1; 1049 1050 /* 1051 * No LBR entry, no basic block, no rewinding 1052 */ 1053 if (!cpuc->lbr_stack.nr || !from || !to) 1054 return 0; 1055 1056 /* 1057 * Basic blocks should never cross user/kernel boundaries 1058 */ 1059 if (kernel_ip(ip) != kernel_ip(to)) 1060 return 0; 1061 1062 /* 1063 * unsigned math, either ip is before the start (impossible) or 1064 * the basic block is larger than 1 page (sanity) 1065 */ 1066 if ((ip - to) > PEBS_FIXUP_SIZE) 1067 return 0; 1068 1069 /* 1070 * We sampled a branch insn, rewind using the LBR stack 1071 */ 1072 if (ip == to) { 1073 set_linear_ip(regs, from); 1074 return 1; 1075 } 1076 1077 size = ip - to; 1078 if (!kernel_ip(ip)) { 1079 int bytes; 1080 u8 *buf = this_cpu_read(insn_buffer); 1081 1082 /* 'size' must fit our buffer, see above */ 1083 bytes = copy_from_user_nmi(buf, (void __user *)to, size); 1084 if (bytes != 0) 1085 return 0; 1086 1087 kaddr = buf; 1088 } else { 1089 kaddr = (void *)to; 1090 } 1091 1092 do { 1093 struct insn insn; 1094 1095 old_to = to; 1096 1097 #ifdef CONFIG_X86_64 1098 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32); 1099 #endif 1100 insn_init(&insn, kaddr, size, is_64bit); 1101 insn_get_length(&insn); 1102 /* 1103 * Make sure there was not a problem decoding the 1104 * instruction and getting the length. This is 1105 * doubly important because we have an infinite 1106 * loop if insn.length=0. 1107 */ 1108 if (!insn.length) 1109 break; 1110 1111 to += insn.length; 1112 kaddr += insn.length; 1113 size -= insn.length; 1114 } while (to < ip); 1115 1116 if (to == ip) { 1117 set_linear_ip(regs, old_to); 1118 return 1; 1119 } 1120 1121 /* 1122 * Even though we decoded the basic block, the instruction stream 1123 * never matched the given IP, either the TO or the IP got corrupted. 1124 */ 1125 return 0; 1126 } 1127 1128 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs) 1129 { 1130 if (pebs->tsx_tuning) { 1131 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning }; 1132 return tsx.cycles_last_block; 1133 } 1134 return 0; 1135 } 1136 1137 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs) 1138 { 1139 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32; 1140 1141 /* For RTM XABORTs also log the abort code from AX */ 1142 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1)) 1143 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT; 1144 return txn; 1145 } 1146 1147 static void setup_pebs_sample_data(struct perf_event *event, 1148 struct pt_regs *iregs, void *__pebs, 1149 struct perf_sample_data *data, 1150 struct pt_regs *regs) 1151 { 1152 #define PERF_X86_EVENT_PEBS_HSW_PREC \ 1153 (PERF_X86_EVENT_PEBS_ST_HSW | \ 1154 PERF_X86_EVENT_PEBS_LD_HSW | \ 1155 PERF_X86_EVENT_PEBS_NA_HSW) 1156 /* 1157 * We cast to the biggest pebs_record but are careful not to 1158 * unconditionally access the 'extra' entries. 1159 */ 1160 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1161 struct pebs_record_skl *pebs = __pebs; 1162 u64 sample_type; 1163 int fll, fst, dsrc; 1164 int fl = event->hw.flags; 1165 1166 if (pebs == NULL) 1167 return; 1168 1169 sample_type = event->attr.sample_type; 1170 dsrc = sample_type & PERF_SAMPLE_DATA_SRC; 1171 1172 fll = fl & PERF_X86_EVENT_PEBS_LDLAT; 1173 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC); 1174 1175 perf_sample_data_init(data, 0, event->hw.last_period); 1176 1177 data->period = event->hw.last_period; 1178 1179 /* 1180 * Use latency for weight (only avail with PEBS-LL) 1181 */ 1182 if (fll && (sample_type & PERF_SAMPLE_WEIGHT)) 1183 data->weight = pebs->lat; 1184 1185 /* 1186 * data.data_src encodes the data source 1187 */ 1188 if (dsrc) { 1189 u64 val = PERF_MEM_NA; 1190 if (fll) 1191 val = load_latency_data(pebs->dse); 1192 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC)) 1193 val = precise_datala_hsw(event, pebs->dse); 1194 else if (fst) 1195 val = precise_store_data(pebs->dse); 1196 data->data_src.val = val; 1197 } 1198 1199 /* 1200 * We must however always use iregs for the unwinder to stay sane; the 1201 * record BP,SP,IP can point into thin air when the record is from a 1202 * previous PMI context or an (I)RET happened between the record and 1203 * PMI. 1204 */ 1205 if (sample_type & PERF_SAMPLE_CALLCHAIN) 1206 data->callchain = perf_callchain(event, iregs); 1207 1208 /* 1209 * We use the interrupt regs as a base because the PEBS record does not 1210 * contain a full regs set, specifically it seems to lack segment 1211 * descriptors, which get used by things like user_mode(). 1212 * 1213 * In the simple case fix up only the IP for PERF_SAMPLE_IP. 1214 */ 1215 *regs = *iregs; 1216 1217 /* 1218 * Initialize regs_>flags from PEBS, 1219 * Clear exact bit (which uses x86 EFLAGS Reserved bit 3), 1220 * i.e., do not rely on it being zero: 1221 */ 1222 regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT; 1223 1224 if (sample_type & PERF_SAMPLE_REGS_INTR) { 1225 regs->ax = pebs->ax; 1226 regs->bx = pebs->bx; 1227 regs->cx = pebs->cx; 1228 regs->dx = pebs->dx; 1229 regs->si = pebs->si; 1230 regs->di = pebs->di; 1231 1232 regs->bp = pebs->bp; 1233 regs->sp = pebs->sp; 1234 1235 #ifndef CONFIG_X86_32 1236 regs->r8 = pebs->r8; 1237 regs->r9 = pebs->r9; 1238 regs->r10 = pebs->r10; 1239 regs->r11 = pebs->r11; 1240 regs->r12 = pebs->r12; 1241 regs->r13 = pebs->r13; 1242 regs->r14 = pebs->r14; 1243 regs->r15 = pebs->r15; 1244 #endif 1245 } 1246 1247 if (event->attr.precise_ip > 1) { 1248 /* 1249 * Haswell and later processors have an 'eventing IP' 1250 * (real IP) which fixes the off-by-1 skid in hardware. 1251 * Use it when precise_ip >= 2 : 1252 */ 1253 if (x86_pmu.intel_cap.pebs_format >= 2) { 1254 set_linear_ip(regs, pebs->real_ip); 1255 regs->flags |= PERF_EFLAGS_EXACT; 1256 } else { 1257 /* Otherwise, use PEBS off-by-1 IP: */ 1258 set_linear_ip(regs, pebs->ip); 1259 1260 /* 1261 * With precise_ip >= 2, try to fix up the off-by-1 IP 1262 * using the LBR. If successful, the fixup function 1263 * corrects regs->ip and calls set_linear_ip() on regs: 1264 */ 1265 if (intel_pmu_pebs_fixup_ip(regs)) 1266 regs->flags |= PERF_EFLAGS_EXACT; 1267 } 1268 } else { 1269 /* 1270 * When precise_ip == 1, return the PEBS off-by-1 IP, 1271 * no fixup attempted: 1272 */ 1273 set_linear_ip(regs, pebs->ip); 1274 } 1275 1276 1277 if ((sample_type & (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR)) && 1278 x86_pmu.intel_cap.pebs_format >= 1) 1279 data->addr = pebs->dla; 1280 1281 if (x86_pmu.intel_cap.pebs_format >= 2) { 1282 /* Only set the TSX weight when no memory weight. */ 1283 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll) 1284 data->weight = intel_hsw_weight(pebs); 1285 1286 if (sample_type & PERF_SAMPLE_TRANSACTION) 1287 data->txn = intel_hsw_transaction(pebs); 1288 } 1289 1290 /* 1291 * v3 supplies an accurate time stamp, so we use that 1292 * for the time stamp. 1293 * 1294 * We can only do this for the default trace clock. 1295 */ 1296 if (x86_pmu.intel_cap.pebs_format >= 3 && 1297 event->attr.use_clockid == 0) 1298 data->time = native_sched_clock_from_tsc(pebs->tsc); 1299 1300 if (has_branch_stack(event)) 1301 data->br_stack = &cpuc->lbr_stack; 1302 } 1303 1304 static inline void * 1305 get_next_pebs_record_by_bit(void *base, void *top, int bit) 1306 { 1307 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1308 void *at; 1309 u64 pebs_status; 1310 1311 /* 1312 * fmt0 does not have a status bitfield (does not use 1313 * perf_record_nhm format) 1314 */ 1315 if (x86_pmu.intel_cap.pebs_format < 1) 1316 return base; 1317 1318 if (base == NULL) 1319 return NULL; 1320 1321 for (at = base; at < top; at += x86_pmu.pebs_record_size) { 1322 struct pebs_record_nhm *p = at; 1323 1324 if (test_bit(bit, (unsigned long *)&p->status)) { 1325 /* PEBS v3 has accurate status bits */ 1326 if (x86_pmu.intel_cap.pebs_format >= 3) 1327 return at; 1328 1329 if (p->status == (1 << bit)) 1330 return at; 1331 1332 /* clear non-PEBS bit and re-check */ 1333 pebs_status = p->status & cpuc->pebs_enabled; 1334 pebs_status &= PEBS_COUNTER_MASK; 1335 if (pebs_status == (1 << bit)) 1336 return at; 1337 } 1338 } 1339 return NULL; 1340 } 1341 1342 void intel_pmu_auto_reload_read(struct perf_event *event) 1343 { 1344 WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)); 1345 1346 perf_pmu_disable(event->pmu); 1347 intel_pmu_drain_pebs_buffer(); 1348 perf_pmu_enable(event->pmu); 1349 } 1350 1351 /* 1352 * Special variant of intel_pmu_save_and_restart() for auto-reload. 1353 */ 1354 static int 1355 intel_pmu_save_and_restart_reload(struct perf_event *event, int count) 1356 { 1357 struct hw_perf_event *hwc = &event->hw; 1358 int shift = 64 - x86_pmu.cntval_bits; 1359 u64 period = hwc->sample_period; 1360 u64 prev_raw_count, new_raw_count; 1361 s64 new, old; 1362 1363 WARN_ON(!period); 1364 1365 /* 1366 * drain_pebs() only happens when the PMU is disabled. 1367 */ 1368 WARN_ON(this_cpu_read(cpu_hw_events.enabled)); 1369 1370 prev_raw_count = local64_read(&hwc->prev_count); 1371 rdpmcl(hwc->event_base_rdpmc, new_raw_count); 1372 local64_set(&hwc->prev_count, new_raw_count); 1373 1374 /* 1375 * Since the counter increments a negative counter value and 1376 * overflows on the sign switch, giving the interval: 1377 * 1378 * [-period, 0] 1379 * 1380 * the difference between two consequtive reads is: 1381 * 1382 * A) value2 - value1; 1383 * when no overflows have happened in between, 1384 * 1385 * B) (0 - value1) + (value2 - (-period)); 1386 * when one overflow happened in between, 1387 * 1388 * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period)); 1389 * when @n overflows happened in between. 1390 * 1391 * Here A) is the obvious difference, B) is the extension to the 1392 * discrete interval, where the first term is to the top of the 1393 * interval and the second term is from the bottom of the next 1394 * interval and C) the extension to multiple intervals, where the 1395 * middle term is the whole intervals covered. 1396 * 1397 * An equivalent of C, by reduction, is: 1398 * 1399 * value2 - value1 + n * period 1400 */ 1401 new = ((s64)(new_raw_count << shift) >> shift); 1402 old = ((s64)(prev_raw_count << shift) >> shift); 1403 local64_add(new - old + count * period, &event->count); 1404 1405 perf_event_update_userpage(event); 1406 1407 return 0; 1408 } 1409 1410 static void __intel_pmu_pebs_event(struct perf_event *event, 1411 struct pt_regs *iregs, 1412 void *base, void *top, 1413 int bit, int count) 1414 { 1415 struct hw_perf_event *hwc = &event->hw; 1416 struct perf_sample_data data; 1417 struct pt_regs regs; 1418 void *at = get_next_pebs_record_by_bit(base, top, bit); 1419 1420 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { 1421 /* 1422 * Now, auto-reload is only enabled in fixed period mode. 1423 * The reload value is always hwc->sample_period. 1424 * May need to change it, if auto-reload is enabled in 1425 * freq mode later. 1426 */ 1427 intel_pmu_save_and_restart_reload(event, count); 1428 } else if (!intel_pmu_save_and_restart(event)) 1429 return; 1430 1431 while (count > 1) { 1432 setup_pebs_sample_data(event, iregs, at, &data, ®s); 1433 perf_event_output(event, &data, ®s); 1434 at += x86_pmu.pebs_record_size; 1435 at = get_next_pebs_record_by_bit(at, top, bit); 1436 count--; 1437 } 1438 1439 setup_pebs_sample_data(event, iregs, at, &data, ®s); 1440 1441 /* 1442 * All but the last records are processed. 1443 * The last one is left to be able to call the overflow handler. 1444 */ 1445 if (perf_event_overflow(event, &data, ®s)) { 1446 x86_pmu_stop(event, 0); 1447 return; 1448 } 1449 1450 } 1451 1452 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs) 1453 { 1454 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1455 struct debug_store *ds = cpuc->ds; 1456 struct perf_event *event = cpuc->events[0]; /* PMC0 only */ 1457 struct pebs_record_core *at, *top; 1458 int n; 1459 1460 if (!x86_pmu.pebs_active) 1461 return; 1462 1463 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base; 1464 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index; 1465 1466 /* 1467 * Whatever else happens, drain the thing 1468 */ 1469 ds->pebs_index = ds->pebs_buffer_base; 1470 1471 if (!test_bit(0, cpuc->active_mask)) 1472 return; 1473 1474 WARN_ON_ONCE(!event); 1475 1476 if (!event->attr.precise_ip) 1477 return; 1478 1479 n = top - at; 1480 if (n <= 0) { 1481 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 1482 intel_pmu_save_and_restart_reload(event, 0); 1483 return; 1484 } 1485 1486 __intel_pmu_pebs_event(event, iregs, at, top, 0, n); 1487 } 1488 1489 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) 1490 { 1491 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1492 struct debug_store *ds = cpuc->ds; 1493 struct perf_event *event; 1494 void *base, *at, *top; 1495 short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {}; 1496 short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {}; 1497 int bit, i, size; 1498 u64 mask; 1499 1500 if (!x86_pmu.pebs_active) 1501 return; 1502 1503 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base; 1504 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index; 1505 1506 ds->pebs_index = ds->pebs_buffer_base; 1507 1508 mask = (1ULL << x86_pmu.max_pebs_events) - 1; 1509 size = x86_pmu.max_pebs_events; 1510 if (x86_pmu.flags & PMU_FL_PEBS_ALL) { 1511 mask |= ((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED; 1512 size = INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed; 1513 } 1514 1515 if (unlikely(base >= top)) { 1516 /* 1517 * The drain_pebs() could be called twice in a short period 1518 * for auto-reload event in pmu::read(). There are no 1519 * overflows have happened in between. 1520 * It needs to call intel_pmu_save_and_restart_reload() to 1521 * update the event->count for this case. 1522 */ 1523 for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, 1524 size) { 1525 event = cpuc->events[bit]; 1526 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 1527 intel_pmu_save_and_restart_reload(event, 0); 1528 } 1529 return; 1530 } 1531 1532 for (at = base; at < top; at += x86_pmu.pebs_record_size) { 1533 struct pebs_record_nhm *p = at; 1534 u64 pebs_status; 1535 1536 pebs_status = p->status & cpuc->pebs_enabled; 1537 pebs_status &= mask; 1538 1539 /* PEBS v3 has more accurate status bits */ 1540 if (x86_pmu.intel_cap.pebs_format >= 3) { 1541 for_each_set_bit(bit, (unsigned long *)&pebs_status, 1542 size) 1543 counts[bit]++; 1544 1545 continue; 1546 } 1547 1548 /* 1549 * On some CPUs the PEBS status can be zero when PEBS is 1550 * racing with clearing of GLOBAL_STATUS. 1551 * 1552 * Normally we would drop that record, but in the 1553 * case when there is only a single active PEBS event 1554 * we can assume it's for that event. 1555 */ 1556 if (!pebs_status && cpuc->pebs_enabled && 1557 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1))) 1558 pebs_status = cpuc->pebs_enabled; 1559 1560 bit = find_first_bit((unsigned long *)&pebs_status, 1561 x86_pmu.max_pebs_events); 1562 if (bit >= x86_pmu.max_pebs_events) 1563 continue; 1564 1565 /* 1566 * The PEBS hardware does not deal well with the situation 1567 * when events happen near to each other and multiple bits 1568 * are set. But it should happen rarely. 1569 * 1570 * If these events include one PEBS and multiple non-PEBS 1571 * events, it doesn't impact PEBS record. The record will 1572 * be handled normally. (slow path) 1573 * 1574 * If these events include two or more PEBS events, the 1575 * records for the events can be collapsed into a single 1576 * one, and it's not possible to reconstruct all events 1577 * that caused the PEBS record. It's called collision. 1578 * If collision happened, the record will be dropped. 1579 */ 1580 if (p->status != (1ULL << bit)) { 1581 for_each_set_bit(i, (unsigned long *)&pebs_status, 1582 x86_pmu.max_pebs_events) 1583 error[i]++; 1584 continue; 1585 } 1586 1587 counts[bit]++; 1588 } 1589 1590 for (bit = 0; bit < size; bit++) { 1591 if ((counts[bit] == 0) && (error[bit] == 0)) 1592 continue; 1593 1594 event = cpuc->events[bit]; 1595 if (WARN_ON_ONCE(!event)) 1596 continue; 1597 1598 if (WARN_ON_ONCE(!event->attr.precise_ip)) 1599 continue; 1600 1601 /* log dropped samples number */ 1602 if (error[bit]) { 1603 perf_log_lost_samples(event, error[bit]); 1604 1605 if (perf_event_account_interrupt(event)) 1606 x86_pmu_stop(event, 0); 1607 } 1608 1609 if (counts[bit]) { 1610 __intel_pmu_pebs_event(event, iregs, base, 1611 top, bit, counts[bit]); 1612 } 1613 } 1614 } 1615 1616 /* 1617 * BTS, PEBS probe and setup 1618 */ 1619 1620 void __init intel_ds_init(void) 1621 { 1622 /* 1623 * No support for 32bit formats 1624 */ 1625 if (!boot_cpu_has(X86_FEATURE_DTES64)) 1626 return; 1627 1628 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS); 1629 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS); 1630 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE; 1631 if (x86_pmu.version <= 4) 1632 x86_pmu.pebs_no_isolation = 1; 1633 if (x86_pmu.pebs) { 1634 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-'; 1635 int format = x86_pmu.intel_cap.pebs_format; 1636 1637 switch (format) { 1638 case 0: 1639 pr_cont("PEBS fmt0%c, ", pebs_type); 1640 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core); 1641 /* 1642 * Using >PAGE_SIZE buffers makes the WRMSR to 1643 * PERF_GLOBAL_CTRL in intel_pmu_enable_all() 1644 * mysteriously hang on Core2. 1645 * 1646 * As a workaround, we don't do this. 1647 */ 1648 x86_pmu.pebs_buffer_size = PAGE_SIZE; 1649 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core; 1650 break; 1651 1652 case 1: 1653 pr_cont("PEBS fmt1%c, ", pebs_type); 1654 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm); 1655 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 1656 break; 1657 1658 case 2: 1659 pr_cont("PEBS fmt2%c, ", pebs_type); 1660 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw); 1661 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 1662 break; 1663 1664 case 3: 1665 pr_cont("PEBS fmt3%c, ", pebs_type); 1666 x86_pmu.pebs_record_size = 1667 sizeof(struct pebs_record_skl); 1668 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 1669 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME; 1670 break; 1671 1672 default: 1673 pr_cont("no PEBS fmt%d%c, ", format, pebs_type); 1674 x86_pmu.pebs = 0; 1675 } 1676 } 1677 } 1678 1679 void perf_restore_debug_store(void) 1680 { 1681 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 1682 1683 if (!x86_pmu.bts && !x86_pmu.pebs) 1684 return; 1685 1686 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds); 1687 } 1688