1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/bitops.h> 3 #include <linux/types.h> 4 #include <linux/slab.h> 5 #include <linux/sched/clock.h> 6 7 #include <asm/cpu_entry_area.h> 8 #include <asm/debugreg.h> 9 #include <asm/perf_event.h> 10 #include <asm/tlbflush.h> 11 #include <asm/insn.h> 12 #include <asm/io.h> 13 #include <asm/msr.h> 14 #include <asm/timer.h> 15 16 #include "../perf_event.h" 17 18 /* Waste a full page so it can be mapped into the cpu_entry_area */ 19 DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store); 20 21 /* The size of a BTS record in bytes: */ 22 #define BTS_RECORD_SIZE 24 23 24 #define PEBS_FIXUP_SIZE PAGE_SIZE 25 26 /* 27 * pebs_record_32 for p4 and core not supported 28 29 struct pebs_record_32 { 30 u32 flags, ip; 31 u32 ax, bc, cx, dx; 32 u32 si, di, bp, sp; 33 }; 34 35 */ 36 37 union intel_x86_pebs_dse { 38 u64 val; 39 struct { 40 unsigned int ld_dse:4; 41 unsigned int ld_stlb_miss:1; 42 unsigned int ld_locked:1; 43 unsigned int ld_data_blk:1; 44 unsigned int ld_addr_blk:1; 45 unsigned int ld_reserved:24; 46 }; 47 struct { 48 unsigned int st_l1d_hit:1; 49 unsigned int st_reserved1:3; 50 unsigned int st_stlb_miss:1; 51 unsigned int st_locked:1; 52 unsigned int st_reserved2:26; 53 }; 54 struct { 55 unsigned int st_lat_dse:4; 56 unsigned int st_lat_stlb_miss:1; 57 unsigned int st_lat_locked:1; 58 unsigned int ld_reserved3:26; 59 }; 60 struct { 61 unsigned int mtl_dse:5; 62 unsigned int mtl_locked:1; 63 unsigned int mtl_stlb_miss:1; 64 unsigned int mtl_fwd_blk:1; 65 unsigned int ld_reserved4:24; 66 }; 67 struct { 68 unsigned int lnc_dse:8; 69 unsigned int ld_reserved5:2; 70 unsigned int lnc_stlb_miss:1; 71 unsigned int lnc_locked:1; 72 unsigned int lnc_data_blk:1; 73 unsigned int lnc_addr_blk:1; 74 unsigned int ld_reserved6:18; 75 }; 76 }; 77 78 79 /* 80 * Map PEBS Load Latency Data Source encodings to generic 81 * memory data source information 82 */ 83 #define P(a, b) PERF_MEM_S(a, b) 84 #define OP_LH (P(OP, LOAD) | P(LVL, HIT)) 85 #define LEVEL(x) P(LVLNUM, x) 86 #define REM P(REMOTE, REMOTE) 87 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS)) 88 89 /* Version for Sandy Bridge and later */ 90 static u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX] = { 91 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */ 92 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */ 93 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */ 94 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */ 95 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */ 96 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */ 97 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */ 98 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */ 99 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */ 100 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/ 101 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */ 102 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */ 103 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */ 104 OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */ 105 OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */ 106 OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */ 107 }; 108 109 /* Patch up minor differences in the bits */ 110 void __init intel_pmu_pebs_data_source_nhm(void) 111 { 112 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); 113 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); 114 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); 115 } 116 117 static void __init __intel_pmu_pebs_data_source_skl(bool pmem, u64 *data_source) 118 { 119 u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4); 120 121 data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT); 122 data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT); 123 data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); 124 data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD); 125 data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM); 126 } 127 128 void __init intel_pmu_pebs_data_source_skl(bool pmem) 129 { 130 __intel_pmu_pebs_data_source_skl(pmem, pebs_data_source); 131 } 132 133 static void __init __intel_pmu_pebs_data_source_grt(u64 *data_source) 134 { 135 data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); 136 data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); 137 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD); 138 } 139 140 void __init intel_pmu_pebs_data_source_grt(void) 141 { 142 __intel_pmu_pebs_data_source_grt(pebs_data_source); 143 } 144 145 void __init intel_pmu_pebs_data_source_adl(void) 146 { 147 u64 *data_source; 148 149 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source; 150 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); 151 __intel_pmu_pebs_data_source_skl(false, data_source); 152 153 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source; 154 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); 155 __intel_pmu_pebs_data_source_grt(data_source); 156 } 157 158 static void __init __intel_pmu_pebs_data_source_cmt(u64 *data_source) 159 { 160 data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD); 161 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); 162 data_source[0x0a] = OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, NONE); 163 data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); 164 data_source[0x0c] = OP_LH | LEVEL(RAM) | REM | P(SNOOPX, FWD); 165 data_source[0x0d] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, HITM); 166 } 167 168 void __init intel_pmu_pebs_data_source_mtl(void) 169 { 170 u64 *data_source; 171 172 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source; 173 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); 174 __intel_pmu_pebs_data_source_skl(false, data_source); 175 176 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source; 177 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); 178 __intel_pmu_pebs_data_source_cmt(data_source); 179 } 180 181 void __init intel_pmu_pebs_data_source_arl_h(void) 182 { 183 u64 *data_source; 184 185 intel_pmu_pebs_data_source_lnl(); 186 187 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX].pebs_data_source; 188 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); 189 __intel_pmu_pebs_data_source_cmt(data_source); 190 } 191 192 void __init intel_pmu_pebs_data_source_cmt(void) 193 { 194 __intel_pmu_pebs_data_source_cmt(pebs_data_source); 195 } 196 197 /* Version for Lion Cove and later */ 198 static u64 lnc_pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX] = { 199 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA), /* 0x00: ukn L3 */ 200 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 hit */ 201 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x02: L1 hit */ 202 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x03: LFB/L1 Miss Handling Buffer hit */ 203 0, /* 0x04: Reserved */ 204 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x05: L2 Hit */ 205 OP_LH | LEVEL(L2_MHB) | P(SNOOP, NONE), /* 0x06: L2 Miss Handling Buffer Hit */ 206 0, /* 0x07: Reserved */ 207 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x08: L3 Hit */ 208 0, /* 0x09: Reserved */ 209 0, /* 0x0a: Reserved */ 210 0, /* 0x0b: Reserved */ 211 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD), /* 0x0c: L3 Hit Snoop Fwd */ 212 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x0d: L3 Hit Snoop HitM */ 213 0, /* 0x0e: Reserved */ 214 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x0f: L3 Miss Snoop HitM */ 215 OP_LH | LEVEL(MSC) | P(SNOOP, NONE), /* 0x10: Memory-side Cache Hit */ 216 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, NONE), /* 0x11: Local Memory Hit */ 217 }; 218 219 void __init intel_pmu_pebs_data_source_lnl(void) 220 { 221 u64 *data_source; 222 223 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source; 224 memcpy(data_source, lnc_pebs_data_source, sizeof(lnc_pebs_data_source)); 225 226 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source; 227 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); 228 __intel_pmu_pebs_data_source_cmt(data_source); 229 } 230 231 static u64 precise_store_data(u64 status) 232 { 233 union intel_x86_pebs_dse dse; 234 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); 235 236 dse.val = status; 237 238 /* 239 * bit 4: TLB access 240 * 1 = stored missed 2nd level TLB 241 * 242 * so it either hit the walker or the OS 243 * otherwise hit 2nd level TLB 244 */ 245 if (dse.st_stlb_miss) 246 val |= P(TLB, MISS); 247 else 248 val |= P(TLB, HIT); 249 250 /* 251 * bit 0: hit L1 data cache 252 * if not set, then all we know is that 253 * it missed L1D 254 */ 255 if (dse.st_l1d_hit) 256 val |= P(LVL, HIT); 257 else 258 val |= P(LVL, MISS); 259 260 /* 261 * bit 5: Locked prefix 262 */ 263 if (dse.st_locked) 264 val |= P(LOCK, LOCKED); 265 266 return val; 267 } 268 269 static u64 precise_datala_hsw(struct perf_event *event, u64 status) 270 { 271 union perf_mem_data_src dse; 272 273 dse.val = PERF_MEM_NA; 274 275 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) 276 dse.mem_op = PERF_MEM_OP_STORE; 277 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW) 278 dse.mem_op = PERF_MEM_OP_LOAD; 279 280 /* 281 * L1 info only valid for following events: 282 * 283 * MEM_UOPS_RETIRED.STLB_MISS_STORES 284 * MEM_UOPS_RETIRED.LOCK_STORES 285 * MEM_UOPS_RETIRED.SPLIT_STORES 286 * MEM_UOPS_RETIRED.ALL_STORES 287 */ 288 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) { 289 if (status & 1) 290 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT; 291 else 292 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS; 293 } 294 return dse.val; 295 } 296 297 static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock) 298 { 299 /* 300 * TLB access 301 * 0 = did not miss 2nd level TLB 302 * 1 = missed 2nd level TLB 303 */ 304 if (tlb) 305 *val |= P(TLB, MISS) | P(TLB, L2); 306 else 307 *val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); 308 309 /* locked prefix */ 310 if (lock) 311 *val |= P(LOCK, LOCKED); 312 } 313 314 /* Retrieve the latency data for e-core of ADL */ 315 static u64 __grt_latency_data(struct perf_event *event, u64 status, 316 u8 dse, bool tlb, bool lock, bool blk) 317 { 318 u64 val; 319 320 WARN_ON_ONCE(is_hybrid() && 321 hybrid_pmu(event->pmu)->pmu_type == hybrid_big); 322 323 dse &= PERF_PEBS_DATA_SOURCE_GRT_MASK; 324 val = hybrid_var(event->pmu, pebs_data_source)[dse]; 325 326 pebs_set_tlb_lock(&val, tlb, lock); 327 328 if (blk) 329 val |= P(BLK, DATA); 330 else 331 val |= P(BLK, NA); 332 333 return val; 334 } 335 336 u64 grt_latency_data(struct perf_event *event, u64 status) 337 { 338 union intel_x86_pebs_dse dse; 339 340 dse.val = status; 341 342 return __grt_latency_data(event, status, dse.ld_dse, 343 dse.ld_locked, dse.ld_stlb_miss, 344 dse.ld_data_blk); 345 } 346 347 /* Retrieve the latency data for e-core of MTL */ 348 u64 cmt_latency_data(struct perf_event *event, u64 status) 349 { 350 union intel_x86_pebs_dse dse; 351 352 dse.val = status; 353 354 return __grt_latency_data(event, status, dse.mtl_dse, 355 dse.mtl_stlb_miss, dse.mtl_locked, 356 dse.mtl_fwd_blk); 357 } 358 359 static u64 lnc_latency_data(struct perf_event *event, u64 status) 360 { 361 union intel_x86_pebs_dse dse; 362 union perf_mem_data_src src; 363 u64 val; 364 365 dse.val = status; 366 367 /* LNC core latency data */ 368 val = hybrid_var(event->pmu, pebs_data_source)[status & PERF_PEBS_DATA_SOURCE_MASK]; 369 if (!val) 370 val = P(OP, LOAD) | LEVEL(NA) | P(SNOOP, NA); 371 372 if (dse.lnc_stlb_miss) 373 val |= P(TLB, MISS) | P(TLB, L2); 374 else 375 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); 376 377 if (dse.lnc_locked) 378 val |= P(LOCK, LOCKED); 379 380 if (dse.lnc_data_blk) 381 val |= P(BLK, DATA); 382 if (dse.lnc_addr_blk) 383 val |= P(BLK, ADDR); 384 if (!dse.lnc_data_blk && !dse.lnc_addr_blk) 385 val |= P(BLK, NA); 386 387 src.val = val; 388 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) 389 src.mem_op = P(OP, STORE); 390 391 return src.val; 392 } 393 394 u64 lnl_latency_data(struct perf_event *event, u64 status) 395 { 396 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 397 398 if (pmu->pmu_type == hybrid_small) 399 return cmt_latency_data(event, status); 400 401 return lnc_latency_data(event, status); 402 } 403 404 u64 arl_h_latency_data(struct perf_event *event, u64 status) 405 { 406 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 407 408 if (pmu->pmu_type == hybrid_tiny) 409 return cmt_latency_data(event, status); 410 411 return lnl_latency_data(event, status); 412 } 413 414 static u64 load_latency_data(struct perf_event *event, u64 status) 415 { 416 union intel_x86_pebs_dse dse; 417 u64 val; 418 419 dse.val = status; 420 421 /* 422 * use the mapping table for bit 0-3 423 */ 424 val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse]; 425 426 /* 427 * Nehalem models do not support TLB, Lock infos 428 */ 429 if (x86_pmu.pebs_no_tlb) { 430 val |= P(TLB, NA) | P(LOCK, NA); 431 return val; 432 } 433 434 pebs_set_tlb_lock(&val, dse.ld_stlb_miss, dse.ld_locked); 435 436 /* 437 * Ice Lake and earlier models do not support block infos. 438 */ 439 if (!x86_pmu.pebs_block) { 440 val |= P(BLK, NA); 441 return val; 442 } 443 /* 444 * bit 6: load was blocked since its data could not be forwarded 445 * from a preceding store 446 */ 447 if (dse.ld_data_blk) 448 val |= P(BLK, DATA); 449 450 /* 451 * bit 7: load was blocked due to potential address conflict with 452 * a preceding store 453 */ 454 if (dse.ld_addr_blk) 455 val |= P(BLK, ADDR); 456 457 if (!dse.ld_data_blk && !dse.ld_addr_blk) 458 val |= P(BLK, NA); 459 460 return val; 461 } 462 463 static u64 store_latency_data(struct perf_event *event, u64 status) 464 { 465 union intel_x86_pebs_dse dse; 466 union perf_mem_data_src src; 467 u64 val; 468 469 dse.val = status; 470 471 /* 472 * use the mapping table for bit 0-3 473 */ 474 val = hybrid_var(event->pmu, pebs_data_source)[dse.st_lat_dse]; 475 476 pebs_set_tlb_lock(&val, dse.st_lat_stlb_miss, dse.st_lat_locked); 477 478 val |= P(BLK, NA); 479 480 /* 481 * the pebs_data_source table is only for loads 482 * so override the mem_op to say STORE instead 483 */ 484 src.val = val; 485 src.mem_op = P(OP,STORE); 486 487 return src.val; 488 } 489 490 struct pebs_record_core { 491 u64 flags, ip; 492 u64 ax, bx, cx, dx; 493 u64 si, di, bp, sp; 494 u64 r8, r9, r10, r11; 495 u64 r12, r13, r14, r15; 496 }; 497 498 struct pebs_record_nhm { 499 u64 flags, ip; 500 u64 ax, bx, cx, dx; 501 u64 si, di, bp, sp; 502 u64 r8, r9, r10, r11; 503 u64 r12, r13, r14, r15; 504 u64 status, dla, dse, lat; 505 }; 506 507 /* 508 * Same as pebs_record_nhm, with two additional fields. 509 */ 510 struct pebs_record_hsw { 511 u64 flags, ip; 512 u64 ax, bx, cx, dx; 513 u64 si, di, bp, sp; 514 u64 r8, r9, r10, r11; 515 u64 r12, r13, r14, r15; 516 u64 status, dla, dse, lat; 517 u64 real_ip, tsx_tuning; 518 }; 519 520 union hsw_tsx_tuning { 521 struct { 522 u32 cycles_last_block : 32, 523 hle_abort : 1, 524 rtm_abort : 1, 525 instruction_abort : 1, 526 non_instruction_abort : 1, 527 retry : 1, 528 data_conflict : 1, 529 capacity_writes : 1, 530 capacity_reads : 1; 531 }; 532 u64 value; 533 }; 534 535 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL 536 537 /* Same as HSW, plus TSC */ 538 539 struct pebs_record_skl { 540 u64 flags, ip; 541 u64 ax, bx, cx, dx; 542 u64 si, di, bp, sp; 543 u64 r8, r9, r10, r11; 544 u64 r12, r13, r14, r15; 545 u64 status, dla, dse, lat; 546 u64 real_ip, tsx_tuning; 547 u64 tsc; 548 }; 549 550 void init_debug_store_on_cpu(int cpu) 551 { 552 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; 553 554 if (!ds) 555 return; 556 557 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 558 (u32)((u64)(unsigned long)ds), 559 (u32)((u64)(unsigned long)ds >> 32)); 560 } 561 562 void fini_debug_store_on_cpu(int cpu) 563 { 564 if (!per_cpu(cpu_hw_events, cpu).ds) 565 return; 566 567 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); 568 } 569 570 static DEFINE_PER_CPU(void *, insn_buffer); 571 572 static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot) 573 { 574 unsigned long start = (unsigned long)cea; 575 phys_addr_t pa; 576 size_t msz = 0; 577 578 pa = virt_to_phys(addr); 579 580 preempt_disable(); 581 for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE) 582 cea_set_pte(cea, pa, prot); 583 584 /* 585 * This is a cross-CPU update of the cpu_entry_area, we must shoot down 586 * all TLB entries for it. 587 */ 588 flush_tlb_kernel_range(start, start + size); 589 preempt_enable(); 590 } 591 592 static void ds_clear_cea(void *cea, size_t size) 593 { 594 unsigned long start = (unsigned long)cea; 595 size_t msz = 0; 596 597 preempt_disable(); 598 for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE) 599 cea_set_pte(cea, 0, PAGE_NONE); 600 601 flush_tlb_kernel_range(start, start + size); 602 preempt_enable(); 603 } 604 605 static void *dsalloc_pages(size_t size, gfp_t flags, int cpu) 606 { 607 unsigned int order = get_order(size); 608 int node = cpu_to_node(cpu); 609 struct page *page; 610 611 page = __alloc_pages_node(node, flags | __GFP_ZERO, order); 612 return page ? page_address(page) : NULL; 613 } 614 615 static void dsfree_pages(const void *buffer, size_t size) 616 { 617 if (buffer) 618 free_pages((unsigned long)buffer, get_order(size)); 619 } 620 621 static int alloc_pebs_buffer(int cpu) 622 { 623 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 624 struct debug_store *ds = hwev->ds; 625 size_t bsiz = x86_pmu.pebs_buffer_size; 626 int max, node = cpu_to_node(cpu); 627 void *buffer, *insn_buff, *cea; 628 629 if (!x86_pmu.ds_pebs) 630 return 0; 631 632 buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu); 633 if (unlikely(!buffer)) 634 return -ENOMEM; 635 636 /* 637 * HSW+ already provides us the eventing ip; no need to allocate this 638 * buffer then. 639 */ 640 if (x86_pmu.intel_cap.pebs_format < 2) { 641 insn_buff = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node); 642 if (!insn_buff) { 643 dsfree_pages(buffer, bsiz); 644 return -ENOMEM; 645 } 646 per_cpu(insn_buffer, cpu) = insn_buff; 647 } 648 hwev->ds_pebs_vaddr = buffer; 649 /* Update the cpu entry area mapping */ 650 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; 651 ds->pebs_buffer_base = (unsigned long) cea; 652 ds_update_cea(cea, buffer, bsiz, PAGE_KERNEL); 653 ds->pebs_index = ds->pebs_buffer_base; 654 max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size); 655 ds->pebs_absolute_maximum = ds->pebs_buffer_base + max; 656 return 0; 657 } 658 659 static void release_pebs_buffer(int cpu) 660 { 661 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 662 void *cea; 663 664 if (!x86_pmu.ds_pebs) 665 return; 666 667 kfree(per_cpu(insn_buffer, cpu)); 668 per_cpu(insn_buffer, cpu) = NULL; 669 670 /* Clear the fixmap */ 671 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; 672 ds_clear_cea(cea, x86_pmu.pebs_buffer_size); 673 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size); 674 hwev->ds_pebs_vaddr = NULL; 675 } 676 677 static int alloc_bts_buffer(int cpu) 678 { 679 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 680 struct debug_store *ds = hwev->ds; 681 void *buffer, *cea; 682 int max; 683 684 if (!x86_pmu.bts) 685 return 0; 686 687 buffer = dsalloc_pages(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, cpu); 688 if (unlikely(!buffer)) { 689 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__); 690 return -ENOMEM; 691 } 692 hwev->ds_bts_vaddr = buffer; 693 /* Update the fixmap */ 694 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; 695 ds->bts_buffer_base = (unsigned long) cea; 696 ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL); 697 ds->bts_index = ds->bts_buffer_base; 698 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE; 699 ds->bts_absolute_maximum = ds->bts_buffer_base + 700 max * BTS_RECORD_SIZE; 701 ds->bts_interrupt_threshold = ds->bts_absolute_maximum - 702 (max / 16) * BTS_RECORD_SIZE; 703 return 0; 704 } 705 706 static void release_bts_buffer(int cpu) 707 { 708 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 709 void *cea; 710 711 if (!x86_pmu.bts) 712 return; 713 714 /* Clear the fixmap */ 715 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; 716 ds_clear_cea(cea, BTS_BUFFER_SIZE); 717 dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE); 718 hwev->ds_bts_vaddr = NULL; 719 } 720 721 static int alloc_ds_buffer(int cpu) 722 { 723 struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store; 724 725 memset(ds, 0, sizeof(*ds)); 726 per_cpu(cpu_hw_events, cpu).ds = ds; 727 return 0; 728 } 729 730 static void release_ds_buffer(int cpu) 731 { 732 per_cpu(cpu_hw_events, cpu).ds = NULL; 733 } 734 735 void release_ds_buffers(void) 736 { 737 int cpu; 738 739 if (!x86_pmu.bts && !x86_pmu.ds_pebs) 740 return; 741 742 for_each_possible_cpu(cpu) 743 release_ds_buffer(cpu); 744 745 for_each_possible_cpu(cpu) { 746 /* 747 * Again, ignore errors from offline CPUs, they will no longer 748 * observe cpu_hw_events.ds and not program the DS_AREA when 749 * they come up. 750 */ 751 fini_debug_store_on_cpu(cpu); 752 } 753 754 for_each_possible_cpu(cpu) { 755 if (x86_pmu.ds_pebs) 756 release_pebs_buffer(cpu); 757 release_bts_buffer(cpu); 758 } 759 } 760 761 void reserve_ds_buffers(void) 762 { 763 int bts_err = 0, pebs_err = 0; 764 int cpu; 765 766 x86_pmu.bts_active = 0; 767 768 if (x86_pmu.ds_pebs) 769 x86_pmu.pebs_active = 0; 770 771 if (!x86_pmu.bts && !x86_pmu.ds_pebs) 772 return; 773 774 if (!x86_pmu.bts) 775 bts_err = 1; 776 777 if (!x86_pmu.ds_pebs) 778 pebs_err = 1; 779 780 for_each_possible_cpu(cpu) { 781 if (alloc_ds_buffer(cpu)) { 782 bts_err = 1; 783 pebs_err = 1; 784 } 785 786 if (!bts_err && alloc_bts_buffer(cpu)) 787 bts_err = 1; 788 789 if (x86_pmu.ds_pebs && !pebs_err && 790 alloc_pebs_buffer(cpu)) 791 pebs_err = 1; 792 793 if (bts_err && pebs_err) 794 break; 795 } 796 797 if (bts_err) { 798 for_each_possible_cpu(cpu) 799 release_bts_buffer(cpu); 800 } 801 802 if (x86_pmu.ds_pebs && pebs_err) { 803 for_each_possible_cpu(cpu) 804 release_pebs_buffer(cpu); 805 } 806 807 if (bts_err && pebs_err) { 808 for_each_possible_cpu(cpu) 809 release_ds_buffer(cpu); 810 } else { 811 if (x86_pmu.bts && !bts_err) 812 x86_pmu.bts_active = 1; 813 814 if (x86_pmu.ds_pebs && !pebs_err) 815 x86_pmu.pebs_active = 1; 816 817 for_each_possible_cpu(cpu) { 818 /* 819 * Ignores wrmsr_on_cpu() errors for offline CPUs they 820 * will get this call through intel_pmu_cpu_starting(). 821 */ 822 init_debug_store_on_cpu(cpu); 823 } 824 } 825 } 826 827 /* 828 * BTS 829 */ 830 831 struct event_constraint bts_constraint = 832 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0); 833 834 void intel_pmu_enable_bts(u64 config) 835 { 836 unsigned long debugctlmsr; 837 838 debugctlmsr = get_debugctlmsr(); 839 840 debugctlmsr |= DEBUGCTLMSR_TR; 841 debugctlmsr |= DEBUGCTLMSR_BTS; 842 if (config & ARCH_PERFMON_EVENTSEL_INT) 843 debugctlmsr |= DEBUGCTLMSR_BTINT; 844 845 if (!(config & ARCH_PERFMON_EVENTSEL_OS)) 846 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS; 847 848 if (!(config & ARCH_PERFMON_EVENTSEL_USR)) 849 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR; 850 851 update_debugctlmsr(debugctlmsr); 852 } 853 854 void intel_pmu_disable_bts(void) 855 { 856 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 857 unsigned long debugctlmsr; 858 859 if (!cpuc->ds) 860 return; 861 862 debugctlmsr = get_debugctlmsr(); 863 864 debugctlmsr &= 865 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT | 866 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR); 867 868 update_debugctlmsr(debugctlmsr); 869 } 870 871 int intel_pmu_drain_bts_buffer(void) 872 { 873 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 874 struct debug_store *ds = cpuc->ds; 875 struct bts_record { 876 u64 from; 877 u64 to; 878 u64 flags; 879 }; 880 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 881 struct bts_record *at, *base, *top; 882 struct perf_output_handle handle; 883 struct perf_event_header header; 884 struct perf_sample_data data; 885 unsigned long skip = 0; 886 struct pt_regs regs; 887 888 if (!event) 889 return 0; 890 891 if (!x86_pmu.bts_active) 892 return 0; 893 894 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base; 895 top = (struct bts_record *)(unsigned long)ds->bts_index; 896 897 if (top <= base) 898 return 0; 899 900 memset(®s, 0, sizeof(regs)); 901 902 ds->bts_index = ds->bts_buffer_base; 903 904 perf_sample_data_init(&data, 0, event->hw.last_period); 905 906 /* 907 * BTS leaks kernel addresses in branches across the cpl boundary, 908 * such as traps or system calls, so unless the user is asking for 909 * kernel tracing (and right now it's not possible), we'd need to 910 * filter them out. But first we need to count how many of those we 911 * have in the current batch. This is an extra O(n) pass, however, 912 * it's much faster than the other one especially considering that 913 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the 914 * alloc_bts_buffer()). 915 */ 916 for (at = base; at < top; at++) { 917 /* 918 * Note that right now *this* BTS code only works if 919 * attr::exclude_kernel is set, but let's keep this extra 920 * check here in case that changes. 921 */ 922 if (event->attr.exclude_kernel && 923 (kernel_ip(at->from) || kernel_ip(at->to))) 924 skip++; 925 } 926 927 /* 928 * Prepare a generic sample, i.e. fill in the invariant fields. 929 * We will overwrite the from and to address before we output 930 * the sample. 931 */ 932 rcu_read_lock(); 933 perf_prepare_sample(&data, event, ®s); 934 perf_prepare_header(&header, &data, event, ®s); 935 936 if (perf_output_begin(&handle, &data, event, 937 header.size * (top - base - skip))) 938 goto unlock; 939 940 for (at = base; at < top; at++) { 941 /* Filter out any records that contain kernel addresses. */ 942 if (event->attr.exclude_kernel && 943 (kernel_ip(at->from) || kernel_ip(at->to))) 944 continue; 945 946 data.ip = at->from; 947 data.addr = at->to; 948 949 perf_output_sample(&handle, &header, &data, event); 950 } 951 952 perf_output_end(&handle); 953 954 /* There's new data available. */ 955 event->hw.interrupts++; 956 event->pending_kill = POLL_IN; 957 unlock: 958 rcu_read_unlock(); 959 return 1; 960 } 961 962 void intel_pmu_drain_pebs_buffer(void) 963 { 964 struct perf_sample_data data; 965 966 static_call(x86_pmu_drain_pebs)(NULL, &data); 967 } 968 969 /* 970 * PEBS 971 */ 972 struct event_constraint intel_core2_pebs_event_constraints[] = { 973 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ 974 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */ 975 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */ 976 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */ 977 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ 978 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 979 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01), 980 EVENT_CONSTRAINT_END 981 }; 982 983 struct event_constraint intel_atom_pebs_event_constraints[] = { 984 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ 985 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */ 986 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ 987 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 988 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01), 989 /* Allow all events as PEBS with no flags */ 990 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), 991 EVENT_CONSTRAINT_END 992 }; 993 994 struct event_constraint intel_slm_pebs_event_constraints[] = { 995 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 996 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x1), 997 /* Allow all events as PEBS with no flags */ 998 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), 999 EVENT_CONSTRAINT_END 1000 }; 1001 1002 struct event_constraint intel_glm_pebs_event_constraints[] = { 1003 /* Allow all events as PEBS with no flags */ 1004 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), 1005 EVENT_CONSTRAINT_END 1006 }; 1007 1008 struct event_constraint intel_grt_pebs_event_constraints[] = { 1009 /* Allow all events as PEBS with no flags */ 1010 INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3), 1011 INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xf), 1012 EVENT_CONSTRAINT_END 1013 }; 1014 1015 struct event_constraint intel_nehalem_pebs_event_constraints[] = { 1016 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ 1017 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ 1018 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ 1019 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */ 1020 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ 1021 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ 1022 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */ 1023 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ 1024 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ 1025 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ 1026 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ 1027 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 1028 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f), 1029 EVENT_CONSTRAINT_END 1030 }; 1031 1032 struct event_constraint intel_westmere_pebs_event_constraints[] = { 1033 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ 1034 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ 1035 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ 1036 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */ 1037 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ 1038 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ 1039 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */ 1040 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ 1041 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ 1042 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ 1043 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ 1044 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 1045 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f), 1046 EVENT_CONSTRAINT_END 1047 }; 1048 1049 struct event_constraint intel_snb_pebs_event_constraints[] = { 1050 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 1051 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ 1052 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ 1053 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 1054 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf), 1055 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ 1056 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 1057 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 1058 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 1059 /* Allow all events as PEBS with no flags */ 1060 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 1061 EVENT_CONSTRAINT_END 1062 }; 1063 1064 struct event_constraint intel_ivb_pebs_event_constraints[] = { 1065 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 1066 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ 1067 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ 1068 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 1069 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf), 1070 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 1071 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2), 1072 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ 1073 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 1074 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 1075 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 1076 /* Allow all events as PEBS with no flags */ 1077 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 1078 EVENT_CONSTRAINT_END 1079 }; 1080 1081 struct event_constraint intel_hsw_pebs_event_constraints[] = { 1082 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 1083 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ 1084 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 1085 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf), 1086 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 1087 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2), 1088 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ 1089 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ 1090 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ 1091 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ 1092 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ 1093 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ 1094 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ 1095 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ 1096 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 1097 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ 1098 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ 1099 /* Allow all events as PEBS with no flags */ 1100 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 1101 EVENT_CONSTRAINT_END 1102 }; 1103 1104 struct event_constraint intel_bdw_pebs_event_constraints[] = { 1105 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 1106 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ 1107 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 1108 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf), 1109 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 1110 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2), 1111 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ 1112 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ 1113 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ 1114 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ 1115 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ 1116 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ 1117 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ 1118 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ 1119 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 1120 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ 1121 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ 1122 /* Allow all events as PEBS with no flags */ 1123 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 1124 EVENT_CONSTRAINT_END 1125 }; 1126 1127 1128 struct event_constraint intel_skl_pebs_event_constraints[] = { 1129 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 1130 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 1131 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2), 1132 /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */ 1133 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f), 1134 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */ 1135 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */ 1136 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */ 1137 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */ 1138 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */ 1139 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */ 1140 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */ 1141 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */ 1142 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */ 1143 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 1144 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 1145 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */ 1146 /* Allow all events as PEBS with no flags */ 1147 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 1148 EVENT_CONSTRAINT_END 1149 }; 1150 1151 struct event_constraint intel_icl_pebs_event_constraints[] = { 1152 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x100000000ULL), /* old INST_RETIRED.PREC_DIST */ 1153 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */ 1154 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), /* SLOTS */ 1155 1156 INTEL_PLD_CONSTRAINT(0x1cd, 0xff), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 1157 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */ 1158 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */ 1159 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */ 1160 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */ 1161 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */ 1162 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */ 1163 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */ 1164 1165 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), /* MEM_LOAD_*_RETIRED.* */ 1166 1167 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 1168 1169 /* 1170 * Everything else is handled by PMU_FL_PEBS_ALL, because we 1171 * need the full constraints from the main table. 1172 */ 1173 1174 EVENT_CONSTRAINT_END 1175 }; 1176 1177 struct event_constraint intel_glc_pebs_event_constraints[] = { 1178 INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */ 1179 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), 1180 1181 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe), 1182 INTEL_PLD_CONSTRAINT(0x1cd, 0xfe), 1183 INTEL_PSD_CONSTRAINT(0x2cd, 0x1), 1184 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */ 1185 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */ 1186 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */ 1187 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */ 1188 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */ 1189 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */ 1190 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */ 1191 1192 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), 1193 1194 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf), 1195 1196 /* 1197 * Everything else is handled by PMU_FL_PEBS_ALL, because we 1198 * need the full constraints from the main table. 1199 */ 1200 1201 EVENT_CONSTRAINT_END 1202 }; 1203 1204 struct event_constraint intel_lnc_pebs_event_constraints[] = { 1205 INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */ 1206 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), 1207 1208 INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0x3fc), 1209 INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3), 1210 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */ 1211 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */ 1212 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */ 1213 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */ 1214 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */ 1215 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */ 1216 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */ 1217 1218 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), 1219 1220 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf), 1221 1222 /* 1223 * Everything else is handled by PMU_FL_PEBS_ALL, because we 1224 * need the full constraints from the main table. 1225 */ 1226 1227 EVENT_CONSTRAINT_END 1228 }; 1229 1230 struct event_constraint *intel_pebs_constraints(struct perf_event *event) 1231 { 1232 struct event_constraint *pebs_constraints = hybrid(event->pmu, pebs_constraints); 1233 struct event_constraint *c; 1234 1235 if (!event->attr.precise_ip) 1236 return NULL; 1237 1238 if (pebs_constraints) { 1239 for_each_event_constraint(c, pebs_constraints) { 1240 if (constraint_match(c, event->hw.config)) { 1241 event->hw.flags |= c->flags; 1242 return c; 1243 } 1244 } 1245 } 1246 1247 /* 1248 * Extended PEBS support 1249 * Makes the PEBS code search the normal constraints. 1250 */ 1251 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 1252 return NULL; 1253 1254 return &emptyconstraint; 1255 } 1256 1257 /* 1258 * We need the sched_task callback even for per-cpu events when we use 1259 * the large interrupt threshold, such that we can provide PID and TID 1260 * to PEBS samples. 1261 */ 1262 static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc) 1263 { 1264 if (cpuc->n_pebs == cpuc->n_pebs_via_pt) 1265 return false; 1266 1267 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs); 1268 } 1269 1270 void intel_pmu_pebs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in) 1271 { 1272 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1273 1274 if (!sched_in && pebs_needs_sched_cb(cpuc)) 1275 intel_pmu_drain_pebs_buffer(); 1276 } 1277 1278 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc) 1279 { 1280 struct debug_store *ds = cpuc->ds; 1281 int max_pebs_events = intel_pmu_max_num_pebs(cpuc->pmu); 1282 u64 threshold; 1283 int reserved; 1284 1285 if (cpuc->n_pebs_via_pt) 1286 return; 1287 1288 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 1289 reserved = max_pebs_events + x86_pmu_max_num_counters_fixed(cpuc->pmu); 1290 else 1291 reserved = max_pebs_events; 1292 1293 if (cpuc->n_pebs == cpuc->n_large_pebs) { 1294 threshold = ds->pebs_absolute_maximum - 1295 reserved * cpuc->pebs_record_size; 1296 } else { 1297 threshold = ds->pebs_buffer_base + cpuc->pebs_record_size; 1298 } 1299 1300 ds->pebs_interrupt_threshold = threshold; 1301 } 1302 1303 #define PEBS_DATACFG_CNTRS(x) \ 1304 ((x >> PEBS_DATACFG_CNTR_SHIFT) & PEBS_DATACFG_CNTR_MASK) 1305 1306 #define PEBS_DATACFG_CNTR_BIT(x) \ 1307 (((1ULL << x) & PEBS_DATACFG_CNTR_MASK) << PEBS_DATACFG_CNTR_SHIFT) 1308 1309 #define PEBS_DATACFG_FIX(x) \ 1310 ((x >> PEBS_DATACFG_FIX_SHIFT) & PEBS_DATACFG_FIX_MASK) 1311 1312 #define PEBS_DATACFG_FIX_BIT(x) \ 1313 (((1ULL << (x)) & PEBS_DATACFG_FIX_MASK) \ 1314 << PEBS_DATACFG_FIX_SHIFT) 1315 1316 static void adaptive_pebs_record_size_update(void) 1317 { 1318 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1319 u64 pebs_data_cfg = cpuc->pebs_data_cfg; 1320 int sz = sizeof(struct pebs_basic); 1321 1322 if (pebs_data_cfg & PEBS_DATACFG_MEMINFO) 1323 sz += sizeof(struct pebs_meminfo); 1324 if (pebs_data_cfg & PEBS_DATACFG_GP) 1325 sz += sizeof(struct pebs_gprs); 1326 if (pebs_data_cfg & PEBS_DATACFG_XMMS) 1327 sz += sizeof(struct pebs_xmm); 1328 if (pebs_data_cfg & PEBS_DATACFG_LBRS) 1329 sz += x86_pmu.lbr_nr * sizeof(struct lbr_entry); 1330 if (pebs_data_cfg & (PEBS_DATACFG_METRICS | PEBS_DATACFG_CNTR)) { 1331 sz += sizeof(struct pebs_cntr_header); 1332 1333 /* Metrics base and Metrics Data */ 1334 if (pebs_data_cfg & PEBS_DATACFG_METRICS) 1335 sz += 2 * sizeof(u64); 1336 1337 if (pebs_data_cfg & PEBS_DATACFG_CNTR) { 1338 sz += (hweight64(PEBS_DATACFG_CNTRS(pebs_data_cfg)) + 1339 hweight64(PEBS_DATACFG_FIX(pebs_data_cfg))) * 1340 sizeof(u64); 1341 } 1342 } 1343 1344 cpuc->pebs_record_size = sz; 1345 } 1346 1347 static void __intel_pmu_pebs_update_cfg(struct perf_event *event, 1348 int idx, u64 *pebs_data_cfg) 1349 { 1350 if (is_metric_event(event)) { 1351 *pebs_data_cfg |= PEBS_DATACFG_METRICS; 1352 return; 1353 } 1354 1355 *pebs_data_cfg |= PEBS_DATACFG_CNTR; 1356 1357 if (idx >= INTEL_PMC_IDX_FIXED) 1358 *pebs_data_cfg |= PEBS_DATACFG_FIX_BIT(idx - INTEL_PMC_IDX_FIXED); 1359 else 1360 *pebs_data_cfg |= PEBS_DATACFG_CNTR_BIT(idx); 1361 } 1362 1363 1364 void intel_pmu_pebs_late_setup(struct cpu_hw_events *cpuc) 1365 { 1366 struct perf_event *event; 1367 u64 pebs_data_cfg = 0; 1368 int i; 1369 1370 for (i = 0; i < cpuc->n_events; i++) { 1371 event = cpuc->event_list[i]; 1372 if (!is_pebs_counter_event_group(event)) 1373 continue; 1374 __intel_pmu_pebs_update_cfg(event, cpuc->assign[i], &pebs_data_cfg); 1375 } 1376 1377 if (pebs_data_cfg & ~cpuc->pebs_data_cfg) 1378 cpuc->pebs_data_cfg |= pebs_data_cfg | PEBS_UPDATE_DS_SW; 1379 } 1380 1381 #define PERF_PEBS_MEMINFO_TYPE (PERF_SAMPLE_ADDR | PERF_SAMPLE_DATA_SRC | \ 1382 PERF_SAMPLE_PHYS_ADDR | \ 1383 PERF_SAMPLE_WEIGHT_TYPE | \ 1384 PERF_SAMPLE_TRANSACTION | \ 1385 PERF_SAMPLE_DATA_PAGE_SIZE) 1386 1387 static u64 pebs_update_adaptive_cfg(struct perf_event *event) 1388 { 1389 struct perf_event_attr *attr = &event->attr; 1390 u64 sample_type = attr->sample_type; 1391 u64 pebs_data_cfg = 0; 1392 bool gprs, tsx_weight; 1393 1394 if (!(sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) && 1395 attr->precise_ip > 1) 1396 return pebs_data_cfg; 1397 1398 if (sample_type & PERF_PEBS_MEMINFO_TYPE) 1399 pebs_data_cfg |= PEBS_DATACFG_MEMINFO; 1400 1401 /* 1402 * We need GPRs when: 1403 * + user requested them 1404 * + precise_ip < 2 for the non event IP 1405 * + For RTM TSX weight we need GPRs for the abort code. 1406 */ 1407 gprs = ((sample_type & PERF_SAMPLE_REGS_INTR) && 1408 (attr->sample_regs_intr & PEBS_GP_REGS)) || 1409 ((sample_type & PERF_SAMPLE_REGS_USER) && 1410 (attr->sample_regs_user & PEBS_GP_REGS)); 1411 1412 tsx_weight = (sample_type & PERF_SAMPLE_WEIGHT_TYPE) && 1413 ((attr->config & INTEL_ARCH_EVENT_MASK) == 1414 x86_pmu.rtm_abort_event); 1415 1416 if (gprs || (attr->precise_ip < 2) || tsx_weight) 1417 pebs_data_cfg |= PEBS_DATACFG_GP; 1418 1419 if ((sample_type & PERF_SAMPLE_REGS_INTR) && 1420 (attr->sample_regs_intr & PERF_REG_EXTENDED_MASK)) 1421 pebs_data_cfg |= PEBS_DATACFG_XMMS; 1422 1423 if (sample_type & PERF_SAMPLE_BRANCH_STACK) { 1424 /* 1425 * For now always log all LBRs. Could configure this 1426 * later. 1427 */ 1428 pebs_data_cfg |= PEBS_DATACFG_LBRS | 1429 ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT); 1430 } 1431 1432 return pebs_data_cfg; 1433 } 1434 1435 static void 1436 pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, 1437 struct perf_event *event, bool add) 1438 { 1439 struct pmu *pmu = event->pmu; 1440 1441 /* 1442 * Make sure we get updated with the first PEBS event. 1443 * During removal, ->pebs_data_cfg is still valid for 1444 * the last PEBS event. Don't clear it. 1445 */ 1446 if ((cpuc->n_pebs == 1) && add) 1447 cpuc->pebs_data_cfg = PEBS_UPDATE_DS_SW; 1448 1449 if (needed_cb != pebs_needs_sched_cb(cpuc)) { 1450 if (!needed_cb) 1451 perf_sched_cb_inc(pmu); 1452 else 1453 perf_sched_cb_dec(pmu); 1454 1455 cpuc->pebs_data_cfg |= PEBS_UPDATE_DS_SW; 1456 } 1457 1458 /* 1459 * The PEBS record doesn't shrink on pmu::del(). Doing so would require 1460 * iterating all remaining PEBS events to reconstruct the config. 1461 */ 1462 if (x86_pmu.intel_cap.pebs_baseline && add) { 1463 u64 pebs_data_cfg; 1464 1465 pebs_data_cfg = pebs_update_adaptive_cfg(event); 1466 /* 1467 * Be sure to update the thresholds when we change the record. 1468 */ 1469 if (pebs_data_cfg & ~cpuc->pebs_data_cfg) 1470 cpuc->pebs_data_cfg |= pebs_data_cfg | PEBS_UPDATE_DS_SW; 1471 } 1472 } 1473 1474 void intel_pmu_pebs_add(struct perf_event *event) 1475 { 1476 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1477 struct hw_perf_event *hwc = &event->hw; 1478 bool needed_cb = pebs_needs_sched_cb(cpuc); 1479 1480 cpuc->n_pebs++; 1481 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) 1482 cpuc->n_large_pebs++; 1483 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT) 1484 cpuc->n_pebs_via_pt++; 1485 1486 pebs_update_state(needed_cb, cpuc, event, true); 1487 } 1488 1489 static void intel_pmu_pebs_via_pt_disable(struct perf_event *event) 1490 { 1491 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1492 1493 if (!is_pebs_pt(event)) 1494 return; 1495 1496 if (!(cpuc->pebs_enabled & ~PEBS_VIA_PT_MASK)) 1497 cpuc->pebs_enabled &= ~PEBS_VIA_PT_MASK; 1498 } 1499 1500 static void intel_pmu_pebs_via_pt_enable(struct perf_event *event) 1501 { 1502 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1503 struct hw_perf_event *hwc = &event->hw; 1504 struct debug_store *ds = cpuc->ds; 1505 u64 value = ds->pebs_event_reset[hwc->idx]; 1506 u32 base = MSR_RELOAD_PMC0; 1507 unsigned int idx = hwc->idx; 1508 1509 if (!is_pebs_pt(event)) 1510 return; 1511 1512 if (!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS)) 1513 cpuc->pebs_enabled |= PEBS_PMI_AFTER_EACH_RECORD; 1514 1515 cpuc->pebs_enabled |= PEBS_OUTPUT_PT; 1516 1517 if (hwc->idx >= INTEL_PMC_IDX_FIXED) { 1518 base = MSR_RELOAD_FIXED_CTR0; 1519 idx = hwc->idx - INTEL_PMC_IDX_FIXED; 1520 if (x86_pmu.intel_cap.pebs_format < 5) 1521 value = ds->pebs_event_reset[MAX_PEBS_EVENTS_FMT4 + idx]; 1522 else 1523 value = ds->pebs_event_reset[MAX_PEBS_EVENTS + idx]; 1524 } 1525 wrmsrq(base + idx, value); 1526 } 1527 1528 static inline void intel_pmu_drain_large_pebs(struct cpu_hw_events *cpuc) 1529 { 1530 if (cpuc->n_pebs == cpuc->n_large_pebs && 1531 cpuc->n_pebs != cpuc->n_pebs_via_pt) 1532 intel_pmu_drain_pebs_buffer(); 1533 } 1534 1535 void intel_pmu_pebs_enable(struct perf_event *event) 1536 { 1537 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1538 u64 pebs_data_cfg = cpuc->pebs_data_cfg & ~PEBS_UPDATE_DS_SW; 1539 struct hw_perf_event *hwc = &event->hw; 1540 struct debug_store *ds = cpuc->ds; 1541 unsigned int idx = hwc->idx; 1542 1543 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; 1544 1545 cpuc->pebs_enabled |= 1ULL << hwc->idx; 1546 1547 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5)) 1548 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32); 1549 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) 1550 cpuc->pebs_enabled |= 1ULL << 63; 1551 1552 if (x86_pmu.intel_cap.pebs_baseline) { 1553 hwc->config |= ICL_EVENTSEL_ADAPTIVE; 1554 if (pebs_data_cfg != cpuc->active_pebs_data_cfg) { 1555 /* 1556 * drain_pebs() assumes uniform record size; 1557 * hence we need to drain when changing said 1558 * size. 1559 */ 1560 intel_pmu_drain_pebs_buffer(); 1561 adaptive_pebs_record_size_update(); 1562 wrmsrq(MSR_PEBS_DATA_CFG, pebs_data_cfg); 1563 cpuc->active_pebs_data_cfg = pebs_data_cfg; 1564 } 1565 } 1566 if (cpuc->pebs_data_cfg & PEBS_UPDATE_DS_SW) { 1567 cpuc->pebs_data_cfg = pebs_data_cfg; 1568 pebs_update_threshold(cpuc); 1569 } 1570 1571 if (idx >= INTEL_PMC_IDX_FIXED) { 1572 if (x86_pmu.intel_cap.pebs_format < 5) 1573 idx = MAX_PEBS_EVENTS_FMT4 + (idx - INTEL_PMC_IDX_FIXED); 1574 else 1575 idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED); 1576 } 1577 1578 /* 1579 * Use auto-reload if possible to save a MSR write in the PMI. 1580 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD. 1581 */ 1582 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { 1583 ds->pebs_event_reset[idx] = 1584 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; 1585 } else { 1586 ds->pebs_event_reset[idx] = 0; 1587 } 1588 1589 intel_pmu_pebs_via_pt_enable(event); 1590 } 1591 1592 void intel_pmu_pebs_del(struct perf_event *event) 1593 { 1594 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1595 struct hw_perf_event *hwc = &event->hw; 1596 bool needed_cb = pebs_needs_sched_cb(cpuc); 1597 1598 cpuc->n_pebs--; 1599 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) 1600 cpuc->n_large_pebs--; 1601 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT) 1602 cpuc->n_pebs_via_pt--; 1603 1604 pebs_update_state(needed_cb, cpuc, event, false); 1605 } 1606 1607 void intel_pmu_pebs_disable(struct perf_event *event) 1608 { 1609 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1610 struct hw_perf_event *hwc = &event->hw; 1611 1612 intel_pmu_drain_large_pebs(cpuc); 1613 1614 cpuc->pebs_enabled &= ~(1ULL << hwc->idx); 1615 1616 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && 1617 (x86_pmu.version < 5)) 1618 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32)); 1619 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) 1620 cpuc->pebs_enabled &= ~(1ULL << 63); 1621 1622 intel_pmu_pebs_via_pt_disable(event); 1623 1624 if (cpuc->enabled) 1625 wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 1626 1627 hwc->config |= ARCH_PERFMON_EVENTSEL_INT; 1628 } 1629 1630 void intel_pmu_pebs_enable_all(void) 1631 { 1632 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1633 1634 if (cpuc->pebs_enabled) 1635 wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 1636 } 1637 1638 void intel_pmu_pebs_disable_all(void) 1639 { 1640 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1641 1642 if (cpuc->pebs_enabled) 1643 __intel_pmu_pebs_disable_all(); 1644 } 1645 1646 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs) 1647 { 1648 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1649 unsigned long from = cpuc->lbr_entries[0].from; 1650 unsigned long old_to, to = cpuc->lbr_entries[0].to; 1651 unsigned long ip = regs->ip; 1652 int is_64bit = 0; 1653 void *kaddr; 1654 int size; 1655 1656 /* 1657 * We don't need to fixup if the PEBS assist is fault like 1658 */ 1659 if (!x86_pmu.intel_cap.pebs_trap) 1660 return 1; 1661 1662 /* 1663 * No LBR entry, no basic block, no rewinding 1664 */ 1665 if (!cpuc->lbr_stack.nr || !from || !to) 1666 return 0; 1667 1668 /* 1669 * Basic blocks should never cross user/kernel boundaries 1670 */ 1671 if (kernel_ip(ip) != kernel_ip(to)) 1672 return 0; 1673 1674 /* 1675 * unsigned math, either ip is before the start (impossible) or 1676 * the basic block is larger than 1 page (sanity) 1677 */ 1678 if ((ip - to) > PEBS_FIXUP_SIZE) 1679 return 0; 1680 1681 /* 1682 * We sampled a branch insn, rewind using the LBR stack 1683 */ 1684 if (ip == to) { 1685 set_linear_ip(regs, from); 1686 return 1; 1687 } 1688 1689 size = ip - to; 1690 if (!kernel_ip(ip)) { 1691 int bytes; 1692 u8 *buf = this_cpu_read(insn_buffer); 1693 1694 /* 'size' must fit our buffer, see above */ 1695 bytes = copy_from_user_nmi(buf, (void __user *)to, size); 1696 if (bytes != 0) 1697 return 0; 1698 1699 kaddr = buf; 1700 } else { 1701 kaddr = (void *)to; 1702 } 1703 1704 do { 1705 struct insn insn; 1706 1707 old_to = to; 1708 1709 #ifdef CONFIG_X86_64 1710 is_64bit = kernel_ip(to) || any_64bit_mode(regs); 1711 #endif 1712 insn_init(&insn, kaddr, size, is_64bit); 1713 1714 /* 1715 * Make sure there was not a problem decoding the instruction. 1716 * This is doubly important because we have an infinite loop if 1717 * insn.length=0. 1718 */ 1719 if (insn_get_length(&insn)) 1720 break; 1721 1722 to += insn.length; 1723 kaddr += insn.length; 1724 size -= insn.length; 1725 } while (to < ip); 1726 1727 if (to == ip) { 1728 set_linear_ip(regs, old_to); 1729 return 1; 1730 } 1731 1732 /* 1733 * Even though we decoded the basic block, the instruction stream 1734 * never matched the given IP, either the TO or the IP got corrupted. 1735 */ 1736 return 0; 1737 } 1738 1739 static inline u64 intel_get_tsx_weight(u64 tsx_tuning) 1740 { 1741 if (tsx_tuning) { 1742 union hsw_tsx_tuning tsx = { .value = tsx_tuning }; 1743 return tsx.cycles_last_block; 1744 } 1745 return 0; 1746 } 1747 1748 static inline u64 intel_get_tsx_transaction(u64 tsx_tuning, u64 ax) 1749 { 1750 u64 txn = (tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32; 1751 1752 /* For RTM XABORTs also log the abort code from AX */ 1753 if ((txn & PERF_TXN_TRANSACTION) && (ax & 1)) 1754 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT; 1755 return txn; 1756 } 1757 1758 static inline u64 get_pebs_status(void *n) 1759 { 1760 if (x86_pmu.intel_cap.pebs_format < 4) 1761 return ((struct pebs_record_nhm *)n)->status; 1762 return ((struct pebs_basic *)n)->applicable_counters; 1763 } 1764 1765 #define PERF_X86_EVENT_PEBS_HSW_PREC \ 1766 (PERF_X86_EVENT_PEBS_ST_HSW | \ 1767 PERF_X86_EVENT_PEBS_LD_HSW | \ 1768 PERF_X86_EVENT_PEBS_NA_HSW) 1769 1770 static u64 get_data_src(struct perf_event *event, u64 aux) 1771 { 1772 u64 val = PERF_MEM_NA; 1773 int fl = event->hw.flags; 1774 bool fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC); 1775 1776 if (fl & PERF_X86_EVENT_PEBS_LDLAT) 1777 val = load_latency_data(event, aux); 1778 else if (fl & PERF_X86_EVENT_PEBS_STLAT) 1779 val = store_latency_data(event, aux); 1780 else if (fl & PERF_X86_EVENT_PEBS_LAT_HYBRID) 1781 val = x86_pmu.pebs_latency_data(event, aux); 1782 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC)) 1783 val = precise_datala_hsw(event, aux); 1784 else if (fst) 1785 val = precise_store_data(aux); 1786 return val; 1787 } 1788 1789 static void setup_pebs_time(struct perf_event *event, 1790 struct perf_sample_data *data, 1791 u64 tsc) 1792 { 1793 /* Converting to a user-defined clock is not supported yet. */ 1794 if (event->attr.use_clockid != 0) 1795 return; 1796 1797 /* 1798 * Doesn't support the conversion when the TSC is unstable. 1799 * The TSC unstable case is a corner case and very unlikely to 1800 * happen. If it happens, the TSC in a PEBS record will be 1801 * dropped and fall back to perf_event_clock(). 1802 */ 1803 if (!using_native_sched_clock() || !sched_clock_stable()) 1804 return; 1805 1806 data->time = native_sched_clock_from_tsc(tsc) + __sched_clock_offset; 1807 data->sample_flags |= PERF_SAMPLE_TIME; 1808 } 1809 1810 #define PERF_SAMPLE_ADDR_TYPE (PERF_SAMPLE_ADDR | \ 1811 PERF_SAMPLE_PHYS_ADDR | \ 1812 PERF_SAMPLE_DATA_PAGE_SIZE) 1813 1814 static void setup_pebs_fixed_sample_data(struct perf_event *event, 1815 struct pt_regs *iregs, void *__pebs, 1816 struct perf_sample_data *data, 1817 struct pt_regs *regs) 1818 { 1819 /* 1820 * We cast to the biggest pebs_record but are careful not to 1821 * unconditionally access the 'extra' entries. 1822 */ 1823 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1824 struct pebs_record_skl *pebs = __pebs; 1825 u64 sample_type; 1826 int fll; 1827 1828 if (pebs == NULL) 1829 return; 1830 1831 sample_type = event->attr.sample_type; 1832 fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT; 1833 1834 perf_sample_data_init(data, 0, event->hw.last_period); 1835 1836 /* 1837 * Use latency for weight (only avail with PEBS-LL) 1838 */ 1839 if (fll && (sample_type & PERF_SAMPLE_WEIGHT_TYPE)) { 1840 data->weight.full = pebs->lat; 1841 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE; 1842 } 1843 1844 /* 1845 * data.data_src encodes the data source 1846 */ 1847 if (sample_type & PERF_SAMPLE_DATA_SRC) { 1848 data->data_src.val = get_data_src(event, pebs->dse); 1849 data->sample_flags |= PERF_SAMPLE_DATA_SRC; 1850 } 1851 1852 /* 1853 * We must however always use iregs for the unwinder to stay sane; the 1854 * record BP,SP,IP can point into thin air when the record is from a 1855 * previous PMI context or an (I)RET happened between the record and 1856 * PMI. 1857 */ 1858 perf_sample_save_callchain(data, event, iregs); 1859 1860 /* 1861 * We use the interrupt regs as a base because the PEBS record does not 1862 * contain a full regs set, specifically it seems to lack segment 1863 * descriptors, which get used by things like user_mode(). 1864 * 1865 * In the simple case fix up only the IP for PERF_SAMPLE_IP. 1866 */ 1867 *regs = *iregs; 1868 1869 /* 1870 * Initialize regs_>flags from PEBS, 1871 * Clear exact bit (which uses x86 EFLAGS Reserved bit 3), 1872 * i.e., do not rely on it being zero: 1873 */ 1874 regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT; 1875 1876 if (sample_type & PERF_SAMPLE_REGS_INTR) { 1877 regs->ax = pebs->ax; 1878 regs->bx = pebs->bx; 1879 regs->cx = pebs->cx; 1880 regs->dx = pebs->dx; 1881 regs->si = pebs->si; 1882 regs->di = pebs->di; 1883 1884 regs->bp = pebs->bp; 1885 regs->sp = pebs->sp; 1886 1887 #ifndef CONFIG_X86_32 1888 regs->r8 = pebs->r8; 1889 regs->r9 = pebs->r9; 1890 regs->r10 = pebs->r10; 1891 regs->r11 = pebs->r11; 1892 regs->r12 = pebs->r12; 1893 regs->r13 = pebs->r13; 1894 regs->r14 = pebs->r14; 1895 regs->r15 = pebs->r15; 1896 #endif 1897 } 1898 1899 if (event->attr.precise_ip > 1) { 1900 /* 1901 * Haswell and later processors have an 'eventing IP' 1902 * (real IP) which fixes the off-by-1 skid in hardware. 1903 * Use it when precise_ip >= 2 : 1904 */ 1905 if (x86_pmu.intel_cap.pebs_format >= 2) { 1906 set_linear_ip(regs, pebs->real_ip); 1907 regs->flags |= PERF_EFLAGS_EXACT; 1908 } else { 1909 /* Otherwise, use PEBS off-by-1 IP: */ 1910 set_linear_ip(regs, pebs->ip); 1911 1912 /* 1913 * With precise_ip >= 2, try to fix up the off-by-1 IP 1914 * using the LBR. If successful, the fixup function 1915 * corrects regs->ip and calls set_linear_ip() on regs: 1916 */ 1917 if (intel_pmu_pebs_fixup_ip(regs)) 1918 regs->flags |= PERF_EFLAGS_EXACT; 1919 } 1920 } else { 1921 /* 1922 * When precise_ip == 1, return the PEBS off-by-1 IP, 1923 * no fixup attempted: 1924 */ 1925 set_linear_ip(regs, pebs->ip); 1926 } 1927 1928 1929 if ((sample_type & PERF_SAMPLE_ADDR_TYPE) && 1930 x86_pmu.intel_cap.pebs_format >= 1) { 1931 data->addr = pebs->dla; 1932 data->sample_flags |= PERF_SAMPLE_ADDR; 1933 } 1934 1935 if (x86_pmu.intel_cap.pebs_format >= 2) { 1936 /* Only set the TSX weight when no memory weight. */ 1937 if ((sample_type & PERF_SAMPLE_WEIGHT_TYPE) && !fll) { 1938 data->weight.full = intel_get_tsx_weight(pebs->tsx_tuning); 1939 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE; 1940 } 1941 if (sample_type & PERF_SAMPLE_TRANSACTION) { 1942 data->txn = intel_get_tsx_transaction(pebs->tsx_tuning, 1943 pebs->ax); 1944 data->sample_flags |= PERF_SAMPLE_TRANSACTION; 1945 } 1946 } 1947 1948 /* 1949 * v3 supplies an accurate time stamp, so we use that 1950 * for the time stamp. 1951 * 1952 * We can only do this for the default trace clock. 1953 */ 1954 if (x86_pmu.intel_cap.pebs_format >= 3) 1955 setup_pebs_time(event, data, pebs->tsc); 1956 1957 perf_sample_save_brstack(data, event, &cpuc->lbr_stack, NULL); 1958 } 1959 1960 static void adaptive_pebs_save_regs(struct pt_regs *regs, 1961 struct pebs_gprs *gprs) 1962 { 1963 regs->ax = gprs->ax; 1964 regs->bx = gprs->bx; 1965 regs->cx = gprs->cx; 1966 regs->dx = gprs->dx; 1967 regs->si = gprs->si; 1968 regs->di = gprs->di; 1969 regs->bp = gprs->bp; 1970 regs->sp = gprs->sp; 1971 #ifndef CONFIG_X86_32 1972 regs->r8 = gprs->r8; 1973 regs->r9 = gprs->r9; 1974 regs->r10 = gprs->r10; 1975 regs->r11 = gprs->r11; 1976 regs->r12 = gprs->r12; 1977 regs->r13 = gprs->r13; 1978 regs->r14 = gprs->r14; 1979 regs->r15 = gprs->r15; 1980 #endif 1981 } 1982 1983 static void intel_perf_event_update_pmc(struct perf_event *event, u64 pmc) 1984 { 1985 int shift = 64 - x86_pmu.cntval_bits; 1986 struct hw_perf_event *hwc; 1987 u64 delta, prev_pmc; 1988 1989 /* 1990 * A recorded counter may not have an assigned event in the 1991 * following cases. The value should be dropped. 1992 * - An event is deleted. There is still an active PEBS event. 1993 * The PEBS record doesn't shrink on pmu::del(). 1994 * If the counter of the deleted event once occurred in a PEBS 1995 * record, PEBS still records the counter until the counter is 1996 * reassigned. 1997 * - An event is stopped for some reason, e.g., throttled. 1998 * During this period, another event is added and takes the 1999 * counter of the stopped event. The stopped event is assigned 2000 * to another new and uninitialized counter, since the 2001 * x86_pmu_start(RELOAD) is not invoked for a stopped event. 2002 * The PEBS__DATA_CFG is updated regardless of the event state. 2003 * The uninitialized counter can be recorded in a PEBS record. 2004 * But the cpuc->events[uninitialized_counter] is always NULL, 2005 * because the event is stopped. The uninitialized value is 2006 * safely dropped. 2007 */ 2008 if (!event) 2009 return; 2010 2011 hwc = &event->hw; 2012 prev_pmc = local64_read(&hwc->prev_count); 2013 2014 /* Only update the count when the PMU is disabled */ 2015 WARN_ON(this_cpu_read(cpu_hw_events.enabled)); 2016 local64_set(&hwc->prev_count, pmc); 2017 2018 delta = (pmc << shift) - (prev_pmc << shift); 2019 delta >>= shift; 2020 2021 local64_add(delta, &event->count); 2022 local64_sub(delta, &hwc->period_left); 2023 } 2024 2025 static inline void __setup_pebs_counter_group(struct cpu_hw_events *cpuc, 2026 struct perf_event *event, 2027 struct pebs_cntr_header *cntr, 2028 void *next_record) 2029 { 2030 int bit; 2031 2032 for_each_set_bit(bit, (unsigned long *)&cntr->cntr, INTEL_PMC_MAX_GENERIC) { 2033 intel_perf_event_update_pmc(cpuc->events[bit], *(u64 *)next_record); 2034 next_record += sizeof(u64); 2035 } 2036 2037 for_each_set_bit(bit, (unsigned long *)&cntr->fixed, INTEL_PMC_MAX_FIXED) { 2038 /* The slots event will be handled with perf_metric later */ 2039 if ((cntr->metrics == INTEL_CNTR_METRICS) && 2040 (bit + INTEL_PMC_IDX_FIXED == INTEL_PMC_IDX_FIXED_SLOTS)) { 2041 next_record += sizeof(u64); 2042 continue; 2043 } 2044 intel_perf_event_update_pmc(cpuc->events[bit + INTEL_PMC_IDX_FIXED], 2045 *(u64 *)next_record); 2046 next_record += sizeof(u64); 2047 } 2048 2049 /* HW will reload the value right after the overflow. */ 2050 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2051 local64_set(&event->hw.prev_count, (u64)-event->hw.sample_period); 2052 2053 if (cntr->metrics == INTEL_CNTR_METRICS) { 2054 static_call(intel_pmu_update_topdown_event) 2055 (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS], 2056 (u64 *)next_record); 2057 next_record += 2 * sizeof(u64); 2058 } 2059 } 2060 2061 #define PEBS_LATENCY_MASK 0xffff 2062 2063 /* 2064 * With adaptive PEBS the layout depends on what fields are configured. 2065 */ 2066 static void setup_pebs_adaptive_sample_data(struct perf_event *event, 2067 struct pt_regs *iregs, void *__pebs, 2068 struct perf_sample_data *data, 2069 struct pt_regs *regs) 2070 { 2071 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2072 struct pebs_basic *basic = __pebs; 2073 void *next_record = basic + 1; 2074 u64 sample_type, format_group; 2075 struct pebs_meminfo *meminfo = NULL; 2076 struct pebs_gprs *gprs = NULL; 2077 struct x86_perf_regs *perf_regs; 2078 2079 if (basic == NULL) 2080 return; 2081 2082 perf_regs = container_of(regs, struct x86_perf_regs, regs); 2083 perf_regs->xmm_regs = NULL; 2084 2085 sample_type = event->attr.sample_type; 2086 format_group = basic->format_group; 2087 perf_sample_data_init(data, 0, event->hw.last_period); 2088 2089 setup_pebs_time(event, data, basic->tsc); 2090 2091 /* 2092 * We must however always use iregs for the unwinder to stay sane; the 2093 * record BP,SP,IP can point into thin air when the record is from a 2094 * previous PMI context or an (I)RET happened between the record and 2095 * PMI. 2096 */ 2097 perf_sample_save_callchain(data, event, iregs); 2098 2099 *regs = *iregs; 2100 /* The ip in basic is EventingIP */ 2101 set_linear_ip(regs, basic->ip); 2102 regs->flags = PERF_EFLAGS_EXACT; 2103 2104 if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT) { 2105 if (x86_pmu.flags & PMU_FL_RETIRE_LATENCY) 2106 data->weight.var3_w = basic->retire_latency; 2107 else 2108 data->weight.var3_w = 0; 2109 } 2110 2111 /* 2112 * The record for MEMINFO is in front of GP 2113 * But PERF_SAMPLE_TRANSACTION needs gprs->ax. 2114 * Save the pointer here but process later. 2115 */ 2116 if (format_group & PEBS_DATACFG_MEMINFO) { 2117 meminfo = next_record; 2118 next_record = meminfo + 1; 2119 } 2120 2121 if (format_group & PEBS_DATACFG_GP) { 2122 gprs = next_record; 2123 next_record = gprs + 1; 2124 2125 if (event->attr.precise_ip < 2) { 2126 set_linear_ip(regs, gprs->ip); 2127 regs->flags &= ~PERF_EFLAGS_EXACT; 2128 } 2129 2130 if (sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)) 2131 adaptive_pebs_save_regs(regs, gprs); 2132 } 2133 2134 if (format_group & PEBS_DATACFG_MEMINFO) { 2135 if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) { 2136 u64 latency = x86_pmu.flags & PMU_FL_INSTR_LATENCY ? 2137 meminfo->cache_latency : meminfo->mem_latency; 2138 2139 if (x86_pmu.flags & PMU_FL_INSTR_LATENCY) 2140 data->weight.var2_w = meminfo->instr_latency; 2141 2142 /* 2143 * Although meminfo::latency is defined as a u64, 2144 * only the lower 32 bits include the valid data 2145 * in practice on Ice Lake and earlier platforms. 2146 */ 2147 if (sample_type & PERF_SAMPLE_WEIGHT) { 2148 data->weight.full = latency ?: 2149 intel_get_tsx_weight(meminfo->tsx_tuning); 2150 } else { 2151 data->weight.var1_dw = (u32)latency ?: 2152 intel_get_tsx_weight(meminfo->tsx_tuning); 2153 } 2154 2155 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE; 2156 } 2157 2158 if (sample_type & PERF_SAMPLE_DATA_SRC) { 2159 data->data_src.val = get_data_src(event, meminfo->aux); 2160 data->sample_flags |= PERF_SAMPLE_DATA_SRC; 2161 } 2162 2163 if (sample_type & PERF_SAMPLE_ADDR_TYPE) { 2164 data->addr = meminfo->address; 2165 data->sample_flags |= PERF_SAMPLE_ADDR; 2166 } 2167 2168 if (sample_type & PERF_SAMPLE_TRANSACTION) { 2169 data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning, 2170 gprs ? gprs->ax : 0); 2171 data->sample_flags |= PERF_SAMPLE_TRANSACTION; 2172 } 2173 } 2174 2175 if (format_group & PEBS_DATACFG_XMMS) { 2176 struct pebs_xmm *xmm = next_record; 2177 2178 next_record = xmm + 1; 2179 perf_regs->xmm_regs = xmm->xmm; 2180 } 2181 2182 if (format_group & PEBS_DATACFG_LBRS) { 2183 struct lbr_entry *lbr = next_record; 2184 int num_lbr = ((format_group >> PEBS_DATACFG_LBR_SHIFT) 2185 & 0xff) + 1; 2186 next_record = next_record + num_lbr * sizeof(struct lbr_entry); 2187 2188 if (has_branch_stack(event)) { 2189 intel_pmu_store_pebs_lbrs(lbr); 2190 intel_pmu_lbr_save_brstack(data, cpuc, event); 2191 } 2192 } 2193 2194 if (format_group & (PEBS_DATACFG_CNTR | PEBS_DATACFG_METRICS)) { 2195 struct pebs_cntr_header *cntr = next_record; 2196 unsigned int nr; 2197 2198 next_record += sizeof(struct pebs_cntr_header); 2199 /* 2200 * The PEBS_DATA_CFG is a global register, which is the 2201 * superset configuration for all PEBS events. 2202 * For the PEBS record of non-sample-read group, ignore 2203 * the counter snapshot fields. 2204 */ 2205 if (is_pebs_counter_event_group(event)) { 2206 __setup_pebs_counter_group(cpuc, event, cntr, next_record); 2207 data->sample_flags |= PERF_SAMPLE_READ; 2208 } 2209 2210 nr = hweight32(cntr->cntr) + hweight32(cntr->fixed); 2211 if (cntr->metrics == INTEL_CNTR_METRICS) 2212 nr += 2; 2213 next_record += nr * sizeof(u64); 2214 } 2215 2216 WARN_ONCE(next_record != __pebs + basic->format_size, 2217 "PEBS record size %u, expected %llu, config %llx\n", 2218 basic->format_size, 2219 (u64)(next_record - __pebs), 2220 format_group); 2221 } 2222 2223 static inline void * 2224 get_next_pebs_record_by_bit(void *base, void *top, int bit) 2225 { 2226 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2227 void *at; 2228 u64 pebs_status; 2229 2230 /* 2231 * fmt0 does not have a status bitfield (does not use 2232 * perf_record_nhm format) 2233 */ 2234 if (x86_pmu.intel_cap.pebs_format < 1) 2235 return base; 2236 2237 if (base == NULL) 2238 return NULL; 2239 2240 for (at = base; at < top; at += cpuc->pebs_record_size) { 2241 unsigned long status = get_pebs_status(at); 2242 2243 if (test_bit(bit, (unsigned long *)&status)) { 2244 /* PEBS v3 has accurate status bits */ 2245 if (x86_pmu.intel_cap.pebs_format >= 3) 2246 return at; 2247 2248 if (status == (1 << bit)) 2249 return at; 2250 2251 /* clear non-PEBS bit and re-check */ 2252 pebs_status = status & cpuc->pebs_enabled; 2253 pebs_status &= PEBS_COUNTER_MASK; 2254 if (pebs_status == (1 << bit)) 2255 return at; 2256 } 2257 } 2258 return NULL; 2259 } 2260 2261 /* 2262 * Special variant of intel_pmu_save_and_restart() for auto-reload. 2263 */ 2264 static int 2265 intel_pmu_save_and_restart_reload(struct perf_event *event, int count) 2266 { 2267 struct hw_perf_event *hwc = &event->hw; 2268 int shift = 64 - x86_pmu.cntval_bits; 2269 u64 period = hwc->sample_period; 2270 u64 prev_raw_count, new_raw_count; 2271 s64 new, old; 2272 2273 WARN_ON(!period); 2274 2275 /* 2276 * drain_pebs() only happens when the PMU is disabled. 2277 */ 2278 WARN_ON(this_cpu_read(cpu_hw_events.enabled)); 2279 2280 prev_raw_count = local64_read(&hwc->prev_count); 2281 new_raw_count = rdpmc(hwc->event_base_rdpmc); 2282 local64_set(&hwc->prev_count, new_raw_count); 2283 2284 /* 2285 * Since the counter increments a negative counter value and 2286 * overflows on the sign switch, giving the interval: 2287 * 2288 * [-period, 0] 2289 * 2290 * the difference between two consecutive reads is: 2291 * 2292 * A) value2 - value1; 2293 * when no overflows have happened in between, 2294 * 2295 * B) (0 - value1) + (value2 - (-period)); 2296 * when one overflow happened in between, 2297 * 2298 * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period)); 2299 * when @n overflows happened in between. 2300 * 2301 * Here A) is the obvious difference, B) is the extension to the 2302 * discrete interval, where the first term is to the top of the 2303 * interval and the second term is from the bottom of the next 2304 * interval and C) the extension to multiple intervals, where the 2305 * middle term is the whole intervals covered. 2306 * 2307 * An equivalent of C, by reduction, is: 2308 * 2309 * value2 - value1 + n * period 2310 */ 2311 new = ((s64)(new_raw_count << shift) >> shift); 2312 old = ((s64)(prev_raw_count << shift) >> shift); 2313 local64_add(new - old + count * period, &event->count); 2314 2315 local64_set(&hwc->period_left, -new); 2316 2317 perf_event_update_userpage(event); 2318 2319 return 0; 2320 } 2321 2322 typedef void (*setup_fn)(struct perf_event *, struct pt_regs *, void *, 2323 struct perf_sample_data *, struct pt_regs *); 2324 2325 static struct pt_regs dummy_iregs; 2326 2327 static __always_inline void 2328 __intel_pmu_pebs_event(struct perf_event *event, 2329 struct pt_regs *iregs, 2330 struct pt_regs *regs, 2331 struct perf_sample_data *data, 2332 void *at, 2333 setup_fn setup_sample) 2334 { 2335 setup_sample(event, iregs, at, data, regs); 2336 perf_event_output(event, data, regs); 2337 } 2338 2339 static __always_inline void 2340 __intel_pmu_pebs_last_event(struct perf_event *event, 2341 struct pt_regs *iregs, 2342 struct pt_regs *regs, 2343 struct perf_sample_data *data, 2344 void *at, 2345 int count, 2346 setup_fn setup_sample) 2347 { 2348 struct hw_perf_event *hwc = &event->hw; 2349 2350 setup_sample(event, iregs, at, data, regs); 2351 if (iregs == &dummy_iregs) { 2352 /* 2353 * The PEBS records may be drained in the non-overflow context, 2354 * e.g., large PEBS + context switch. Perf should treat the 2355 * last record the same as other PEBS records, and doesn't 2356 * invoke the generic overflow handler. 2357 */ 2358 perf_event_output(event, data, regs); 2359 } else { 2360 /* 2361 * All but the last records are processed. 2362 * The last one is left to be able to call the overflow handler. 2363 */ 2364 perf_event_overflow(event, data, regs); 2365 } 2366 2367 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { 2368 if ((is_pebs_counter_event_group(event))) { 2369 /* 2370 * The value of each sample has been updated when setup 2371 * the corresponding sample data. 2372 */ 2373 perf_event_update_userpage(event); 2374 } else { 2375 /* 2376 * Now, auto-reload is only enabled in fixed period mode. 2377 * The reload value is always hwc->sample_period. 2378 * May need to change it, if auto-reload is enabled in 2379 * freq mode later. 2380 */ 2381 intel_pmu_save_and_restart_reload(event, count); 2382 } 2383 } else { 2384 /* 2385 * For a non-precise event, it's possible the 2386 * counters-snapshotting records a positive value for the 2387 * overflowed event. Then the HW auto-reload mechanism 2388 * reset the counter to 0 immediately, because the 2389 * pebs_event_reset is cleared if the PERF_X86_EVENT_AUTO_RELOAD 2390 * is not set. The counter backwards may be observed in a 2391 * PMI handler. 2392 * 2393 * Since the event value has been updated when processing the 2394 * counters-snapshotting record, only needs to set the new 2395 * period for the counter. 2396 */ 2397 if (is_pebs_counter_event_group(event)) 2398 static_call(x86_pmu_set_period)(event); 2399 else 2400 intel_pmu_save_and_restart(event); 2401 } 2402 } 2403 2404 static __always_inline void 2405 __intel_pmu_pebs_events(struct perf_event *event, 2406 struct pt_regs *iregs, 2407 struct perf_sample_data *data, 2408 void *base, void *top, 2409 int bit, int count, 2410 setup_fn setup_sample) 2411 { 2412 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2413 struct x86_perf_regs perf_regs; 2414 struct pt_regs *regs = &perf_regs.regs; 2415 void *at = get_next_pebs_record_by_bit(base, top, bit); 2416 int cnt = count; 2417 2418 if (!iregs) 2419 iregs = &dummy_iregs; 2420 2421 while (cnt > 1) { 2422 __intel_pmu_pebs_event(event, iregs, regs, data, at, setup_sample); 2423 at += cpuc->pebs_record_size; 2424 at = get_next_pebs_record_by_bit(at, top, bit); 2425 cnt--; 2426 } 2427 2428 __intel_pmu_pebs_last_event(event, iregs, regs, data, at, count, setup_sample); 2429 } 2430 2431 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs, struct perf_sample_data *data) 2432 { 2433 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2434 struct debug_store *ds = cpuc->ds; 2435 struct perf_event *event = cpuc->events[0]; /* PMC0 only */ 2436 struct pebs_record_core *at, *top; 2437 int n; 2438 2439 if (!x86_pmu.pebs_active) 2440 return; 2441 2442 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base; 2443 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index; 2444 2445 /* 2446 * Whatever else happens, drain the thing 2447 */ 2448 ds->pebs_index = ds->pebs_buffer_base; 2449 2450 if (!test_bit(0, cpuc->active_mask)) 2451 return; 2452 2453 WARN_ON_ONCE(!event); 2454 2455 if (!event->attr.precise_ip) 2456 return; 2457 2458 n = top - at; 2459 if (n <= 0) { 2460 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2461 intel_pmu_save_and_restart_reload(event, 0); 2462 return; 2463 } 2464 2465 __intel_pmu_pebs_events(event, iregs, data, at, top, 0, n, 2466 setup_pebs_fixed_sample_data); 2467 } 2468 2469 static void intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events *cpuc, u64 mask) 2470 { 2471 u64 pebs_enabled = cpuc->pebs_enabled & mask; 2472 struct perf_event *event; 2473 int bit; 2474 2475 /* 2476 * The drain_pebs() could be called twice in a short period 2477 * for auto-reload event in pmu::read(). There are no 2478 * overflows have happened in between. 2479 * It needs to call intel_pmu_save_and_restart_reload() to 2480 * update the event->count for this case. 2481 */ 2482 for_each_set_bit(bit, (unsigned long *)&pebs_enabled, X86_PMC_IDX_MAX) { 2483 event = cpuc->events[bit]; 2484 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2485 intel_pmu_save_and_restart_reload(event, 0); 2486 } 2487 } 2488 2489 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_data *data) 2490 { 2491 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2492 struct debug_store *ds = cpuc->ds; 2493 struct perf_event *event; 2494 void *base, *at, *top; 2495 short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {}; 2496 short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {}; 2497 int max_pebs_events = intel_pmu_max_num_pebs(NULL); 2498 int bit, i, size; 2499 u64 mask; 2500 2501 if (!x86_pmu.pebs_active) 2502 return; 2503 2504 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base; 2505 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index; 2506 2507 ds->pebs_index = ds->pebs_buffer_base; 2508 2509 mask = x86_pmu.pebs_events_mask; 2510 size = max_pebs_events; 2511 if (x86_pmu.flags & PMU_FL_PEBS_ALL) { 2512 mask |= x86_pmu.fixed_cntr_mask64 << INTEL_PMC_IDX_FIXED; 2513 size = INTEL_PMC_IDX_FIXED + x86_pmu_max_num_counters_fixed(NULL); 2514 } 2515 2516 if (unlikely(base >= top)) { 2517 intel_pmu_pebs_event_update_no_drain(cpuc, mask); 2518 return; 2519 } 2520 2521 for (at = base; at < top; at += x86_pmu.pebs_record_size) { 2522 struct pebs_record_nhm *p = at; 2523 u64 pebs_status; 2524 2525 pebs_status = p->status & cpuc->pebs_enabled; 2526 pebs_status &= mask; 2527 2528 /* PEBS v3 has more accurate status bits */ 2529 if (x86_pmu.intel_cap.pebs_format >= 3) { 2530 for_each_set_bit(bit, (unsigned long *)&pebs_status, size) 2531 counts[bit]++; 2532 2533 continue; 2534 } 2535 2536 /* 2537 * On some CPUs the PEBS status can be zero when PEBS is 2538 * racing with clearing of GLOBAL_STATUS. 2539 * 2540 * Normally we would drop that record, but in the 2541 * case when there is only a single active PEBS event 2542 * we can assume it's for that event. 2543 */ 2544 if (!pebs_status && cpuc->pebs_enabled && 2545 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1))) 2546 pebs_status = p->status = cpuc->pebs_enabled; 2547 2548 bit = find_first_bit((unsigned long *)&pebs_status, 2549 max_pebs_events); 2550 2551 if (!(x86_pmu.pebs_events_mask & (1 << bit))) 2552 continue; 2553 2554 /* 2555 * The PEBS hardware does not deal well with the situation 2556 * when events happen near to each other and multiple bits 2557 * are set. But it should happen rarely. 2558 * 2559 * If these events include one PEBS and multiple non-PEBS 2560 * events, it doesn't impact PEBS record. The record will 2561 * be handled normally. (slow path) 2562 * 2563 * If these events include two or more PEBS events, the 2564 * records for the events can be collapsed into a single 2565 * one, and it's not possible to reconstruct all events 2566 * that caused the PEBS record. It's called collision. 2567 * If collision happened, the record will be dropped. 2568 */ 2569 if (pebs_status != (1ULL << bit)) { 2570 for_each_set_bit(i, (unsigned long *)&pebs_status, size) 2571 error[i]++; 2572 continue; 2573 } 2574 2575 counts[bit]++; 2576 } 2577 2578 for_each_set_bit(bit, (unsigned long *)&mask, size) { 2579 if ((counts[bit] == 0) && (error[bit] == 0)) 2580 continue; 2581 2582 event = cpuc->events[bit]; 2583 if (WARN_ON_ONCE(!event)) 2584 continue; 2585 2586 if (WARN_ON_ONCE(!event->attr.precise_ip)) 2587 continue; 2588 2589 /* log dropped samples number */ 2590 if (error[bit]) { 2591 perf_log_lost_samples(event, error[bit]); 2592 2593 if (iregs) 2594 perf_event_account_interrupt(event); 2595 } 2596 2597 if (counts[bit]) { 2598 __intel_pmu_pebs_events(event, iregs, data, base, 2599 top, bit, counts[bit], 2600 setup_pebs_fixed_sample_data); 2601 } 2602 } 2603 } 2604 2605 static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_data *data) 2606 { 2607 short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {}; 2608 void *last[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS]; 2609 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2610 struct debug_store *ds = cpuc->ds; 2611 struct x86_perf_regs perf_regs; 2612 struct pt_regs *regs = &perf_regs.regs; 2613 struct pebs_basic *basic; 2614 struct perf_event *event; 2615 void *base, *at, *top; 2616 int bit; 2617 u64 mask; 2618 2619 if (!x86_pmu.pebs_active) 2620 return; 2621 2622 base = (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base; 2623 top = (struct pebs_basic *)(unsigned long)ds->pebs_index; 2624 2625 ds->pebs_index = ds->pebs_buffer_base; 2626 2627 mask = hybrid(cpuc->pmu, pebs_events_mask) | 2628 (hybrid(cpuc->pmu, fixed_cntr_mask64) << INTEL_PMC_IDX_FIXED); 2629 2630 if (unlikely(base >= top)) { 2631 intel_pmu_pebs_event_update_no_drain(cpuc, mask); 2632 return; 2633 } 2634 2635 if (!iregs) 2636 iregs = &dummy_iregs; 2637 2638 /* Process all but the last event for each counter. */ 2639 for (at = base; at < top; at += basic->format_size) { 2640 u64 pebs_status; 2641 2642 basic = at; 2643 if (basic->format_size != cpuc->pebs_record_size) 2644 continue; 2645 2646 pebs_status = basic->applicable_counters & cpuc->pebs_enabled & mask; 2647 for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) { 2648 event = cpuc->events[bit]; 2649 2650 if (WARN_ON_ONCE(!event) || 2651 WARN_ON_ONCE(!event->attr.precise_ip)) 2652 continue; 2653 2654 if (counts[bit]++) { 2655 __intel_pmu_pebs_event(event, iregs, regs, data, last[bit], 2656 setup_pebs_adaptive_sample_data); 2657 } 2658 last[bit] = at; 2659 } 2660 } 2661 2662 for_each_set_bit(bit, (unsigned long *)&mask, X86_PMC_IDX_MAX) { 2663 if (!counts[bit]) 2664 continue; 2665 2666 event = cpuc->events[bit]; 2667 2668 __intel_pmu_pebs_last_event(event, iregs, regs, data, last[bit], 2669 counts[bit], setup_pebs_adaptive_sample_data); 2670 } 2671 } 2672 2673 /* 2674 * PEBS probe and setup 2675 */ 2676 2677 void __init intel_pebs_init(void) 2678 { 2679 /* 2680 * No support for 32bit formats 2681 */ 2682 if (!boot_cpu_has(X86_FEATURE_DTES64)) 2683 return; 2684 2685 x86_pmu.ds_pebs = boot_cpu_has(X86_FEATURE_PEBS); 2686 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE; 2687 if (x86_pmu.version <= 4) 2688 x86_pmu.pebs_no_isolation = 1; 2689 2690 if (x86_pmu.ds_pebs) { 2691 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-'; 2692 char *pebs_qual = ""; 2693 int format = x86_pmu.intel_cap.pebs_format; 2694 2695 if (format < 4) 2696 x86_pmu.intel_cap.pebs_baseline = 0; 2697 2698 x86_pmu.pebs_enable = intel_pmu_pebs_enable; 2699 x86_pmu.pebs_disable = intel_pmu_pebs_disable; 2700 x86_pmu.pebs_enable_all = intel_pmu_pebs_enable_all; 2701 x86_pmu.pebs_disable_all = intel_pmu_pebs_disable_all; 2702 2703 switch (format) { 2704 case 0: 2705 pr_cont("PEBS fmt0%c, ", pebs_type); 2706 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core); 2707 /* 2708 * Using >PAGE_SIZE buffers makes the WRMSR to 2709 * PERF_GLOBAL_CTRL in intel_pmu_enable_all() 2710 * mysteriously hang on Core2. 2711 * 2712 * As a workaround, we don't do this. 2713 */ 2714 x86_pmu.pebs_buffer_size = PAGE_SIZE; 2715 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core; 2716 break; 2717 2718 case 1: 2719 pr_cont("PEBS fmt1%c, ", pebs_type); 2720 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm); 2721 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 2722 break; 2723 2724 case 2: 2725 pr_cont("PEBS fmt2%c, ", pebs_type); 2726 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw); 2727 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 2728 break; 2729 2730 case 3: 2731 pr_cont("PEBS fmt3%c, ", pebs_type); 2732 x86_pmu.pebs_record_size = 2733 sizeof(struct pebs_record_skl); 2734 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 2735 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME; 2736 break; 2737 2738 case 6: 2739 if (x86_pmu.intel_cap.pebs_baseline) { 2740 x86_pmu.large_pebs_flags |= PERF_SAMPLE_READ; 2741 x86_pmu.late_setup = intel_pmu_late_setup; 2742 } 2743 fallthrough; 2744 case 5: 2745 x86_pmu.pebs_ept = 1; 2746 fallthrough; 2747 case 4: 2748 x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl; 2749 x86_pmu.pebs_record_size = sizeof(struct pebs_basic); 2750 if (x86_pmu.intel_cap.pebs_baseline) { 2751 x86_pmu.large_pebs_flags |= 2752 PERF_SAMPLE_BRANCH_STACK | 2753 PERF_SAMPLE_TIME; 2754 x86_pmu.flags |= PMU_FL_PEBS_ALL; 2755 x86_pmu.pebs_capable = ~0ULL; 2756 pebs_qual = "-baseline"; 2757 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS; 2758 } else { 2759 /* Only basic record supported */ 2760 x86_pmu.large_pebs_flags &= 2761 ~(PERF_SAMPLE_ADDR | 2762 PERF_SAMPLE_TIME | 2763 PERF_SAMPLE_DATA_SRC | 2764 PERF_SAMPLE_TRANSACTION | 2765 PERF_SAMPLE_REGS_USER | 2766 PERF_SAMPLE_REGS_INTR); 2767 } 2768 pr_cont("PEBS fmt%d%c%s, ", format, pebs_type, pebs_qual); 2769 2770 /* 2771 * The PEBS-via-PT is not supported on hybrid platforms, 2772 * because not all CPUs of a hybrid machine support it. 2773 * The global x86_pmu.intel_cap, which only contains the 2774 * common capabilities, is used to check the availability 2775 * of the feature. The per-PMU pebs_output_pt_available 2776 * in a hybrid machine should be ignored. 2777 */ 2778 if (x86_pmu.intel_cap.pebs_output_pt_available) { 2779 pr_cont("PEBS-via-PT, "); 2780 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_AUX_OUTPUT; 2781 } 2782 2783 break; 2784 2785 default: 2786 pr_cont("no PEBS fmt%d%c, ", format, pebs_type); 2787 x86_pmu.ds_pebs = 0; 2788 } 2789 } 2790 } 2791 2792 void perf_restore_debug_store(void) 2793 { 2794 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2795 2796 if (!x86_pmu.bts && !x86_pmu.ds_pebs) 2797 return; 2798 2799 wrmsrq(MSR_IA32_DS_AREA, (unsigned long)ds); 2800 } 2801