1 /* 2 * Support cstate residency counters 3 * 4 * Copyright (C) 2015, Intel Corp. 5 * Author: Kan Liang (kan.liang@intel.com) 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Library General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Library General Public License for more details. 16 * 17 */ 18 19 /* 20 * This file export cstate related free running (read-only) counters 21 * for perf. These counters may be use simultaneously by other tools, 22 * such as turbostat. However, it still make sense to implement them 23 * in perf. Because we can conveniently collect them together with 24 * other events, and allow to use them from tools without special MSR 25 * access code. 26 * 27 * The events only support system-wide mode counting. There is no 28 * sampling support because it is not supported by the hardware. 29 * 30 * According to counters' scope and category, two PMUs are registered 31 * with the perf_event core subsystem. 32 * - 'cstate_core': The counter is available for each physical core. 33 * The counters include CORE_C*_RESIDENCY. 34 * - 'cstate_pkg': The counter is available for each physical package. 35 * The counters include PKG_C*_RESIDENCY. 36 * 37 * All of these counters are specified in the Intel® 64 and IA-32 38 * Architectures Software Developer.s Manual Vol3b. 39 * 40 * Model specific counters: 41 * MSR_CORE_C1_RES: CORE C1 Residency Counter 42 * perf code: 0x00 43 * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL 44 * MTL,SRF,GRR 45 * Scope: Core (each processor core has a MSR) 46 * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter 47 * perf code: 0x01 48 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM, 49 * CNL,KBL,CML,TNT 50 * Scope: Core 51 * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter 52 * perf code: 0x02 53 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, 54 * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, 55 * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF, 56 * GRR 57 * Scope: Core 58 * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter 59 * perf code: 0x03 60 * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML, 61 * ICL,TGL,RKL,ADL,RPL,MTL 62 * Scope: Core 63 * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. 64 * perf code: 0x00 65 * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, 66 * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL, 67 * RPL,SPR,MTL 68 * Scope: Package (physical package) 69 * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. 70 * perf code: 0x01 71 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, 72 * GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL, 73 * ADL,RPL,MTL 74 * Scope: Package (physical package) 75 * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. 76 * perf code: 0x02 77 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, 78 * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, 79 * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF 80 * Scope: Package (physical package) 81 * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. 82 * perf code: 0x03 83 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL, 84 * KBL,CML,ICL,TGL,RKL,ADL,RPL,MTL 85 * Scope: Package (physical package) 86 * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter. 87 * perf code: 0x04 88 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL, 89 * ADL,RPL,MTL 90 * Scope: Package (physical package) 91 * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter. 92 * perf code: 0x05 93 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL, 94 * ADL,RPL,MTL 95 * Scope: Package (physical package) 96 * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. 97 * perf code: 0x06 98 * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL, 99 * TNT,RKL,ADL,RPL,MTL 100 * Scope: Package (physical package) 101 * MSR_MODULE_C6_RES_MS: Module C6 Residency Counter. 102 * perf code: 0x00 103 * Available model: SRF,GRR 104 * Scope: A cluster of cores shared L2 cache 105 * 106 */ 107 108 #include <linux/module.h> 109 #include <linux/slab.h> 110 #include <linux/perf_event.h> 111 #include <linux/nospec.h> 112 #include <asm/cpu_device_id.h> 113 #include <asm/intel-family.h> 114 #include "../perf_event.h" 115 #include "../probe.h" 116 117 MODULE_LICENSE("GPL"); 118 119 #define DEFINE_CSTATE_FORMAT_ATTR(_var, _name, _format) \ 120 static ssize_t __cstate_##_var##_show(struct device *dev, \ 121 struct device_attribute *attr, \ 122 char *page) \ 123 { \ 124 BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \ 125 return sprintf(page, _format "\n"); \ 126 } \ 127 static struct device_attribute format_attr_##_var = \ 128 __ATTR(_name, 0444, __cstate_##_var##_show, NULL) 129 130 static ssize_t cstate_get_attr_cpumask(struct device *dev, 131 struct device_attribute *attr, 132 char *buf); 133 134 /* Model -> events mapping */ 135 struct cstate_model { 136 unsigned long core_events; 137 unsigned long pkg_events; 138 unsigned long module_events; 139 unsigned long quirks; 140 }; 141 142 /* Quirk flags */ 143 #define SLM_PKG_C6_USE_C7_MSR (1UL << 0) 144 #define KNL_CORE_C6_MSR (1UL << 1) 145 146 /* cstate_core PMU */ 147 static struct pmu cstate_core_pmu; 148 static bool has_cstate_core; 149 150 enum perf_cstate_core_events { 151 PERF_CSTATE_CORE_C1_RES = 0, 152 PERF_CSTATE_CORE_C3_RES, 153 PERF_CSTATE_CORE_C6_RES, 154 PERF_CSTATE_CORE_C7_RES, 155 156 PERF_CSTATE_CORE_EVENT_MAX, 157 }; 158 159 PMU_EVENT_ATTR_STRING(c1-residency, attr_cstate_core_c1, "event=0x00"); 160 PMU_EVENT_ATTR_STRING(c3-residency, attr_cstate_core_c3, "event=0x01"); 161 PMU_EVENT_ATTR_STRING(c6-residency, attr_cstate_core_c6, "event=0x02"); 162 PMU_EVENT_ATTR_STRING(c7-residency, attr_cstate_core_c7, "event=0x03"); 163 164 static unsigned long core_msr_mask; 165 166 PMU_EVENT_GROUP(events, cstate_core_c1); 167 PMU_EVENT_GROUP(events, cstate_core_c3); 168 PMU_EVENT_GROUP(events, cstate_core_c6); 169 PMU_EVENT_GROUP(events, cstate_core_c7); 170 171 static bool test_msr(int idx, void *data) 172 { 173 return test_bit(idx, (unsigned long *) data); 174 } 175 176 static struct perf_msr core_msr[] = { 177 [PERF_CSTATE_CORE_C1_RES] = { MSR_CORE_C1_RES, &group_cstate_core_c1, test_msr }, 178 [PERF_CSTATE_CORE_C3_RES] = { MSR_CORE_C3_RESIDENCY, &group_cstate_core_c3, test_msr }, 179 [PERF_CSTATE_CORE_C6_RES] = { MSR_CORE_C6_RESIDENCY, &group_cstate_core_c6, test_msr }, 180 [PERF_CSTATE_CORE_C7_RES] = { MSR_CORE_C7_RESIDENCY, &group_cstate_core_c7, test_msr }, 181 }; 182 183 static struct attribute *attrs_empty[] = { 184 NULL, 185 }; 186 187 /* 188 * There are no default events, but we need to create 189 * "events" group (with empty attrs) before updating 190 * it with detected events. 191 */ 192 static struct attribute_group cstate_events_attr_group = { 193 .name = "events", 194 .attrs = attrs_empty, 195 }; 196 197 DEFINE_CSTATE_FORMAT_ATTR(cstate_event, event, "config:0-63"); 198 static struct attribute *cstate_format_attrs[] = { 199 &format_attr_cstate_event.attr, 200 NULL, 201 }; 202 203 static struct attribute_group cstate_format_attr_group = { 204 .name = "format", 205 .attrs = cstate_format_attrs, 206 }; 207 208 static cpumask_t cstate_core_cpu_mask; 209 static DEVICE_ATTR(cpumask, S_IRUGO, cstate_get_attr_cpumask, NULL); 210 211 static struct attribute *cstate_cpumask_attrs[] = { 212 &dev_attr_cpumask.attr, 213 NULL, 214 }; 215 216 static struct attribute_group cpumask_attr_group = { 217 .attrs = cstate_cpumask_attrs, 218 }; 219 220 static const struct attribute_group *cstate_attr_groups[] = { 221 &cstate_events_attr_group, 222 &cstate_format_attr_group, 223 &cpumask_attr_group, 224 NULL, 225 }; 226 227 /* cstate_pkg PMU */ 228 static struct pmu cstate_pkg_pmu; 229 static bool has_cstate_pkg; 230 231 enum perf_cstate_pkg_events { 232 PERF_CSTATE_PKG_C2_RES = 0, 233 PERF_CSTATE_PKG_C3_RES, 234 PERF_CSTATE_PKG_C6_RES, 235 PERF_CSTATE_PKG_C7_RES, 236 PERF_CSTATE_PKG_C8_RES, 237 PERF_CSTATE_PKG_C9_RES, 238 PERF_CSTATE_PKG_C10_RES, 239 240 PERF_CSTATE_PKG_EVENT_MAX, 241 }; 242 243 PMU_EVENT_ATTR_STRING(c2-residency, attr_cstate_pkg_c2, "event=0x00"); 244 PMU_EVENT_ATTR_STRING(c3-residency, attr_cstate_pkg_c3, "event=0x01"); 245 PMU_EVENT_ATTR_STRING(c6-residency, attr_cstate_pkg_c6, "event=0x02"); 246 PMU_EVENT_ATTR_STRING(c7-residency, attr_cstate_pkg_c7, "event=0x03"); 247 PMU_EVENT_ATTR_STRING(c8-residency, attr_cstate_pkg_c8, "event=0x04"); 248 PMU_EVENT_ATTR_STRING(c9-residency, attr_cstate_pkg_c9, "event=0x05"); 249 PMU_EVENT_ATTR_STRING(c10-residency, attr_cstate_pkg_c10, "event=0x06"); 250 251 static unsigned long pkg_msr_mask; 252 253 PMU_EVENT_GROUP(events, cstate_pkg_c2); 254 PMU_EVENT_GROUP(events, cstate_pkg_c3); 255 PMU_EVENT_GROUP(events, cstate_pkg_c6); 256 PMU_EVENT_GROUP(events, cstate_pkg_c7); 257 PMU_EVENT_GROUP(events, cstate_pkg_c8); 258 PMU_EVENT_GROUP(events, cstate_pkg_c9); 259 PMU_EVENT_GROUP(events, cstate_pkg_c10); 260 261 static struct perf_msr pkg_msr[] = { 262 [PERF_CSTATE_PKG_C2_RES] = { MSR_PKG_C2_RESIDENCY, &group_cstate_pkg_c2, test_msr }, 263 [PERF_CSTATE_PKG_C3_RES] = { MSR_PKG_C3_RESIDENCY, &group_cstate_pkg_c3, test_msr }, 264 [PERF_CSTATE_PKG_C6_RES] = { MSR_PKG_C6_RESIDENCY, &group_cstate_pkg_c6, test_msr }, 265 [PERF_CSTATE_PKG_C7_RES] = { MSR_PKG_C7_RESIDENCY, &group_cstate_pkg_c7, test_msr }, 266 [PERF_CSTATE_PKG_C8_RES] = { MSR_PKG_C8_RESIDENCY, &group_cstate_pkg_c8, test_msr }, 267 [PERF_CSTATE_PKG_C9_RES] = { MSR_PKG_C9_RESIDENCY, &group_cstate_pkg_c9, test_msr }, 268 [PERF_CSTATE_PKG_C10_RES] = { MSR_PKG_C10_RESIDENCY, &group_cstate_pkg_c10, test_msr }, 269 }; 270 271 static cpumask_t cstate_pkg_cpu_mask; 272 273 /* cstate_module PMU */ 274 static struct pmu cstate_module_pmu; 275 static bool has_cstate_module; 276 277 enum perf_cstate_module_events { 278 PERF_CSTATE_MODULE_C6_RES = 0, 279 280 PERF_CSTATE_MODULE_EVENT_MAX, 281 }; 282 283 PMU_EVENT_ATTR_STRING(c6-residency, attr_cstate_module_c6, "event=0x00"); 284 285 static unsigned long module_msr_mask; 286 287 PMU_EVENT_GROUP(events, cstate_module_c6); 288 289 static struct perf_msr module_msr[] = { 290 [PERF_CSTATE_MODULE_C6_RES] = { MSR_MODULE_C6_RES_MS, &group_cstate_module_c6, test_msr }, 291 }; 292 293 static cpumask_t cstate_module_cpu_mask; 294 295 static ssize_t cstate_get_attr_cpumask(struct device *dev, 296 struct device_attribute *attr, 297 char *buf) 298 { 299 struct pmu *pmu = dev_get_drvdata(dev); 300 301 if (pmu == &cstate_core_pmu) 302 return cpumap_print_to_pagebuf(true, buf, &cstate_core_cpu_mask); 303 else if (pmu == &cstate_pkg_pmu) 304 return cpumap_print_to_pagebuf(true, buf, &cstate_pkg_cpu_mask); 305 else if (pmu == &cstate_module_pmu) 306 return cpumap_print_to_pagebuf(true, buf, &cstate_module_cpu_mask); 307 else 308 return 0; 309 } 310 311 static int cstate_pmu_event_init(struct perf_event *event) 312 { 313 u64 cfg = event->attr.config; 314 int cpu; 315 316 if (event->attr.type != event->pmu->type) 317 return -ENOENT; 318 319 /* unsupported modes and filters */ 320 if (event->attr.sample_period) /* no sampling */ 321 return -EINVAL; 322 323 if (event->cpu < 0) 324 return -EINVAL; 325 326 if (event->pmu == &cstate_core_pmu) { 327 if (cfg >= PERF_CSTATE_CORE_EVENT_MAX) 328 return -EINVAL; 329 cfg = array_index_nospec((unsigned long)cfg, PERF_CSTATE_CORE_EVENT_MAX); 330 if (!(core_msr_mask & (1 << cfg))) 331 return -EINVAL; 332 event->hw.event_base = core_msr[cfg].msr; 333 cpu = cpumask_any_and(&cstate_core_cpu_mask, 334 topology_sibling_cpumask(event->cpu)); 335 } else if (event->pmu == &cstate_pkg_pmu) { 336 if (cfg >= PERF_CSTATE_PKG_EVENT_MAX) 337 return -EINVAL; 338 cfg = array_index_nospec((unsigned long)cfg, PERF_CSTATE_PKG_EVENT_MAX); 339 if (!(pkg_msr_mask & (1 << cfg))) 340 return -EINVAL; 341 342 event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG; 343 344 event->hw.event_base = pkg_msr[cfg].msr; 345 cpu = cpumask_any_and(&cstate_pkg_cpu_mask, 346 topology_die_cpumask(event->cpu)); 347 } else if (event->pmu == &cstate_module_pmu) { 348 if (cfg >= PERF_CSTATE_MODULE_EVENT_MAX) 349 return -EINVAL; 350 cfg = array_index_nospec((unsigned long)cfg, PERF_CSTATE_MODULE_EVENT_MAX); 351 if (!(module_msr_mask & (1 << cfg))) 352 return -EINVAL; 353 event->hw.event_base = module_msr[cfg].msr; 354 cpu = cpumask_any_and(&cstate_module_cpu_mask, 355 topology_cluster_cpumask(event->cpu)); 356 } else { 357 return -ENOENT; 358 } 359 360 if (cpu >= nr_cpu_ids) 361 return -ENODEV; 362 363 event->cpu = cpu; 364 event->hw.config = cfg; 365 event->hw.idx = -1; 366 return 0; 367 } 368 369 static inline u64 cstate_pmu_read_counter(struct perf_event *event) 370 { 371 u64 val; 372 373 rdmsrl(event->hw.event_base, val); 374 return val; 375 } 376 377 static void cstate_pmu_event_update(struct perf_event *event) 378 { 379 struct hw_perf_event *hwc = &event->hw; 380 u64 prev_raw_count, new_raw_count; 381 382 prev_raw_count = local64_read(&hwc->prev_count); 383 do { 384 new_raw_count = cstate_pmu_read_counter(event); 385 } while (!local64_try_cmpxchg(&hwc->prev_count, 386 &prev_raw_count, new_raw_count)); 387 388 local64_add(new_raw_count - prev_raw_count, &event->count); 389 } 390 391 static void cstate_pmu_event_start(struct perf_event *event, int mode) 392 { 393 local64_set(&event->hw.prev_count, cstate_pmu_read_counter(event)); 394 } 395 396 static void cstate_pmu_event_stop(struct perf_event *event, int mode) 397 { 398 cstate_pmu_event_update(event); 399 } 400 401 static void cstate_pmu_event_del(struct perf_event *event, int mode) 402 { 403 cstate_pmu_event_stop(event, PERF_EF_UPDATE); 404 } 405 406 static int cstate_pmu_event_add(struct perf_event *event, int mode) 407 { 408 if (mode & PERF_EF_START) 409 cstate_pmu_event_start(event, mode); 410 411 return 0; 412 } 413 414 /* 415 * Check if exiting cpu is the designated reader. If so migrate the 416 * events when there is a valid target available 417 */ 418 static int cstate_cpu_exit(unsigned int cpu) 419 { 420 unsigned int target; 421 422 if (has_cstate_core && 423 cpumask_test_and_clear_cpu(cpu, &cstate_core_cpu_mask)) { 424 425 target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu); 426 /* Migrate events if there is a valid target */ 427 if (target < nr_cpu_ids) { 428 cpumask_set_cpu(target, &cstate_core_cpu_mask); 429 perf_pmu_migrate_context(&cstate_core_pmu, cpu, target); 430 } 431 } 432 433 if (has_cstate_pkg && 434 cpumask_test_and_clear_cpu(cpu, &cstate_pkg_cpu_mask)) { 435 436 target = cpumask_any_but(topology_die_cpumask(cpu), cpu); 437 /* Migrate events if there is a valid target */ 438 if (target < nr_cpu_ids) { 439 cpumask_set_cpu(target, &cstate_pkg_cpu_mask); 440 perf_pmu_migrate_context(&cstate_pkg_pmu, cpu, target); 441 } 442 } 443 444 if (has_cstate_module && 445 cpumask_test_and_clear_cpu(cpu, &cstate_module_cpu_mask)) { 446 447 target = cpumask_any_but(topology_cluster_cpumask(cpu), cpu); 448 /* Migrate events if there is a valid target */ 449 if (target < nr_cpu_ids) { 450 cpumask_set_cpu(target, &cstate_module_cpu_mask); 451 perf_pmu_migrate_context(&cstate_module_pmu, cpu, target); 452 } 453 } 454 return 0; 455 } 456 457 static int cstate_cpu_init(unsigned int cpu) 458 { 459 unsigned int target; 460 461 /* 462 * If this is the first online thread of that core, set it in 463 * the core cpu mask as the designated reader. 464 */ 465 target = cpumask_any_and(&cstate_core_cpu_mask, 466 topology_sibling_cpumask(cpu)); 467 468 if (has_cstate_core && target >= nr_cpu_ids) 469 cpumask_set_cpu(cpu, &cstate_core_cpu_mask); 470 471 /* 472 * If this is the first online thread of that package, set it 473 * in the package cpu mask as the designated reader. 474 */ 475 target = cpumask_any_and(&cstate_pkg_cpu_mask, 476 topology_die_cpumask(cpu)); 477 if (has_cstate_pkg && target >= nr_cpu_ids) 478 cpumask_set_cpu(cpu, &cstate_pkg_cpu_mask); 479 480 /* 481 * If this is the first online thread of that cluster, set it 482 * in the cluster cpu mask as the designated reader. 483 */ 484 target = cpumask_any_and(&cstate_module_cpu_mask, 485 topology_cluster_cpumask(cpu)); 486 if (has_cstate_module && target >= nr_cpu_ids) 487 cpumask_set_cpu(cpu, &cstate_module_cpu_mask); 488 489 return 0; 490 } 491 492 static const struct attribute_group *core_attr_update[] = { 493 &group_cstate_core_c1, 494 &group_cstate_core_c3, 495 &group_cstate_core_c6, 496 &group_cstate_core_c7, 497 NULL, 498 }; 499 500 static const struct attribute_group *pkg_attr_update[] = { 501 &group_cstate_pkg_c2, 502 &group_cstate_pkg_c3, 503 &group_cstate_pkg_c6, 504 &group_cstate_pkg_c7, 505 &group_cstate_pkg_c8, 506 &group_cstate_pkg_c9, 507 &group_cstate_pkg_c10, 508 NULL, 509 }; 510 511 static const struct attribute_group *module_attr_update[] = { 512 &group_cstate_module_c6, 513 NULL 514 }; 515 516 static struct pmu cstate_core_pmu = { 517 .attr_groups = cstate_attr_groups, 518 .attr_update = core_attr_update, 519 .name = "cstate_core", 520 .task_ctx_nr = perf_invalid_context, 521 .event_init = cstate_pmu_event_init, 522 .add = cstate_pmu_event_add, 523 .del = cstate_pmu_event_del, 524 .start = cstate_pmu_event_start, 525 .stop = cstate_pmu_event_stop, 526 .read = cstate_pmu_event_update, 527 .capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, 528 .module = THIS_MODULE, 529 }; 530 531 static struct pmu cstate_pkg_pmu = { 532 .attr_groups = cstate_attr_groups, 533 .attr_update = pkg_attr_update, 534 .name = "cstate_pkg", 535 .task_ctx_nr = perf_invalid_context, 536 .event_init = cstate_pmu_event_init, 537 .add = cstate_pmu_event_add, 538 .del = cstate_pmu_event_del, 539 .start = cstate_pmu_event_start, 540 .stop = cstate_pmu_event_stop, 541 .read = cstate_pmu_event_update, 542 .capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, 543 .module = THIS_MODULE, 544 }; 545 546 static struct pmu cstate_module_pmu = { 547 .attr_groups = cstate_attr_groups, 548 .attr_update = module_attr_update, 549 .name = "cstate_module", 550 .task_ctx_nr = perf_invalid_context, 551 .event_init = cstate_pmu_event_init, 552 .add = cstate_pmu_event_add, 553 .del = cstate_pmu_event_del, 554 .start = cstate_pmu_event_start, 555 .stop = cstate_pmu_event_stop, 556 .read = cstate_pmu_event_update, 557 .capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, 558 .module = THIS_MODULE, 559 }; 560 561 static const struct cstate_model nhm_cstates __initconst = { 562 .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | 563 BIT(PERF_CSTATE_CORE_C6_RES), 564 565 .pkg_events = BIT(PERF_CSTATE_PKG_C3_RES) | 566 BIT(PERF_CSTATE_PKG_C6_RES) | 567 BIT(PERF_CSTATE_PKG_C7_RES), 568 }; 569 570 static const struct cstate_model snb_cstates __initconst = { 571 .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | 572 BIT(PERF_CSTATE_CORE_C6_RES) | 573 BIT(PERF_CSTATE_CORE_C7_RES), 574 575 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 576 BIT(PERF_CSTATE_PKG_C3_RES) | 577 BIT(PERF_CSTATE_PKG_C6_RES) | 578 BIT(PERF_CSTATE_PKG_C7_RES), 579 }; 580 581 static const struct cstate_model hswult_cstates __initconst = { 582 .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | 583 BIT(PERF_CSTATE_CORE_C6_RES) | 584 BIT(PERF_CSTATE_CORE_C7_RES), 585 586 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 587 BIT(PERF_CSTATE_PKG_C3_RES) | 588 BIT(PERF_CSTATE_PKG_C6_RES) | 589 BIT(PERF_CSTATE_PKG_C7_RES) | 590 BIT(PERF_CSTATE_PKG_C8_RES) | 591 BIT(PERF_CSTATE_PKG_C9_RES) | 592 BIT(PERF_CSTATE_PKG_C10_RES), 593 }; 594 595 static const struct cstate_model cnl_cstates __initconst = { 596 .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 597 BIT(PERF_CSTATE_CORE_C3_RES) | 598 BIT(PERF_CSTATE_CORE_C6_RES) | 599 BIT(PERF_CSTATE_CORE_C7_RES), 600 601 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 602 BIT(PERF_CSTATE_PKG_C3_RES) | 603 BIT(PERF_CSTATE_PKG_C6_RES) | 604 BIT(PERF_CSTATE_PKG_C7_RES) | 605 BIT(PERF_CSTATE_PKG_C8_RES) | 606 BIT(PERF_CSTATE_PKG_C9_RES) | 607 BIT(PERF_CSTATE_PKG_C10_RES), 608 }; 609 610 static const struct cstate_model icl_cstates __initconst = { 611 .core_events = BIT(PERF_CSTATE_CORE_C6_RES) | 612 BIT(PERF_CSTATE_CORE_C7_RES), 613 614 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 615 BIT(PERF_CSTATE_PKG_C3_RES) | 616 BIT(PERF_CSTATE_PKG_C6_RES) | 617 BIT(PERF_CSTATE_PKG_C7_RES) | 618 BIT(PERF_CSTATE_PKG_C8_RES) | 619 BIT(PERF_CSTATE_PKG_C9_RES) | 620 BIT(PERF_CSTATE_PKG_C10_RES), 621 }; 622 623 static const struct cstate_model icx_cstates __initconst = { 624 .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 625 BIT(PERF_CSTATE_CORE_C6_RES), 626 627 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 628 BIT(PERF_CSTATE_PKG_C6_RES), 629 }; 630 631 static const struct cstate_model adl_cstates __initconst = { 632 .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 633 BIT(PERF_CSTATE_CORE_C6_RES) | 634 BIT(PERF_CSTATE_CORE_C7_RES), 635 636 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 637 BIT(PERF_CSTATE_PKG_C3_RES) | 638 BIT(PERF_CSTATE_PKG_C6_RES) | 639 BIT(PERF_CSTATE_PKG_C7_RES) | 640 BIT(PERF_CSTATE_PKG_C8_RES) | 641 BIT(PERF_CSTATE_PKG_C9_RES) | 642 BIT(PERF_CSTATE_PKG_C10_RES), 643 }; 644 645 static const struct cstate_model slm_cstates __initconst = { 646 .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 647 BIT(PERF_CSTATE_CORE_C6_RES), 648 649 .pkg_events = BIT(PERF_CSTATE_PKG_C6_RES), 650 .quirks = SLM_PKG_C6_USE_C7_MSR, 651 }; 652 653 654 static const struct cstate_model knl_cstates __initconst = { 655 .core_events = BIT(PERF_CSTATE_CORE_C6_RES), 656 657 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 658 BIT(PERF_CSTATE_PKG_C3_RES) | 659 BIT(PERF_CSTATE_PKG_C6_RES), 660 .quirks = KNL_CORE_C6_MSR, 661 }; 662 663 664 static const struct cstate_model glm_cstates __initconst = { 665 .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 666 BIT(PERF_CSTATE_CORE_C3_RES) | 667 BIT(PERF_CSTATE_CORE_C6_RES), 668 669 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 670 BIT(PERF_CSTATE_PKG_C3_RES) | 671 BIT(PERF_CSTATE_PKG_C6_RES) | 672 BIT(PERF_CSTATE_PKG_C10_RES), 673 }; 674 675 static const struct cstate_model grr_cstates __initconst = { 676 .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 677 BIT(PERF_CSTATE_CORE_C6_RES), 678 679 .module_events = BIT(PERF_CSTATE_MODULE_C6_RES), 680 }; 681 682 static const struct cstate_model srf_cstates __initconst = { 683 .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 684 BIT(PERF_CSTATE_CORE_C6_RES), 685 686 .pkg_events = BIT(PERF_CSTATE_PKG_C6_RES), 687 688 .module_events = BIT(PERF_CSTATE_MODULE_C6_RES), 689 }; 690 691 692 static const struct x86_cpu_id intel_cstates_match[] __initconst = { 693 X86_MATCH_VFM(INTEL_NEHALEM, &nhm_cstates), 694 X86_MATCH_VFM(INTEL_NEHALEM_EP, &nhm_cstates), 695 X86_MATCH_VFM(INTEL_NEHALEM_EX, &nhm_cstates), 696 697 X86_MATCH_VFM(INTEL_WESTMERE, &nhm_cstates), 698 X86_MATCH_VFM(INTEL_WESTMERE_EP, &nhm_cstates), 699 X86_MATCH_VFM(INTEL_WESTMERE_EX, &nhm_cstates), 700 701 X86_MATCH_VFM(INTEL_SANDYBRIDGE, &snb_cstates), 702 X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &snb_cstates), 703 704 X86_MATCH_VFM(INTEL_IVYBRIDGE, &snb_cstates), 705 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &snb_cstates), 706 707 X86_MATCH_VFM(INTEL_HASWELL, &snb_cstates), 708 X86_MATCH_VFM(INTEL_HASWELL_X, &snb_cstates), 709 X86_MATCH_VFM(INTEL_HASWELL_G, &snb_cstates), 710 711 X86_MATCH_VFM(INTEL_HASWELL_L, &hswult_cstates), 712 713 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &slm_cstates), 714 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_D, &slm_cstates), 715 X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &slm_cstates), 716 717 X86_MATCH_VFM(INTEL_BROADWELL, &snb_cstates), 718 X86_MATCH_VFM(INTEL_BROADWELL_D, &snb_cstates), 719 X86_MATCH_VFM(INTEL_BROADWELL_G, &snb_cstates), 720 X86_MATCH_VFM(INTEL_BROADWELL_X, &snb_cstates), 721 722 X86_MATCH_VFM(INTEL_SKYLAKE_L, &snb_cstates), 723 X86_MATCH_VFM(INTEL_SKYLAKE, &snb_cstates), 724 X86_MATCH_VFM(INTEL_SKYLAKE_X, &snb_cstates), 725 726 X86_MATCH_VFM(INTEL_KABYLAKE_L, &hswult_cstates), 727 X86_MATCH_VFM(INTEL_KABYLAKE, &hswult_cstates), 728 X86_MATCH_VFM(INTEL_COMETLAKE_L, &hswult_cstates), 729 X86_MATCH_VFM(INTEL_COMETLAKE, &hswult_cstates), 730 731 X86_MATCH_VFM(INTEL_CANNONLAKE_L, &cnl_cstates), 732 733 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &knl_cstates), 734 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &knl_cstates), 735 736 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &glm_cstates), 737 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &glm_cstates), 738 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &glm_cstates), 739 X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &glm_cstates), 740 X86_MATCH_VFM(INTEL_ATOM_TREMONT, &glm_cstates), 741 X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &glm_cstates), 742 X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &adl_cstates), 743 X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X, &srf_cstates), 744 X86_MATCH_VFM(INTEL_ATOM_CRESTMONT, &grr_cstates), 745 746 X86_MATCH_VFM(INTEL_ICELAKE_L, &icl_cstates), 747 X86_MATCH_VFM(INTEL_ICELAKE, &icl_cstates), 748 X86_MATCH_VFM(INTEL_ICELAKE_X, &icx_cstates), 749 X86_MATCH_VFM(INTEL_ICELAKE_D, &icx_cstates), 750 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &icx_cstates), 751 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &icx_cstates), 752 X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, &icx_cstates), 753 X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, &icx_cstates), 754 755 X86_MATCH_VFM(INTEL_TIGERLAKE_L, &icl_cstates), 756 X86_MATCH_VFM(INTEL_TIGERLAKE, &icl_cstates), 757 X86_MATCH_VFM(INTEL_ROCKETLAKE, &icl_cstates), 758 X86_MATCH_VFM(INTEL_ALDERLAKE, &adl_cstates), 759 X86_MATCH_VFM(INTEL_ALDERLAKE_L, &adl_cstates), 760 X86_MATCH_VFM(INTEL_RAPTORLAKE, &adl_cstates), 761 X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &adl_cstates), 762 X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &adl_cstates), 763 X86_MATCH_VFM(INTEL_METEORLAKE, &adl_cstates), 764 X86_MATCH_VFM(INTEL_METEORLAKE_L, &adl_cstates), 765 { }, 766 }; 767 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match); 768 769 static int __init cstate_probe(const struct cstate_model *cm) 770 { 771 /* SLM has different MSR for PKG C6 */ 772 if (cm->quirks & SLM_PKG_C6_USE_C7_MSR) 773 pkg_msr[PERF_CSTATE_PKG_C6_RES].msr = MSR_PKG_C7_RESIDENCY; 774 775 /* KNL has different MSR for CORE C6 */ 776 if (cm->quirks & KNL_CORE_C6_MSR) 777 pkg_msr[PERF_CSTATE_CORE_C6_RES].msr = MSR_KNL_CORE_C6_RESIDENCY; 778 779 780 core_msr_mask = perf_msr_probe(core_msr, PERF_CSTATE_CORE_EVENT_MAX, 781 true, (void *) &cm->core_events); 782 783 pkg_msr_mask = perf_msr_probe(pkg_msr, PERF_CSTATE_PKG_EVENT_MAX, 784 true, (void *) &cm->pkg_events); 785 786 module_msr_mask = perf_msr_probe(module_msr, PERF_CSTATE_MODULE_EVENT_MAX, 787 true, (void *) &cm->module_events); 788 789 has_cstate_core = !!core_msr_mask; 790 has_cstate_pkg = !!pkg_msr_mask; 791 has_cstate_module = !!module_msr_mask; 792 793 return (has_cstate_core || has_cstate_pkg || has_cstate_module) ? 0 : -ENODEV; 794 } 795 796 static inline void cstate_cleanup(void) 797 { 798 cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_ONLINE); 799 cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_STARTING); 800 801 if (has_cstate_core) 802 perf_pmu_unregister(&cstate_core_pmu); 803 804 if (has_cstate_pkg) 805 perf_pmu_unregister(&cstate_pkg_pmu); 806 807 if (has_cstate_module) 808 perf_pmu_unregister(&cstate_module_pmu); 809 } 810 811 static int __init cstate_init(void) 812 { 813 int err; 814 815 cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_STARTING, 816 "perf/x86/cstate:starting", cstate_cpu_init, NULL); 817 cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_ONLINE, 818 "perf/x86/cstate:online", NULL, cstate_cpu_exit); 819 820 if (has_cstate_core) { 821 err = perf_pmu_register(&cstate_core_pmu, cstate_core_pmu.name, -1); 822 if (err) { 823 has_cstate_core = false; 824 pr_info("Failed to register cstate core pmu\n"); 825 cstate_cleanup(); 826 return err; 827 } 828 } 829 830 if (has_cstate_pkg) { 831 if (topology_max_dies_per_package() > 1) { 832 err = perf_pmu_register(&cstate_pkg_pmu, 833 "cstate_die", -1); 834 } else { 835 err = perf_pmu_register(&cstate_pkg_pmu, 836 cstate_pkg_pmu.name, -1); 837 } 838 if (err) { 839 has_cstate_pkg = false; 840 pr_info("Failed to register cstate pkg pmu\n"); 841 cstate_cleanup(); 842 return err; 843 } 844 } 845 846 if (has_cstate_module) { 847 err = perf_pmu_register(&cstate_module_pmu, cstate_module_pmu.name, -1); 848 if (err) { 849 has_cstate_module = false; 850 pr_info("Failed to register cstate cluster pmu\n"); 851 cstate_cleanup(); 852 return err; 853 } 854 } 855 return 0; 856 } 857 858 static int __init cstate_pmu_init(void) 859 { 860 const struct x86_cpu_id *id; 861 int err; 862 863 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 864 return -ENODEV; 865 866 id = x86_match_cpu(intel_cstates_match); 867 if (!id) 868 return -ENODEV; 869 870 err = cstate_probe((const struct cstate_model *) id->driver_data); 871 if (err) 872 return err; 873 874 return cstate_init(); 875 } 876 module_init(cstate_pmu_init); 877 878 static void __exit cstate_pmu_exit(void) 879 { 880 cstate_cleanup(); 881 } 882 module_exit(cstate_pmu_exit); 883