1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Per core/cpu state 4 * 5 * Used to coordinate shared registers between HT threads or 6 * among events on a single PMU. 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/stddef.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/export.h> 16 #include <linux/nmi.h> 17 #include <linux/kvm_host.h> 18 19 #include <asm/cpufeature.h> 20 #include <asm/debugreg.h> 21 #include <asm/hardirq.h> 22 #include <asm/intel-family.h> 23 #include <asm/intel_pt.h> 24 #include <asm/apic.h> 25 #include <asm/cpu_device_id.h> 26 27 #include "../perf_event.h" 28 29 /* 30 * Intel PerfMon, used on Core and later. 31 */ 32 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 33 { 34 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 35 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 36 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 37 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 38 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 39 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 40 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 41 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 42 }; 43 44 static struct event_constraint intel_core_event_constraints[] __read_mostly = 45 { 46 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 47 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 48 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 49 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 50 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 51 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 52 EVENT_CONSTRAINT_END 53 }; 54 55 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 56 { 57 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 58 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 59 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 60 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 61 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 62 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 63 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 64 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 65 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 66 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 67 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 68 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 69 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 70 EVENT_CONSTRAINT_END 71 }; 72 73 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 74 { 75 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 76 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 77 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 78 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 79 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 80 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 81 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 82 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 83 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 84 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 85 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 86 EVENT_CONSTRAINT_END 87 }; 88 89 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 90 { 91 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 92 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 93 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 94 EVENT_EXTRA_END 95 }; 96 97 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 98 { 99 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 100 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 101 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 102 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 103 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 104 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 105 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 106 EVENT_CONSTRAINT_END 107 }; 108 109 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 110 { 111 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 112 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 113 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 114 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 115 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 116 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 117 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 118 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 119 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 120 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 121 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 122 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 123 124 /* 125 * When HT is off these events can only run on the bottom 4 counters 126 * When HT is on, they are impacted by the HT bug and require EXCL access 127 */ 128 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 129 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 130 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 131 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 132 133 EVENT_CONSTRAINT_END 134 }; 135 136 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 137 { 138 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 139 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 140 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 141 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 142 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ 143 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 144 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 145 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 146 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 147 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 148 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 149 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 150 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 151 152 /* 153 * When HT is off these events can only run on the bottom 4 counters 154 * When HT is on, they are impacted by the HT bug and require EXCL access 155 */ 156 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 157 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 158 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 159 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 160 161 EVENT_CONSTRAINT_END 162 }; 163 164 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 165 { 166 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 167 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 168 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 169 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 170 EVENT_EXTRA_END 171 }; 172 173 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 174 { 175 EVENT_CONSTRAINT_END 176 }; 177 178 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 179 { 180 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 181 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 182 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 183 EVENT_CONSTRAINT_END 184 }; 185 186 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly = 187 { 188 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 189 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 190 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 191 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 192 FIXED_EVENT_CONSTRAINT(0x0500, 4), 193 FIXED_EVENT_CONSTRAINT(0x0600, 5), 194 FIXED_EVENT_CONSTRAINT(0x0700, 6), 195 FIXED_EVENT_CONSTRAINT(0x0800, 7), 196 FIXED_EVENT_CONSTRAINT(0x0900, 8), 197 FIXED_EVENT_CONSTRAINT(0x0a00, 9), 198 FIXED_EVENT_CONSTRAINT(0x0b00, 10), 199 FIXED_EVENT_CONSTRAINT(0x0c00, 11), 200 FIXED_EVENT_CONSTRAINT(0x0d00, 12), 201 FIXED_EVENT_CONSTRAINT(0x0e00, 13), 202 FIXED_EVENT_CONSTRAINT(0x0f00, 14), 203 FIXED_EVENT_CONSTRAINT(0x1000, 15), 204 EVENT_CONSTRAINT_END 205 }; 206 207 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 208 { 209 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 210 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 211 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 212 EVENT_CONSTRAINT_END 213 }; 214 215 static struct event_constraint intel_grt_event_constraints[] __read_mostly = { 216 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 217 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 218 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 219 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 220 EVENT_CONSTRAINT_END 221 }; 222 223 static struct event_constraint intel_skt_event_constraints[] __read_mostly = { 224 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 225 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 226 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 227 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 228 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */ 229 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */ 230 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */ 231 EVENT_CONSTRAINT_END 232 }; 233 234 static struct event_constraint intel_skl_event_constraints[] = { 235 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 236 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 237 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 238 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 239 240 /* 241 * when HT is off, these can only run on the bottom 4 counters 242 */ 243 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 244 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 245 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 246 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 247 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 248 249 EVENT_CONSTRAINT_END 250 }; 251 252 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 253 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 254 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 255 EVENT_EXTRA_END 256 }; 257 258 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 259 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 260 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 261 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 262 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 263 EVENT_EXTRA_END 264 }; 265 266 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 267 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 268 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 269 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 270 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 271 EVENT_EXTRA_END 272 }; 273 274 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 275 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 276 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 277 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 278 /* 279 * Note the low 8 bits eventsel code is not a continuous field, containing 280 * some #GPing bits. These are masked out. 281 */ 282 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 283 EVENT_EXTRA_END 284 }; 285 286 static struct event_constraint intel_icl_event_constraints[] = { 287 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 288 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ 289 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 290 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 291 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 292 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 293 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 294 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 295 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 296 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 297 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 298 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 299 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 300 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf), 301 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 302 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 303 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 304 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 305 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 306 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 307 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 308 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 309 INTEL_EVENT_CONSTRAINT(0xef, 0xf), 310 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 311 EVENT_CONSTRAINT_END 312 }; 313 314 static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 315 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 316 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 317 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 318 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 319 EVENT_EXTRA_END 320 }; 321 322 static struct extra_reg intel_glc_extra_regs[] __read_mostly = { 323 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 324 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 325 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 326 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 327 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 328 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 329 EVENT_EXTRA_END 330 }; 331 332 static struct event_constraint intel_glc_event_constraints[] = { 333 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 334 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 335 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 336 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 337 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 338 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 339 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 340 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 341 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 342 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 343 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 344 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 345 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 346 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 347 348 INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 349 INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 350 /* 351 * Generally event codes < 0x90 are restricted to counters 0-3. 352 * The 0x2E and 0x3C are exception, which has no restriction. 353 */ 354 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 355 356 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 357 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 358 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 359 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 360 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 361 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 362 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 363 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 364 /* 365 * Generally event codes >= 0x90 are likely to have no restrictions. 366 * The exception are defined as above. 367 */ 368 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 369 370 EVENT_CONSTRAINT_END 371 }; 372 373 static struct extra_reg intel_rwc_extra_regs[] __read_mostly = { 374 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 375 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 376 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 377 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 378 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 379 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 380 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 381 EVENT_EXTRA_END 382 }; 383 384 static struct event_constraint intel_lnc_event_constraints[] = { 385 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 386 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 387 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 388 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 389 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 390 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 391 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 392 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 393 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 394 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 395 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 396 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 397 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 398 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 399 400 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), 401 INTEL_UEVENT_CONSTRAINT(0x0175, 0x4), 402 403 INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff), 404 INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff), 405 /* 406 * Generally event codes < 0x90 are restricted to counters 0-3. 407 * The 0x2E and 0x3C are exception, which has no restriction. 408 */ 409 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 410 411 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 412 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 413 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 414 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 415 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 416 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 417 INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1), 418 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8), 419 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3), 420 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 421 422 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 423 /* 424 * Generally event codes >= 0x90 are likely to have no restrictions. 425 * The exception are defined as above. 426 */ 427 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0x3ff), 428 429 EVENT_CONSTRAINT_END 430 }; 431 432 433 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 434 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 435 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 436 437 static struct attribute *nhm_mem_events_attrs[] = { 438 EVENT_PTR(mem_ld_nhm), 439 NULL, 440 }; 441 442 /* 443 * topdown events for Intel Core CPUs. 444 * 445 * The events are all in slots, which is a free slot in a 4 wide 446 * pipeline. Some events are already reported in slots, for cycle 447 * events we multiply by the pipeline width (4). 448 * 449 * With Hyper Threading on, topdown metrics are either summed or averaged 450 * between the threads of a core: (count_t0 + count_t1). 451 * 452 * For the average case the metric is always scaled to pipeline width, 453 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 454 */ 455 456 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 457 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 458 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 459 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 460 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 461 "event=0xe,umask=0x1"); /* uops_issued.any */ 462 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 463 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 464 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 465 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 466 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 467 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 468 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 469 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 470 "4", "2"); 471 472 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 473 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 474 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 475 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 476 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 477 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 478 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 479 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 480 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 481 482 static struct attribute *snb_events_attrs[] = { 483 EVENT_PTR(td_slots_issued), 484 EVENT_PTR(td_slots_retired), 485 EVENT_PTR(td_fetch_bubbles), 486 EVENT_PTR(td_total_slots), 487 EVENT_PTR(td_total_slots_scale), 488 EVENT_PTR(td_recovery_bubbles), 489 EVENT_PTR(td_recovery_bubbles_scale), 490 NULL, 491 }; 492 493 static struct attribute *snb_mem_events_attrs[] = { 494 EVENT_PTR(mem_ld_snb), 495 EVENT_PTR(mem_st_snb), 496 NULL, 497 }; 498 499 static struct event_constraint intel_hsw_event_constraints[] = { 500 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 501 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 502 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 503 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 504 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 505 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 506 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 507 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 508 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 509 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 510 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 511 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 512 513 /* 514 * When HT is off these events can only run on the bottom 4 counters 515 * When HT is on, they are impacted by the HT bug and require EXCL access 516 */ 517 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 518 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 519 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 520 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 521 522 EVENT_CONSTRAINT_END 523 }; 524 525 static struct event_constraint intel_bdw_event_constraints[] = { 526 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 527 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 528 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 529 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 530 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 531 /* 532 * when HT is off, these can only run on the bottom 4 counters 533 */ 534 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 535 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 536 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 537 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 538 EVENT_CONSTRAINT_END 539 }; 540 541 static u64 intel_pmu_event_map(int hw_event) 542 { 543 return intel_perfmon_event_map[hw_event]; 544 } 545 546 static __initconst const u64 glc_hw_cache_event_ids 547 [PERF_COUNT_HW_CACHE_MAX] 548 [PERF_COUNT_HW_CACHE_OP_MAX] 549 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 550 { 551 [ C(L1D ) ] = { 552 [ C(OP_READ) ] = { 553 [ C(RESULT_ACCESS) ] = 0x81d0, 554 [ C(RESULT_MISS) ] = 0xe124, 555 }, 556 [ C(OP_WRITE) ] = { 557 [ C(RESULT_ACCESS) ] = 0x82d0, 558 }, 559 }, 560 [ C(L1I ) ] = { 561 [ C(OP_READ) ] = { 562 [ C(RESULT_MISS) ] = 0xe424, 563 }, 564 [ C(OP_WRITE) ] = { 565 [ C(RESULT_ACCESS) ] = -1, 566 [ C(RESULT_MISS) ] = -1, 567 }, 568 }, 569 [ C(LL ) ] = { 570 [ C(OP_READ) ] = { 571 [ C(RESULT_ACCESS) ] = 0x12a, 572 [ C(RESULT_MISS) ] = 0x12a, 573 }, 574 [ C(OP_WRITE) ] = { 575 [ C(RESULT_ACCESS) ] = 0x12a, 576 [ C(RESULT_MISS) ] = 0x12a, 577 }, 578 }, 579 [ C(DTLB) ] = { 580 [ C(OP_READ) ] = { 581 [ C(RESULT_ACCESS) ] = 0x81d0, 582 [ C(RESULT_MISS) ] = 0xe12, 583 }, 584 [ C(OP_WRITE) ] = { 585 [ C(RESULT_ACCESS) ] = 0x82d0, 586 [ C(RESULT_MISS) ] = 0xe13, 587 }, 588 }, 589 [ C(ITLB) ] = { 590 [ C(OP_READ) ] = { 591 [ C(RESULT_ACCESS) ] = -1, 592 [ C(RESULT_MISS) ] = 0xe11, 593 }, 594 [ C(OP_WRITE) ] = { 595 [ C(RESULT_ACCESS) ] = -1, 596 [ C(RESULT_MISS) ] = -1, 597 }, 598 [ C(OP_PREFETCH) ] = { 599 [ C(RESULT_ACCESS) ] = -1, 600 [ C(RESULT_MISS) ] = -1, 601 }, 602 }, 603 [ C(BPU ) ] = { 604 [ C(OP_READ) ] = { 605 [ C(RESULT_ACCESS) ] = 0x4c4, 606 [ C(RESULT_MISS) ] = 0x4c5, 607 }, 608 [ C(OP_WRITE) ] = { 609 [ C(RESULT_ACCESS) ] = -1, 610 [ C(RESULT_MISS) ] = -1, 611 }, 612 [ C(OP_PREFETCH) ] = { 613 [ C(RESULT_ACCESS) ] = -1, 614 [ C(RESULT_MISS) ] = -1, 615 }, 616 }, 617 [ C(NODE) ] = { 618 [ C(OP_READ) ] = { 619 [ C(RESULT_ACCESS) ] = 0x12a, 620 [ C(RESULT_MISS) ] = 0x12a, 621 }, 622 }, 623 }; 624 625 static __initconst const u64 glc_hw_cache_extra_regs 626 [PERF_COUNT_HW_CACHE_MAX] 627 [PERF_COUNT_HW_CACHE_OP_MAX] 628 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 629 { 630 [ C(LL ) ] = { 631 [ C(OP_READ) ] = { 632 [ C(RESULT_ACCESS) ] = 0x10001, 633 [ C(RESULT_MISS) ] = 0x3fbfc00001, 634 }, 635 [ C(OP_WRITE) ] = { 636 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, 637 [ C(RESULT_MISS) ] = 0x3f3fc00002, 638 }, 639 }, 640 [ C(NODE) ] = { 641 [ C(OP_READ) ] = { 642 [ C(RESULT_ACCESS) ] = 0x10c000001, 643 [ C(RESULT_MISS) ] = 0x3fb3000001, 644 }, 645 }, 646 }; 647 648 /* 649 * Notes on the events: 650 * - data reads do not include code reads (comparable to earlier tables) 651 * - data counts include speculative execution (except L1 write, dtlb, bpu) 652 * - remote node access includes remote memory, remote cache, remote mmio. 653 * - prefetches are not included in the counts. 654 * - icache miss does not include decoded icache 655 */ 656 657 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 658 #define SKL_DEMAND_RFO BIT_ULL(1) 659 #define SKL_ANY_RESPONSE BIT_ULL(16) 660 #define SKL_SUPPLIER_NONE BIT_ULL(17) 661 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 662 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 663 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 664 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 665 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 666 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 667 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 668 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 669 #define SKL_SPL_HIT BIT_ULL(30) 670 #define SKL_SNOOP_NONE BIT_ULL(31) 671 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 672 #define SKL_SNOOP_MISS BIT_ULL(33) 673 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 674 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 675 #define SKL_SNOOP_HITM BIT_ULL(36) 676 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 677 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 678 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 679 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 680 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 681 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 682 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 683 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 684 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 685 SKL_SNOOP_HITM|SKL_SPL_HIT) 686 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 687 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 688 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 689 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 690 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 691 692 static __initconst const u64 skl_hw_cache_event_ids 693 [PERF_COUNT_HW_CACHE_MAX] 694 [PERF_COUNT_HW_CACHE_OP_MAX] 695 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 696 { 697 [ C(L1D ) ] = { 698 [ C(OP_READ) ] = { 699 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 700 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 701 }, 702 [ C(OP_WRITE) ] = { 703 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 704 [ C(RESULT_MISS) ] = 0x0, 705 }, 706 [ C(OP_PREFETCH) ] = { 707 [ C(RESULT_ACCESS) ] = 0x0, 708 [ C(RESULT_MISS) ] = 0x0, 709 }, 710 }, 711 [ C(L1I ) ] = { 712 [ C(OP_READ) ] = { 713 [ C(RESULT_ACCESS) ] = 0x0, 714 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 715 }, 716 [ C(OP_WRITE) ] = { 717 [ C(RESULT_ACCESS) ] = -1, 718 [ C(RESULT_MISS) ] = -1, 719 }, 720 [ C(OP_PREFETCH) ] = { 721 [ C(RESULT_ACCESS) ] = 0x0, 722 [ C(RESULT_MISS) ] = 0x0, 723 }, 724 }, 725 [ C(LL ) ] = { 726 [ C(OP_READ) ] = { 727 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 728 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 729 }, 730 [ C(OP_WRITE) ] = { 731 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 732 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 733 }, 734 [ C(OP_PREFETCH) ] = { 735 [ C(RESULT_ACCESS) ] = 0x0, 736 [ C(RESULT_MISS) ] = 0x0, 737 }, 738 }, 739 [ C(DTLB) ] = { 740 [ C(OP_READ) ] = { 741 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 742 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 743 }, 744 [ C(OP_WRITE) ] = { 745 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 746 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 747 }, 748 [ C(OP_PREFETCH) ] = { 749 [ C(RESULT_ACCESS) ] = 0x0, 750 [ C(RESULT_MISS) ] = 0x0, 751 }, 752 }, 753 [ C(ITLB) ] = { 754 [ C(OP_READ) ] = { 755 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 756 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 757 }, 758 [ C(OP_WRITE) ] = { 759 [ C(RESULT_ACCESS) ] = -1, 760 [ C(RESULT_MISS) ] = -1, 761 }, 762 [ C(OP_PREFETCH) ] = { 763 [ C(RESULT_ACCESS) ] = -1, 764 [ C(RESULT_MISS) ] = -1, 765 }, 766 }, 767 [ C(BPU ) ] = { 768 [ C(OP_READ) ] = { 769 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 770 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 771 }, 772 [ C(OP_WRITE) ] = { 773 [ C(RESULT_ACCESS) ] = -1, 774 [ C(RESULT_MISS) ] = -1, 775 }, 776 [ C(OP_PREFETCH) ] = { 777 [ C(RESULT_ACCESS) ] = -1, 778 [ C(RESULT_MISS) ] = -1, 779 }, 780 }, 781 [ C(NODE) ] = { 782 [ C(OP_READ) ] = { 783 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 784 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 785 }, 786 [ C(OP_WRITE) ] = { 787 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 788 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 789 }, 790 [ C(OP_PREFETCH) ] = { 791 [ C(RESULT_ACCESS) ] = 0x0, 792 [ C(RESULT_MISS) ] = 0x0, 793 }, 794 }, 795 }; 796 797 static __initconst const u64 skl_hw_cache_extra_regs 798 [PERF_COUNT_HW_CACHE_MAX] 799 [PERF_COUNT_HW_CACHE_OP_MAX] 800 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 801 { 802 [ C(LL ) ] = { 803 [ C(OP_READ) ] = { 804 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 805 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 806 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 807 SKL_L3_MISS|SKL_ANY_SNOOP| 808 SKL_SUPPLIER_NONE, 809 }, 810 [ C(OP_WRITE) ] = { 811 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 812 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 813 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 814 SKL_L3_MISS|SKL_ANY_SNOOP| 815 SKL_SUPPLIER_NONE, 816 }, 817 [ C(OP_PREFETCH) ] = { 818 [ C(RESULT_ACCESS) ] = 0x0, 819 [ C(RESULT_MISS) ] = 0x0, 820 }, 821 }, 822 [ C(NODE) ] = { 823 [ C(OP_READ) ] = { 824 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 825 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 826 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 827 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 828 }, 829 [ C(OP_WRITE) ] = { 830 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 831 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 832 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 833 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 834 }, 835 [ C(OP_PREFETCH) ] = { 836 [ C(RESULT_ACCESS) ] = 0x0, 837 [ C(RESULT_MISS) ] = 0x0, 838 }, 839 }, 840 }; 841 842 #define SNB_DMND_DATA_RD (1ULL << 0) 843 #define SNB_DMND_RFO (1ULL << 1) 844 #define SNB_DMND_IFETCH (1ULL << 2) 845 #define SNB_DMND_WB (1ULL << 3) 846 #define SNB_PF_DATA_RD (1ULL << 4) 847 #define SNB_PF_RFO (1ULL << 5) 848 #define SNB_PF_IFETCH (1ULL << 6) 849 #define SNB_LLC_DATA_RD (1ULL << 7) 850 #define SNB_LLC_RFO (1ULL << 8) 851 #define SNB_LLC_IFETCH (1ULL << 9) 852 #define SNB_BUS_LOCKS (1ULL << 10) 853 #define SNB_STRM_ST (1ULL << 11) 854 #define SNB_OTHER (1ULL << 15) 855 #define SNB_RESP_ANY (1ULL << 16) 856 #define SNB_NO_SUPP (1ULL << 17) 857 #define SNB_LLC_HITM (1ULL << 18) 858 #define SNB_LLC_HITE (1ULL << 19) 859 #define SNB_LLC_HITS (1ULL << 20) 860 #define SNB_LLC_HITF (1ULL << 21) 861 #define SNB_LOCAL (1ULL << 22) 862 #define SNB_REMOTE (0xffULL << 23) 863 #define SNB_SNP_NONE (1ULL << 31) 864 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 865 #define SNB_SNP_MISS (1ULL << 33) 866 #define SNB_NO_FWD (1ULL << 34) 867 #define SNB_SNP_FWD (1ULL << 35) 868 #define SNB_HITM (1ULL << 36) 869 #define SNB_NON_DRAM (1ULL << 37) 870 871 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 872 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 873 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 874 875 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 876 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 877 SNB_HITM) 878 879 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 880 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 881 882 #define SNB_L3_ACCESS SNB_RESP_ANY 883 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 884 885 static __initconst const u64 snb_hw_cache_extra_regs 886 [PERF_COUNT_HW_CACHE_MAX] 887 [PERF_COUNT_HW_CACHE_OP_MAX] 888 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 889 { 890 [ C(LL ) ] = { 891 [ C(OP_READ) ] = { 892 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 893 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 894 }, 895 [ C(OP_WRITE) ] = { 896 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 897 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 898 }, 899 [ C(OP_PREFETCH) ] = { 900 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 901 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 902 }, 903 }, 904 [ C(NODE) ] = { 905 [ C(OP_READ) ] = { 906 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 907 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 908 }, 909 [ C(OP_WRITE) ] = { 910 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 911 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 912 }, 913 [ C(OP_PREFETCH) ] = { 914 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 915 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 916 }, 917 }, 918 }; 919 920 static __initconst const u64 snb_hw_cache_event_ids 921 [PERF_COUNT_HW_CACHE_MAX] 922 [PERF_COUNT_HW_CACHE_OP_MAX] 923 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 924 { 925 [ C(L1D) ] = { 926 [ C(OP_READ) ] = { 927 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 928 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 929 }, 930 [ C(OP_WRITE) ] = { 931 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 932 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 933 }, 934 [ C(OP_PREFETCH) ] = { 935 [ C(RESULT_ACCESS) ] = 0x0, 936 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 937 }, 938 }, 939 [ C(L1I ) ] = { 940 [ C(OP_READ) ] = { 941 [ C(RESULT_ACCESS) ] = 0x0, 942 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 943 }, 944 [ C(OP_WRITE) ] = { 945 [ C(RESULT_ACCESS) ] = -1, 946 [ C(RESULT_MISS) ] = -1, 947 }, 948 [ C(OP_PREFETCH) ] = { 949 [ C(RESULT_ACCESS) ] = 0x0, 950 [ C(RESULT_MISS) ] = 0x0, 951 }, 952 }, 953 [ C(LL ) ] = { 954 [ C(OP_READ) ] = { 955 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 956 [ C(RESULT_ACCESS) ] = 0x01b7, 957 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 958 [ C(RESULT_MISS) ] = 0x01b7, 959 }, 960 [ C(OP_WRITE) ] = { 961 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 962 [ C(RESULT_ACCESS) ] = 0x01b7, 963 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 964 [ C(RESULT_MISS) ] = 0x01b7, 965 }, 966 [ C(OP_PREFETCH) ] = { 967 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 968 [ C(RESULT_ACCESS) ] = 0x01b7, 969 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 970 [ C(RESULT_MISS) ] = 0x01b7, 971 }, 972 }, 973 [ C(DTLB) ] = { 974 [ C(OP_READ) ] = { 975 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 976 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 977 }, 978 [ C(OP_WRITE) ] = { 979 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 980 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 981 }, 982 [ C(OP_PREFETCH) ] = { 983 [ C(RESULT_ACCESS) ] = 0x0, 984 [ C(RESULT_MISS) ] = 0x0, 985 }, 986 }, 987 [ C(ITLB) ] = { 988 [ C(OP_READ) ] = { 989 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 990 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 991 }, 992 [ C(OP_WRITE) ] = { 993 [ C(RESULT_ACCESS) ] = -1, 994 [ C(RESULT_MISS) ] = -1, 995 }, 996 [ C(OP_PREFETCH) ] = { 997 [ C(RESULT_ACCESS) ] = -1, 998 [ C(RESULT_MISS) ] = -1, 999 }, 1000 }, 1001 [ C(BPU ) ] = { 1002 [ C(OP_READ) ] = { 1003 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1004 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1005 }, 1006 [ C(OP_WRITE) ] = { 1007 [ C(RESULT_ACCESS) ] = -1, 1008 [ C(RESULT_MISS) ] = -1, 1009 }, 1010 [ C(OP_PREFETCH) ] = { 1011 [ C(RESULT_ACCESS) ] = -1, 1012 [ C(RESULT_MISS) ] = -1, 1013 }, 1014 }, 1015 [ C(NODE) ] = { 1016 [ C(OP_READ) ] = { 1017 [ C(RESULT_ACCESS) ] = 0x01b7, 1018 [ C(RESULT_MISS) ] = 0x01b7, 1019 }, 1020 [ C(OP_WRITE) ] = { 1021 [ C(RESULT_ACCESS) ] = 0x01b7, 1022 [ C(RESULT_MISS) ] = 0x01b7, 1023 }, 1024 [ C(OP_PREFETCH) ] = { 1025 [ C(RESULT_ACCESS) ] = 0x01b7, 1026 [ C(RESULT_MISS) ] = 0x01b7, 1027 }, 1028 }, 1029 1030 }; 1031 1032 /* 1033 * Notes on the events: 1034 * - data reads do not include code reads (comparable to earlier tables) 1035 * - data counts include speculative execution (except L1 write, dtlb, bpu) 1036 * - remote node access includes remote memory, remote cache, remote mmio. 1037 * - prefetches are not included in the counts because they are not 1038 * reliably counted. 1039 */ 1040 1041 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 1042 #define HSW_DEMAND_RFO BIT_ULL(1) 1043 #define HSW_ANY_RESPONSE BIT_ULL(16) 1044 #define HSW_SUPPLIER_NONE BIT_ULL(17) 1045 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 1046 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 1047 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 1048 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 1049 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 1050 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 1051 HSW_L3_MISS_REMOTE_HOP2P) 1052 #define HSW_SNOOP_NONE BIT_ULL(31) 1053 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 1054 #define HSW_SNOOP_MISS BIT_ULL(33) 1055 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 1056 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 1057 #define HSW_SNOOP_HITM BIT_ULL(36) 1058 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 1059 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 1060 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 1061 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 1062 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 1063 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 1064 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 1065 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 1066 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 1067 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 1068 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 1069 1070 #define BDW_L3_MISS_LOCAL BIT(26) 1071 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 1072 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 1073 HSW_L3_MISS_REMOTE_HOP2P) 1074 1075 1076 static __initconst const u64 hsw_hw_cache_event_ids 1077 [PERF_COUNT_HW_CACHE_MAX] 1078 [PERF_COUNT_HW_CACHE_OP_MAX] 1079 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1080 { 1081 [ C(L1D ) ] = { 1082 [ C(OP_READ) ] = { 1083 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1084 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 1085 }, 1086 [ C(OP_WRITE) ] = { 1087 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1088 [ C(RESULT_MISS) ] = 0x0, 1089 }, 1090 [ C(OP_PREFETCH) ] = { 1091 [ C(RESULT_ACCESS) ] = 0x0, 1092 [ C(RESULT_MISS) ] = 0x0, 1093 }, 1094 }, 1095 [ C(L1I ) ] = { 1096 [ C(OP_READ) ] = { 1097 [ C(RESULT_ACCESS) ] = 0x0, 1098 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 1099 }, 1100 [ C(OP_WRITE) ] = { 1101 [ C(RESULT_ACCESS) ] = -1, 1102 [ C(RESULT_MISS) ] = -1, 1103 }, 1104 [ C(OP_PREFETCH) ] = { 1105 [ C(RESULT_ACCESS) ] = 0x0, 1106 [ C(RESULT_MISS) ] = 0x0, 1107 }, 1108 }, 1109 [ C(LL ) ] = { 1110 [ C(OP_READ) ] = { 1111 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1112 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1113 }, 1114 [ C(OP_WRITE) ] = { 1115 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1116 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1117 }, 1118 [ C(OP_PREFETCH) ] = { 1119 [ C(RESULT_ACCESS) ] = 0x0, 1120 [ C(RESULT_MISS) ] = 0x0, 1121 }, 1122 }, 1123 [ C(DTLB) ] = { 1124 [ C(OP_READ) ] = { 1125 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1126 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1127 }, 1128 [ C(OP_WRITE) ] = { 1129 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1130 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1131 }, 1132 [ C(OP_PREFETCH) ] = { 1133 [ C(RESULT_ACCESS) ] = 0x0, 1134 [ C(RESULT_MISS) ] = 0x0, 1135 }, 1136 }, 1137 [ C(ITLB) ] = { 1138 [ C(OP_READ) ] = { 1139 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1140 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1141 }, 1142 [ C(OP_WRITE) ] = { 1143 [ C(RESULT_ACCESS) ] = -1, 1144 [ C(RESULT_MISS) ] = -1, 1145 }, 1146 [ C(OP_PREFETCH) ] = { 1147 [ C(RESULT_ACCESS) ] = -1, 1148 [ C(RESULT_MISS) ] = -1, 1149 }, 1150 }, 1151 [ C(BPU ) ] = { 1152 [ C(OP_READ) ] = { 1153 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1154 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1155 }, 1156 [ C(OP_WRITE) ] = { 1157 [ C(RESULT_ACCESS) ] = -1, 1158 [ C(RESULT_MISS) ] = -1, 1159 }, 1160 [ C(OP_PREFETCH) ] = { 1161 [ C(RESULT_ACCESS) ] = -1, 1162 [ C(RESULT_MISS) ] = -1, 1163 }, 1164 }, 1165 [ C(NODE) ] = { 1166 [ C(OP_READ) ] = { 1167 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1168 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1169 }, 1170 [ C(OP_WRITE) ] = { 1171 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1172 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1173 }, 1174 [ C(OP_PREFETCH) ] = { 1175 [ C(RESULT_ACCESS) ] = 0x0, 1176 [ C(RESULT_MISS) ] = 0x0, 1177 }, 1178 }, 1179 }; 1180 1181 static __initconst const u64 hsw_hw_cache_extra_regs 1182 [PERF_COUNT_HW_CACHE_MAX] 1183 [PERF_COUNT_HW_CACHE_OP_MAX] 1184 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1185 { 1186 [ C(LL ) ] = { 1187 [ C(OP_READ) ] = { 1188 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1189 HSW_LLC_ACCESS, 1190 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1191 HSW_L3_MISS|HSW_ANY_SNOOP, 1192 }, 1193 [ C(OP_WRITE) ] = { 1194 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1195 HSW_LLC_ACCESS, 1196 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1197 HSW_L3_MISS|HSW_ANY_SNOOP, 1198 }, 1199 [ C(OP_PREFETCH) ] = { 1200 [ C(RESULT_ACCESS) ] = 0x0, 1201 [ C(RESULT_MISS) ] = 0x0, 1202 }, 1203 }, 1204 [ C(NODE) ] = { 1205 [ C(OP_READ) ] = { 1206 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1207 HSW_L3_MISS_LOCAL_DRAM| 1208 HSW_SNOOP_DRAM, 1209 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1210 HSW_L3_MISS_REMOTE| 1211 HSW_SNOOP_DRAM, 1212 }, 1213 [ C(OP_WRITE) ] = { 1214 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1215 HSW_L3_MISS_LOCAL_DRAM| 1216 HSW_SNOOP_DRAM, 1217 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1218 HSW_L3_MISS_REMOTE| 1219 HSW_SNOOP_DRAM, 1220 }, 1221 [ C(OP_PREFETCH) ] = { 1222 [ C(RESULT_ACCESS) ] = 0x0, 1223 [ C(RESULT_MISS) ] = 0x0, 1224 }, 1225 }, 1226 }; 1227 1228 static __initconst const u64 westmere_hw_cache_event_ids 1229 [PERF_COUNT_HW_CACHE_MAX] 1230 [PERF_COUNT_HW_CACHE_OP_MAX] 1231 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1232 { 1233 [ C(L1D) ] = { 1234 [ C(OP_READ) ] = { 1235 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1236 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1237 }, 1238 [ C(OP_WRITE) ] = { 1239 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1240 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1241 }, 1242 [ C(OP_PREFETCH) ] = { 1243 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1244 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1245 }, 1246 }, 1247 [ C(L1I ) ] = { 1248 [ C(OP_READ) ] = { 1249 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1250 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1251 }, 1252 [ C(OP_WRITE) ] = { 1253 [ C(RESULT_ACCESS) ] = -1, 1254 [ C(RESULT_MISS) ] = -1, 1255 }, 1256 [ C(OP_PREFETCH) ] = { 1257 [ C(RESULT_ACCESS) ] = 0x0, 1258 [ C(RESULT_MISS) ] = 0x0, 1259 }, 1260 }, 1261 [ C(LL ) ] = { 1262 [ C(OP_READ) ] = { 1263 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1264 [ C(RESULT_ACCESS) ] = 0x01b7, 1265 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1266 [ C(RESULT_MISS) ] = 0x01b7, 1267 }, 1268 /* 1269 * Use RFO, not WRITEBACK, because a write miss would typically occur 1270 * on RFO. 1271 */ 1272 [ C(OP_WRITE) ] = { 1273 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1274 [ C(RESULT_ACCESS) ] = 0x01b7, 1275 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1276 [ C(RESULT_MISS) ] = 0x01b7, 1277 }, 1278 [ C(OP_PREFETCH) ] = { 1279 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1280 [ C(RESULT_ACCESS) ] = 0x01b7, 1281 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1282 [ C(RESULT_MISS) ] = 0x01b7, 1283 }, 1284 }, 1285 [ C(DTLB) ] = { 1286 [ C(OP_READ) ] = { 1287 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1288 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1289 }, 1290 [ C(OP_WRITE) ] = { 1291 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1292 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1293 }, 1294 [ C(OP_PREFETCH) ] = { 1295 [ C(RESULT_ACCESS) ] = 0x0, 1296 [ C(RESULT_MISS) ] = 0x0, 1297 }, 1298 }, 1299 [ C(ITLB) ] = { 1300 [ C(OP_READ) ] = { 1301 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1302 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1303 }, 1304 [ C(OP_WRITE) ] = { 1305 [ C(RESULT_ACCESS) ] = -1, 1306 [ C(RESULT_MISS) ] = -1, 1307 }, 1308 [ C(OP_PREFETCH) ] = { 1309 [ C(RESULT_ACCESS) ] = -1, 1310 [ C(RESULT_MISS) ] = -1, 1311 }, 1312 }, 1313 [ C(BPU ) ] = { 1314 [ C(OP_READ) ] = { 1315 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1316 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1317 }, 1318 [ C(OP_WRITE) ] = { 1319 [ C(RESULT_ACCESS) ] = -1, 1320 [ C(RESULT_MISS) ] = -1, 1321 }, 1322 [ C(OP_PREFETCH) ] = { 1323 [ C(RESULT_ACCESS) ] = -1, 1324 [ C(RESULT_MISS) ] = -1, 1325 }, 1326 }, 1327 [ C(NODE) ] = { 1328 [ C(OP_READ) ] = { 1329 [ C(RESULT_ACCESS) ] = 0x01b7, 1330 [ C(RESULT_MISS) ] = 0x01b7, 1331 }, 1332 [ C(OP_WRITE) ] = { 1333 [ C(RESULT_ACCESS) ] = 0x01b7, 1334 [ C(RESULT_MISS) ] = 0x01b7, 1335 }, 1336 [ C(OP_PREFETCH) ] = { 1337 [ C(RESULT_ACCESS) ] = 0x01b7, 1338 [ C(RESULT_MISS) ] = 0x01b7, 1339 }, 1340 }, 1341 }; 1342 1343 /* 1344 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1345 * See IA32 SDM Vol 3B 30.6.1.3 1346 */ 1347 1348 #define NHM_DMND_DATA_RD (1 << 0) 1349 #define NHM_DMND_RFO (1 << 1) 1350 #define NHM_DMND_IFETCH (1 << 2) 1351 #define NHM_DMND_WB (1 << 3) 1352 #define NHM_PF_DATA_RD (1 << 4) 1353 #define NHM_PF_DATA_RFO (1 << 5) 1354 #define NHM_PF_IFETCH (1 << 6) 1355 #define NHM_OFFCORE_OTHER (1 << 7) 1356 #define NHM_UNCORE_HIT (1 << 8) 1357 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1358 #define NHM_OTHER_CORE_HITM (1 << 10) 1359 /* reserved */ 1360 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1361 #define NHM_REMOTE_DRAM (1 << 13) 1362 #define NHM_LOCAL_DRAM (1 << 14) 1363 #define NHM_NON_DRAM (1 << 15) 1364 1365 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1366 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1367 1368 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1369 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1370 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1371 1372 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1373 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1374 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1375 1376 static __initconst const u64 nehalem_hw_cache_extra_regs 1377 [PERF_COUNT_HW_CACHE_MAX] 1378 [PERF_COUNT_HW_CACHE_OP_MAX] 1379 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1380 { 1381 [ C(LL ) ] = { 1382 [ C(OP_READ) ] = { 1383 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1384 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1385 }, 1386 [ C(OP_WRITE) ] = { 1387 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1388 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1389 }, 1390 [ C(OP_PREFETCH) ] = { 1391 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1392 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1393 }, 1394 }, 1395 [ C(NODE) ] = { 1396 [ C(OP_READ) ] = { 1397 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1398 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1399 }, 1400 [ C(OP_WRITE) ] = { 1401 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1402 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1403 }, 1404 [ C(OP_PREFETCH) ] = { 1405 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1406 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1407 }, 1408 }, 1409 }; 1410 1411 static __initconst const u64 nehalem_hw_cache_event_ids 1412 [PERF_COUNT_HW_CACHE_MAX] 1413 [PERF_COUNT_HW_CACHE_OP_MAX] 1414 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1415 { 1416 [ C(L1D) ] = { 1417 [ C(OP_READ) ] = { 1418 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1419 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1420 }, 1421 [ C(OP_WRITE) ] = { 1422 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1423 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1424 }, 1425 [ C(OP_PREFETCH) ] = { 1426 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1427 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1428 }, 1429 }, 1430 [ C(L1I ) ] = { 1431 [ C(OP_READ) ] = { 1432 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1433 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1434 }, 1435 [ C(OP_WRITE) ] = { 1436 [ C(RESULT_ACCESS) ] = -1, 1437 [ C(RESULT_MISS) ] = -1, 1438 }, 1439 [ C(OP_PREFETCH) ] = { 1440 [ C(RESULT_ACCESS) ] = 0x0, 1441 [ C(RESULT_MISS) ] = 0x0, 1442 }, 1443 }, 1444 [ C(LL ) ] = { 1445 [ C(OP_READ) ] = { 1446 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1447 [ C(RESULT_ACCESS) ] = 0x01b7, 1448 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1449 [ C(RESULT_MISS) ] = 0x01b7, 1450 }, 1451 /* 1452 * Use RFO, not WRITEBACK, because a write miss would typically occur 1453 * on RFO. 1454 */ 1455 [ C(OP_WRITE) ] = { 1456 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1457 [ C(RESULT_ACCESS) ] = 0x01b7, 1458 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1459 [ C(RESULT_MISS) ] = 0x01b7, 1460 }, 1461 [ C(OP_PREFETCH) ] = { 1462 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1463 [ C(RESULT_ACCESS) ] = 0x01b7, 1464 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1465 [ C(RESULT_MISS) ] = 0x01b7, 1466 }, 1467 }, 1468 [ C(DTLB) ] = { 1469 [ C(OP_READ) ] = { 1470 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1471 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1472 }, 1473 [ C(OP_WRITE) ] = { 1474 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1475 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1476 }, 1477 [ C(OP_PREFETCH) ] = { 1478 [ C(RESULT_ACCESS) ] = 0x0, 1479 [ C(RESULT_MISS) ] = 0x0, 1480 }, 1481 }, 1482 [ C(ITLB) ] = { 1483 [ C(OP_READ) ] = { 1484 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1485 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1486 }, 1487 [ C(OP_WRITE) ] = { 1488 [ C(RESULT_ACCESS) ] = -1, 1489 [ C(RESULT_MISS) ] = -1, 1490 }, 1491 [ C(OP_PREFETCH) ] = { 1492 [ C(RESULT_ACCESS) ] = -1, 1493 [ C(RESULT_MISS) ] = -1, 1494 }, 1495 }, 1496 [ C(BPU ) ] = { 1497 [ C(OP_READ) ] = { 1498 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1499 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1500 }, 1501 [ C(OP_WRITE) ] = { 1502 [ C(RESULT_ACCESS) ] = -1, 1503 [ C(RESULT_MISS) ] = -1, 1504 }, 1505 [ C(OP_PREFETCH) ] = { 1506 [ C(RESULT_ACCESS) ] = -1, 1507 [ C(RESULT_MISS) ] = -1, 1508 }, 1509 }, 1510 [ C(NODE) ] = { 1511 [ C(OP_READ) ] = { 1512 [ C(RESULT_ACCESS) ] = 0x01b7, 1513 [ C(RESULT_MISS) ] = 0x01b7, 1514 }, 1515 [ C(OP_WRITE) ] = { 1516 [ C(RESULT_ACCESS) ] = 0x01b7, 1517 [ C(RESULT_MISS) ] = 0x01b7, 1518 }, 1519 [ C(OP_PREFETCH) ] = { 1520 [ C(RESULT_ACCESS) ] = 0x01b7, 1521 [ C(RESULT_MISS) ] = 0x01b7, 1522 }, 1523 }, 1524 }; 1525 1526 static __initconst const u64 core2_hw_cache_event_ids 1527 [PERF_COUNT_HW_CACHE_MAX] 1528 [PERF_COUNT_HW_CACHE_OP_MAX] 1529 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1530 { 1531 [ C(L1D) ] = { 1532 [ C(OP_READ) ] = { 1533 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1534 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1535 }, 1536 [ C(OP_WRITE) ] = { 1537 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1538 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1539 }, 1540 [ C(OP_PREFETCH) ] = { 1541 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1542 [ C(RESULT_MISS) ] = 0, 1543 }, 1544 }, 1545 [ C(L1I ) ] = { 1546 [ C(OP_READ) ] = { 1547 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1548 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1549 }, 1550 [ C(OP_WRITE) ] = { 1551 [ C(RESULT_ACCESS) ] = -1, 1552 [ C(RESULT_MISS) ] = -1, 1553 }, 1554 [ C(OP_PREFETCH) ] = { 1555 [ C(RESULT_ACCESS) ] = 0, 1556 [ C(RESULT_MISS) ] = 0, 1557 }, 1558 }, 1559 [ C(LL ) ] = { 1560 [ C(OP_READ) ] = { 1561 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1562 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1563 }, 1564 [ C(OP_WRITE) ] = { 1565 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1566 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1567 }, 1568 [ C(OP_PREFETCH) ] = { 1569 [ C(RESULT_ACCESS) ] = 0, 1570 [ C(RESULT_MISS) ] = 0, 1571 }, 1572 }, 1573 [ C(DTLB) ] = { 1574 [ C(OP_READ) ] = { 1575 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1576 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1577 }, 1578 [ C(OP_WRITE) ] = { 1579 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1580 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1581 }, 1582 [ C(OP_PREFETCH) ] = { 1583 [ C(RESULT_ACCESS) ] = 0, 1584 [ C(RESULT_MISS) ] = 0, 1585 }, 1586 }, 1587 [ C(ITLB) ] = { 1588 [ C(OP_READ) ] = { 1589 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1590 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1591 }, 1592 [ C(OP_WRITE) ] = { 1593 [ C(RESULT_ACCESS) ] = -1, 1594 [ C(RESULT_MISS) ] = -1, 1595 }, 1596 [ C(OP_PREFETCH) ] = { 1597 [ C(RESULT_ACCESS) ] = -1, 1598 [ C(RESULT_MISS) ] = -1, 1599 }, 1600 }, 1601 [ C(BPU ) ] = { 1602 [ C(OP_READ) ] = { 1603 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1604 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1605 }, 1606 [ C(OP_WRITE) ] = { 1607 [ C(RESULT_ACCESS) ] = -1, 1608 [ C(RESULT_MISS) ] = -1, 1609 }, 1610 [ C(OP_PREFETCH) ] = { 1611 [ C(RESULT_ACCESS) ] = -1, 1612 [ C(RESULT_MISS) ] = -1, 1613 }, 1614 }, 1615 }; 1616 1617 static __initconst const u64 atom_hw_cache_event_ids 1618 [PERF_COUNT_HW_CACHE_MAX] 1619 [PERF_COUNT_HW_CACHE_OP_MAX] 1620 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1621 { 1622 [ C(L1D) ] = { 1623 [ C(OP_READ) ] = { 1624 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1625 [ C(RESULT_MISS) ] = 0, 1626 }, 1627 [ C(OP_WRITE) ] = { 1628 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1629 [ C(RESULT_MISS) ] = 0, 1630 }, 1631 [ C(OP_PREFETCH) ] = { 1632 [ C(RESULT_ACCESS) ] = 0x0, 1633 [ C(RESULT_MISS) ] = 0, 1634 }, 1635 }, 1636 [ C(L1I ) ] = { 1637 [ C(OP_READ) ] = { 1638 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1639 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1640 }, 1641 [ C(OP_WRITE) ] = { 1642 [ C(RESULT_ACCESS) ] = -1, 1643 [ C(RESULT_MISS) ] = -1, 1644 }, 1645 [ C(OP_PREFETCH) ] = { 1646 [ C(RESULT_ACCESS) ] = 0, 1647 [ C(RESULT_MISS) ] = 0, 1648 }, 1649 }, 1650 [ C(LL ) ] = { 1651 [ C(OP_READ) ] = { 1652 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1653 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1654 }, 1655 [ C(OP_WRITE) ] = { 1656 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1657 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1658 }, 1659 [ C(OP_PREFETCH) ] = { 1660 [ C(RESULT_ACCESS) ] = 0, 1661 [ C(RESULT_MISS) ] = 0, 1662 }, 1663 }, 1664 [ C(DTLB) ] = { 1665 [ C(OP_READ) ] = { 1666 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1667 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1668 }, 1669 [ C(OP_WRITE) ] = { 1670 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1671 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1672 }, 1673 [ C(OP_PREFETCH) ] = { 1674 [ C(RESULT_ACCESS) ] = 0, 1675 [ C(RESULT_MISS) ] = 0, 1676 }, 1677 }, 1678 [ C(ITLB) ] = { 1679 [ C(OP_READ) ] = { 1680 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1681 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1682 }, 1683 [ C(OP_WRITE) ] = { 1684 [ C(RESULT_ACCESS) ] = -1, 1685 [ C(RESULT_MISS) ] = -1, 1686 }, 1687 [ C(OP_PREFETCH) ] = { 1688 [ C(RESULT_ACCESS) ] = -1, 1689 [ C(RESULT_MISS) ] = -1, 1690 }, 1691 }, 1692 [ C(BPU ) ] = { 1693 [ C(OP_READ) ] = { 1694 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1695 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1696 }, 1697 [ C(OP_WRITE) ] = { 1698 [ C(RESULT_ACCESS) ] = -1, 1699 [ C(RESULT_MISS) ] = -1, 1700 }, 1701 [ C(OP_PREFETCH) ] = { 1702 [ C(RESULT_ACCESS) ] = -1, 1703 [ C(RESULT_MISS) ] = -1, 1704 }, 1705 }, 1706 }; 1707 1708 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1709 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1710 /* no_alloc_cycles.not_delivered */ 1711 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1712 "event=0xca,umask=0x50"); 1713 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1714 /* uops_retired.all */ 1715 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1716 "event=0xc2,umask=0x10"); 1717 /* uops_retired.all */ 1718 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1719 "event=0xc2,umask=0x10"); 1720 1721 static struct attribute *slm_events_attrs[] = { 1722 EVENT_PTR(td_total_slots_slm), 1723 EVENT_PTR(td_total_slots_scale_slm), 1724 EVENT_PTR(td_fetch_bubbles_slm), 1725 EVENT_PTR(td_fetch_bubbles_scale_slm), 1726 EVENT_PTR(td_slots_issued_slm), 1727 EVENT_PTR(td_slots_retired_slm), 1728 NULL 1729 }; 1730 1731 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1732 { 1733 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1734 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1735 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1736 EVENT_EXTRA_END 1737 }; 1738 1739 #define SLM_DMND_READ SNB_DMND_DATA_RD 1740 #define SLM_DMND_WRITE SNB_DMND_RFO 1741 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1742 1743 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1744 #define SLM_LLC_ACCESS SNB_RESP_ANY 1745 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1746 1747 static __initconst const u64 slm_hw_cache_extra_regs 1748 [PERF_COUNT_HW_CACHE_MAX] 1749 [PERF_COUNT_HW_CACHE_OP_MAX] 1750 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1751 { 1752 [ C(LL ) ] = { 1753 [ C(OP_READ) ] = { 1754 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1755 [ C(RESULT_MISS) ] = 0, 1756 }, 1757 [ C(OP_WRITE) ] = { 1758 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1759 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1760 }, 1761 [ C(OP_PREFETCH) ] = { 1762 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1763 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1764 }, 1765 }, 1766 }; 1767 1768 static __initconst const u64 slm_hw_cache_event_ids 1769 [PERF_COUNT_HW_CACHE_MAX] 1770 [PERF_COUNT_HW_CACHE_OP_MAX] 1771 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1772 { 1773 [ C(L1D) ] = { 1774 [ C(OP_READ) ] = { 1775 [ C(RESULT_ACCESS) ] = 0, 1776 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1777 }, 1778 [ C(OP_WRITE) ] = { 1779 [ C(RESULT_ACCESS) ] = 0, 1780 [ C(RESULT_MISS) ] = 0, 1781 }, 1782 [ C(OP_PREFETCH) ] = { 1783 [ C(RESULT_ACCESS) ] = 0, 1784 [ C(RESULT_MISS) ] = 0, 1785 }, 1786 }, 1787 [ C(L1I ) ] = { 1788 [ C(OP_READ) ] = { 1789 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1790 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1791 }, 1792 [ C(OP_WRITE) ] = { 1793 [ C(RESULT_ACCESS) ] = -1, 1794 [ C(RESULT_MISS) ] = -1, 1795 }, 1796 [ C(OP_PREFETCH) ] = { 1797 [ C(RESULT_ACCESS) ] = 0, 1798 [ C(RESULT_MISS) ] = 0, 1799 }, 1800 }, 1801 [ C(LL ) ] = { 1802 [ C(OP_READ) ] = { 1803 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1804 [ C(RESULT_ACCESS) ] = 0x01b7, 1805 [ C(RESULT_MISS) ] = 0, 1806 }, 1807 [ C(OP_WRITE) ] = { 1808 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1809 [ C(RESULT_ACCESS) ] = 0x01b7, 1810 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1811 [ C(RESULT_MISS) ] = 0x01b7, 1812 }, 1813 [ C(OP_PREFETCH) ] = { 1814 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1815 [ C(RESULT_ACCESS) ] = 0x01b7, 1816 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1817 [ C(RESULT_MISS) ] = 0x01b7, 1818 }, 1819 }, 1820 [ C(DTLB) ] = { 1821 [ C(OP_READ) ] = { 1822 [ C(RESULT_ACCESS) ] = 0, 1823 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1824 }, 1825 [ C(OP_WRITE) ] = { 1826 [ C(RESULT_ACCESS) ] = 0, 1827 [ C(RESULT_MISS) ] = 0, 1828 }, 1829 [ C(OP_PREFETCH) ] = { 1830 [ C(RESULT_ACCESS) ] = 0, 1831 [ C(RESULT_MISS) ] = 0, 1832 }, 1833 }, 1834 [ C(ITLB) ] = { 1835 [ C(OP_READ) ] = { 1836 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1837 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1838 }, 1839 [ C(OP_WRITE) ] = { 1840 [ C(RESULT_ACCESS) ] = -1, 1841 [ C(RESULT_MISS) ] = -1, 1842 }, 1843 [ C(OP_PREFETCH) ] = { 1844 [ C(RESULT_ACCESS) ] = -1, 1845 [ C(RESULT_MISS) ] = -1, 1846 }, 1847 }, 1848 [ C(BPU ) ] = { 1849 [ C(OP_READ) ] = { 1850 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1851 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1852 }, 1853 [ C(OP_WRITE) ] = { 1854 [ C(RESULT_ACCESS) ] = -1, 1855 [ C(RESULT_MISS) ] = -1, 1856 }, 1857 [ C(OP_PREFETCH) ] = { 1858 [ C(RESULT_ACCESS) ] = -1, 1859 [ C(RESULT_MISS) ] = -1, 1860 }, 1861 }, 1862 }; 1863 1864 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1865 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1866 /* UOPS_NOT_DELIVERED.ANY */ 1867 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1868 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1869 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1870 /* UOPS_RETIRED.ANY */ 1871 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1872 /* UOPS_ISSUED.ANY */ 1873 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1874 1875 static struct attribute *glm_events_attrs[] = { 1876 EVENT_PTR(td_total_slots_glm), 1877 EVENT_PTR(td_total_slots_scale_glm), 1878 EVENT_PTR(td_fetch_bubbles_glm), 1879 EVENT_PTR(td_recovery_bubbles_glm), 1880 EVENT_PTR(td_slots_issued_glm), 1881 EVENT_PTR(td_slots_retired_glm), 1882 NULL 1883 }; 1884 1885 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1886 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1887 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1888 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1889 EVENT_EXTRA_END 1890 }; 1891 1892 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 1893 #define GLM_DEMAND_RFO BIT_ULL(1) 1894 #define GLM_ANY_RESPONSE BIT_ULL(16) 1895 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1896 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1897 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1898 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1899 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1900 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1901 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1902 1903 static __initconst const u64 glm_hw_cache_event_ids 1904 [PERF_COUNT_HW_CACHE_MAX] 1905 [PERF_COUNT_HW_CACHE_OP_MAX] 1906 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1907 [C(L1D)] = { 1908 [C(OP_READ)] = { 1909 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1910 [C(RESULT_MISS)] = 0x0, 1911 }, 1912 [C(OP_WRITE)] = { 1913 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1914 [C(RESULT_MISS)] = 0x0, 1915 }, 1916 [C(OP_PREFETCH)] = { 1917 [C(RESULT_ACCESS)] = 0x0, 1918 [C(RESULT_MISS)] = 0x0, 1919 }, 1920 }, 1921 [C(L1I)] = { 1922 [C(OP_READ)] = { 1923 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1924 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1925 }, 1926 [C(OP_WRITE)] = { 1927 [C(RESULT_ACCESS)] = -1, 1928 [C(RESULT_MISS)] = -1, 1929 }, 1930 [C(OP_PREFETCH)] = { 1931 [C(RESULT_ACCESS)] = 0x0, 1932 [C(RESULT_MISS)] = 0x0, 1933 }, 1934 }, 1935 [C(LL)] = { 1936 [C(OP_READ)] = { 1937 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1938 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1939 }, 1940 [C(OP_WRITE)] = { 1941 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1942 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1943 }, 1944 [C(OP_PREFETCH)] = { 1945 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1946 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1947 }, 1948 }, 1949 [C(DTLB)] = { 1950 [C(OP_READ)] = { 1951 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1952 [C(RESULT_MISS)] = 0x0, 1953 }, 1954 [C(OP_WRITE)] = { 1955 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1956 [C(RESULT_MISS)] = 0x0, 1957 }, 1958 [C(OP_PREFETCH)] = { 1959 [C(RESULT_ACCESS)] = 0x0, 1960 [C(RESULT_MISS)] = 0x0, 1961 }, 1962 }, 1963 [C(ITLB)] = { 1964 [C(OP_READ)] = { 1965 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1966 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1967 }, 1968 [C(OP_WRITE)] = { 1969 [C(RESULT_ACCESS)] = -1, 1970 [C(RESULT_MISS)] = -1, 1971 }, 1972 [C(OP_PREFETCH)] = { 1973 [C(RESULT_ACCESS)] = -1, 1974 [C(RESULT_MISS)] = -1, 1975 }, 1976 }, 1977 [C(BPU)] = { 1978 [C(OP_READ)] = { 1979 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1980 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1981 }, 1982 [C(OP_WRITE)] = { 1983 [C(RESULT_ACCESS)] = -1, 1984 [C(RESULT_MISS)] = -1, 1985 }, 1986 [C(OP_PREFETCH)] = { 1987 [C(RESULT_ACCESS)] = -1, 1988 [C(RESULT_MISS)] = -1, 1989 }, 1990 }, 1991 }; 1992 1993 static __initconst const u64 glm_hw_cache_extra_regs 1994 [PERF_COUNT_HW_CACHE_MAX] 1995 [PERF_COUNT_HW_CACHE_OP_MAX] 1996 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1997 [C(LL)] = { 1998 [C(OP_READ)] = { 1999 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2000 GLM_LLC_ACCESS, 2001 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2002 GLM_LLC_MISS, 2003 }, 2004 [C(OP_WRITE)] = { 2005 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2006 GLM_LLC_ACCESS, 2007 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2008 GLM_LLC_MISS, 2009 }, 2010 [C(OP_PREFETCH)] = { 2011 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 2012 GLM_LLC_ACCESS, 2013 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 2014 GLM_LLC_MISS, 2015 }, 2016 }, 2017 }; 2018 2019 static __initconst const u64 glp_hw_cache_event_ids 2020 [PERF_COUNT_HW_CACHE_MAX] 2021 [PERF_COUNT_HW_CACHE_OP_MAX] 2022 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2023 [C(L1D)] = { 2024 [C(OP_READ)] = { 2025 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2026 [C(RESULT_MISS)] = 0x0, 2027 }, 2028 [C(OP_WRITE)] = { 2029 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2030 [C(RESULT_MISS)] = 0x0, 2031 }, 2032 [C(OP_PREFETCH)] = { 2033 [C(RESULT_ACCESS)] = 0x0, 2034 [C(RESULT_MISS)] = 0x0, 2035 }, 2036 }, 2037 [C(L1I)] = { 2038 [C(OP_READ)] = { 2039 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 2040 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 2041 }, 2042 [C(OP_WRITE)] = { 2043 [C(RESULT_ACCESS)] = -1, 2044 [C(RESULT_MISS)] = -1, 2045 }, 2046 [C(OP_PREFETCH)] = { 2047 [C(RESULT_ACCESS)] = 0x0, 2048 [C(RESULT_MISS)] = 0x0, 2049 }, 2050 }, 2051 [C(LL)] = { 2052 [C(OP_READ)] = { 2053 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2054 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2055 }, 2056 [C(OP_WRITE)] = { 2057 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2058 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2059 }, 2060 [C(OP_PREFETCH)] = { 2061 [C(RESULT_ACCESS)] = 0x0, 2062 [C(RESULT_MISS)] = 0x0, 2063 }, 2064 }, 2065 [C(DTLB)] = { 2066 [C(OP_READ)] = { 2067 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2068 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 2069 }, 2070 [C(OP_WRITE)] = { 2071 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2072 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 2073 }, 2074 [C(OP_PREFETCH)] = { 2075 [C(RESULT_ACCESS)] = 0x0, 2076 [C(RESULT_MISS)] = 0x0, 2077 }, 2078 }, 2079 [C(ITLB)] = { 2080 [C(OP_READ)] = { 2081 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 2082 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 2083 }, 2084 [C(OP_WRITE)] = { 2085 [C(RESULT_ACCESS)] = -1, 2086 [C(RESULT_MISS)] = -1, 2087 }, 2088 [C(OP_PREFETCH)] = { 2089 [C(RESULT_ACCESS)] = -1, 2090 [C(RESULT_MISS)] = -1, 2091 }, 2092 }, 2093 [C(BPU)] = { 2094 [C(OP_READ)] = { 2095 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 2096 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 2097 }, 2098 [C(OP_WRITE)] = { 2099 [C(RESULT_ACCESS)] = -1, 2100 [C(RESULT_MISS)] = -1, 2101 }, 2102 [C(OP_PREFETCH)] = { 2103 [C(RESULT_ACCESS)] = -1, 2104 [C(RESULT_MISS)] = -1, 2105 }, 2106 }, 2107 }; 2108 2109 static __initconst const u64 glp_hw_cache_extra_regs 2110 [PERF_COUNT_HW_CACHE_MAX] 2111 [PERF_COUNT_HW_CACHE_OP_MAX] 2112 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2113 [C(LL)] = { 2114 [C(OP_READ)] = { 2115 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2116 GLM_LLC_ACCESS, 2117 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2118 GLM_LLC_MISS, 2119 }, 2120 [C(OP_WRITE)] = { 2121 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2122 GLM_LLC_ACCESS, 2123 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2124 GLM_LLC_MISS, 2125 }, 2126 [C(OP_PREFETCH)] = { 2127 [C(RESULT_ACCESS)] = 0x0, 2128 [C(RESULT_MISS)] = 0x0, 2129 }, 2130 }, 2131 }; 2132 2133 #define TNT_LOCAL_DRAM BIT_ULL(26) 2134 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 2135 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 2136 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 2137 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 2138 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 2139 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 2140 2141 static __initconst const u64 tnt_hw_cache_extra_regs 2142 [PERF_COUNT_HW_CACHE_MAX] 2143 [PERF_COUNT_HW_CACHE_OP_MAX] 2144 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2145 [C(LL)] = { 2146 [C(OP_READ)] = { 2147 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 2148 TNT_LLC_ACCESS, 2149 [C(RESULT_MISS)] = TNT_DEMAND_READ| 2150 TNT_LLC_MISS, 2151 }, 2152 [C(OP_WRITE)] = { 2153 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 2154 TNT_LLC_ACCESS, 2155 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 2156 TNT_LLC_MISS, 2157 }, 2158 [C(OP_PREFETCH)] = { 2159 [C(RESULT_ACCESS)] = 0x0, 2160 [C(RESULT_MISS)] = 0x0, 2161 }, 2162 }, 2163 }; 2164 2165 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2166 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2167 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2168 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2169 2170 static struct attribute *tnt_events_attrs[] = { 2171 EVENT_PTR(td_fe_bound_tnt), 2172 EVENT_PTR(td_retiring_tnt), 2173 EVENT_PTR(td_bad_spec_tnt), 2174 EVENT_PTR(td_be_bound_tnt), 2175 NULL, 2176 }; 2177 2178 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 2179 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2180 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 2181 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 2182 EVENT_EXTRA_END 2183 }; 2184 2185 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3"); 2186 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6"); 2187 2188 static struct attribute *grt_mem_attrs[] = { 2189 EVENT_PTR(mem_ld_grt), 2190 EVENT_PTR(mem_st_grt), 2191 NULL 2192 }; 2193 2194 static struct extra_reg intel_grt_extra_regs[] __read_mostly = { 2195 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2196 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 2197 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 2198 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2199 EVENT_EXTRA_END 2200 }; 2201 2202 EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0"); 2203 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0"); 2204 2205 static struct attribute *cmt_events_attrs[] = { 2206 EVENT_PTR(td_fe_bound_tnt), 2207 EVENT_PTR(td_retiring_cmt), 2208 EVENT_PTR(td_bad_spec_cmt), 2209 EVENT_PTR(td_be_bound_tnt), 2210 NULL 2211 }; 2212 2213 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = { 2214 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2215 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0), 2216 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1), 2217 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2218 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0), 2219 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1), 2220 EVENT_EXTRA_END 2221 }; 2222 2223 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2224 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2225 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 2226 #define KNL_MCDRAM_FAR BIT_ULL(22) 2227 #define KNL_DDR_LOCAL BIT_ULL(23) 2228 #define KNL_DDR_FAR BIT_ULL(24) 2229 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2230 KNL_DDR_LOCAL | KNL_DDR_FAR) 2231 #define KNL_L2_READ SLM_DMND_READ 2232 #define KNL_L2_WRITE SLM_DMND_WRITE 2233 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2234 #define KNL_L2_ACCESS SLM_LLC_ACCESS 2235 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2236 KNL_DRAM_ANY | SNB_SNP_ANY | \ 2237 SNB_NON_DRAM) 2238 2239 static __initconst const u64 knl_hw_cache_extra_regs 2240 [PERF_COUNT_HW_CACHE_MAX] 2241 [PERF_COUNT_HW_CACHE_OP_MAX] 2242 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2243 [C(LL)] = { 2244 [C(OP_READ)] = { 2245 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2246 [C(RESULT_MISS)] = 0, 2247 }, 2248 [C(OP_WRITE)] = { 2249 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2250 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2251 }, 2252 [C(OP_PREFETCH)] = { 2253 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2254 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2255 }, 2256 }, 2257 }; 2258 2259 /* 2260 * Used from PMIs where the LBRs are already disabled. 2261 * 2262 * This function could be called consecutively. It is required to remain in 2263 * disabled state if called consecutively. 2264 * 2265 * During consecutive calls, the same disable value will be written to related 2266 * registers, so the PMU state remains unchanged. 2267 * 2268 * intel_bts events don't coexist with intel PMU's BTS events because of 2269 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2270 * disabled around intel PMU's event batching etc, only inside the PMI handler. 2271 * 2272 * Avoid PEBS_ENABLE MSR access in PMIs. 2273 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 2274 * It doesn't matter if the PEBS is enabled or not. 2275 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 2276 * access PEBS_ENABLE MSR in disable_all()/enable_all(). 2277 * However, there are some cases which may change PEBS status, e.g. PMI 2278 * throttle. The PEBS_ENABLE should be updated where the status changes. 2279 */ 2280 static __always_inline void __intel_pmu_disable_all(bool bts) 2281 { 2282 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2283 2284 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2285 2286 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2287 intel_pmu_disable_bts(); 2288 } 2289 2290 static __always_inline void intel_pmu_disable_all(void) 2291 { 2292 __intel_pmu_disable_all(true); 2293 intel_pmu_pebs_disable_all(); 2294 intel_pmu_lbr_disable_all(); 2295 } 2296 2297 static void __intel_pmu_enable_all(int added, bool pmi) 2298 { 2299 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2300 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2301 2302 intel_pmu_lbr_enable_all(pmi); 2303 2304 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) { 2305 wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val); 2306 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val; 2307 } 2308 2309 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 2310 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2311 2312 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2313 struct perf_event *event = 2314 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2315 2316 if (WARN_ON_ONCE(!event)) 2317 return; 2318 2319 intel_pmu_enable_bts(event->hw.config); 2320 } 2321 } 2322 2323 static void intel_pmu_enable_all(int added) 2324 { 2325 intel_pmu_pebs_enable_all(); 2326 __intel_pmu_enable_all(added, false); 2327 } 2328 2329 static noinline int 2330 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, 2331 unsigned int cnt, unsigned long flags) 2332 { 2333 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2334 2335 intel_pmu_lbr_read(); 2336 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); 2337 2338 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); 2339 intel_pmu_enable_all(0); 2340 local_irq_restore(flags); 2341 return cnt; 2342 } 2343 2344 static int 2345 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2346 { 2347 unsigned long flags; 2348 2349 /* must not have branches... */ 2350 local_irq_save(flags); 2351 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2352 __intel_pmu_lbr_disable(); 2353 /* ... until here */ 2354 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2355 } 2356 2357 static int 2358 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2359 { 2360 unsigned long flags; 2361 2362 /* must not have branches... */ 2363 local_irq_save(flags); 2364 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2365 __intel_pmu_arch_lbr_disable(); 2366 /* ... until here */ 2367 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2368 } 2369 2370 /* 2371 * Workaround for: 2372 * Intel Errata AAK100 (model 26) 2373 * Intel Errata AAP53 (model 30) 2374 * Intel Errata BD53 (model 44) 2375 * 2376 * The official story: 2377 * These chips need to be 'reset' when adding counters by programming the 2378 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2379 * in sequence on the same PMC or on different PMCs. 2380 * 2381 * In practice it appears some of these events do in fact count, and 2382 * we need to program all 4 events. 2383 */ 2384 static void intel_pmu_nhm_workaround(void) 2385 { 2386 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2387 static const unsigned long nhm_magic[4] = { 2388 0x4300B5, 2389 0x4300D2, 2390 0x4300B1, 2391 0x4300B1 2392 }; 2393 struct perf_event *event; 2394 int i; 2395 2396 /* 2397 * The Errata requires below steps: 2398 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2399 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2400 * the corresponding PMCx; 2401 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2402 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2403 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2404 */ 2405 2406 /* 2407 * The real steps we choose are a little different from above. 2408 * A) To reduce MSR operations, we don't run step 1) as they 2409 * are already cleared before this function is called; 2410 * B) Call x86_perf_event_update to save PMCx before configuring 2411 * PERFEVTSELx with magic number; 2412 * C) With step 5), we do clear only when the PERFEVTSELx is 2413 * not used currently. 2414 * D) Call x86_perf_event_set_period to restore PMCx; 2415 */ 2416 2417 /* We always operate 4 pairs of PERF Counters */ 2418 for (i = 0; i < 4; i++) { 2419 event = cpuc->events[i]; 2420 if (event) 2421 static_call(x86_pmu_update)(event); 2422 } 2423 2424 for (i = 0; i < 4; i++) { 2425 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2426 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2427 } 2428 2429 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2430 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2431 2432 for (i = 0; i < 4; i++) { 2433 event = cpuc->events[i]; 2434 2435 if (event) { 2436 static_call(x86_pmu_set_period)(event); 2437 __x86_pmu_enable_event(&event->hw, 2438 ARCH_PERFMON_EVENTSEL_ENABLE); 2439 } else 2440 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2441 } 2442 } 2443 2444 static void intel_pmu_nhm_enable_all(int added) 2445 { 2446 if (added) 2447 intel_pmu_nhm_workaround(); 2448 intel_pmu_enable_all(added); 2449 } 2450 2451 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2452 { 2453 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2454 2455 if (cpuc->tfa_shadow != val) { 2456 cpuc->tfa_shadow = val; 2457 wrmsrl(MSR_TSX_FORCE_ABORT, val); 2458 } 2459 } 2460 2461 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2462 { 2463 /* 2464 * We're going to use PMC3, make sure TFA is set before we touch it. 2465 */ 2466 if (cntr == 3) 2467 intel_set_tfa(cpuc, true); 2468 } 2469 2470 static void intel_tfa_pmu_enable_all(int added) 2471 { 2472 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2473 2474 /* 2475 * If we find PMC3 is no longer used when we enable the PMU, we can 2476 * clear TFA. 2477 */ 2478 if (!test_bit(3, cpuc->active_mask)) 2479 intel_set_tfa(cpuc, false); 2480 2481 intel_pmu_enable_all(added); 2482 } 2483 2484 static inline u64 intel_pmu_get_status(void) 2485 { 2486 u64 status; 2487 2488 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2489 2490 return status; 2491 } 2492 2493 static inline void intel_pmu_ack_status(u64 ack) 2494 { 2495 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2496 } 2497 2498 static inline bool event_is_checkpointed(struct perf_event *event) 2499 { 2500 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2501 } 2502 2503 static inline void intel_set_masks(struct perf_event *event, int idx) 2504 { 2505 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2506 2507 if (event->attr.exclude_host) 2508 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2509 if (event->attr.exclude_guest) 2510 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2511 if (event_is_checkpointed(event)) 2512 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2513 } 2514 2515 static inline void intel_clear_masks(struct perf_event *event, int idx) 2516 { 2517 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2518 2519 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2520 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2521 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2522 } 2523 2524 static void intel_pmu_disable_fixed(struct perf_event *event) 2525 { 2526 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2527 struct hw_perf_event *hwc = &event->hw; 2528 int idx = hwc->idx; 2529 u64 mask; 2530 2531 if (is_topdown_idx(idx)) { 2532 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2533 2534 /* 2535 * When there are other active TopDown events, 2536 * don't disable the fixed counter 3. 2537 */ 2538 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2539 return; 2540 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2541 } 2542 2543 intel_clear_masks(event, idx); 2544 2545 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK); 2546 cpuc->fixed_ctrl_val &= ~mask; 2547 } 2548 2549 static void intel_pmu_disable_event(struct perf_event *event) 2550 { 2551 struct hw_perf_event *hwc = &event->hw; 2552 int idx = hwc->idx; 2553 2554 switch (idx) { 2555 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2556 intel_clear_masks(event, idx); 2557 x86_pmu_disable_event(event); 2558 break; 2559 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2560 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2561 intel_pmu_disable_fixed(event); 2562 break; 2563 case INTEL_PMC_IDX_FIXED_BTS: 2564 intel_pmu_disable_bts(); 2565 intel_pmu_drain_bts_buffer(); 2566 return; 2567 case INTEL_PMC_IDX_FIXED_VLBR: 2568 intel_clear_masks(event, idx); 2569 break; 2570 default: 2571 intel_clear_masks(event, idx); 2572 pr_warn("Failed to disable the event with invalid index %d\n", 2573 idx); 2574 return; 2575 } 2576 2577 /* 2578 * Needs to be called after x86_pmu_disable_event, 2579 * so we don't trigger the event without PEBS bit set. 2580 */ 2581 if (unlikely(event->attr.precise_ip)) 2582 intel_pmu_pebs_disable(event); 2583 } 2584 2585 static void intel_pmu_assign_event(struct perf_event *event, int idx) 2586 { 2587 if (is_pebs_pt(event)) 2588 perf_report_aux_output_id(event, idx); 2589 } 2590 2591 static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event) 2592 { 2593 return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK; 2594 } 2595 2596 static void intel_pmu_del_event(struct perf_event *event) 2597 { 2598 if (intel_pmu_needs_branch_stack(event)) 2599 intel_pmu_lbr_del(event); 2600 if (event->attr.precise_ip) 2601 intel_pmu_pebs_del(event); 2602 } 2603 2604 static int icl_set_topdown_event_period(struct perf_event *event) 2605 { 2606 struct hw_perf_event *hwc = &event->hw; 2607 s64 left = local64_read(&hwc->period_left); 2608 2609 /* 2610 * The values in PERF_METRICS MSR are derived from fixed counter 3. 2611 * Software should start both registers, PERF_METRICS and fixed 2612 * counter 3, from zero. 2613 * Clear PERF_METRICS and Fixed counter 3 in initialization. 2614 * After that, both MSRs will be cleared for each read. 2615 * Don't need to clear them again. 2616 */ 2617 if (left == x86_pmu.max_period) { 2618 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2619 wrmsrl(MSR_PERF_METRICS, 0); 2620 hwc->saved_slots = 0; 2621 hwc->saved_metric = 0; 2622 } 2623 2624 if ((hwc->saved_slots) && is_slots_event(event)) { 2625 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2626 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric); 2627 } 2628 2629 perf_event_update_userpage(event); 2630 2631 return 0; 2632 } 2633 2634 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period); 2635 2636 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 2637 { 2638 u32 val; 2639 2640 /* 2641 * The metric is reported as an 8bit integer fraction 2642 * summing up to 0xff. 2643 * slots-in-metric = (Metric / 0xff) * slots 2644 */ 2645 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 2646 return mul_u64_u32_div(slots, val, 0xff); 2647 } 2648 2649 static u64 icl_get_topdown_value(struct perf_event *event, 2650 u64 slots, u64 metrics) 2651 { 2652 int idx = event->hw.idx; 2653 u64 delta; 2654 2655 if (is_metric_idx(idx)) 2656 delta = icl_get_metrics_event_value(metrics, slots, idx); 2657 else 2658 delta = slots; 2659 2660 return delta; 2661 } 2662 2663 static void __icl_update_topdown_event(struct perf_event *event, 2664 u64 slots, u64 metrics, 2665 u64 last_slots, u64 last_metrics) 2666 { 2667 u64 delta, last = 0; 2668 2669 delta = icl_get_topdown_value(event, slots, metrics); 2670 if (last_slots) 2671 last = icl_get_topdown_value(event, last_slots, last_metrics); 2672 2673 /* 2674 * The 8bit integer fraction of metric may be not accurate, 2675 * especially when the changes is very small. 2676 * For example, if only a few bad_spec happens, the fraction 2677 * may be reduced from 1 to 0. If so, the bad_spec event value 2678 * will be 0 which is definitely less than the last value. 2679 * Avoid update event->count for this case. 2680 */ 2681 if (delta > last) { 2682 delta -= last; 2683 local64_add(delta, &event->count); 2684 } 2685 } 2686 2687 static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 2688 u64 metrics, int metric_end) 2689 { 2690 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2691 struct perf_event *other; 2692 int idx; 2693 2694 event->hw.saved_slots = slots; 2695 event->hw.saved_metric = metrics; 2696 2697 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2698 if (!is_topdown_idx(idx)) 2699 continue; 2700 other = cpuc->events[idx]; 2701 other->hw.saved_slots = slots; 2702 other->hw.saved_metric = metrics; 2703 } 2704 } 2705 2706 /* 2707 * Update all active Topdown events. 2708 * 2709 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 2710 * modify by a NMI. PMU has to be disabled before calling this function. 2711 */ 2712 2713 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end) 2714 { 2715 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2716 struct perf_event *other; 2717 u64 slots, metrics; 2718 bool reset = true; 2719 int idx; 2720 2721 /* read Fixed counter 3 */ 2722 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); 2723 if (!slots) 2724 return 0; 2725 2726 /* read PERF_METRICS */ 2727 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); 2728 2729 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2730 if (!is_topdown_idx(idx)) 2731 continue; 2732 other = cpuc->events[idx]; 2733 __icl_update_topdown_event(other, slots, metrics, 2734 event ? event->hw.saved_slots : 0, 2735 event ? event->hw.saved_metric : 0); 2736 } 2737 2738 /* 2739 * Check and update this event, which may have been cleared 2740 * in active_mask e.g. x86_pmu_stop() 2741 */ 2742 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 2743 __icl_update_topdown_event(event, slots, metrics, 2744 event->hw.saved_slots, 2745 event->hw.saved_metric); 2746 2747 /* 2748 * In x86_pmu_stop(), the event is cleared in active_mask first, 2749 * then drain the delta, which indicates context switch for 2750 * counting. 2751 * Save metric and slots for context switch. 2752 * Don't need to reset the PERF_METRICS and Fixed counter 3. 2753 * Because the values will be restored in next schedule in. 2754 */ 2755 update_saved_topdown_regs(event, slots, metrics, metric_end); 2756 reset = false; 2757 } 2758 2759 if (reset) { 2760 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 2761 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2762 wrmsrl(MSR_PERF_METRICS, 0); 2763 if (event) 2764 update_saved_topdown_regs(event, 0, 0, metric_end); 2765 } 2766 2767 return slots; 2768 } 2769 2770 static u64 icl_update_topdown_event(struct perf_event *event) 2771 { 2772 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 2773 x86_pmu.num_topdown_events - 1); 2774 } 2775 2776 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, x86_perf_event_update); 2777 2778 static void intel_pmu_read_topdown_event(struct perf_event *event) 2779 { 2780 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2781 2782 /* Only need to call update_topdown_event() once for group read. */ 2783 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) && 2784 !is_slots_event(event)) 2785 return; 2786 2787 perf_pmu_disable(event->pmu); 2788 static_call(intel_pmu_update_topdown_event)(event); 2789 perf_pmu_enable(event->pmu); 2790 } 2791 2792 static void intel_pmu_read_event(struct perf_event *event) 2793 { 2794 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2795 intel_pmu_auto_reload_read(event); 2796 else if (is_topdown_count(event)) 2797 intel_pmu_read_topdown_event(event); 2798 else 2799 x86_perf_event_update(event); 2800 } 2801 2802 static void intel_pmu_enable_fixed(struct perf_event *event) 2803 { 2804 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2805 struct hw_perf_event *hwc = &event->hw; 2806 u64 mask, bits = 0; 2807 int idx = hwc->idx; 2808 2809 if (is_topdown_idx(idx)) { 2810 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2811 /* 2812 * When there are other active TopDown events, 2813 * don't enable the fixed counter 3 again. 2814 */ 2815 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2816 return; 2817 2818 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2819 } 2820 2821 intel_set_masks(event, idx); 2822 2823 /* 2824 * Enable IRQ generation (0x8), if not PEBS, 2825 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2826 * if requested: 2827 */ 2828 if (!event->attr.precise_ip) 2829 bits |= INTEL_FIXED_0_ENABLE_PMI; 2830 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2831 bits |= INTEL_FIXED_0_USER; 2832 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2833 bits |= INTEL_FIXED_0_KERNEL; 2834 2835 /* 2836 * ANY bit is supported in v3 and up 2837 */ 2838 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2839 bits |= INTEL_FIXED_0_ANYTHREAD; 2840 2841 idx -= INTEL_PMC_IDX_FIXED; 2842 bits = intel_fixed_bits_by_idx(idx, bits); 2843 mask = intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK); 2844 2845 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2846 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); 2847 mask |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); 2848 } 2849 2850 cpuc->fixed_ctrl_val &= ~mask; 2851 cpuc->fixed_ctrl_val |= bits; 2852 } 2853 2854 static void intel_pmu_enable_event(struct perf_event *event) 2855 { 2856 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE; 2857 struct hw_perf_event *hwc = &event->hw; 2858 int idx = hwc->idx; 2859 2860 if (unlikely(event->attr.precise_ip)) 2861 intel_pmu_pebs_enable(event); 2862 2863 switch (idx) { 2864 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2865 if (branch_sample_counters(event)) 2866 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR; 2867 intel_set_masks(event, idx); 2868 __x86_pmu_enable_event(hwc, enable_mask); 2869 break; 2870 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2871 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2872 intel_pmu_enable_fixed(event); 2873 break; 2874 case INTEL_PMC_IDX_FIXED_BTS: 2875 if (!__this_cpu_read(cpu_hw_events.enabled)) 2876 return; 2877 intel_pmu_enable_bts(hwc->config); 2878 break; 2879 case INTEL_PMC_IDX_FIXED_VLBR: 2880 intel_set_masks(event, idx); 2881 break; 2882 default: 2883 pr_warn("Failed to enable the event with invalid index %d\n", 2884 idx); 2885 } 2886 } 2887 2888 static void intel_pmu_add_event(struct perf_event *event) 2889 { 2890 if (event->attr.precise_ip) 2891 intel_pmu_pebs_add(event); 2892 if (intel_pmu_needs_branch_stack(event)) 2893 intel_pmu_lbr_add(event); 2894 } 2895 2896 /* 2897 * Save and restart an expired event. Called by NMI contexts, 2898 * so it has to be careful about preempting normal event ops: 2899 */ 2900 int intel_pmu_save_and_restart(struct perf_event *event) 2901 { 2902 static_call(x86_pmu_update)(event); 2903 /* 2904 * For a checkpointed counter always reset back to 0. This 2905 * avoids a situation where the counter overflows, aborts the 2906 * transaction and is then set back to shortly before the 2907 * overflow, and overflows and aborts again. 2908 */ 2909 if (unlikely(event_is_checkpointed(event))) { 2910 /* No race with NMIs because the counter should not be armed */ 2911 wrmsrl(event->hw.event_base, 0); 2912 local64_set(&event->hw.prev_count, 0); 2913 } 2914 return static_call(x86_pmu_set_period)(event); 2915 } 2916 2917 static int intel_pmu_set_period(struct perf_event *event) 2918 { 2919 if (unlikely(is_topdown_count(event))) 2920 return static_call(intel_pmu_set_topdown_event_period)(event); 2921 2922 return x86_perf_event_set_period(event); 2923 } 2924 2925 static u64 intel_pmu_update(struct perf_event *event) 2926 { 2927 if (unlikely(is_topdown_count(event))) 2928 return static_call(intel_pmu_update_topdown_event)(event); 2929 2930 return x86_perf_event_update(event); 2931 } 2932 2933 static void intel_pmu_reset(void) 2934 { 2935 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2936 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2937 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask); 2938 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask); 2939 unsigned long flags; 2940 int idx; 2941 2942 if (!*(u64 *)cntr_mask) 2943 return; 2944 2945 local_irq_save(flags); 2946 2947 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2948 2949 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) { 2950 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2951 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2952 } 2953 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) { 2954 if (fixed_counter_disabled(idx, cpuc->pmu)) 2955 continue; 2956 wrmsrl_safe(x86_pmu_fixed_ctr_addr(idx), 0ull); 2957 } 2958 2959 if (ds) 2960 ds->bts_index = ds->bts_buffer_base; 2961 2962 /* Ack all overflows and disable fixed counters */ 2963 if (x86_pmu.version >= 2) { 2964 intel_pmu_ack_status(intel_pmu_get_status()); 2965 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2966 } 2967 2968 /* Reset LBRs and LBR freezing */ 2969 if (x86_pmu.lbr_nr) { 2970 update_debugctlmsr(get_debugctlmsr() & 2971 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2972 } 2973 2974 local_irq_restore(flags); 2975 } 2976 2977 /* 2978 * We may be running with guest PEBS events created by KVM, and the 2979 * PEBS records are logged into the guest's DS and invisible to host. 2980 * 2981 * In the case of guest PEBS overflow, we only trigger a fake event 2982 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM. 2983 * The guest will then vm-entry and check the guest DS area to read 2984 * the guest PEBS records. 2985 * 2986 * The contents and other behavior of the guest event do not matter. 2987 */ 2988 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs, 2989 struct perf_sample_data *data) 2990 { 2991 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2992 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask; 2993 struct perf_event *event = NULL; 2994 int bit; 2995 2996 if (!unlikely(perf_guest_state())) 2997 return; 2998 2999 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active || 3000 !guest_pebs_idxs) 3001 return; 3002 3003 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) { 3004 event = cpuc->events[bit]; 3005 if (!event->attr.precise_ip) 3006 continue; 3007 3008 perf_sample_data_init(data, 0, event->hw.last_period); 3009 if (perf_event_overflow(event, data, regs)) 3010 x86_pmu_stop(event, 0); 3011 3012 /* Inject one fake event is enough. */ 3013 break; 3014 } 3015 } 3016 3017 static int handle_pmi_common(struct pt_regs *regs, u64 status) 3018 { 3019 struct perf_sample_data data; 3020 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3021 int bit; 3022 int handled = 0; 3023 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 3024 3025 inc_irq_stat(apic_perf_irqs); 3026 3027 /* 3028 * Ignore a range of extra bits in status that do not indicate 3029 * overflow by themselves. 3030 */ 3031 status &= ~(GLOBAL_STATUS_COND_CHG | 3032 GLOBAL_STATUS_ASIF | 3033 GLOBAL_STATUS_LBRS_FROZEN); 3034 if (!status) 3035 return 0; 3036 /* 3037 * In case multiple PEBS events are sampled at the same time, 3038 * it is possible to have GLOBAL_STATUS bit 62 set indicating 3039 * PEBS buffer overflow and also seeing at most 3 PEBS counters 3040 * having their bits set in the status register. This is a sign 3041 * that there was at least one PEBS record pending at the time 3042 * of the PMU interrupt. PEBS counters must only be processed 3043 * via the drain_pebs() calls and not via the regular sample 3044 * processing loop coming after that the function, otherwise 3045 * phony regular samples may be generated in the sampling buffer 3046 * not marked with the EXACT tag. Another possibility is to have 3047 * one PEBS event and at least one non-PEBS event which overflows 3048 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 3049 * not be set, yet the overflow status bit for the PEBS counter will 3050 * be on Skylake. 3051 * 3052 * To avoid this problem, we systematically ignore the PEBS-enabled 3053 * counters from the GLOBAL_STATUS mask and we always process PEBS 3054 * events via drain_pebs(). 3055 */ 3056 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable); 3057 3058 /* 3059 * PEBS overflow sets bit 62 in the global status register 3060 */ 3061 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 3062 u64 pebs_enabled = cpuc->pebs_enabled; 3063 3064 handled++; 3065 x86_pmu_handle_guest_pebs(regs, &data); 3066 x86_pmu.drain_pebs(regs, &data); 3067 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 3068 3069 /* 3070 * PMI throttle may be triggered, which stops the PEBS event. 3071 * Although cpuc->pebs_enabled is updated accordingly, the 3072 * MSR_IA32_PEBS_ENABLE is not updated. Because the 3073 * cpuc->enabled has been forced to 0 in PMI. 3074 * Update the MSR if pebs_enabled is changed. 3075 */ 3076 if (pebs_enabled != cpuc->pebs_enabled) 3077 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 3078 } 3079 3080 /* 3081 * Intel PT 3082 */ 3083 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 3084 handled++; 3085 if (!perf_guest_handle_intel_pt_intr()) 3086 intel_pt_interrupt(); 3087 } 3088 3089 /* 3090 * Intel Perf metrics 3091 */ 3092 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 3093 handled++; 3094 static_call(intel_pmu_update_topdown_event)(NULL); 3095 } 3096 3097 /* 3098 * Checkpointed counters can lead to 'spurious' PMIs because the 3099 * rollback caused by the PMI will have cleared the overflow status 3100 * bit. Therefore always force probe these counters. 3101 */ 3102 status |= cpuc->intel_cp_status; 3103 3104 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 3105 struct perf_event *event = cpuc->events[bit]; 3106 3107 handled++; 3108 3109 if (!test_bit(bit, cpuc->active_mask)) 3110 continue; 3111 3112 if (!intel_pmu_save_and_restart(event)) 3113 continue; 3114 3115 perf_sample_data_init(&data, 0, event->hw.last_period); 3116 3117 if (has_branch_stack(event)) 3118 intel_pmu_lbr_save_brstack(&data, cpuc, event); 3119 3120 if (perf_event_overflow(event, &data, regs)) 3121 x86_pmu_stop(event, 0); 3122 } 3123 3124 return handled; 3125 } 3126 3127 /* 3128 * This handler is triggered by the local APIC, so the APIC IRQ handling 3129 * rules apply: 3130 */ 3131 static int intel_pmu_handle_irq(struct pt_regs *regs) 3132 { 3133 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3134 bool late_ack = hybrid_bit(cpuc->pmu, late_ack); 3135 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); 3136 int loops; 3137 u64 status; 3138 int handled; 3139 int pmu_enabled; 3140 3141 /* 3142 * Save the PMU state. 3143 * It needs to be restored when leaving the handler. 3144 */ 3145 pmu_enabled = cpuc->enabled; 3146 /* 3147 * In general, the early ACK is only applied for old platforms. 3148 * For the big core starts from Haswell, the late ACK should be 3149 * applied. 3150 * For the small core after Tremont, we have to do the ACK right 3151 * before re-enabling counters, which is in the middle of the 3152 * NMI handler. 3153 */ 3154 if (!late_ack && !mid_ack) 3155 apic_write(APIC_LVTPC, APIC_DM_NMI); 3156 intel_bts_disable_local(); 3157 cpuc->enabled = 0; 3158 __intel_pmu_disable_all(true); 3159 handled = intel_pmu_drain_bts_buffer(); 3160 handled += intel_bts_interrupt(); 3161 status = intel_pmu_get_status(); 3162 if (!status) 3163 goto done; 3164 3165 loops = 0; 3166 again: 3167 intel_pmu_lbr_read(); 3168 intel_pmu_ack_status(status); 3169 if (++loops > 100) { 3170 static bool warned; 3171 3172 if (!warned) { 3173 WARN(1, "perfevents: irq loop stuck!\n"); 3174 perf_event_print_debug(); 3175 warned = true; 3176 } 3177 intel_pmu_reset(); 3178 goto done; 3179 } 3180 3181 handled += handle_pmi_common(regs, status); 3182 3183 /* 3184 * Repeat if there is more work to be done: 3185 */ 3186 status = intel_pmu_get_status(); 3187 if (status) 3188 goto again; 3189 3190 done: 3191 if (mid_ack) 3192 apic_write(APIC_LVTPC, APIC_DM_NMI); 3193 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 3194 cpuc->enabled = pmu_enabled; 3195 if (pmu_enabled) 3196 __intel_pmu_enable_all(0, true); 3197 intel_bts_enable_local(); 3198 3199 /* 3200 * Only unmask the NMI after the overflow counters 3201 * have been reset. This avoids spurious NMIs on 3202 * Haswell CPUs. 3203 */ 3204 if (late_ack) 3205 apic_write(APIC_LVTPC, APIC_DM_NMI); 3206 return handled; 3207 } 3208 3209 static struct event_constraint * 3210 intel_bts_constraints(struct perf_event *event) 3211 { 3212 if (unlikely(intel_pmu_has_bts(event))) 3213 return &bts_constraint; 3214 3215 return NULL; 3216 } 3217 3218 /* 3219 * Note: matches a fake event, like Fixed2. 3220 */ 3221 static struct event_constraint * 3222 intel_vlbr_constraints(struct perf_event *event) 3223 { 3224 struct event_constraint *c = &vlbr_constraint; 3225 3226 if (unlikely(constraint_match(c, event->hw.config))) { 3227 event->hw.flags |= c->flags; 3228 return c; 3229 } 3230 3231 return NULL; 3232 } 3233 3234 static int intel_alt_er(struct cpu_hw_events *cpuc, 3235 int idx, u64 config) 3236 { 3237 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); 3238 int alt_idx = idx; 3239 3240 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 3241 return idx; 3242 3243 if (idx == EXTRA_REG_RSP_0) 3244 alt_idx = EXTRA_REG_RSP_1; 3245 3246 if (idx == EXTRA_REG_RSP_1) 3247 alt_idx = EXTRA_REG_RSP_0; 3248 3249 if (config & ~extra_regs[alt_idx].valid_mask) 3250 return idx; 3251 3252 return alt_idx; 3253 } 3254 3255 static void intel_fixup_er(struct perf_event *event, int idx) 3256 { 3257 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); 3258 event->hw.extra_reg.idx = idx; 3259 3260 if (idx == EXTRA_REG_RSP_0) { 3261 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3262 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event; 3263 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 3264 } else if (idx == EXTRA_REG_RSP_1) { 3265 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3266 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event; 3267 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 3268 } 3269 } 3270 3271 /* 3272 * manage allocation of shared extra msr for certain events 3273 * 3274 * sharing can be: 3275 * per-cpu: to be shared between the various events on a single PMU 3276 * per-core: per-cpu + shared by HT threads 3277 */ 3278 static struct event_constraint * 3279 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 3280 struct perf_event *event, 3281 struct hw_perf_event_extra *reg) 3282 { 3283 struct event_constraint *c = &emptyconstraint; 3284 struct er_account *era; 3285 unsigned long flags; 3286 int idx = reg->idx; 3287 3288 /* 3289 * reg->alloc can be set due to existing state, so for fake cpuc we 3290 * need to ignore this, otherwise we might fail to allocate proper fake 3291 * state for this extra reg constraint. Also see the comment below. 3292 */ 3293 if (reg->alloc && !cpuc->is_fake) 3294 return NULL; /* call x86_get_event_constraint() */ 3295 3296 again: 3297 era = &cpuc->shared_regs->regs[idx]; 3298 /* 3299 * we use spin_lock_irqsave() to avoid lockdep issues when 3300 * passing a fake cpuc 3301 */ 3302 raw_spin_lock_irqsave(&era->lock, flags); 3303 3304 if (!atomic_read(&era->ref) || era->config == reg->config) { 3305 3306 /* 3307 * If its a fake cpuc -- as per validate_{group,event}() we 3308 * shouldn't touch event state and we can avoid doing so 3309 * since both will only call get_event_constraints() once 3310 * on each event, this avoids the need for reg->alloc. 3311 * 3312 * Not doing the ER fixup will only result in era->reg being 3313 * wrong, but since we won't actually try and program hardware 3314 * this isn't a problem either. 3315 */ 3316 if (!cpuc->is_fake) { 3317 if (idx != reg->idx) 3318 intel_fixup_er(event, idx); 3319 3320 /* 3321 * x86_schedule_events() can call get_event_constraints() 3322 * multiple times on events in the case of incremental 3323 * scheduling(). reg->alloc ensures we only do the ER 3324 * allocation once. 3325 */ 3326 reg->alloc = 1; 3327 } 3328 3329 /* lock in msr value */ 3330 era->config = reg->config; 3331 era->reg = reg->reg; 3332 3333 /* one more user */ 3334 atomic_inc(&era->ref); 3335 3336 /* 3337 * need to call x86_get_event_constraint() 3338 * to check if associated event has constraints 3339 */ 3340 c = NULL; 3341 } else { 3342 idx = intel_alt_er(cpuc, idx, reg->config); 3343 if (idx != reg->idx) { 3344 raw_spin_unlock_irqrestore(&era->lock, flags); 3345 goto again; 3346 } 3347 } 3348 raw_spin_unlock_irqrestore(&era->lock, flags); 3349 3350 return c; 3351 } 3352 3353 static void 3354 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3355 struct hw_perf_event_extra *reg) 3356 { 3357 struct er_account *era; 3358 3359 /* 3360 * Only put constraint if extra reg was actually allocated. Also takes 3361 * care of event which do not use an extra shared reg. 3362 * 3363 * Also, if this is a fake cpuc we shouldn't touch any event state 3364 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3365 * either since it'll be thrown out. 3366 */ 3367 if (!reg->alloc || cpuc->is_fake) 3368 return; 3369 3370 era = &cpuc->shared_regs->regs[reg->idx]; 3371 3372 /* one fewer user */ 3373 atomic_dec(&era->ref); 3374 3375 /* allocate again next time */ 3376 reg->alloc = 0; 3377 } 3378 3379 static struct event_constraint * 3380 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3381 struct perf_event *event) 3382 { 3383 struct event_constraint *c = NULL, *d; 3384 struct hw_perf_event_extra *xreg, *breg; 3385 3386 xreg = &event->hw.extra_reg; 3387 if (xreg->idx != EXTRA_REG_NONE) { 3388 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3389 if (c == &emptyconstraint) 3390 return c; 3391 } 3392 breg = &event->hw.branch_reg; 3393 if (breg->idx != EXTRA_REG_NONE) { 3394 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3395 if (d == &emptyconstraint) { 3396 __intel_shared_reg_put_constraints(cpuc, xreg); 3397 c = d; 3398 } 3399 } 3400 return c; 3401 } 3402 3403 struct event_constraint * 3404 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3405 struct perf_event *event) 3406 { 3407 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); 3408 struct event_constraint *c; 3409 3410 if (event_constraints) { 3411 for_each_event_constraint(c, event_constraints) { 3412 if (constraint_match(c, event->hw.config)) { 3413 event->hw.flags |= c->flags; 3414 return c; 3415 } 3416 } 3417 } 3418 3419 return &hybrid_var(cpuc->pmu, unconstrained); 3420 } 3421 3422 static struct event_constraint * 3423 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3424 struct perf_event *event) 3425 { 3426 struct event_constraint *c; 3427 3428 c = intel_vlbr_constraints(event); 3429 if (c) 3430 return c; 3431 3432 c = intel_bts_constraints(event); 3433 if (c) 3434 return c; 3435 3436 c = intel_shared_regs_constraints(cpuc, event); 3437 if (c) 3438 return c; 3439 3440 c = intel_pebs_constraints(event); 3441 if (c) 3442 return c; 3443 3444 return x86_get_event_constraints(cpuc, idx, event); 3445 } 3446 3447 static void 3448 intel_start_scheduling(struct cpu_hw_events *cpuc) 3449 { 3450 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3451 struct intel_excl_states *xl; 3452 int tid = cpuc->excl_thread_id; 3453 3454 /* 3455 * nothing needed if in group validation mode 3456 */ 3457 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3458 return; 3459 3460 /* 3461 * no exclusion needed 3462 */ 3463 if (WARN_ON_ONCE(!excl_cntrs)) 3464 return; 3465 3466 xl = &excl_cntrs->states[tid]; 3467 3468 xl->sched_started = true; 3469 /* 3470 * lock shared state until we are done scheduling 3471 * in stop_event_scheduling() 3472 * makes scheduling appear as a transaction 3473 */ 3474 raw_spin_lock(&excl_cntrs->lock); 3475 } 3476 3477 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3478 { 3479 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3480 struct event_constraint *c = cpuc->event_constraint[idx]; 3481 struct intel_excl_states *xl; 3482 int tid = cpuc->excl_thread_id; 3483 3484 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3485 return; 3486 3487 if (WARN_ON_ONCE(!excl_cntrs)) 3488 return; 3489 3490 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3491 return; 3492 3493 xl = &excl_cntrs->states[tid]; 3494 3495 lockdep_assert_held(&excl_cntrs->lock); 3496 3497 if (c->flags & PERF_X86_EVENT_EXCL) 3498 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3499 else 3500 xl->state[cntr] = INTEL_EXCL_SHARED; 3501 } 3502 3503 static void 3504 intel_stop_scheduling(struct cpu_hw_events *cpuc) 3505 { 3506 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3507 struct intel_excl_states *xl; 3508 int tid = cpuc->excl_thread_id; 3509 3510 /* 3511 * nothing needed if in group validation mode 3512 */ 3513 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3514 return; 3515 /* 3516 * no exclusion needed 3517 */ 3518 if (WARN_ON_ONCE(!excl_cntrs)) 3519 return; 3520 3521 xl = &excl_cntrs->states[tid]; 3522 3523 xl->sched_started = false; 3524 /* 3525 * release shared state lock (acquired in intel_start_scheduling()) 3526 */ 3527 raw_spin_unlock(&excl_cntrs->lock); 3528 } 3529 3530 static struct event_constraint * 3531 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 3532 { 3533 WARN_ON_ONCE(!cpuc->constraint_list); 3534 3535 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 3536 struct event_constraint *cx; 3537 3538 /* 3539 * grab pre-allocated constraint entry 3540 */ 3541 cx = &cpuc->constraint_list[idx]; 3542 3543 /* 3544 * initialize dynamic constraint 3545 * with static constraint 3546 */ 3547 *cx = *c; 3548 3549 /* 3550 * mark constraint as dynamic 3551 */ 3552 cx->flags |= PERF_X86_EVENT_DYNAMIC; 3553 c = cx; 3554 } 3555 3556 return c; 3557 } 3558 3559 static struct event_constraint * 3560 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3561 int idx, struct event_constraint *c) 3562 { 3563 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3564 struct intel_excl_states *xlo; 3565 int tid = cpuc->excl_thread_id; 3566 int is_excl, i, w; 3567 3568 /* 3569 * validating a group does not require 3570 * enforcing cross-thread exclusion 3571 */ 3572 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3573 return c; 3574 3575 /* 3576 * no exclusion needed 3577 */ 3578 if (WARN_ON_ONCE(!excl_cntrs)) 3579 return c; 3580 3581 /* 3582 * because we modify the constraint, we need 3583 * to make a copy. Static constraints come 3584 * from static const tables. 3585 * 3586 * only needed when constraint has not yet 3587 * been cloned (marked dynamic) 3588 */ 3589 c = dyn_constraint(cpuc, c, idx); 3590 3591 /* 3592 * From here on, the constraint is dynamic. 3593 * Either it was just allocated above, or it 3594 * was allocated during a earlier invocation 3595 * of this function 3596 */ 3597 3598 /* 3599 * state of sibling HT 3600 */ 3601 xlo = &excl_cntrs->states[tid ^ 1]; 3602 3603 /* 3604 * event requires exclusive counter access 3605 * across HT threads 3606 */ 3607 is_excl = c->flags & PERF_X86_EVENT_EXCL; 3608 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3609 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3610 if (!cpuc->n_excl++) 3611 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3612 } 3613 3614 /* 3615 * Modify static constraint with current dynamic 3616 * state of thread 3617 * 3618 * EXCLUSIVE: sibling counter measuring exclusive event 3619 * SHARED : sibling counter measuring non-exclusive event 3620 * UNUSED : sibling counter unused 3621 */ 3622 w = c->weight; 3623 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3624 /* 3625 * exclusive event in sibling counter 3626 * our corresponding counter cannot be used 3627 * regardless of our event 3628 */ 3629 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3630 __clear_bit(i, c->idxmsk); 3631 w--; 3632 continue; 3633 } 3634 /* 3635 * if measuring an exclusive event, sibling 3636 * measuring non-exclusive, then counter cannot 3637 * be used 3638 */ 3639 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3640 __clear_bit(i, c->idxmsk); 3641 w--; 3642 continue; 3643 } 3644 } 3645 3646 /* 3647 * if we return an empty mask, then switch 3648 * back to static empty constraint to avoid 3649 * the cost of freeing later on 3650 */ 3651 if (!w) 3652 c = &emptyconstraint; 3653 3654 c->weight = w; 3655 3656 return c; 3657 } 3658 3659 static struct event_constraint * 3660 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3661 struct perf_event *event) 3662 { 3663 struct event_constraint *c1, *c2; 3664 3665 c1 = cpuc->event_constraint[idx]; 3666 3667 /* 3668 * first time only 3669 * - static constraint: no change across incremental scheduling calls 3670 * - dynamic constraint: handled by intel_get_excl_constraints() 3671 */ 3672 c2 = __intel_get_event_constraints(cpuc, idx, event); 3673 if (c1) { 3674 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3675 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3676 c1->weight = c2->weight; 3677 c2 = c1; 3678 } 3679 3680 if (cpuc->excl_cntrs) 3681 return intel_get_excl_constraints(cpuc, event, idx, c2); 3682 3683 /* Not all counters support the branch counter feature. */ 3684 if (branch_sample_counters(event)) { 3685 c2 = dyn_constraint(cpuc, c2, idx); 3686 c2->idxmsk64 &= x86_pmu.lbr_counters; 3687 c2->weight = hweight64(c2->idxmsk64); 3688 } 3689 3690 return c2; 3691 } 3692 3693 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3694 struct perf_event *event) 3695 { 3696 struct hw_perf_event *hwc = &event->hw; 3697 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3698 int tid = cpuc->excl_thread_id; 3699 struct intel_excl_states *xl; 3700 3701 /* 3702 * nothing needed if in group validation mode 3703 */ 3704 if (cpuc->is_fake) 3705 return; 3706 3707 if (WARN_ON_ONCE(!excl_cntrs)) 3708 return; 3709 3710 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3711 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3712 if (!--cpuc->n_excl) 3713 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3714 } 3715 3716 /* 3717 * If event was actually assigned, then mark the counter state as 3718 * unused now. 3719 */ 3720 if (hwc->idx >= 0) { 3721 xl = &excl_cntrs->states[tid]; 3722 3723 /* 3724 * put_constraint may be called from x86_schedule_events() 3725 * which already has the lock held so here make locking 3726 * conditional. 3727 */ 3728 if (!xl->sched_started) 3729 raw_spin_lock(&excl_cntrs->lock); 3730 3731 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3732 3733 if (!xl->sched_started) 3734 raw_spin_unlock(&excl_cntrs->lock); 3735 } 3736 } 3737 3738 static void 3739 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3740 struct perf_event *event) 3741 { 3742 struct hw_perf_event_extra *reg; 3743 3744 reg = &event->hw.extra_reg; 3745 if (reg->idx != EXTRA_REG_NONE) 3746 __intel_shared_reg_put_constraints(cpuc, reg); 3747 3748 reg = &event->hw.branch_reg; 3749 if (reg->idx != EXTRA_REG_NONE) 3750 __intel_shared_reg_put_constraints(cpuc, reg); 3751 } 3752 3753 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3754 struct perf_event *event) 3755 { 3756 intel_put_shared_regs_event_constraints(cpuc, event); 3757 3758 /* 3759 * is PMU has exclusive counter restrictions, then 3760 * all events are subject to and must call the 3761 * put_excl_constraints() routine 3762 */ 3763 if (cpuc->excl_cntrs) 3764 intel_put_excl_constraints(cpuc, event); 3765 } 3766 3767 static void intel_pebs_aliases_core2(struct perf_event *event) 3768 { 3769 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3770 /* 3771 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3772 * (0x003c) so that we can use it with PEBS. 3773 * 3774 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3775 * PEBS capable. However we can use INST_RETIRED.ANY_P 3776 * (0x00c0), which is a PEBS capable event, to get the same 3777 * count. 3778 * 3779 * INST_RETIRED.ANY_P counts the number of cycles that retires 3780 * CNTMASK instructions. By setting CNTMASK to a value (16) 3781 * larger than the maximum number of instructions that can be 3782 * retired per cycle (4) and then inverting the condition, we 3783 * count all cycles that retire 16 or less instructions, which 3784 * is every cycle. 3785 * 3786 * Thereby we gain a PEBS capable cycle counter. 3787 */ 3788 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3789 3790 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3791 event->hw.config = alt_config; 3792 } 3793 } 3794 3795 static void intel_pebs_aliases_snb(struct perf_event *event) 3796 { 3797 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3798 /* 3799 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3800 * (0x003c) so that we can use it with PEBS. 3801 * 3802 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3803 * PEBS capable. However we can use UOPS_RETIRED.ALL 3804 * (0x01c2), which is a PEBS capable event, to get the same 3805 * count. 3806 * 3807 * UOPS_RETIRED.ALL counts the number of cycles that retires 3808 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3809 * larger than the maximum number of micro-ops that can be 3810 * retired per cycle (4) and then inverting the condition, we 3811 * count all cycles that retire 16 or less micro-ops, which 3812 * is every cycle. 3813 * 3814 * Thereby we gain a PEBS capable cycle counter. 3815 */ 3816 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3817 3818 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3819 event->hw.config = alt_config; 3820 } 3821 } 3822 3823 static void intel_pebs_aliases_precdist(struct perf_event *event) 3824 { 3825 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3826 /* 3827 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3828 * (0x003c) so that we can use it with PEBS. 3829 * 3830 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3831 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3832 * (0x01c0), which is a PEBS capable event, to get the same 3833 * count. 3834 * 3835 * The PREC_DIST event has special support to minimize sample 3836 * shadowing effects. One drawback is that it can be 3837 * only programmed on counter 1, but that seems like an 3838 * acceptable trade off. 3839 */ 3840 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3841 3842 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3843 event->hw.config = alt_config; 3844 } 3845 } 3846 3847 static void intel_pebs_aliases_ivb(struct perf_event *event) 3848 { 3849 if (event->attr.precise_ip < 3) 3850 return intel_pebs_aliases_snb(event); 3851 return intel_pebs_aliases_precdist(event); 3852 } 3853 3854 static void intel_pebs_aliases_skl(struct perf_event *event) 3855 { 3856 if (event->attr.precise_ip < 3) 3857 return intel_pebs_aliases_core2(event); 3858 return intel_pebs_aliases_precdist(event); 3859 } 3860 3861 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3862 { 3863 unsigned long flags = x86_pmu.large_pebs_flags; 3864 3865 if (event->attr.use_clockid) 3866 flags &= ~PERF_SAMPLE_TIME; 3867 if (!event->attr.exclude_kernel) 3868 flags &= ~PERF_SAMPLE_REGS_USER; 3869 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3870 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3871 return flags; 3872 } 3873 3874 static int intel_pmu_bts_config(struct perf_event *event) 3875 { 3876 struct perf_event_attr *attr = &event->attr; 3877 3878 if (unlikely(intel_pmu_has_bts(event))) { 3879 /* BTS is not supported by this architecture. */ 3880 if (!x86_pmu.bts_active) 3881 return -EOPNOTSUPP; 3882 3883 /* BTS is currently only allowed for user-mode. */ 3884 if (!attr->exclude_kernel) 3885 return -EOPNOTSUPP; 3886 3887 /* BTS is not allowed for precise events. */ 3888 if (attr->precise_ip) 3889 return -EOPNOTSUPP; 3890 3891 /* disallow bts if conflicting events are present */ 3892 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3893 return -EBUSY; 3894 3895 event->destroy = hw_perf_lbr_event_destroy; 3896 } 3897 3898 return 0; 3899 } 3900 3901 static int core_pmu_hw_config(struct perf_event *event) 3902 { 3903 int ret = x86_pmu_hw_config(event); 3904 3905 if (ret) 3906 return ret; 3907 3908 return intel_pmu_bts_config(event); 3909 } 3910 3911 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 3912 ((x86_pmu.num_topdown_events - 1) << 8)) 3913 3914 static bool is_available_metric_event(struct perf_event *event) 3915 { 3916 return is_metric_event(event) && 3917 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 3918 } 3919 3920 static inline bool is_mem_loads_event(struct perf_event *event) 3921 { 3922 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 3923 } 3924 3925 static inline bool is_mem_loads_aux_event(struct perf_event *event) 3926 { 3927 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 3928 } 3929 3930 static inline bool require_mem_loads_aux_event(struct perf_event *event) 3931 { 3932 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) 3933 return false; 3934 3935 if (is_hybrid()) 3936 return hybrid_pmu(event->pmu)->pmu_type == hybrid_big; 3937 3938 return true; 3939 } 3940 3941 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) 3942 { 3943 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); 3944 3945 return test_bit(idx, (unsigned long *)&intel_cap->capabilities); 3946 } 3947 3948 static int intel_pmu_hw_config(struct perf_event *event) 3949 { 3950 int ret = x86_pmu_hw_config(event); 3951 3952 if (ret) 3953 return ret; 3954 3955 ret = intel_pmu_bts_config(event); 3956 if (ret) 3957 return ret; 3958 3959 if (event->attr.precise_ip) { 3960 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) 3961 return -EINVAL; 3962 3963 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 3964 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3965 if (!(event->attr.sample_type & ~intel_pmu_large_pebs_flags(event)) && 3966 !has_aux_action(event)) { 3967 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3968 event->attach_state |= PERF_ATTACH_SCHED_CB; 3969 } 3970 } 3971 if (x86_pmu.pebs_aliases) 3972 x86_pmu.pebs_aliases(event); 3973 } 3974 3975 if (needs_branch_stack(event)) { 3976 /* Avoid branch stack setup for counting events in SAMPLE READ */ 3977 if (is_sampling_event(event) || 3978 !(event->attr.sample_type & PERF_SAMPLE_READ)) 3979 event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK; 3980 } 3981 3982 if (branch_sample_counters(event)) { 3983 struct perf_event *leader, *sibling; 3984 int num = 0; 3985 3986 if (!(x86_pmu.flags & PMU_FL_BR_CNTR) || 3987 (event->attr.config & ~INTEL_ARCH_EVENT_MASK)) 3988 return -EINVAL; 3989 3990 /* 3991 * The branch counter logging is not supported in the call stack 3992 * mode yet, since we cannot simply flush the LBR during e.g., 3993 * multiplexing. Also, there is no obvious usage with the call 3994 * stack mode. Simply forbids it for now. 3995 * 3996 * If any events in the group enable the branch counter logging 3997 * feature, the group is treated as a branch counter logging 3998 * group, which requires the extra space to store the counters. 3999 */ 4000 leader = event->group_leader; 4001 if (branch_sample_call_stack(leader)) 4002 return -EINVAL; 4003 if (branch_sample_counters(leader)) 4004 num++; 4005 leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS; 4006 4007 for_each_sibling_event(sibling, leader) { 4008 if (branch_sample_call_stack(sibling)) 4009 return -EINVAL; 4010 if (branch_sample_counters(sibling)) 4011 num++; 4012 } 4013 4014 if (num > fls(x86_pmu.lbr_counters)) 4015 return -EINVAL; 4016 /* 4017 * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't 4018 * require any branch stack setup. 4019 * Clear the bit to avoid unnecessary branch stack setup. 4020 */ 4021 if (0 == (event->attr.branch_sample_type & 4022 ~(PERF_SAMPLE_BRANCH_PLM_ALL | 4023 PERF_SAMPLE_BRANCH_COUNTERS))) 4024 event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK; 4025 4026 /* 4027 * Force the leader to be a LBR event. So LBRs can be reset 4028 * with the leader event. See intel_pmu_lbr_del() for details. 4029 */ 4030 if (!intel_pmu_needs_branch_stack(leader)) 4031 return -EINVAL; 4032 } 4033 4034 if (intel_pmu_needs_branch_stack(event)) { 4035 ret = intel_pmu_setup_lbr_filter(event); 4036 if (ret) 4037 return ret; 4038 event->attach_state |= PERF_ATTACH_SCHED_CB; 4039 4040 /* 4041 * BTS is set up earlier in this path, so don't account twice 4042 */ 4043 if (!unlikely(intel_pmu_has_bts(event))) { 4044 /* disallow lbr if conflicting events are present */ 4045 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 4046 return -EBUSY; 4047 4048 event->destroy = hw_perf_lbr_event_destroy; 4049 } 4050 } 4051 4052 if (event->attr.aux_output) { 4053 if (!event->attr.precise_ip) 4054 return -EINVAL; 4055 4056 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 4057 } 4058 4059 if ((event->attr.type == PERF_TYPE_HARDWARE) || 4060 (event->attr.type == PERF_TYPE_HW_CACHE)) 4061 return 0; 4062 4063 /* 4064 * Config Topdown slots and metric events 4065 * 4066 * The slots event on Fixed Counter 3 can support sampling, 4067 * which will be handled normally in x86_perf_event_update(). 4068 * 4069 * Metric events don't support sampling and require being paired 4070 * with a slots event as group leader. When the slots event 4071 * is used in a metrics group, it too cannot support sampling. 4072 */ 4073 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { 4074 if (event->attr.config1 || event->attr.config2) 4075 return -EINVAL; 4076 4077 /* 4078 * The TopDown metrics events and slots event don't 4079 * support any filters. 4080 */ 4081 if (event->attr.config & X86_ALL_EVENT_FLAGS) 4082 return -EINVAL; 4083 4084 if (is_available_metric_event(event)) { 4085 struct perf_event *leader = event->group_leader; 4086 4087 /* The metric events don't support sampling. */ 4088 if (is_sampling_event(event)) 4089 return -EINVAL; 4090 4091 /* The metric events require a slots group leader. */ 4092 if (!is_slots_event(leader)) 4093 return -EINVAL; 4094 4095 /* 4096 * The leader/SLOTS must not be a sampling event for 4097 * metric use; hardware requires it starts at 0 when used 4098 * in conjunction with MSR_PERF_METRICS. 4099 */ 4100 if (is_sampling_event(leader)) 4101 return -EINVAL; 4102 4103 event->event_caps |= PERF_EV_CAP_SIBLING; 4104 /* 4105 * Only once we have a METRICs sibling do we 4106 * need TopDown magic. 4107 */ 4108 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 4109 event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 4110 } 4111 } 4112 4113 /* 4114 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 4115 * doesn't function quite right. As a work-around it needs to always be 4116 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 4117 * The actual count of this second event is irrelevant it just needs 4118 * to be active to make the first event function correctly. 4119 * 4120 * In a group, the auxiliary event must be in front of the load latency 4121 * event. The rule is to simplify the implementation of the check. 4122 * That's because perf cannot have a complete group at the moment. 4123 */ 4124 if (require_mem_loads_aux_event(event) && 4125 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 4126 is_mem_loads_event(event)) { 4127 struct perf_event *leader = event->group_leader; 4128 struct perf_event *sibling = NULL; 4129 4130 /* 4131 * When this memload event is also the first event (no group 4132 * exists yet), then there is no aux event before it. 4133 */ 4134 if (leader == event) 4135 return -ENODATA; 4136 4137 if (!is_mem_loads_aux_event(leader)) { 4138 for_each_sibling_event(sibling, leader) { 4139 if (is_mem_loads_aux_event(sibling)) 4140 break; 4141 } 4142 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 4143 return -ENODATA; 4144 } 4145 } 4146 4147 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 4148 return 0; 4149 4150 if (x86_pmu.version < 3) 4151 return -EINVAL; 4152 4153 ret = perf_allow_cpu(&event->attr); 4154 if (ret) 4155 return ret; 4156 4157 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 4158 4159 return 0; 4160 } 4161 4162 /* 4163 * Currently, the only caller of this function is the atomic_switch_perf_msrs(). 4164 * The host perf context helps to prepare the values of the real hardware for 4165 * a set of msrs that need to be switched atomically in a vmx transaction. 4166 * 4167 * For example, the pseudocode needed to add a new msr should look like: 4168 * 4169 * arr[(*nr)++] = (struct perf_guest_switch_msr){ 4170 * .msr = the hardware msr address, 4171 * .host = the value the hardware has when it doesn't run a guest, 4172 * .guest = the value the hardware has when it runs a guest, 4173 * }; 4174 * 4175 * These values have nothing to do with the emulated values the guest sees 4176 * when it uses {RD,WR}MSR, which should be handled by the KVM context, 4177 * specifically in the intel_pmu_{get,set}_msr(). 4178 */ 4179 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) 4180 { 4181 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4182 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4183 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data; 4184 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 4185 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; 4186 int global_ctrl, pebs_enable; 4187 4188 /* 4189 * In addition to obeying exclude_guest/exclude_host, remove bits being 4190 * used for PEBS when running a guest, because PEBS writes to virtual 4191 * addresses (not physical addresses). 4192 */ 4193 *nr = 0; 4194 global_ctrl = (*nr)++; 4195 arr[global_ctrl] = (struct perf_guest_switch_msr){ 4196 .msr = MSR_CORE_PERF_GLOBAL_CTRL, 4197 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask, 4198 .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask, 4199 }; 4200 4201 if (!x86_pmu.pebs) 4202 return arr; 4203 4204 /* 4205 * If PMU counter has PEBS enabled it is not enough to 4206 * disable counter on a guest entry since PEBS memory 4207 * write can overshoot guest entry and corrupt guest 4208 * memory. Disabling PEBS solves the problem. 4209 * 4210 * Don't do this if the CPU already enforces it. 4211 */ 4212 if (x86_pmu.pebs_no_isolation) { 4213 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4214 .msr = MSR_IA32_PEBS_ENABLE, 4215 .host = cpuc->pebs_enabled, 4216 .guest = 0, 4217 }; 4218 return arr; 4219 } 4220 4221 if (!kvm_pmu || !x86_pmu.pebs_ept) 4222 return arr; 4223 4224 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4225 .msr = MSR_IA32_DS_AREA, 4226 .host = (unsigned long)cpuc->ds, 4227 .guest = kvm_pmu->ds_area, 4228 }; 4229 4230 if (x86_pmu.intel_cap.pebs_baseline) { 4231 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4232 .msr = MSR_PEBS_DATA_CFG, 4233 .host = cpuc->active_pebs_data_cfg, 4234 .guest = kvm_pmu->pebs_data_cfg, 4235 }; 4236 } 4237 4238 pebs_enable = (*nr)++; 4239 arr[pebs_enable] = (struct perf_guest_switch_msr){ 4240 .msr = MSR_IA32_PEBS_ENABLE, 4241 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask, 4242 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask, 4243 }; 4244 4245 if (arr[pebs_enable].host) { 4246 /* Disable guest PEBS if host PEBS is enabled. */ 4247 arr[pebs_enable].guest = 0; 4248 } else { 4249 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */ 4250 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask; 4251 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask; 4252 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ 4253 arr[global_ctrl].guest |= arr[pebs_enable].guest; 4254 } 4255 4256 return arr; 4257 } 4258 4259 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data) 4260 { 4261 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4262 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4263 int idx; 4264 4265 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { 4266 struct perf_event *event = cpuc->events[idx]; 4267 4268 arr[idx].msr = x86_pmu_config_addr(idx); 4269 arr[idx].host = arr[idx].guest = 0; 4270 4271 if (!test_bit(idx, cpuc->active_mask)) 4272 continue; 4273 4274 arr[idx].host = arr[idx].guest = 4275 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 4276 4277 if (event->attr.exclude_host) 4278 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4279 else if (event->attr.exclude_guest) 4280 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4281 } 4282 4283 *nr = x86_pmu_max_num_counters(cpuc->pmu); 4284 return arr; 4285 } 4286 4287 static void core_pmu_enable_event(struct perf_event *event) 4288 { 4289 if (!event->attr.exclude_host) 4290 x86_pmu_enable_event(event); 4291 } 4292 4293 static void core_pmu_enable_all(int added) 4294 { 4295 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4296 int idx; 4297 4298 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { 4299 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 4300 4301 if (!test_bit(idx, cpuc->active_mask) || 4302 cpuc->events[idx]->attr.exclude_host) 4303 continue; 4304 4305 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 4306 } 4307 } 4308 4309 static int hsw_hw_config(struct perf_event *event) 4310 { 4311 int ret = intel_pmu_hw_config(event); 4312 4313 if (ret) 4314 return ret; 4315 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 4316 return 0; 4317 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 4318 4319 /* 4320 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 4321 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 4322 * this combination. 4323 */ 4324 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 4325 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 4326 event->attr.precise_ip > 0)) 4327 return -EOPNOTSUPP; 4328 4329 if (event_is_checkpointed(event)) { 4330 /* 4331 * Sampling of checkpointed events can cause situations where 4332 * the CPU constantly aborts because of a overflow, which is 4333 * then checkpointed back and ignored. Forbid checkpointing 4334 * for sampling. 4335 * 4336 * But still allow a long sampling period, so that perf stat 4337 * from KVM works. 4338 */ 4339 if (event->attr.sample_period > 0 && 4340 event->attr.sample_period < 0x7fffffff) 4341 return -EOPNOTSUPP; 4342 } 4343 return 0; 4344 } 4345 4346 static struct event_constraint counter0_constraint = 4347 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 4348 4349 static struct event_constraint counter1_constraint = 4350 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2); 4351 4352 static struct event_constraint counter0_1_constraint = 4353 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3); 4354 4355 static struct event_constraint counter2_constraint = 4356 EVENT_CONSTRAINT(0, 0x4, 0); 4357 4358 static struct event_constraint fixed0_constraint = 4359 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 4360 4361 static struct event_constraint fixed0_counter0_constraint = 4362 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 4363 4364 static struct event_constraint fixed0_counter0_1_constraint = 4365 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL); 4366 4367 static struct event_constraint counters_1_7_constraint = 4368 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL); 4369 4370 static struct event_constraint * 4371 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4372 struct perf_event *event) 4373 { 4374 struct event_constraint *c; 4375 4376 c = intel_get_event_constraints(cpuc, idx, event); 4377 4378 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 4379 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 4380 if (c->idxmsk64 & (1U << 2)) 4381 return &counter2_constraint; 4382 return &emptyconstraint; 4383 } 4384 4385 return c; 4386 } 4387 4388 static struct event_constraint * 4389 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4390 struct perf_event *event) 4391 { 4392 /* 4393 * Fixed counter 0 has less skid. 4394 * Force instruction:ppp in Fixed counter 0 4395 */ 4396 if ((event->attr.precise_ip == 3) && 4397 constraint_match(&fixed0_constraint, event->hw.config)) 4398 return &fixed0_constraint; 4399 4400 return hsw_get_event_constraints(cpuc, idx, event); 4401 } 4402 4403 static struct event_constraint * 4404 glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4405 struct perf_event *event) 4406 { 4407 struct event_constraint *c; 4408 4409 c = icl_get_event_constraints(cpuc, idx, event); 4410 4411 /* 4412 * The :ppp indicates the Precise Distribution (PDist) facility, which 4413 * is only supported on the GP counter 0. If a :ppp event which is not 4414 * available on the GP counter 0, error out. 4415 * Exception: Instruction PDIR is only available on the fixed counter 0. 4416 */ 4417 if ((event->attr.precise_ip == 3) && 4418 !constraint_match(&fixed0_constraint, event->hw.config)) { 4419 if (c->idxmsk64 & BIT_ULL(0)) 4420 return &counter0_constraint; 4421 4422 return &emptyconstraint; 4423 } 4424 4425 return c; 4426 } 4427 4428 static struct event_constraint * 4429 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4430 struct perf_event *event) 4431 { 4432 struct event_constraint *c; 4433 4434 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 4435 if (event->attr.precise_ip == 3) 4436 return &counter0_constraint; 4437 4438 c = intel_get_event_constraints(cpuc, idx, event); 4439 4440 return c; 4441 } 4442 4443 static struct event_constraint * 4444 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4445 struct perf_event *event) 4446 { 4447 struct event_constraint *c; 4448 4449 c = intel_get_event_constraints(cpuc, idx, event); 4450 4451 /* 4452 * :ppp means to do reduced skid PEBS, 4453 * which is available on PMC0 and fixed counter 0. 4454 */ 4455 if (event->attr.precise_ip == 3) { 4456 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 4457 if (constraint_match(&fixed0_constraint, event->hw.config)) 4458 return &fixed0_counter0_constraint; 4459 4460 return &counter0_constraint; 4461 } 4462 4463 return c; 4464 } 4465 4466 static bool allow_tsx_force_abort = true; 4467 4468 static struct event_constraint * 4469 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4470 struct perf_event *event) 4471 { 4472 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 4473 4474 /* 4475 * Without TFA we must not use PMC3. 4476 */ 4477 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 4478 c = dyn_constraint(cpuc, c, idx); 4479 c->idxmsk64 &= ~(1ULL << 3); 4480 c->weight--; 4481 } 4482 4483 return c; 4484 } 4485 4486 static struct event_constraint * 4487 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4488 struct perf_event *event) 4489 { 4490 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4491 4492 if (pmu->pmu_type == hybrid_big) 4493 return glc_get_event_constraints(cpuc, idx, event); 4494 else if (pmu->pmu_type == hybrid_small) 4495 return tnt_get_event_constraints(cpuc, idx, event); 4496 4497 WARN_ON(1); 4498 return &emptyconstraint; 4499 } 4500 4501 static struct event_constraint * 4502 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4503 struct perf_event *event) 4504 { 4505 struct event_constraint *c; 4506 4507 c = intel_get_event_constraints(cpuc, idx, event); 4508 4509 /* 4510 * The :ppp indicates the Precise Distribution (PDist) facility, which 4511 * is only supported on the GP counter 0 & 1 and Fixed counter 0. 4512 * If a :ppp event which is not available on the above eligible counters, 4513 * error out. 4514 */ 4515 if (event->attr.precise_ip == 3) { 4516 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */ 4517 if (constraint_match(&fixed0_constraint, event->hw.config)) { 4518 /* The fixed counter 0 doesn't support LBR event logging. */ 4519 if (branch_sample_counters(event)) 4520 return &counter0_1_constraint; 4521 else 4522 return &fixed0_counter0_1_constraint; 4523 } 4524 4525 switch (c->idxmsk64 & 0x3ull) { 4526 case 0x1: 4527 return &counter0_constraint; 4528 case 0x2: 4529 return &counter1_constraint; 4530 case 0x3: 4531 return &counter0_1_constraint; 4532 } 4533 return &emptyconstraint; 4534 } 4535 4536 return c; 4537 } 4538 4539 static struct event_constraint * 4540 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4541 struct perf_event *event) 4542 { 4543 struct event_constraint *c; 4544 4545 c = glc_get_event_constraints(cpuc, idx, event); 4546 4547 /* The Retire Latency is not supported by the fixed counter 0. */ 4548 if (event->attr.precise_ip && 4549 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) && 4550 constraint_match(&fixed0_constraint, event->hw.config)) { 4551 /* 4552 * The Instruction PDIR is only available 4553 * on the fixed counter 0. Error out for this case. 4554 */ 4555 if (event->attr.precise_ip == 3) 4556 return &emptyconstraint; 4557 return &counters_1_7_constraint; 4558 } 4559 4560 return c; 4561 } 4562 4563 static struct event_constraint * 4564 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4565 struct perf_event *event) 4566 { 4567 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4568 4569 if (pmu->pmu_type == hybrid_big) 4570 return rwc_get_event_constraints(cpuc, idx, event); 4571 if (pmu->pmu_type == hybrid_small) 4572 return cmt_get_event_constraints(cpuc, idx, event); 4573 4574 WARN_ON(1); 4575 return &emptyconstraint; 4576 } 4577 4578 static int adl_hw_config(struct perf_event *event) 4579 { 4580 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4581 4582 if (pmu->pmu_type == hybrid_big) 4583 return hsw_hw_config(event); 4584 else if (pmu->pmu_type == hybrid_small) 4585 return intel_pmu_hw_config(event); 4586 4587 WARN_ON(1); 4588 return -EOPNOTSUPP; 4589 } 4590 4591 static enum hybrid_cpu_type adl_get_hybrid_cpu_type(void) 4592 { 4593 return HYBRID_INTEL_CORE; 4594 } 4595 4596 static inline bool erratum_hsw11(struct perf_event *event) 4597 { 4598 return (event->hw.config & INTEL_ARCH_EVENT_MASK) == 4599 X86_CONFIG(.event=0xc0, .umask=0x01); 4600 } 4601 4602 static struct event_constraint * 4603 arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4604 struct perf_event *event) 4605 { 4606 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4607 4608 if (pmu->pmu_type == hybrid_tiny) 4609 return cmt_get_event_constraints(cpuc, idx, event); 4610 4611 return mtl_get_event_constraints(cpuc, idx, event); 4612 } 4613 4614 static int arl_h_hw_config(struct perf_event *event) 4615 { 4616 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4617 4618 if (pmu->pmu_type == hybrid_tiny) 4619 return intel_pmu_hw_config(event); 4620 4621 return adl_hw_config(event); 4622 } 4623 4624 /* 4625 * The HSW11 requires a period larger than 100 which is the same as the BDM11. 4626 * A minimum period of 128 is enforced as well for the INST_RETIRED.ALL. 4627 * 4628 * The message 'interrupt took too long' can be observed on any counter which 4629 * was armed with a period < 32 and two events expired in the same NMI. 4630 * A minimum period of 32 is enforced for the rest of the events. 4631 */ 4632 static void hsw_limit_period(struct perf_event *event, s64 *left) 4633 { 4634 *left = max(*left, erratum_hsw11(event) ? 128 : 32); 4635 } 4636 4637 /* 4638 * Broadwell: 4639 * 4640 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 4641 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 4642 * the two to enforce a minimum period of 128 (the smallest value that has bits 4643 * 0-5 cleared and >= 100). 4644 * 4645 * Because of how the code in x86_perf_event_set_period() works, the truncation 4646 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 4647 * to make up for the 'lost' events due to carrying the 'error' in period_left. 4648 * 4649 * Therefore the effective (average) period matches the requested period, 4650 * despite coarser hardware granularity. 4651 */ 4652 static void bdw_limit_period(struct perf_event *event, s64 *left) 4653 { 4654 if (erratum_hsw11(event)) { 4655 if (*left < 128) 4656 *left = 128; 4657 *left &= ~0x3fULL; 4658 } 4659 } 4660 4661 static void nhm_limit_period(struct perf_event *event, s64 *left) 4662 { 4663 *left = max(*left, 32LL); 4664 } 4665 4666 static void glc_limit_period(struct perf_event *event, s64 *left) 4667 { 4668 if (event->attr.precise_ip == 3) 4669 *left = max(*left, 128LL); 4670 } 4671 4672 PMU_FORMAT_ATTR(event, "config:0-7" ); 4673 PMU_FORMAT_ATTR(umask, "config:8-15" ); 4674 PMU_FORMAT_ATTR(edge, "config:18" ); 4675 PMU_FORMAT_ATTR(pc, "config:19" ); 4676 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 4677 PMU_FORMAT_ATTR(inv, "config:23" ); 4678 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 4679 PMU_FORMAT_ATTR(in_tx, "config:32" ); 4680 PMU_FORMAT_ATTR(in_tx_cp, "config:33" ); 4681 PMU_FORMAT_ATTR(eq, "config:36" ); /* v6 + */ 4682 4683 static ssize_t umask2_show(struct device *dev, 4684 struct device_attribute *attr, 4685 char *page) 4686 { 4687 u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2; 4688 4689 if (mask == ARCH_PERFMON_EVENTSEL_UMASK2) 4690 return sprintf(page, "config:8-15,40-47\n"); 4691 4692 /* Roll back to the old format if umask2 is not supported. */ 4693 return sprintf(page, "config:8-15\n"); 4694 } 4695 4696 static struct device_attribute format_attr_umask2 = 4697 __ATTR(umask, 0444, umask2_show, NULL); 4698 4699 static struct attribute *format_evtsel_ext_attrs[] = { 4700 &format_attr_umask2.attr, 4701 &format_attr_eq.attr, 4702 NULL 4703 }; 4704 4705 static umode_t 4706 evtsel_ext_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4707 { 4708 struct device *dev = kobj_to_dev(kobj); 4709 u64 mask; 4710 4711 /* 4712 * The umask and umask2 have different formats but share the 4713 * same attr name. In update mode, the previous value of the 4714 * umask is unconditionally removed before is_visible. If 4715 * umask2 format is not enumerated, it's impossible to roll 4716 * back to the old format. 4717 * Does the check in umask2_show rather than is_visible. 4718 */ 4719 if (i == 0) 4720 return attr->mode; 4721 4722 mask = hybrid(dev_get_drvdata(dev), config_mask); 4723 if (i == 1) 4724 return (mask & ARCH_PERFMON_EVENTSEL_EQ) ? attr->mode : 0; 4725 4726 return 0; 4727 } 4728 4729 static struct attribute *intel_arch_formats_attr[] = { 4730 &format_attr_event.attr, 4731 &format_attr_umask.attr, 4732 &format_attr_edge.attr, 4733 &format_attr_pc.attr, 4734 &format_attr_inv.attr, 4735 &format_attr_cmask.attr, 4736 NULL, 4737 }; 4738 4739 ssize_t intel_event_sysfs_show(char *page, u64 config) 4740 { 4741 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 4742 4743 return x86_event_sysfs_show(page, config, event); 4744 } 4745 4746 static struct intel_shared_regs *allocate_shared_regs(int cpu) 4747 { 4748 struct intel_shared_regs *regs; 4749 int i; 4750 4751 regs = kzalloc_node(sizeof(struct intel_shared_regs), 4752 GFP_KERNEL, cpu_to_node(cpu)); 4753 if (regs) { 4754 /* 4755 * initialize the locks to keep lockdep happy 4756 */ 4757 for (i = 0; i < EXTRA_REG_MAX; i++) 4758 raw_spin_lock_init(®s->regs[i].lock); 4759 4760 regs->core_id = -1; 4761 } 4762 return regs; 4763 } 4764 4765 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 4766 { 4767 struct intel_excl_cntrs *c; 4768 4769 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 4770 GFP_KERNEL, cpu_to_node(cpu)); 4771 if (c) { 4772 raw_spin_lock_init(&c->lock); 4773 c->core_id = -1; 4774 } 4775 return c; 4776 } 4777 4778 4779 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 4780 { 4781 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 4782 4783 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 4784 cpuc->shared_regs = allocate_shared_regs(cpu); 4785 if (!cpuc->shared_regs) 4786 goto err; 4787 } 4788 4789 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_BR_CNTR)) { 4790 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 4791 4792 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 4793 if (!cpuc->constraint_list) 4794 goto err_shared_regs; 4795 } 4796 4797 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4798 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 4799 if (!cpuc->excl_cntrs) 4800 goto err_constraint_list; 4801 4802 cpuc->excl_thread_id = 0; 4803 } 4804 4805 return 0; 4806 4807 err_constraint_list: 4808 kfree(cpuc->constraint_list); 4809 cpuc->constraint_list = NULL; 4810 4811 err_shared_regs: 4812 kfree(cpuc->shared_regs); 4813 cpuc->shared_regs = NULL; 4814 4815 err: 4816 return -ENOMEM; 4817 } 4818 4819 static int intel_pmu_cpu_prepare(int cpu) 4820 { 4821 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 4822 } 4823 4824 static void flip_smm_bit(void *data) 4825 { 4826 unsigned long set = *(unsigned long *)data; 4827 4828 if (set > 0) { 4829 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 4830 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4831 } else { 4832 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 4833 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4834 } 4835 } 4836 4837 static void intel_pmu_check_counters_mask(u64 *cntr_mask, 4838 u64 *fixed_cntr_mask, 4839 u64 *intel_ctrl) 4840 { 4841 unsigned int bit; 4842 4843 bit = fls64(*cntr_mask); 4844 if (bit > INTEL_PMC_MAX_GENERIC) { 4845 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 4846 bit, INTEL_PMC_MAX_GENERIC); 4847 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); 4848 } 4849 *intel_ctrl = *cntr_mask; 4850 4851 bit = fls64(*fixed_cntr_mask); 4852 if (bit > INTEL_PMC_MAX_FIXED) { 4853 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 4854 bit, INTEL_PMC_MAX_FIXED); 4855 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0); 4856 } 4857 4858 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED; 4859 } 4860 4861 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 4862 u64 cntr_mask, 4863 u64 fixed_cntr_mask, 4864 u64 intel_ctrl); 4865 4866 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs); 4867 4868 static inline bool intel_pmu_broken_perf_cap(void) 4869 { 4870 /* The Perf Metric (Bit 15) is always cleared */ 4871 if (boot_cpu_data.x86_vfm == INTEL_METEORLAKE || 4872 boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L) 4873 return true; 4874 4875 return false; 4876 } 4877 4878 static void update_pmu_cap(struct x86_hybrid_pmu *pmu) 4879 { 4880 unsigned int sub_bitmaps, eax, ebx, ecx, edx; 4881 4882 cpuid(ARCH_PERFMON_EXT_LEAF, &sub_bitmaps, &ebx, &ecx, &edx); 4883 4884 if (ebx & ARCH_PERFMON_EXT_UMASK2) 4885 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_UMASK2; 4886 if (ebx & ARCH_PERFMON_EXT_EQ) 4887 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_EQ; 4888 4889 if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF_BIT) { 4890 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF, 4891 &eax, &ebx, &ecx, &edx); 4892 pmu->cntr_mask64 = eax; 4893 pmu->fixed_cntr_mask64 = ebx; 4894 } 4895 4896 if (!intel_pmu_broken_perf_cap()) { 4897 /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */ 4898 rdmsrl(MSR_IA32_PERF_CAPABILITIES, pmu->intel_cap.capabilities); 4899 } 4900 } 4901 4902 static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu) 4903 { 4904 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64, 4905 &pmu->intel_ctrl); 4906 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 4907 pmu->unconstrained = (struct event_constraint) 4908 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 4909 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 4910 4911 if (pmu->intel_cap.perf_metrics) 4912 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 4913 else 4914 pmu->intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 4915 4916 if (pmu->intel_cap.pebs_output_pt_available) 4917 pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT; 4918 else 4919 pmu->pmu.capabilities &= ~PERF_PMU_CAP_AUX_OUTPUT; 4920 4921 intel_pmu_check_event_constraints(pmu->event_constraints, 4922 pmu->cntr_mask64, 4923 pmu->fixed_cntr_mask64, 4924 pmu->intel_ctrl); 4925 4926 intel_pmu_check_extra_regs(pmu->extra_regs); 4927 } 4928 4929 static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void) 4930 { 4931 u8 cpu_type = get_this_hybrid_cpu_type(); 4932 int i; 4933 4934 /* 4935 * This is running on a CPU model that is known to have hybrid 4936 * configurations. But the CPU told us it is not hybrid, shame 4937 * on it. There should be a fixup function provided for these 4938 * troublesome CPUs (->get_hybrid_cpu_type). 4939 */ 4940 if (cpu_type == HYBRID_INTEL_NONE) { 4941 if (x86_pmu.get_hybrid_cpu_type) 4942 cpu_type = x86_pmu.get_hybrid_cpu_type(); 4943 else 4944 return NULL; 4945 } 4946 4947 /* 4948 * This essentially just maps between the 'hybrid_cpu_type' 4949 * and 'hybrid_pmu_type' enums except for ARL-H processor 4950 * which needs to compare atom uarch native id since ARL-H 4951 * contains two different atom uarchs. 4952 */ 4953 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 4954 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type; 4955 u32 native_id; 4956 4957 if (cpu_type == HYBRID_INTEL_CORE && pmu_type == hybrid_big) 4958 return &x86_pmu.hybrid_pmu[i]; 4959 if (cpu_type == HYBRID_INTEL_ATOM) { 4960 if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small) 4961 return &x86_pmu.hybrid_pmu[i]; 4962 4963 native_id = get_this_hybrid_cpu_native_id(); 4964 if (native_id == skt_native_id && pmu_type == hybrid_small) 4965 return &x86_pmu.hybrid_pmu[i]; 4966 if (native_id == cmt_native_id && pmu_type == hybrid_tiny) 4967 return &x86_pmu.hybrid_pmu[i]; 4968 } 4969 } 4970 4971 return NULL; 4972 } 4973 4974 static bool init_hybrid_pmu(int cpu) 4975 { 4976 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4977 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu(); 4978 4979 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { 4980 cpuc->pmu = NULL; 4981 return false; 4982 } 4983 4984 /* Only check and dump the PMU information for the first CPU */ 4985 if (!cpumask_empty(&pmu->supported_cpus)) 4986 goto end; 4987 4988 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) 4989 update_pmu_cap(pmu); 4990 4991 intel_pmu_check_hybrid_pmus(pmu); 4992 4993 if (!check_hw_exists(&pmu->pmu, pmu->cntr_mask, pmu->fixed_cntr_mask)) 4994 return false; 4995 4996 pr_info("%s PMU driver: ", pmu->name); 4997 4998 if (pmu->intel_cap.pebs_output_pt_available) 4999 pr_cont("PEBS-via-PT "); 5000 5001 pr_cont("\n"); 5002 5003 x86_pmu_show_pmu_cap(&pmu->pmu); 5004 5005 end: 5006 cpumask_set_cpu(cpu, &pmu->supported_cpus); 5007 cpuc->pmu = &pmu->pmu; 5008 5009 return true; 5010 } 5011 5012 static void intel_pmu_cpu_starting(int cpu) 5013 { 5014 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 5015 int core_id = topology_core_id(cpu); 5016 int i; 5017 5018 if (is_hybrid() && !init_hybrid_pmu(cpu)) 5019 return; 5020 5021 init_debug_store_on_cpu(cpu); 5022 /* 5023 * Deal with CPUs that don't clear their LBRs on power-up. 5024 */ 5025 intel_pmu_lbr_reset(); 5026 5027 cpuc->lbr_sel = NULL; 5028 5029 if (x86_pmu.flags & PMU_FL_TFA) { 5030 WARN_ON_ONCE(cpuc->tfa_shadow); 5031 cpuc->tfa_shadow = ~0ULL; 5032 intel_set_tfa(cpuc, false); 5033 } 5034 5035 if (x86_pmu.version > 1) 5036 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 5037 5038 /* 5039 * Disable perf metrics if any added CPU doesn't support it. 5040 * 5041 * Turn off the check for a hybrid architecture, because the 5042 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate 5043 * the architecture features. The perf metrics is a model-specific 5044 * feature for now. The corresponding bit should always be 0 on 5045 * a hybrid platform, e.g., Alder Lake. 5046 */ 5047 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 5048 union perf_capabilities perf_cap; 5049 5050 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 5051 if (!perf_cap.perf_metrics) { 5052 x86_pmu.intel_cap.perf_metrics = 0; 5053 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 5054 } 5055 } 5056 5057 if (!cpuc->shared_regs) 5058 return; 5059 5060 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 5061 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 5062 struct intel_shared_regs *pc; 5063 5064 pc = per_cpu(cpu_hw_events, i).shared_regs; 5065 if (pc && pc->core_id == core_id) { 5066 cpuc->kfree_on_online[0] = cpuc->shared_regs; 5067 cpuc->shared_regs = pc; 5068 break; 5069 } 5070 } 5071 cpuc->shared_regs->core_id = core_id; 5072 cpuc->shared_regs->refcnt++; 5073 } 5074 5075 if (x86_pmu.lbr_sel_map) 5076 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 5077 5078 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 5079 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 5080 struct cpu_hw_events *sibling; 5081 struct intel_excl_cntrs *c; 5082 5083 sibling = &per_cpu(cpu_hw_events, i); 5084 c = sibling->excl_cntrs; 5085 if (c && c->core_id == core_id) { 5086 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 5087 cpuc->excl_cntrs = c; 5088 if (!sibling->excl_thread_id) 5089 cpuc->excl_thread_id = 1; 5090 break; 5091 } 5092 } 5093 cpuc->excl_cntrs->core_id = core_id; 5094 cpuc->excl_cntrs->refcnt++; 5095 } 5096 } 5097 5098 static void free_excl_cntrs(struct cpu_hw_events *cpuc) 5099 { 5100 struct intel_excl_cntrs *c; 5101 5102 c = cpuc->excl_cntrs; 5103 if (c) { 5104 if (c->core_id == -1 || --c->refcnt == 0) 5105 kfree(c); 5106 cpuc->excl_cntrs = NULL; 5107 } 5108 5109 kfree(cpuc->constraint_list); 5110 cpuc->constraint_list = NULL; 5111 } 5112 5113 static void intel_pmu_cpu_dying(int cpu) 5114 { 5115 fini_debug_store_on_cpu(cpu); 5116 } 5117 5118 void intel_cpuc_finish(struct cpu_hw_events *cpuc) 5119 { 5120 struct intel_shared_regs *pc; 5121 5122 pc = cpuc->shared_regs; 5123 if (pc) { 5124 if (pc->core_id == -1 || --pc->refcnt == 0) 5125 kfree(pc); 5126 cpuc->shared_regs = NULL; 5127 } 5128 5129 free_excl_cntrs(cpuc); 5130 } 5131 5132 static void intel_pmu_cpu_dead(int cpu) 5133 { 5134 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 5135 5136 intel_cpuc_finish(cpuc); 5137 5138 if (is_hybrid() && cpuc->pmu) 5139 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); 5140 } 5141 5142 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, 5143 bool sched_in) 5144 { 5145 intel_pmu_pebs_sched_task(pmu_ctx, sched_in); 5146 intel_pmu_lbr_sched_task(pmu_ctx, sched_in); 5147 } 5148 5149 static void intel_pmu_swap_task_ctx(struct perf_event_pmu_context *prev_epc, 5150 struct perf_event_pmu_context *next_epc) 5151 { 5152 intel_pmu_lbr_swap_task_ctx(prev_epc, next_epc); 5153 } 5154 5155 static int intel_pmu_check_period(struct perf_event *event, u64 value) 5156 { 5157 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 5158 } 5159 5160 static void intel_aux_output_init(void) 5161 { 5162 /* Refer also intel_pmu_aux_output_match() */ 5163 if (x86_pmu.intel_cap.pebs_output_pt_available) 5164 x86_pmu.assign = intel_pmu_assign_event; 5165 } 5166 5167 static int intel_pmu_aux_output_match(struct perf_event *event) 5168 { 5169 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */ 5170 if (!x86_pmu.intel_cap.pebs_output_pt_available) 5171 return 0; 5172 5173 return is_intel_pt_event(event); 5174 } 5175 5176 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret) 5177 { 5178 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu); 5179 5180 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus); 5181 } 5182 5183 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 5184 5185 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 5186 5187 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 5188 5189 PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63"); 5190 5191 static struct attribute *intel_arch3_formats_attr[] = { 5192 &format_attr_event.attr, 5193 &format_attr_umask.attr, 5194 &format_attr_edge.attr, 5195 &format_attr_pc.attr, 5196 &format_attr_any.attr, 5197 &format_attr_inv.attr, 5198 &format_attr_cmask.attr, 5199 NULL, 5200 }; 5201 5202 static struct attribute *hsw_format_attr[] = { 5203 &format_attr_in_tx.attr, 5204 &format_attr_in_tx_cp.attr, 5205 &format_attr_offcore_rsp.attr, 5206 &format_attr_ldlat.attr, 5207 NULL 5208 }; 5209 5210 static struct attribute *nhm_format_attr[] = { 5211 &format_attr_offcore_rsp.attr, 5212 &format_attr_ldlat.attr, 5213 NULL 5214 }; 5215 5216 static struct attribute *slm_format_attr[] = { 5217 &format_attr_offcore_rsp.attr, 5218 NULL 5219 }; 5220 5221 static struct attribute *cmt_format_attr[] = { 5222 &format_attr_offcore_rsp.attr, 5223 &format_attr_ldlat.attr, 5224 &format_attr_snoop_rsp.attr, 5225 NULL 5226 }; 5227 5228 static struct attribute *skl_format_attr[] = { 5229 &format_attr_frontend.attr, 5230 NULL, 5231 }; 5232 5233 static __initconst const struct x86_pmu core_pmu = { 5234 .name = "core", 5235 .handle_irq = x86_pmu_handle_irq, 5236 .disable_all = x86_pmu_disable_all, 5237 .enable_all = core_pmu_enable_all, 5238 .enable = core_pmu_enable_event, 5239 .disable = x86_pmu_disable_event, 5240 .hw_config = core_pmu_hw_config, 5241 .schedule_events = x86_schedule_events, 5242 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 5243 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 5244 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0, 5245 .event_map = intel_pmu_event_map, 5246 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 5247 .apic = 1, 5248 .large_pebs_flags = LARGE_PEBS_FLAGS, 5249 5250 /* 5251 * Intel PMCs cannot be accessed sanely above 32-bit width, 5252 * so we install an artificial 1<<31 period regardless of 5253 * the generic event period: 5254 */ 5255 .max_period = (1ULL<<31) - 1, 5256 .get_event_constraints = intel_get_event_constraints, 5257 .put_event_constraints = intel_put_event_constraints, 5258 .event_constraints = intel_core_event_constraints, 5259 .guest_get_msrs = core_guest_get_msrs, 5260 .format_attrs = intel_arch_formats_attr, 5261 .events_sysfs_show = intel_event_sysfs_show, 5262 5263 /* 5264 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 5265 * together with PMU version 1 and thus be using core_pmu with 5266 * shared_regs. We need following callbacks here to allocate 5267 * it properly. 5268 */ 5269 .cpu_prepare = intel_pmu_cpu_prepare, 5270 .cpu_starting = intel_pmu_cpu_starting, 5271 .cpu_dying = intel_pmu_cpu_dying, 5272 .cpu_dead = intel_pmu_cpu_dead, 5273 5274 .check_period = intel_pmu_check_period, 5275 5276 .lbr_reset = intel_pmu_lbr_reset_64, 5277 .lbr_read = intel_pmu_lbr_read_64, 5278 .lbr_save = intel_pmu_lbr_save, 5279 .lbr_restore = intel_pmu_lbr_restore, 5280 }; 5281 5282 static __initconst const struct x86_pmu intel_pmu = { 5283 .name = "Intel", 5284 .handle_irq = intel_pmu_handle_irq, 5285 .disable_all = intel_pmu_disable_all, 5286 .enable_all = intel_pmu_enable_all, 5287 .enable = intel_pmu_enable_event, 5288 .disable = intel_pmu_disable_event, 5289 .add = intel_pmu_add_event, 5290 .del = intel_pmu_del_event, 5291 .read = intel_pmu_read_event, 5292 .set_period = intel_pmu_set_period, 5293 .update = intel_pmu_update, 5294 .hw_config = intel_pmu_hw_config, 5295 .schedule_events = x86_schedule_events, 5296 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 5297 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 5298 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0, 5299 .event_map = intel_pmu_event_map, 5300 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 5301 .apic = 1, 5302 .large_pebs_flags = LARGE_PEBS_FLAGS, 5303 /* 5304 * Intel PMCs cannot be accessed sanely above 32 bit width, 5305 * so we install an artificial 1<<31 period regardless of 5306 * the generic event period: 5307 */ 5308 .max_period = (1ULL << 31) - 1, 5309 .get_event_constraints = intel_get_event_constraints, 5310 .put_event_constraints = intel_put_event_constraints, 5311 .pebs_aliases = intel_pebs_aliases_core2, 5312 5313 .format_attrs = intel_arch3_formats_attr, 5314 .events_sysfs_show = intel_event_sysfs_show, 5315 5316 .cpu_prepare = intel_pmu_cpu_prepare, 5317 .cpu_starting = intel_pmu_cpu_starting, 5318 .cpu_dying = intel_pmu_cpu_dying, 5319 .cpu_dead = intel_pmu_cpu_dead, 5320 5321 .guest_get_msrs = intel_guest_get_msrs, 5322 .sched_task = intel_pmu_sched_task, 5323 .swap_task_ctx = intel_pmu_swap_task_ctx, 5324 5325 .check_period = intel_pmu_check_period, 5326 5327 .aux_output_match = intel_pmu_aux_output_match, 5328 5329 .lbr_reset = intel_pmu_lbr_reset_64, 5330 .lbr_read = intel_pmu_lbr_read_64, 5331 .lbr_save = intel_pmu_lbr_save, 5332 .lbr_restore = intel_pmu_lbr_restore, 5333 5334 /* 5335 * SMM has access to all 4 rings and while traditionally SMM code only 5336 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM. 5337 * 5338 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction 5339 * between SMM or not, this results in what should be pure userspace 5340 * counters including SMM data. 5341 * 5342 * This is a clear privilege issue, therefore globally disable 5343 * counting SMM by default. 5344 */ 5345 .attr_freeze_on_smi = 1, 5346 }; 5347 5348 static __init void intel_clovertown_quirk(void) 5349 { 5350 /* 5351 * PEBS is unreliable due to: 5352 * 5353 * AJ67 - PEBS may experience CPL leaks 5354 * AJ68 - PEBS PMI may be delayed by one event 5355 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 5356 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 5357 * 5358 * AJ67 could be worked around by restricting the OS/USR flags. 5359 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 5360 * 5361 * AJ106 could possibly be worked around by not allowing LBR 5362 * usage from PEBS, including the fixup. 5363 * AJ68 could possibly be worked around by always programming 5364 * a pebs_event_reset[0] value and coping with the lost events. 5365 * 5366 * But taken together it might just make sense to not enable PEBS on 5367 * these chips. 5368 */ 5369 pr_warn("PEBS disabled due to CPU errata\n"); 5370 x86_pmu.pebs = 0; 5371 x86_pmu.pebs_constraints = NULL; 5372 } 5373 5374 static const struct x86_cpu_desc isolation_ucodes[] = { 5375 INTEL_CPU_DESC(INTEL_HASWELL, 3, 0x0000001f), 5376 INTEL_CPU_DESC(INTEL_HASWELL_L, 1, 0x0000001e), 5377 INTEL_CPU_DESC(INTEL_HASWELL_G, 1, 0x00000015), 5378 INTEL_CPU_DESC(INTEL_HASWELL_X, 2, 0x00000037), 5379 INTEL_CPU_DESC(INTEL_HASWELL_X, 4, 0x0000000a), 5380 INTEL_CPU_DESC(INTEL_BROADWELL, 4, 0x00000023), 5381 INTEL_CPU_DESC(INTEL_BROADWELL_G, 1, 0x00000014), 5382 INTEL_CPU_DESC(INTEL_BROADWELL_D, 2, 0x00000010), 5383 INTEL_CPU_DESC(INTEL_BROADWELL_D, 3, 0x07000009), 5384 INTEL_CPU_DESC(INTEL_BROADWELL_D, 4, 0x0f000009), 5385 INTEL_CPU_DESC(INTEL_BROADWELL_D, 5, 0x0e000002), 5386 INTEL_CPU_DESC(INTEL_BROADWELL_X, 1, 0x0b000014), 5387 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 3, 0x00000021), 5388 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 4, 0x00000000), 5389 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 5, 0x00000000), 5390 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 6, 0x00000000), 5391 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 7, 0x00000000), 5392 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 11, 0x00000000), 5393 INTEL_CPU_DESC(INTEL_SKYLAKE_L, 3, 0x0000007c), 5394 INTEL_CPU_DESC(INTEL_SKYLAKE, 3, 0x0000007c), 5395 INTEL_CPU_DESC(INTEL_KABYLAKE, 9, 0x0000004e), 5396 INTEL_CPU_DESC(INTEL_KABYLAKE_L, 9, 0x0000004e), 5397 INTEL_CPU_DESC(INTEL_KABYLAKE_L, 10, 0x0000004e), 5398 INTEL_CPU_DESC(INTEL_KABYLAKE_L, 11, 0x0000004e), 5399 INTEL_CPU_DESC(INTEL_KABYLAKE_L, 12, 0x0000004e), 5400 INTEL_CPU_DESC(INTEL_KABYLAKE, 10, 0x0000004e), 5401 INTEL_CPU_DESC(INTEL_KABYLAKE, 11, 0x0000004e), 5402 INTEL_CPU_DESC(INTEL_KABYLAKE, 12, 0x0000004e), 5403 INTEL_CPU_DESC(INTEL_KABYLAKE, 13, 0x0000004e), 5404 {} 5405 }; 5406 5407 static void intel_check_pebs_isolation(void) 5408 { 5409 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 5410 } 5411 5412 static __init void intel_pebs_isolation_quirk(void) 5413 { 5414 WARN_ON_ONCE(x86_pmu.check_microcode); 5415 x86_pmu.check_microcode = intel_check_pebs_isolation; 5416 intel_check_pebs_isolation(); 5417 } 5418 5419 static const struct x86_cpu_desc pebs_ucodes[] = { 5420 INTEL_CPU_DESC(INTEL_SANDYBRIDGE, 7, 0x00000028), 5421 INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X, 6, 0x00000618), 5422 INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X, 7, 0x0000070c), 5423 {} 5424 }; 5425 5426 static bool intel_snb_pebs_broken(void) 5427 { 5428 return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 5429 } 5430 5431 static void intel_snb_check_microcode(void) 5432 { 5433 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 5434 return; 5435 5436 /* 5437 * Serialized by the microcode lock.. 5438 */ 5439 if (x86_pmu.pebs_broken) { 5440 pr_info("PEBS enabled due to microcode update\n"); 5441 x86_pmu.pebs_broken = 0; 5442 } else { 5443 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 5444 x86_pmu.pebs_broken = 1; 5445 } 5446 } 5447 5448 static bool is_lbr_from(unsigned long msr) 5449 { 5450 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 5451 5452 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 5453 } 5454 5455 /* 5456 * Under certain circumstances, access certain MSR may cause #GP. 5457 * The function tests if the input MSR can be safely accessed. 5458 */ 5459 static bool check_msr(unsigned long msr, u64 mask) 5460 { 5461 u64 val_old, val_new, val_tmp; 5462 5463 /* 5464 * Disable the check for real HW, so we don't 5465 * mess with potentially enabled registers: 5466 */ 5467 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 5468 return true; 5469 5470 /* 5471 * Read the current value, change it and read it back to see if it 5472 * matches, this is needed to detect certain hardware emulators 5473 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 5474 */ 5475 if (rdmsrl_safe(msr, &val_old)) 5476 return false; 5477 5478 /* 5479 * Only change the bits which can be updated by wrmsrl. 5480 */ 5481 val_tmp = val_old ^ mask; 5482 5483 if (is_lbr_from(msr)) 5484 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 5485 5486 if (wrmsrl_safe(msr, val_tmp) || 5487 rdmsrl_safe(msr, &val_new)) 5488 return false; 5489 5490 /* 5491 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 5492 * should equal rdmsrl()'s even with the quirk. 5493 */ 5494 if (val_new != val_tmp) 5495 return false; 5496 5497 if (is_lbr_from(msr)) 5498 val_old = lbr_from_signext_quirk_wr(val_old); 5499 5500 /* Here it's sure that the MSR can be safely accessed. 5501 * Restore the old value and return. 5502 */ 5503 wrmsrl(msr, val_old); 5504 5505 return true; 5506 } 5507 5508 static __init void intel_sandybridge_quirk(void) 5509 { 5510 x86_pmu.check_microcode = intel_snb_check_microcode; 5511 cpus_read_lock(); 5512 intel_snb_check_microcode(); 5513 cpus_read_unlock(); 5514 } 5515 5516 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 5517 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 5518 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 5519 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 5520 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 5521 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 5522 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 5523 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 5524 }; 5525 5526 static __init void intel_arch_events_quirk(void) 5527 { 5528 int bit; 5529 5530 /* disable event that reported as not present by cpuid */ 5531 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 5532 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 5533 pr_warn("CPUID marked event: \'%s\' unavailable\n", 5534 intel_arch_events_map[bit].name); 5535 } 5536 } 5537 5538 static __init void intel_nehalem_quirk(void) 5539 { 5540 union cpuid10_ebx ebx; 5541 5542 ebx.full = x86_pmu.events_maskl; 5543 if (ebx.split.no_branch_misses_retired) { 5544 /* 5545 * Erratum AAJ80 detected, we work it around by using 5546 * the BR_MISP_EXEC.ANY event. This will over-count 5547 * branch-misses, but it's still much better than the 5548 * architectural event which is often completely bogus: 5549 */ 5550 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 5551 ebx.split.no_branch_misses_retired = 0; 5552 x86_pmu.events_maskl = ebx.full; 5553 pr_info("CPU erratum AAJ80 worked around\n"); 5554 } 5555 } 5556 5557 /* 5558 * enable software workaround for errata: 5559 * SNB: BJ122 5560 * IVB: BV98 5561 * HSW: HSD29 5562 * 5563 * Only needed when HT is enabled. However detecting 5564 * if HT is enabled is difficult (model specific). So instead, 5565 * we enable the workaround in the early boot, and verify if 5566 * it is needed in a later initcall phase once we have valid 5567 * topology information to check if HT is actually enabled 5568 */ 5569 static __init void intel_ht_bug(void) 5570 { 5571 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 5572 5573 x86_pmu.start_scheduling = intel_start_scheduling; 5574 x86_pmu.commit_scheduling = intel_commit_scheduling; 5575 x86_pmu.stop_scheduling = intel_stop_scheduling; 5576 } 5577 5578 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 5579 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 5580 5581 /* Haswell special events */ 5582 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 5583 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 5584 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 5585 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 5586 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 5587 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 5588 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 5589 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 5590 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 5591 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 5592 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 5593 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 5594 5595 static struct attribute *hsw_events_attrs[] = { 5596 EVENT_PTR(td_slots_issued), 5597 EVENT_PTR(td_slots_retired), 5598 EVENT_PTR(td_fetch_bubbles), 5599 EVENT_PTR(td_total_slots), 5600 EVENT_PTR(td_total_slots_scale), 5601 EVENT_PTR(td_recovery_bubbles), 5602 EVENT_PTR(td_recovery_bubbles_scale), 5603 NULL 5604 }; 5605 5606 static struct attribute *hsw_mem_events_attrs[] = { 5607 EVENT_PTR(mem_ld_hsw), 5608 EVENT_PTR(mem_st_hsw), 5609 NULL, 5610 }; 5611 5612 static struct attribute *hsw_tsx_events_attrs[] = { 5613 EVENT_PTR(tx_start), 5614 EVENT_PTR(tx_commit), 5615 EVENT_PTR(tx_abort), 5616 EVENT_PTR(tx_capacity), 5617 EVENT_PTR(tx_conflict), 5618 EVENT_PTR(el_start), 5619 EVENT_PTR(el_commit), 5620 EVENT_PTR(el_abort), 5621 EVENT_PTR(el_capacity), 5622 EVENT_PTR(el_conflict), 5623 EVENT_PTR(cycles_t), 5624 EVENT_PTR(cycles_ct), 5625 NULL 5626 }; 5627 5628 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 5629 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 5630 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 5631 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 5632 5633 static struct attribute *icl_events_attrs[] = { 5634 EVENT_PTR(mem_ld_hsw), 5635 EVENT_PTR(mem_st_hsw), 5636 NULL, 5637 }; 5638 5639 static struct attribute *icl_td_events_attrs[] = { 5640 EVENT_PTR(slots), 5641 EVENT_PTR(td_retiring), 5642 EVENT_PTR(td_bad_spec), 5643 EVENT_PTR(td_fe_bound), 5644 EVENT_PTR(td_be_bound), 5645 NULL, 5646 }; 5647 5648 static struct attribute *icl_tsx_events_attrs[] = { 5649 EVENT_PTR(tx_start), 5650 EVENT_PTR(tx_abort), 5651 EVENT_PTR(tx_commit), 5652 EVENT_PTR(tx_capacity_read), 5653 EVENT_PTR(tx_capacity_write), 5654 EVENT_PTR(tx_conflict), 5655 EVENT_PTR(el_start), 5656 EVENT_PTR(el_abort), 5657 EVENT_PTR(el_commit), 5658 EVENT_PTR(el_capacity_read), 5659 EVENT_PTR(el_capacity_write), 5660 EVENT_PTR(el_conflict), 5661 EVENT_PTR(cycles_t), 5662 EVENT_PTR(cycles_ct), 5663 NULL, 5664 }; 5665 5666 5667 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 5668 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 5669 5670 static struct attribute *glc_events_attrs[] = { 5671 EVENT_PTR(mem_ld_hsw), 5672 EVENT_PTR(mem_st_spr), 5673 EVENT_PTR(mem_ld_aux), 5674 NULL, 5675 }; 5676 5677 static struct attribute *glc_td_events_attrs[] = { 5678 EVENT_PTR(slots), 5679 EVENT_PTR(td_retiring), 5680 EVENT_PTR(td_bad_spec), 5681 EVENT_PTR(td_fe_bound), 5682 EVENT_PTR(td_be_bound), 5683 EVENT_PTR(td_heavy_ops), 5684 EVENT_PTR(td_br_mispredict), 5685 EVENT_PTR(td_fetch_lat), 5686 EVENT_PTR(td_mem_bound), 5687 NULL, 5688 }; 5689 5690 static struct attribute *glc_tsx_events_attrs[] = { 5691 EVENT_PTR(tx_start), 5692 EVENT_PTR(tx_abort), 5693 EVENT_PTR(tx_commit), 5694 EVENT_PTR(tx_capacity_read), 5695 EVENT_PTR(tx_capacity_write), 5696 EVENT_PTR(tx_conflict), 5697 EVENT_PTR(cycles_t), 5698 EVENT_PTR(cycles_ct), 5699 NULL, 5700 }; 5701 5702 static ssize_t freeze_on_smi_show(struct device *cdev, 5703 struct device_attribute *attr, 5704 char *buf) 5705 { 5706 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 5707 } 5708 5709 static DEFINE_MUTEX(freeze_on_smi_mutex); 5710 5711 static ssize_t freeze_on_smi_store(struct device *cdev, 5712 struct device_attribute *attr, 5713 const char *buf, size_t count) 5714 { 5715 unsigned long val; 5716 ssize_t ret; 5717 5718 ret = kstrtoul(buf, 0, &val); 5719 if (ret) 5720 return ret; 5721 5722 if (val > 1) 5723 return -EINVAL; 5724 5725 mutex_lock(&freeze_on_smi_mutex); 5726 5727 if (x86_pmu.attr_freeze_on_smi == val) 5728 goto done; 5729 5730 x86_pmu.attr_freeze_on_smi = val; 5731 5732 cpus_read_lock(); 5733 on_each_cpu(flip_smm_bit, &val, 1); 5734 cpus_read_unlock(); 5735 done: 5736 mutex_unlock(&freeze_on_smi_mutex); 5737 5738 return count; 5739 } 5740 5741 static void update_tfa_sched(void *ignored) 5742 { 5743 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5744 5745 /* 5746 * check if PMC3 is used 5747 * and if so force schedule out for all event types all contexts 5748 */ 5749 if (test_bit(3, cpuc->active_mask)) 5750 perf_pmu_resched(x86_get_pmu(smp_processor_id())); 5751 } 5752 5753 static ssize_t show_sysctl_tfa(struct device *cdev, 5754 struct device_attribute *attr, 5755 char *buf) 5756 { 5757 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 5758 } 5759 5760 static ssize_t set_sysctl_tfa(struct device *cdev, 5761 struct device_attribute *attr, 5762 const char *buf, size_t count) 5763 { 5764 bool val; 5765 ssize_t ret; 5766 5767 ret = kstrtobool(buf, &val); 5768 if (ret) 5769 return ret; 5770 5771 /* no change */ 5772 if (val == allow_tsx_force_abort) 5773 return count; 5774 5775 allow_tsx_force_abort = val; 5776 5777 cpus_read_lock(); 5778 on_each_cpu(update_tfa_sched, NULL, 1); 5779 cpus_read_unlock(); 5780 5781 return count; 5782 } 5783 5784 5785 static DEVICE_ATTR_RW(freeze_on_smi); 5786 5787 static ssize_t branches_show(struct device *cdev, 5788 struct device_attribute *attr, 5789 char *buf) 5790 { 5791 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 5792 } 5793 5794 static DEVICE_ATTR_RO(branches); 5795 5796 static ssize_t branch_counter_nr_show(struct device *cdev, 5797 struct device_attribute *attr, 5798 char *buf) 5799 { 5800 return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_counters)); 5801 } 5802 5803 static DEVICE_ATTR_RO(branch_counter_nr); 5804 5805 static ssize_t branch_counter_width_show(struct device *cdev, 5806 struct device_attribute *attr, 5807 char *buf) 5808 { 5809 return snprintf(buf, PAGE_SIZE, "%d\n", LBR_INFO_BR_CNTR_BITS); 5810 } 5811 5812 static DEVICE_ATTR_RO(branch_counter_width); 5813 5814 static struct attribute *lbr_attrs[] = { 5815 &dev_attr_branches.attr, 5816 &dev_attr_branch_counter_nr.attr, 5817 &dev_attr_branch_counter_width.attr, 5818 NULL 5819 }; 5820 5821 static umode_t 5822 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5823 { 5824 /* branches */ 5825 if (i == 0) 5826 return x86_pmu.lbr_nr ? attr->mode : 0; 5827 5828 return (x86_pmu.flags & PMU_FL_BR_CNTR) ? attr->mode : 0; 5829 } 5830 5831 static char pmu_name_str[30]; 5832 5833 static DEVICE_STRING_ATTR_RO(pmu_name, 0444, pmu_name_str); 5834 5835 static struct attribute *intel_pmu_caps_attrs[] = { 5836 &dev_attr_pmu_name.attr.attr, 5837 NULL 5838 }; 5839 5840 static DEVICE_ATTR(allow_tsx_force_abort, 0644, 5841 show_sysctl_tfa, 5842 set_sysctl_tfa); 5843 5844 static struct attribute *intel_pmu_attrs[] = { 5845 &dev_attr_freeze_on_smi.attr, 5846 &dev_attr_allow_tsx_force_abort.attr, 5847 NULL, 5848 }; 5849 5850 static umode_t 5851 default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5852 { 5853 if (attr == &dev_attr_allow_tsx_force_abort.attr) 5854 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 5855 5856 return attr->mode; 5857 } 5858 5859 static umode_t 5860 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5861 { 5862 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 5863 } 5864 5865 static umode_t 5866 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5867 { 5868 return x86_pmu.pebs ? attr->mode : 0; 5869 } 5870 5871 static umode_t 5872 mem_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5873 { 5874 if (attr == &event_attr_mem_ld_aux.attr.attr) 5875 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0; 5876 5877 return pebs_is_visible(kobj, attr, i); 5878 } 5879 5880 static umode_t 5881 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5882 { 5883 return x86_pmu.version >= 2 ? attr->mode : 0; 5884 } 5885 5886 static umode_t 5887 td_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5888 { 5889 /* 5890 * Hide the perf metrics topdown events 5891 * if the feature is not enumerated. 5892 */ 5893 if (x86_pmu.num_topdown_events) 5894 return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0; 5895 5896 return attr->mode; 5897 } 5898 5899 static struct attribute_group group_events_td = { 5900 .name = "events", 5901 .is_visible = td_is_visible, 5902 }; 5903 5904 static struct attribute_group group_events_mem = { 5905 .name = "events", 5906 .is_visible = mem_is_visible, 5907 }; 5908 5909 static struct attribute_group group_events_tsx = { 5910 .name = "events", 5911 .is_visible = tsx_is_visible, 5912 }; 5913 5914 static struct attribute_group group_caps_gen = { 5915 .name = "caps", 5916 .attrs = intel_pmu_caps_attrs, 5917 }; 5918 5919 static struct attribute_group group_caps_lbr = { 5920 .name = "caps", 5921 .attrs = lbr_attrs, 5922 .is_visible = lbr_is_visible, 5923 }; 5924 5925 static struct attribute_group group_format_extra = { 5926 .name = "format", 5927 .is_visible = exra_is_visible, 5928 }; 5929 5930 static struct attribute_group group_format_extra_skl = { 5931 .name = "format", 5932 .is_visible = exra_is_visible, 5933 }; 5934 5935 static struct attribute_group group_format_evtsel_ext = { 5936 .name = "format", 5937 .attrs = format_evtsel_ext_attrs, 5938 .is_visible = evtsel_ext_is_visible, 5939 }; 5940 5941 static struct attribute_group group_default = { 5942 .attrs = intel_pmu_attrs, 5943 .is_visible = default_is_visible, 5944 }; 5945 5946 static const struct attribute_group *attr_update[] = { 5947 &group_events_td, 5948 &group_events_mem, 5949 &group_events_tsx, 5950 &group_caps_gen, 5951 &group_caps_lbr, 5952 &group_format_extra, 5953 &group_format_extra_skl, 5954 &group_format_evtsel_ext, 5955 &group_default, 5956 NULL, 5957 }; 5958 5959 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); 5960 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); 5961 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); 5962 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); 5963 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); 5964 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); 5965 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); 5966 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); 5967 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); 5968 5969 static struct attribute *adl_hybrid_events_attrs[] = { 5970 EVENT_PTR(slots_adl), 5971 EVENT_PTR(td_retiring_adl), 5972 EVENT_PTR(td_bad_spec_adl), 5973 EVENT_PTR(td_fe_bound_adl), 5974 EVENT_PTR(td_be_bound_adl), 5975 EVENT_PTR(td_heavy_ops_adl), 5976 EVENT_PTR(td_br_mis_adl), 5977 EVENT_PTR(td_fetch_lat_adl), 5978 EVENT_PTR(td_mem_bound_adl), 5979 NULL, 5980 }; 5981 5982 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_lnl, "event=0xc2,umask=0x02;event=0x00,umask=0x80", hybrid_big_small); 5983 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_lnl, "event=0x9c,umask=0x01;event=0x00,umask=0x82", hybrid_big_small); 5984 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_lnl, "event=0xa4,umask=0x02;event=0x00,umask=0x83", hybrid_big_small); 5985 5986 static struct attribute *lnl_hybrid_events_attrs[] = { 5987 EVENT_PTR(slots_adl), 5988 EVENT_PTR(td_retiring_lnl), 5989 EVENT_PTR(td_bad_spec_adl), 5990 EVENT_PTR(td_fe_bound_lnl), 5991 EVENT_PTR(td_be_bound_lnl), 5992 EVENT_PTR(td_heavy_ops_adl), 5993 EVENT_PTR(td_br_mis_adl), 5994 EVENT_PTR(td_fetch_lat_adl), 5995 EVENT_PTR(td_mem_bound_adl), 5996 NULL 5997 }; 5998 5999 /* The event string must be in PMU IDX order. */ 6000 EVENT_ATTR_STR_HYBRID(topdown-retiring, 6001 td_retiring_arl_h, 6002 "event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0", 6003 hybrid_big_small_tiny); 6004 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, 6005 td_bad_spec_arl_h, 6006 "event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0", 6007 hybrid_big_small_tiny); 6008 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, 6009 td_fe_bound_arl_h, 6010 "event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0", 6011 hybrid_big_small_tiny); 6012 EVENT_ATTR_STR_HYBRID(topdown-be-bound, 6013 td_be_bound_arl_h, 6014 "event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0", 6015 hybrid_big_small_tiny); 6016 6017 static struct attribute *arl_h_hybrid_events_attrs[] = { 6018 EVENT_PTR(slots_adl), 6019 EVENT_PTR(td_retiring_arl_h), 6020 EVENT_PTR(td_bad_spec_arl_h), 6021 EVENT_PTR(td_fe_bound_arl_h), 6022 EVENT_PTR(td_be_bound_arl_h), 6023 EVENT_PTR(td_heavy_ops_adl), 6024 EVENT_PTR(td_br_mis_adl), 6025 EVENT_PTR(td_fetch_lat_adl), 6026 EVENT_PTR(td_mem_bound_adl), 6027 NULL, 6028 }; 6029 6030 /* Must be in IDX order */ 6031 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); 6032 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); 6033 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); 6034 6035 static struct attribute *adl_hybrid_mem_attrs[] = { 6036 EVENT_PTR(mem_ld_adl), 6037 EVENT_PTR(mem_st_adl), 6038 EVENT_PTR(mem_ld_aux_adl), 6039 NULL, 6040 }; 6041 6042 static struct attribute *mtl_hybrid_mem_attrs[] = { 6043 EVENT_PTR(mem_ld_adl), 6044 EVENT_PTR(mem_st_adl), 6045 NULL 6046 }; 6047 6048 EVENT_ATTR_STR_HYBRID(mem-loads, 6049 mem_ld_arl_h, 6050 "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3", 6051 hybrid_big_small_tiny); 6052 EVENT_ATTR_STR_HYBRID(mem-stores, 6053 mem_st_arl_h, 6054 "event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6", 6055 hybrid_big_small_tiny); 6056 6057 static struct attribute *arl_h_hybrid_mem_attrs[] = { 6058 EVENT_PTR(mem_ld_arl_h), 6059 EVENT_PTR(mem_st_arl_h), 6060 NULL, 6061 }; 6062 6063 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); 6064 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); 6065 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); 6066 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); 6067 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); 6068 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); 6069 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); 6070 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); 6071 6072 static struct attribute *adl_hybrid_tsx_attrs[] = { 6073 EVENT_PTR(tx_start_adl), 6074 EVENT_PTR(tx_abort_adl), 6075 EVENT_PTR(tx_commit_adl), 6076 EVENT_PTR(tx_capacity_read_adl), 6077 EVENT_PTR(tx_capacity_write_adl), 6078 EVENT_PTR(tx_conflict_adl), 6079 EVENT_PTR(cycles_t_adl), 6080 EVENT_PTR(cycles_ct_adl), 6081 NULL, 6082 }; 6083 6084 FORMAT_ATTR_HYBRID(in_tx, hybrid_big); 6085 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); 6086 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny); 6087 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny); 6088 FORMAT_ATTR_HYBRID(frontend, hybrid_big); 6089 6090 #define ADL_HYBRID_RTM_FORMAT_ATTR \ 6091 FORMAT_HYBRID_PTR(in_tx), \ 6092 FORMAT_HYBRID_PTR(in_tx_cp) 6093 6094 #define ADL_HYBRID_FORMAT_ATTR \ 6095 FORMAT_HYBRID_PTR(offcore_rsp), \ 6096 FORMAT_HYBRID_PTR(ldlat), \ 6097 FORMAT_HYBRID_PTR(frontend) 6098 6099 static struct attribute *adl_hybrid_extra_attr_rtm[] = { 6100 ADL_HYBRID_RTM_FORMAT_ATTR, 6101 ADL_HYBRID_FORMAT_ATTR, 6102 NULL 6103 }; 6104 6105 static struct attribute *adl_hybrid_extra_attr[] = { 6106 ADL_HYBRID_FORMAT_ATTR, 6107 NULL 6108 }; 6109 6110 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_tiny); 6111 6112 static struct attribute *mtl_hybrid_extra_attr_rtm[] = { 6113 ADL_HYBRID_RTM_FORMAT_ATTR, 6114 ADL_HYBRID_FORMAT_ATTR, 6115 FORMAT_HYBRID_PTR(snoop_rsp), 6116 NULL 6117 }; 6118 6119 static struct attribute *mtl_hybrid_extra_attr[] = { 6120 ADL_HYBRID_FORMAT_ATTR, 6121 FORMAT_HYBRID_PTR(snoop_rsp), 6122 NULL 6123 }; 6124 6125 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) 6126 { 6127 struct device *dev = kobj_to_dev(kobj); 6128 struct x86_hybrid_pmu *pmu = 6129 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6130 struct perf_pmu_events_hybrid_attr *pmu_attr = 6131 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); 6132 6133 return pmu->pmu_type & pmu_attr->pmu_type; 6134 } 6135 6136 static umode_t hybrid_events_is_visible(struct kobject *kobj, 6137 struct attribute *attr, int i) 6138 { 6139 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; 6140 } 6141 6142 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) 6143 { 6144 int cpu = cpumask_first(&pmu->supported_cpus); 6145 6146 return (cpu >= nr_cpu_ids) ? -1 : cpu; 6147 } 6148 6149 static umode_t hybrid_tsx_is_visible(struct kobject *kobj, 6150 struct attribute *attr, int i) 6151 { 6152 struct device *dev = kobj_to_dev(kobj); 6153 struct x86_hybrid_pmu *pmu = 6154 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6155 int cpu = hybrid_find_supported_cpu(pmu); 6156 6157 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; 6158 } 6159 6160 static umode_t hybrid_format_is_visible(struct kobject *kobj, 6161 struct attribute *attr, int i) 6162 { 6163 struct device *dev = kobj_to_dev(kobj); 6164 struct x86_hybrid_pmu *pmu = 6165 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6166 struct perf_pmu_format_hybrid_attr *pmu_attr = 6167 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); 6168 int cpu = hybrid_find_supported_cpu(pmu); 6169 6170 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0; 6171 } 6172 6173 static umode_t hybrid_td_is_visible(struct kobject *kobj, 6174 struct attribute *attr, int i) 6175 { 6176 struct device *dev = kobj_to_dev(kobj); 6177 struct x86_hybrid_pmu *pmu = 6178 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6179 6180 if (!is_attr_for_this_pmu(kobj, attr)) 6181 return 0; 6182 6183 6184 /* Only the big core supports perf metrics */ 6185 if (pmu->pmu_type == hybrid_big) 6186 return pmu->intel_cap.perf_metrics ? attr->mode : 0; 6187 6188 return attr->mode; 6189 } 6190 6191 static struct attribute_group hybrid_group_events_td = { 6192 .name = "events", 6193 .is_visible = hybrid_td_is_visible, 6194 }; 6195 6196 static struct attribute_group hybrid_group_events_mem = { 6197 .name = "events", 6198 .is_visible = hybrid_events_is_visible, 6199 }; 6200 6201 static struct attribute_group hybrid_group_events_tsx = { 6202 .name = "events", 6203 .is_visible = hybrid_tsx_is_visible, 6204 }; 6205 6206 static struct attribute_group hybrid_group_format_extra = { 6207 .name = "format", 6208 .is_visible = hybrid_format_is_visible, 6209 }; 6210 6211 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, 6212 struct device_attribute *attr, 6213 char *buf) 6214 { 6215 struct x86_hybrid_pmu *pmu = 6216 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6217 6218 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus); 6219 } 6220 6221 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); 6222 static struct attribute *intel_hybrid_cpus_attrs[] = { 6223 &dev_attr_cpus.attr, 6224 NULL, 6225 }; 6226 6227 static struct attribute_group hybrid_group_cpus = { 6228 .attrs = intel_hybrid_cpus_attrs, 6229 }; 6230 6231 static const struct attribute_group *hybrid_attr_update[] = { 6232 &hybrid_group_events_td, 6233 &hybrid_group_events_mem, 6234 &hybrid_group_events_tsx, 6235 &group_caps_gen, 6236 &group_caps_lbr, 6237 &hybrid_group_format_extra, 6238 &group_format_evtsel_ext, 6239 &group_default, 6240 &hybrid_group_cpus, 6241 NULL, 6242 }; 6243 6244 static struct attribute *empty_attrs; 6245 6246 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 6247 u64 cntr_mask, 6248 u64 fixed_cntr_mask, 6249 u64 intel_ctrl) 6250 { 6251 struct event_constraint *c; 6252 6253 if (!event_constraints) 6254 return; 6255 6256 /* 6257 * event on fixed counter2 (REF_CYCLES) only works on this 6258 * counter, so do not extend mask to generic counters 6259 */ 6260 for_each_event_constraint(c, event_constraints) { 6261 /* 6262 * Don't extend the topdown slots and metrics 6263 * events to the generic counters. 6264 */ 6265 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 6266 /* 6267 * Disable topdown slots and metrics events, 6268 * if slots event is not in CPUID. 6269 */ 6270 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) 6271 c->idxmsk64 = 0; 6272 c->weight = hweight64(c->idxmsk64); 6273 continue; 6274 } 6275 6276 if (c->cmask == FIXED_EVENT_FLAGS) { 6277 /* Disabled fixed counters which are not in CPUID */ 6278 c->idxmsk64 &= intel_ctrl; 6279 6280 /* 6281 * Don't extend the pseudo-encoding to the 6282 * generic counters 6283 */ 6284 if (!use_fixed_pseudo_encoding(c->code)) 6285 c->idxmsk64 |= cntr_mask; 6286 } 6287 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED); 6288 c->weight = hweight64(c->idxmsk64); 6289 } 6290 } 6291 6292 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) 6293 { 6294 struct extra_reg *er; 6295 6296 /* 6297 * Access extra MSR may cause #GP under certain circumstances. 6298 * E.g. KVM doesn't support offcore event 6299 * Check all extra_regs here. 6300 */ 6301 if (!extra_regs) 6302 return; 6303 6304 for (er = extra_regs; er->msr; er++) { 6305 er->extra_msr_access = check_msr(er->msr, 0x11UL); 6306 /* Disable LBR select mapping */ 6307 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 6308 x86_pmu.lbr_sel_map = NULL; 6309 } 6310 } 6311 6312 static inline int intel_pmu_v6_addr_offset(int index, bool eventsel) 6313 { 6314 return MSR_IA32_PMC_V6_STEP * index; 6315 } 6316 6317 static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = { 6318 { hybrid_small, "cpu_atom" }, 6319 { hybrid_big, "cpu_core" }, 6320 { hybrid_tiny, "cpu_lowpower" }, 6321 }; 6322 6323 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus) 6324 { 6325 unsigned long pmus_mask = pmus; 6326 struct x86_hybrid_pmu *pmu; 6327 int idx = 0, bit; 6328 6329 x86_pmu.num_hybrid_pmus = hweight_long(pmus_mask); 6330 x86_pmu.hybrid_pmu = kcalloc(x86_pmu.num_hybrid_pmus, 6331 sizeof(struct x86_hybrid_pmu), 6332 GFP_KERNEL); 6333 if (!x86_pmu.hybrid_pmu) 6334 return -ENOMEM; 6335 6336 static_branch_enable(&perf_is_hybrid); 6337 x86_pmu.filter = intel_pmu_filter; 6338 6339 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) { 6340 pmu = &x86_pmu.hybrid_pmu[idx++]; 6341 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id; 6342 pmu->name = intel_hybrid_pmu_type_map[bit].name; 6343 6344 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 6345 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 6346 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 6347 pmu->config_mask = X86_RAW_EVENT_MASK; 6348 pmu->unconstrained = (struct event_constraint) 6349 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 6350 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 6351 6352 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6353 if (pmu->pmu_type & hybrid_small_tiny) { 6354 pmu->intel_cap.perf_metrics = 0; 6355 pmu->intel_cap.pebs_output_pt_available = 1; 6356 pmu->mid_ack = true; 6357 } else if (pmu->pmu_type & hybrid_big) { 6358 pmu->intel_cap.perf_metrics = 1; 6359 pmu->intel_cap.pebs_output_pt_available = 0; 6360 pmu->late_ack = true; 6361 } 6362 } 6363 6364 return 0; 6365 } 6366 6367 static __always_inline void intel_pmu_ref_cycles_ext(void) 6368 { 6369 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED))) 6370 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c; 6371 } 6372 6373 static __always_inline void intel_pmu_init_glc(struct pmu *pmu) 6374 { 6375 x86_pmu.late_ack = true; 6376 x86_pmu.limit_period = glc_limit_period; 6377 x86_pmu.pebs_aliases = NULL; 6378 x86_pmu.pebs_prec_dist = true; 6379 x86_pmu.pebs_block = true; 6380 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6381 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6382 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6383 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6384 x86_pmu.lbr_pt_coexist = true; 6385 x86_pmu.num_topdown_events = 8; 6386 static_call_update(intel_pmu_update_topdown_event, 6387 &icl_update_topdown_event); 6388 static_call_update(intel_pmu_set_topdown_event_period, 6389 &icl_set_topdown_event_period); 6390 6391 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6392 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6393 hybrid(pmu, event_constraints) = intel_glc_event_constraints; 6394 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints; 6395 6396 intel_pmu_ref_cycles_ext(); 6397 } 6398 6399 static __always_inline void intel_pmu_init_grt(struct pmu *pmu) 6400 { 6401 x86_pmu.mid_ack = true; 6402 x86_pmu.limit_period = glc_limit_period; 6403 x86_pmu.pebs_aliases = NULL; 6404 x86_pmu.pebs_prec_dist = true; 6405 x86_pmu.pebs_block = true; 6406 x86_pmu.lbr_pt_coexist = true; 6407 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6408 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6409 6410 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6411 memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6412 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6413 hybrid(pmu, event_constraints) = intel_grt_event_constraints; 6414 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints; 6415 hybrid(pmu, extra_regs) = intel_grt_extra_regs; 6416 6417 intel_pmu_ref_cycles_ext(); 6418 } 6419 6420 static __always_inline void intel_pmu_init_lnc(struct pmu *pmu) 6421 { 6422 intel_pmu_init_glc(pmu); 6423 hybrid(pmu, event_constraints) = intel_lnc_event_constraints; 6424 hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints; 6425 hybrid(pmu, extra_regs) = intel_rwc_extra_regs; 6426 } 6427 6428 static __always_inline void intel_pmu_init_skt(struct pmu *pmu) 6429 { 6430 intel_pmu_init_grt(pmu); 6431 hybrid(pmu, event_constraints) = intel_skt_event_constraints; 6432 hybrid(pmu, extra_regs) = intel_cmt_extra_regs; 6433 } 6434 6435 __init int intel_pmu_init(void) 6436 { 6437 struct attribute **extra_skl_attr = &empty_attrs; 6438 struct attribute **extra_attr = &empty_attrs; 6439 struct attribute **td_attr = &empty_attrs; 6440 struct attribute **mem_attr = &empty_attrs; 6441 struct attribute **tsx_attr = &empty_attrs; 6442 union cpuid10_edx edx; 6443 union cpuid10_eax eax; 6444 union cpuid10_ebx ebx; 6445 unsigned int fixed_mask; 6446 bool pmem = false; 6447 int version, i; 6448 char *name; 6449 struct x86_hybrid_pmu *pmu; 6450 6451 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 6452 switch (boot_cpu_data.x86) { 6453 case 0x6: 6454 return p6_pmu_init(); 6455 case 0xb: 6456 return knc_pmu_init(); 6457 case 0xf: 6458 return p4_pmu_init(); 6459 } 6460 return -ENODEV; 6461 } 6462 6463 /* 6464 * Check whether the Architectural PerfMon supports 6465 * Branch Misses Retired hw_event or not. 6466 */ 6467 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); 6468 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 6469 return -ENODEV; 6470 6471 version = eax.split.version_id; 6472 if (version < 2) 6473 x86_pmu = core_pmu; 6474 else 6475 x86_pmu = intel_pmu; 6476 6477 x86_pmu.version = version; 6478 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0); 6479 x86_pmu.cntval_bits = eax.split.bit_width; 6480 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 6481 6482 x86_pmu.events_maskl = ebx.full; 6483 x86_pmu.events_mask_len = eax.split.mask_length; 6484 6485 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64); 6486 x86_pmu.pebs_capable = PEBS_COUNTER_MASK; 6487 6488 /* 6489 * Quirk: v2 perfmon does not report fixed-purpose events, so 6490 * assume at least 3 events, when not running in a hypervisor: 6491 */ 6492 if (version > 1 && version < 5) { 6493 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 6494 6495 x86_pmu.fixed_cntr_mask64 = 6496 GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0); 6497 } else if (version >= 5) 6498 x86_pmu.fixed_cntr_mask64 = fixed_mask; 6499 6500 if (boot_cpu_has(X86_FEATURE_PDCM)) { 6501 u64 capabilities; 6502 6503 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 6504 x86_pmu.intel_cap.capabilities = capabilities; 6505 } 6506 6507 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 6508 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 6509 x86_pmu.lbr_read = intel_pmu_lbr_read_32; 6510 } 6511 6512 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 6513 intel_pmu_arch_lbr_init(); 6514 6515 intel_ds_init(); 6516 6517 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 6518 6519 if (version >= 5) { 6520 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 6521 if (x86_pmu.intel_cap.anythread_deprecated) 6522 pr_cont(" AnyThread deprecated, "); 6523 } 6524 6525 /* 6526 * Install the hw-cache-events table: 6527 */ 6528 switch (boot_cpu_data.x86_vfm) { 6529 case INTEL_CORE_YONAH: 6530 pr_cont("Core events, "); 6531 name = "core"; 6532 break; 6533 6534 case INTEL_CORE2_MEROM: 6535 x86_add_quirk(intel_clovertown_quirk); 6536 fallthrough; 6537 6538 case INTEL_CORE2_MEROM_L: 6539 case INTEL_CORE2_PENRYN: 6540 case INTEL_CORE2_DUNNINGTON: 6541 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 6542 sizeof(hw_cache_event_ids)); 6543 6544 intel_pmu_lbr_init_core(); 6545 6546 x86_pmu.event_constraints = intel_core2_event_constraints; 6547 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 6548 pr_cont("Core2 events, "); 6549 name = "core2"; 6550 break; 6551 6552 case INTEL_NEHALEM: 6553 case INTEL_NEHALEM_EP: 6554 case INTEL_NEHALEM_EX: 6555 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 6556 sizeof(hw_cache_event_ids)); 6557 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 6558 sizeof(hw_cache_extra_regs)); 6559 6560 intel_pmu_lbr_init_nhm(); 6561 6562 x86_pmu.event_constraints = intel_nehalem_event_constraints; 6563 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 6564 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 6565 x86_pmu.extra_regs = intel_nehalem_extra_regs; 6566 x86_pmu.limit_period = nhm_limit_period; 6567 6568 mem_attr = nhm_mem_events_attrs; 6569 6570 /* UOPS_ISSUED.STALLED_CYCLES */ 6571 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6572 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6573 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 6574 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6575 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 6576 6577 intel_pmu_pebs_data_source_nhm(); 6578 x86_add_quirk(intel_nehalem_quirk); 6579 x86_pmu.pebs_no_tlb = 1; 6580 extra_attr = nhm_format_attr; 6581 6582 pr_cont("Nehalem events, "); 6583 name = "nehalem"; 6584 break; 6585 6586 case INTEL_ATOM_BONNELL: 6587 case INTEL_ATOM_BONNELL_MID: 6588 case INTEL_ATOM_SALTWELL: 6589 case INTEL_ATOM_SALTWELL_MID: 6590 case INTEL_ATOM_SALTWELL_TABLET: 6591 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 6592 sizeof(hw_cache_event_ids)); 6593 6594 intel_pmu_lbr_init_atom(); 6595 6596 x86_pmu.event_constraints = intel_gen_event_constraints; 6597 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 6598 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 6599 pr_cont("Atom events, "); 6600 name = "bonnell"; 6601 break; 6602 6603 case INTEL_ATOM_SILVERMONT: 6604 case INTEL_ATOM_SILVERMONT_D: 6605 case INTEL_ATOM_SILVERMONT_MID: 6606 case INTEL_ATOM_AIRMONT: 6607 case INTEL_ATOM_AIRMONT_MID: 6608 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 6609 sizeof(hw_cache_event_ids)); 6610 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 6611 sizeof(hw_cache_extra_regs)); 6612 6613 intel_pmu_lbr_init_slm(); 6614 6615 x86_pmu.event_constraints = intel_slm_event_constraints; 6616 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 6617 x86_pmu.extra_regs = intel_slm_extra_regs; 6618 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6619 td_attr = slm_events_attrs; 6620 extra_attr = slm_format_attr; 6621 pr_cont("Silvermont events, "); 6622 name = "silvermont"; 6623 break; 6624 6625 case INTEL_ATOM_GOLDMONT: 6626 case INTEL_ATOM_GOLDMONT_D: 6627 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 6628 sizeof(hw_cache_event_ids)); 6629 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 6630 sizeof(hw_cache_extra_regs)); 6631 6632 intel_pmu_lbr_init_skl(); 6633 6634 x86_pmu.event_constraints = intel_slm_event_constraints; 6635 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 6636 x86_pmu.extra_regs = intel_glm_extra_regs; 6637 /* 6638 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 6639 * for precise cycles. 6640 * :pp is identical to :ppp 6641 */ 6642 x86_pmu.pebs_aliases = NULL; 6643 x86_pmu.pebs_prec_dist = true; 6644 x86_pmu.lbr_pt_coexist = true; 6645 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6646 td_attr = glm_events_attrs; 6647 extra_attr = slm_format_attr; 6648 pr_cont("Goldmont events, "); 6649 name = "goldmont"; 6650 break; 6651 6652 case INTEL_ATOM_GOLDMONT_PLUS: 6653 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 6654 sizeof(hw_cache_event_ids)); 6655 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 6656 sizeof(hw_cache_extra_regs)); 6657 6658 intel_pmu_lbr_init_skl(); 6659 6660 x86_pmu.event_constraints = intel_slm_event_constraints; 6661 x86_pmu.extra_regs = intel_glm_extra_regs; 6662 /* 6663 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 6664 * for precise cycles. 6665 */ 6666 x86_pmu.pebs_aliases = NULL; 6667 x86_pmu.pebs_prec_dist = true; 6668 x86_pmu.lbr_pt_coexist = true; 6669 x86_pmu.pebs_capable = ~0ULL; 6670 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6671 x86_pmu.flags |= PMU_FL_PEBS_ALL; 6672 x86_pmu.get_event_constraints = glp_get_event_constraints; 6673 td_attr = glm_events_attrs; 6674 /* Goldmont Plus has 4-wide pipeline */ 6675 event_attr_td_total_slots_scale_glm.event_str = "4"; 6676 extra_attr = slm_format_attr; 6677 pr_cont("Goldmont plus events, "); 6678 name = "goldmont_plus"; 6679 break; 6680 6681 case INTEL_ATOM_TREMONT_D: 6682 case INTEL_ATOM_TREMONT: 6683 case INTEL_ATOM_TREMONT_L: 6684 x86_pmu.late_ack = true; 6685 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 6686 sizeof(hw_cache_event_ids)); 6687 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 6688 sizeof(hw_cache_extra_regs)); 6689 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6690 6691 intel_pmu_lbr_init_skl(); 6692 6693 x86_pmu.event_constraints = intel_slm_event_constraints; 6694 x86_pmu.extra_regs = intel_tnt_extra_regs; 6695 /* 6696 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 6697 * for precise cycles. 6698 */ 6699 x86_pmu.pebs_aliases = NULL; 6700 x86_pmu.pebs_prec_dist = true; 6701 x86_pmu.lbr_pt_coexist = true; 6702 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6703 x86_pmu.get_event_constraints = tnt_get_event_constraints; 6704 td_attr = tnt_events_attrs; 6705 extra_attr = slm_format_attr; 6706 pr_cont("Tremont events, "); 6707 name = "Tremont"; 6708 break; 6709 6710 case INTEL_ATOM_GRACEMONT: 6711 intel_pmu_init_grt(NULL); 6712 intel_pmu_pebs_data_source_grt(); 6713 x86_pmu.pebs_latency_data = grt_latency_data; 6714 x86_pmu.get_event_constraints = tnt_get_event_constraints; 6715 td_attr = tnt_events_attrs; 6716 mem_attr = grt_mem_attrs; 6717 extra_attr = nhm_format_attr; 6718 pr_cont("Gracemont events, "); 6719 name = "gracemont"; 6720 break; 6721 6722 case INTEL_ATOM_CRESTMONT: 6723 case INTEL_ATOM_CRESTMONT_X: 6724 intel_pmu_init_grt(NULL); 6725 x86_pmu.extra_regs = intel_cmt_extra_regs; 6726 intel_pmu_pebs_data_source_cmt(); 6727 x86_pmu.pebs_latency_data = cmt_latency_data; 6728 x86_pmu.get_event_constraints = cmt_get_event_constraints; 6729 td_attr = cmt_events_attrs; 6730 mem_attr = grt_mem_attrs; 6731 extra_attr = cmt_format_attr; 6732 pr_cont("Crestmont events, "); 6733 name = "crestmont"; 6734 break; 6735 6736 case INTEL_WESTMERE: 6737 case INTEL_WESTMERE_EP: 6738 case INTEL_WESTMERE_EX: 6739 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 6740 sizeof(hw_cache_event_ids)); 6741 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 6742 sizeof(hw_cache_extra_regs)); 6743 6744 intel_pmu_lbr_init_nhm(); 6745 6746 x86_pmu.event_constraints = intel_westmere_event_constraints; 6747 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 6748 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 6749 x86_pmu.extra_regs = intel_westmere_extra_regs; 6750 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6751 6752 mem_attr = nhm_mem_events_attrs; 6753 6754 /* UOPS_ISSUED.STALLED_CYCLES */ 6755 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6756 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6757 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 6758 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6759 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 6760 6761 intel_pmu_pebs_data_source_nhm(); 6762 extra_attr = nhm_format_attr; 6763 pr_cont("Westmere events, "); 6764 name = "westmere"; 6765 break; 6766 6767 case INTEL_SANDYBRIDGE: 6768 case INTEL_SANDYBRIDGE_X: 6769 x86_add_quirk(intel_sandybridge_quirk); 6770 x86_add_quirk(intel_ht_bug); 6771 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 6772 sizeof(hw_cache_event_ids)); 6773 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 6774 sizeof(hw_cache_extra_regs)); 6775 6776 intel_pmu_lbr_init_snb(); 6777 6778 x86_pmu.event_constraints = intel_snb_event_constraints; 6779 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 6780 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 6781 if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X) 6782 x86_pmu.extra_regs = intel_snbep_extra_regs; 6783 else 6784 x86_pmu.extra_regs = intel_snb_extra_regs; 6785 6786 6787 /* all extra regs are per-cpu when HT is on */ 6788 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6789 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6790 6791 td_attr = snb_events_attrs; 6792 mem_attr = snb_mem_events_attrs; 6793 6794 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 6795 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6796 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6797 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 6798 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6799 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 6800 6801 extra_attr = nhm_format_attr; 6802 6803 pr_cont("SandyBridge events, "); 6804 name = "sandybridge"; 6805 break; 6806 6807 case INTEL_IVYBRIDGE: 6808 case INTEL_IVYBRIDGE_X: 6809 x86_add_quirk(intel_ht_bug); 6810 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 6811 sizeof(hw_cache_event_ids)); 6812 /* dTLB-load-misses on IVB is different than SNB */ 6813 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 6814 6815 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 6816 sizeof(hw_cache_extra_regs)); 6817 6818 intel_pmu_lbr_init_snb(); 6819 6820 x86_pmu.event_constraints = intel_ivb_event_constraints; 6821 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 6822 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6823 x86_pmu.pebs_prec_dist = true; 6824 if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X) 6825 x86_pmu.extra_regs = intel_snbep_extra_regs; 6826 else 6827 x86_pmu.extra_regs = intel_snb_extra_regs; 6828 /* all extra regs are per-cpu when HT is on */ 6829 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6830 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6831 6832 td_attr = snb_events_attrs; 6833 mem_attr = snb_mem_events_attrs; 6834 6835 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 6836 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6837 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6838 6839 extra_attr = nhm_format_attr; 6840 6841 pr_cont("IvyBridge events, "); 6842 name = "ivybridge"; 6843 break; 6844 6845 6846 case INTEL_HASWELL: 6847 case INTEL_HASWELL_X: 6848 case INTEL_HASWELL_L: 6849 case INTEL_HASWELL_G: 6850 x86_add_quirk(intel_ht_bug); 6851 x86_add_quirk(intel_pebs_isolation_quirk); 6852 x86_pmu.late_ack = true; 6853 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6854 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6855 6856 intel_pmu_lbr_init_hsw(); 6857 6858 x86_pmu.event_constraints = intel_hsw_event_constraints; 6859 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 6860 x86_pmu.extra_regs = intel_snbep_extra_regs; 6861 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6862 x86_pmu.pebs_prec_dist = true; 6863 /* all extra regs are per-cpu when HT is on */ 6864 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6865 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6866 6867 x86_pmu.hw_config = hsw_hw_config; 6868 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6869 x86_pmu.limit_period = hsw_limit_period; 6870 x86_pmu.lbr_double_abort = true; 6871 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6872 hsw_format_attr : nhm_format_attr; 6873 td_attr = hsw_events_attrs; 6874 mem_attr = hsw_mem_events_attrs; 6875 tsx_attr = hsw_tsx_events_attrs; 6876 pr_cont("Haswell events, "); 6877 name = "haswell"; 6878 break; 6879 6880 case INTEL_BROADWELL: 6881 case INTEL_BROADWELL_D: 6882 case INTEL_BROADWELL_G: 6883 case INTEL_BROADWELL_X: 6884 x86_add_quirk(intel_pebs_isolation_quirk); 6885 x86_pmu.late_ack = true; 6886 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6887 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6888 6889 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 6890 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 6891 BDW_L3_MISS|HSW_SNOOP_DRAM; 6892 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 6893 HSW_SNOOP_DRAM; 6894 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 6895 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6896 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 6897 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6898 6899 intel_pmu_lbr_init_hsw(); 6900 6901 x86_pmu.event_constraints = intel_bdw_event_constraints; 6902 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 6903 x86_pmu.extra_regs = intel_snbep_extra_regs; 6904 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6905 x86_pmu.pebs_prec_dist = true; 6906 /* all extra regs are per-cpu when HT is on */ 6907 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6908 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6909 6910 x86_pmu.hw_config = hsw_hw_config; 6911 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6912 x86_pmu.limit_period = bdw_limit_period; 6913 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6914 hsw_format_attr : nhm_format_attr; 6915 td_attr = hsw_events_attrs; 6916 mem_attr = hsw_mem_events_attrs; 6917 tsx_attr = hsw_tsx_events_attrs; 6918 pr_cont("Broadwell events, "); 6919 name = "broadwell"; 6920 break; 6921 6922 case INTEL_XEON_PHI_KNL: 6923 case INTEL_XEON_PHI_KNM: 6924 memcpy(hw_cache_event_ids, 6925 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6926 memcpy(hw_cache_extra_regs, 6927 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6928 intel_pmu_lbr_init_knl(); 6929 6930 x86_pmu.event_constraints = intel_slm_event_constraints; 6931 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 6932 x86_pmu.extra_regs = intel_knl_extra_regs; 6933 6934 /* all extra regs are per-cpu when HT is on */ 6935 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6936 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6937 extra_attr = slm_format_attr; 6938 pr_cont("Knights Landing/Mill events, "); 6939 name = "knights-landing"; 6940 break; 6941 6942 case INTEL_SKYLAKE_X: 6943 pmem = true; 6944 fallthrough; 6945 case INTEL_SKYLAKE_L: 6946 case INTEL_SKYLAKE: 6947 case INTEL_KABYLAKE_L: 6948 case INTEL_KABYLAKE: 6949 case INTEL_COMETLAKE_L: 6950 case INTEL_COMETLAKE: 6951 x86_add_quirk(intel_pebs_isolation_quirk); 6952 x86_pmu.late_ack = true; 6953 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6954 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6955 intel_pmu_lbr_init_skl(); 6956 6957 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 6958 event_attr_td_recovery_bubbles.event_str_noht = 6959 "event=0xd,umask=0x1,cmask=1"; 6960 event_attr_td_recovery_bubbles.event_str_ht = 6961 "event=0xd,umask=0x1,cmask=1,any=1"; 6962 6963 x86_pmu.event_constraints = intel_skl_event_constraints; 6964 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 6965 x86_pmu.extra_regs = intel_skl_extra_regs; 6966 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 6967 x86_pmu.pebs_prec_dist = true; 6968 /* all extra regs are per-cpu when HT is on */ 6969 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6970 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6971 6972 x86_pmu.hw_config = hsw_hw_config; 6973 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6974 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6975 hsw_format_attr : nhm_format_attr; 6976 extra_skl_attr = skl_format_attr; 6977 td_attr = hsw_events_attrs; 6978 mem_attr = hsw_mem_events_attrs; 6979 tsx_attr = hsw_tsx_events_attrs; 6980 intel_pmu_pebs_data_source_skl(pmem); 6981 6982 /* 6983 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. 6984 * TSX force abort hooks are not required on these systems. Only deploy 6985 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. 6986 */ 6987 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && 6988 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { 6989 x86_pmu.flags |= PMU_FL_TFA; 6990 x86_pmu.get_event_constraints = tfa_get_event_constraints; 6991 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 6992 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 6993 } 6994 6995 pr_cont("Skylake events, "); 6996 name = "skylake"; 6997 break; 6998 6999 case INTEL_ICELAKE_X: 7000 case INTEL_ICELAKE_D: 7001 x86_pmu.pebs_ept = 1; 7002 pmem = true; 7003 fallthrough; 7004 case INTEL_ICELAKE_L: 7005 case INTEL_ICELAKE: 7006 case INTEL_TIGERLAKE_L: 7007 case INTEL_TIGERLAKE: 7008 case INTEL_ROCKETLAKE: 7009 x86_pmu.late_ack = true; 7010 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7011 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7012 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 7013 intel_pmu_lbr_init_skl(); 7014 7015 x86_pmu.event_constraints = intel_icl_event_constraints; 7016 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 7017 x86_pmu.extra_regs = intel_icl_extra_regs; 7018 x86_pmu.pebs_aliases = NULL; 7019 x86_pmu.pebs_prec_dist = true; 7020 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7021 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7022 7023 x86_pmu.hw_config = hsw_hw_config; 7024 x86_pmu.get_event_constraints = icl_get_event_constraints; 7025 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7026 hsw_format_attr : nhm_format_attr; 7027 extra_skl_attr = skl_format_attr; 7028 mem_attr = icl_events_attrs; 7029 td_attr = icl_td_events_attrs; 7030 tsx_attr = icl_tsx_events_attrs; 7031 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 7032 x86_pmu.lbr_pt_coexist = true; 7033 intel_pmu_pebs_data_source_skl(pmem); 7034 x86_pmu.num_topdown_events = 4; 7035 static_call_update(intel_pmu_update_topdown_event, 7036 &icl_update_topdown_event); 7037 static_call_update(intel_pmu_set_topdown_event_period, 7038 &icl_set_topdown_event_period); 7039 pr_cont("Icelake events, "); 7040 name = "icelake"; 7041 break; 7042 7043 case INTEL_SAPPHIRERAPIDS_X: 7044 case INTEL_EMERALDRAPIDS_X: 7045 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 7046 x86_pmu.extra_regs = intel_glc_extra_regs; 7047 pr_cont("Sapphire Rapids events, "); 7048 name = "sapphire_rapids"; 7049 goto glc_common; 7050 7051 case INTEL_GRANITERAPIDS_X: 7052 case INTEL_GRANITERAPIDS_D: 7053 x86_pmu.extra_regs = intel_rwc_extra_regs; 7054 pr_cont("Granite Rapids events, "); 7055 name = "granite_rapids"; 7056 7057 glc_common: 7058 intel_pmu_init_glc(NULL); 7059 x86_pmu.pebs_ept = 1; 7060 x86_pmu.hw_config = hsw_hw_config; 7061 x86_pmu.get_event_constraints = glc_get_event_constraints; 7062 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7063 hsw_format_attr : nhm_format_attr; 7064 extra_skl_attr = skl_format_attr; 7065 mem_attr = glc_events_attrs; 7066 td_attr = glc_td_events_attrs; 7067 tsx_attr = glc_tsx_events_attrs; 7068 intel_pmu_pebs_data_source_skl(true); 7069 break; 7070 7071 case INTEL_ALDERLAKE: 7072 case INTEL_ALDERLAKE_L: 7073 case INTEL_RAPTORLAKE: 7074 case INTEL_RAPTORLAKE_P: 7075 case INTEL_RAPTORLAKE_S: 7076 /* 7077 * Alder Lake has 2 types of CPU, core and atom. 7078 * 7079 * Initialize the common PerfMon capabilities here. 7080 */ 7081 intel_pmu_init_hybrid(hybrid_big_small); 7082 7083 x86_pmu.pebs_latency_data = grt_latency_data; 7084 x86_pmu.get_event_constraints = adl_get_event_constraints; 7085 x86_pmu.hw_config = adl_hw_config; 7086 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; 7087 7088 td_attr = adl_hybrid_events_attrs; 7089 mem_attr = adl_hybrid_mem_attrs; 7090 tsx_attr = adl_hybrid_tsx_attrs; 7091 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7092 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; 7093 7094 /* Initialize big core specific PerfMon capabilities.*/ 7095 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7096 intel_pmu_init_glc(&pmu->pmu); 7097 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 7098 pmu->cntr_mask64 <<= 2; 7099 pmu->cntr_mask64 |= 0x3; 7100 pmu->fixed_cntr_mask64 <<= 1; 7101 pmu->fixed_cntr_mask64 |= 0x1; 7102 } else { 7103 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 7104 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 7105 } 7106 7107 /* 7108 * Quirk: For some Alder Lake machine, when all E-cores are disabled in 7109 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However, 7110 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will 7111 * mistakenly add extra counters for P-cores. Correct the number of 7112 * counters here. 7113 */ 7114 if ((x86_pmu_num_counters(&pmu->pmu) > 8) || (x86_pmu_num_counters_fixed(&pmu->pmu) > 4)) { 7115 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 7116 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 7117 } 7118 7119 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 7120 pmu->unconstrained = (struct event_constraint) 7121 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 7122 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 7123 7124 pmu->extra_regs = intel_glc_extra_regs; 7125 7126 /* Initialize Atom core specific PerfMon capabilities.*/ 7127 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7128 intel_pmu_init_grt(&pmu->pmu); 7129 7130 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 7131 intel_pmu_pebs_data_source_adl(); 7132 pr_cont("Alderlake Hybrid events, "); 7133 name = "alderlake_hybrid"; 7134 break; 7135 7136 case INTEL_METEORLAKE: 7137 case INTEL_METEORLAKE_L: 7138 intel_pmu_init_hybrid(hybrid_big_small); 7139 7140 x86_pmu.pebs_latency_data = cmt_latency_data; 7141 x86_pmu.get_event_constraints = mtl_get_event_constraints; 7142 x86_pmu.hw_config = adl_hw_config; 7143 7144 td_attr = adl_hybrid_events_attrs; 7145 mem_attr = mtl_hybrid_mem_attrs; 7146 tsx_attr = adl_hybrid_tsx_attrs; 7147 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7148 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 7149 7150 /* Initialize big core specific PerfMon capabilities.*/ 7151 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7152 intel_pmu_init_glc(&pmu->pmu); 7153 pmu->extra_regs = intel_rwc_extra_regs; 7154 7155 /* Initialize Atom core specific PerfMon capabilities.*/ 7156 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7157 intel_pmu_init_grt(&pmu->pmu); 7158 pmu->extra_regs = intel_cmt_extra_regs; 7159 7160 intel_pmu_pebs_data_source_mtl(); 7161 pr_cont("Meteorlake Hybrid events, "); 7162 name = "meteorlake_hybrid"; 7163 break; 7164 7165 case INTEL_LUNARLAKE_M: 7166 case INTEL_ARROWLAKE: 7167 intel_pmu_init_hybrid(hybrid_big_small); 7168 7169 x86_pmu.pebs_latency_data = lnl_latency_data; 7170 x86_pmu.get_event_constraints = mtl_get_event_constraints; 7171 x86_pmu.hw_config = adl_hw_config; 7172 7173 td_attr = lnl_hybrid_events_attrs; 7174 mem_attr = mtl_hybrid_mem_attrs; 7175 tsx_attr = adl_hybrid_tsx_attrs; 7176 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7177 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 7178 7179 /* Initialize big core specific PerfMon capabilities.*/ 7180 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7181 intel_pmu_init_lnc(&pmu->pmu); 7182 7183 /* Initialize Atom core specific PerfMon capabilities.*/ 7184 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7185 intel_pmu_init_skt(&pmu->pmu); 7186 7187 intel_pmu_pebs_data_source_lnl(); 7188 pr_cont("Lunarlake Hybrid events, "); 7189 name = "lunarlake_hybrid"; 7190 break; 7191 7192 case INTEL_ARROWLAKE_H: 7193 intel_pmu_init_hybrid(hybrid_big_small_tiny); 7194 7195 x86_pmu.pebs_latency_data = arl_h_latency_data; 7196 x86_pmu.get_event_constraints = arl_h_get_event_constraints; 7197 x86_pmu.hw_config = arl_h_hw_config; 7198 7199 td_attr = arl_h_hybrid_events_attrs; 7200 mem_attr = arl_h_hybrid_mem_attrs; 7201 tsx_attr = adl_hybrid_tsx_attrs; 7202 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7203 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 7204 7205 /* Initialize big core specific PerfMon capabilities. */ 7206 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7207 intel_pmu_init_lnc(&pmu->pmu); 7208 7209 /* Initialize Atom core specific PerfMon capabilities. */ 7210 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7211 intel_pmu_init_skt(&pmu->pmu); 7212 7213 /* Initialize Lower Power Atom specific PerfMon capabilities. */ 7214 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX]; 7215 intel_pmu_init_grt(&pmu->pmu); 7216 pmu->extra_regs = intel_cmt_extra_regs; 7217 7218 intel_pmu_pebs_data_source_arl_h(); 7219 pr_cont("ArrowLake-H Hybrid events, "); 7220 name = "arrowlake_h_hybrid"; 7221 break; 7222 7223 default: 7224 switch (x86_pmu.version) { 7225 case 1: 7226 x86_pmu.event_constraints = intel_v1_event_constraints; 7227 pr_cont("generic architected perfmon v1, "); 7228 name = "generic_arch_v1"; 7229 break; 7230 case 2: 7231 case 3: 7232 case 4: 7233 /* 7234 * default constraints for v2 and up 7235 */ 7236 x86_pmu.event_constraints = intel_gen_event_constraints; 7237 pr_cont("generic architected perfmon, "); 7238 name = "generic_arch_v2+"; 7239 break; 7240 default: 7241 /* 7242 * The default constraints for v5 and up can support up to 7243 * 16 fixed counters. For the fixed counters 4 and later, 7244 * the pseudo-encoding is applied. 7245 * The constraints may be cut according to the CPUID enumeration 7246 * by inserting the EVENT_CONSTRAINT_END. 7247 */ 7248 if (fls64(x86_pmu.fixed_cntr_mask64) > INTEL_PMC_MAX_FIXED) 7249 x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0); 7250 intel_v5_gen_event_constraints[fls64(x86_pmu.fixed_cntr_mask64)].weight = -1; 7251 x86_pmu.event_constraints = intel_v5_gen_event_constraints; 7252 pr_cont("generic architected perfmon, "); 7253 name = "generic_arch_v5+"; 7254 break; 7255 } 7256 } 7257 7258 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 7259 7260 if (!is_hybrid()) { 7261 group_events_td.attrs = td_attr; 7262 group_events_mem.attrs = mem_attr; 7263 group_events_tsx.attrs = tsx_attr; 7264 group_format_extra.attrs = extra_attr; 7265 group_format_extra_skl.attrs = extra_skl_attr; 7266 7267 x86_pmu.attr_update = attr_update; 7268 } else { 7269 hybrid_group_events_td.attrs = td_attr; 7270 hybrid_group_events_mem.attrs = mem_attr; 7271 hybrid_group_events_tsx.attrs = tsx_attr; 7272 hybrid_group_format_extra.attrs = extra_attr; 7273 7274 x86_pmu.attr_update = hybrid_attr_update; 7275 } 7276 7277 intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64, 7278 &x86_pmu.fixed_cntr_mask64, 7279 &x86_pmu.intel_ctrl); 7280 7281 /* AnyThread may be deprecated on arch perfmon v5 or later */ 7282 if (x86_pmu.intel_cap.anythread_deprecated) 7283 x86_pmu.format_attrs = intel_arch_formats_attr; 7284 7285 intel_pmu_check_event_constraints(x86_pmu.event_constraints, 7286 x86_pmu.cntr_mask64, 7287 x86_pmu.fixed_cntr_mask64, 7288 x86_pmu.intel_ctrl); 7289 /* 7290 * Access LBR MSR may cause #GP under certain circumstances. 7291 * Check all LBR MSR here. 7292 * Disable LBR access if any LBR MSRs can not be accessed. 7293 */ 7294 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 7295 x86_pmu.lbr_nr = 0; 7296 for (i = 0; i < x86_pmu.lbr_nr; i++) { 7297 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 7298 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 7299 x86_pmu.lbr_nr = 0; 7300 } 7301 7302 if (x86_pmu.lbr_nr) { 7303 intel_pmu_lbr_init(); 7304 7305 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 7306 7307 /* only support branch_stack snapshot for perfmon >= v2 */ 7308 if (x86_pmu.disable_all == intel_pmu_disable_all) { 7309 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) { 7310 static_call_update(perf_snapshot_branch_stack, 7311 intel_pmu_snapshot_arch_branch_stack); 7312 } else { 7313 static_call_update(perf_snapshot_branch_stack, 7314 intel_pmu_snapshot_branch_stack); 7315 } 7316 } 7317 } 7318 7319 intel_pmu_check_extra_regs(x86_pmu.extra_regs); 7320 7321 /* Support full width counters using alternative MSR range */ 7322 if (x86_pmu.intel_cap.full_width_write) { 7323 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 7324 x86_pmu.perfctr = MSR_IA32_PMC0; 7325 pr_cont("full-width counters, "); 7326 } 7327 7328 /* Support V6+ MSR Aliasing */ 7329 if (x86_pmu.version >= 6) { 7330 x86_pmu.perfctr = MSR_IA32_PMC_V6_GP0_CTR; 7331 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A; 7332 x86_pmu.fixedctr = MSR_IA32_PMC_V6_FX0_CTR; 7333 x86_pmu.addr_offset = intel_pmu_v6_addr_offset; 7334 } 7335 7336 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 7337 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 7338 7339 if (x86_pmu.intel_cap.pebs_timing_info) 7340 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY; 7341 7342 intel_aux_output_init(); 7343 7344 return 0; 7345 } 7346 7347 /* 7348 * HT bug: phase 2 init 7349 * Called once we have valid topology information to check 7350 * whether or not HT is enabled 7351 * If HT is off, then we disable the workaround 7352 */ 7353 static __init int fixup_ht_bug(void) 7354 { 7355 int c; 7356 /* 7357 * problem not present on this CPU model, nothing to do 7358 */ 7359 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 7360 return 0; 7361 7362 if (topology_max_smt_threads() > 1) { 7363 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 7364 return 0; 7365 } 7366 7367 cpus_read_lock(); 7368 7369 hardlockup_detector_perf_stop(); 7370 7371 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 7372 7373 x86_pmu.start_scheduling = NULL; 7374 x86_pmu.commit_scheduling = NULL; 7375 x86_pmu.stop_scheduling = NULL; 7376 7377 hardlockup_detector_perf_restart(); 7378 7379 for_each_online_cpu(c) 7380 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 7381 7382 cpus_read_unlock(); 7383 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 7384 return 0; 7385 } 7386 subsys_initcall(fixup_ht_bug) 7387