1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Per core/cpu state 4 * 5 * Used to coordinate shared registers between HT threads or 6 * among events on a single PMU. 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/stddef.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/export.h> 16 #include <linux/nmi.h> 17 #include <linux/kvm_host.h> 18 19 #include <asm/cpufeature.h> 20 #include <asm/cpuid/api.h> 21 #include <asm/debugreg.h> 22 #include <asm/hardirq.h> 23 #include <asm/intel-family.h> 24 #include <asm/intel_pt.h> 25 #include <asm/apic.h> 26 #include <asm/cpu_device_id.h> 27 #include <asm/msr.h> 28 29 #include "../perf_event.h" 30 31 /* 32 * Intel PerfMon, used on Core and later. 33 */ 34 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 35 { 36 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 37 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 38 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 39 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 40 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 41 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 42 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 43 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 44 }; 45 46 static struct event_constraint intel_core_event_constraints[] __read_mostly = 47 { 48 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 49 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 50 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 51 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 52 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 53 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 54 EVENT_CONSTRAINT_END 55 }; 56 57 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 58 { 59 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 60 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 61 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 62 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 63 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 64 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 65 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 66 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 67 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 68 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 69 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 70 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 71 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 72 EVENT_CONSTRAINT_END 73 }; 74 75 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 76 { 77 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 78 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 79 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 80 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 81 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 82 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 83 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 84 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 85 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 86 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 87 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 88 EVENT_CONSTRAINT_END 89 }; 90 91 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 92 { 93 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 94 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 95 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 96 EVENT_EXTRA_END 97 }; 98 99 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 100 { 101 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 102 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 103 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 104 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 105 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 106 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 107 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 108 EVENT_CONSTRAINT_END 109 }; 110 111 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 112 { 113 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 114 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 115 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 116 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 117 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 118 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 119 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 120 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 121 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 122 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 123 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 124 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 125 126 /* 127 * When HT is off these events can only run on the bottom 4 counters 128 * When HT is on, they are impacted by the HT bug and require EXCL access 129 */ 130 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 131 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 132 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 133 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 134 135 EVENT_CONSTRAINT_END 136 }; 137 138 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 139 { 140 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 141 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 142 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 143 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 144 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ 145 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 146 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 147 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 148 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 149 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 150 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 151 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 152 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 153 154 /* 155 * When HT is off these events can only run on the bottom 4 counters 156 * When HT is on, they are impacted by the HT bug and require EXCL access 157 */ 158 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 159 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 160 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 161 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 162 163 EVENT_CONSTRAINT_END 164 }; 165 166 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 167 { 168 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 169 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 170 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 171 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 172 EVENT_EXTRA_END 173 }; 174 175 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 176 { 177 EVENT_CONSTRAINT_END 178 }; 179 180 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 181 { 182 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 183 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 184 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 185 EVENT_CONSTRAINT_END 186 }; 187 188 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly = 189 { 190 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 191 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 192 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 193 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 194 FIXED_EVENT_CONSTRAINT(0x0500, 4), 195 FIXED_EVENT_CONSTRAINT(0x0600, 5), 196 FIXED_EVENT_CONSTRAINT(0x0700, 6), 197 FIXED_EVENT_CONSTRAINT(0x0800, 7), 198 FIXED_EVENT_CONSTRAINT(0x0900, 8), 199 FIXED_EVENT_CONSTRAINT(0x0a00, 9), 200 FIXED_EVENT_CONSTRAINT(0x0b00, 10), 201 FIXED_EVENT_CONSTRAINT(0x0c00, 11), 202 FIXED_EVENT_CONSTRAINT(0x0d00, 12), 203 FIXED_EVENT_CONSTRAINT(0x0e00, 13), 204 FIXED_EVENT_CONSTRAINT(0x0f00, 14), 205 FIXED_EVENT_CONSTRAINT(0x1000, 15), 206 EVENT_CONSTRAINT_END 207 }; 208 209 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 210 { 211 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 212 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 213 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 214 EVENT_CONSTRAINT_END 215 }; 216 217 static struct event_constraint intel_grt_event_constraints[] __read_mostly = { 218 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 219 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 220 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 221 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 222 EVENT_CONSTRAINT_END 223 }; 224 225 static struct event_constraint intel_skt_event_constraints[] __read_mostly = { 226 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 227 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 228 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 229 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 230 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */ 231 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */ 232 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */ 233 EVENT_CONSTRAINT_END 234 }; 235 236 static struct event_constraint intel_arw_event_constraints[] __read_mostly = { 237 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 238 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 239 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 240 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 241 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */ 242 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */ 243 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */ 244 INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1), 245 INTEL_UEVENT_CONSTRAINT(0x02b7, 0x2), 246 INTEL_UEVENT_CONSTRAINT(0x04b7, 0x4), 247 INTEL_UEVENT_CONSTRAINT(0x08b7, 0x8), 248 INTEL_UEVENT_CONSTRAINT(0x01d4, 0x1), 249 INTEL_UEVENT_CONSTRAINT(0x02d4, 0x2), 250 INTEL_UEVENT_CONSTRAINT(0x04d4, 0x4), 251 INTEL_UEVENT_CONSTRAINT(0x08d4, 0x8), 252 INTEL_UEVENT_CONSTRAINT(0x0175, 0x1), 253 INTEL_UEVENT_CONSTRAINT(0x0275, 0x2), 254 INTEL_UEVENT_CONSTRAINT(0x21d3, 0x1), 255 INTEL_UEVENT_CONSTRAINT(0x22d3, 0x1), 256 EVENT_CONSTRAINT_END 257 }; 258 259 static struct event_constraint intel_skl_event_constraints[] = { 260 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 261 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 262 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 263 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 264 265 /* 266 * when HT is off, these can only run on the bottom 4 counters 267 */ 268 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 269 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 270 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 271 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 272 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 273 274 EVENT_CONSTRAINT_END 275 }; 276 277 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 278 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 279 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 280 EVENT_EXTRA_END 281 }; 282 283 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 284 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 285 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 286 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 287 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 288 EVENT_EXTRA_END 289 }; 290 291 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 292 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 293 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 294 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 295 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 296 EVENT_EXTRA_END 297 }; 298 299 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 300 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 301 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 302 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 303 /* 304 * Note the low 8 bits eventsel code is not a continuous field, containing 305 * some #GPing bits. These are masked out. 306 */ 307 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 308 EVENT_EXTRA_END 309 }; 310 311 static struct event_constraint intel_icl_event_constraints[] = { 312 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 313 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ 314 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 315 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 316 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 317 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 318 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 319 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 320 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 321 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 322 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 323 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 324 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 325 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf), 326 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 327 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 328 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 329 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 330 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 331 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 332 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 333 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 334 INTEL_EVENT_CONSTRAINT(0xef, 0xf), 335 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 336 EVENT_CONSTRAINT_END 337 }; 338 339 static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 340 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 341 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 342 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 343 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 344 EVENT_EXTRA_END 345 }; 346 347 static struct extra_reg intel_glc_extra_regs[] __read_mostly = { 348 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 349 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 350 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 351 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 352 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 353 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 354 EVENT_EXTRA_END 355 }; 356 357 static struct event_constraint intel_glc_event_constraints[] = { 358 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 359 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 360 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 361 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 362 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 363 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 364 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 365 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 366 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 367 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 368 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 369 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 370 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 371 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 372 373 INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 374 INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 375 /* 376 * Generally event codes < 0x90 are restricted to counters 0-3. 377 * The 0x2E and 0x3C are exception, which has no restriction. 378 */ 379 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 380 381 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 382 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 383 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 384 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 385 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 386 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 387 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 388 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 389 /* 390 * Generally event codes >= 0x90 are likely to have no restrictions. 391 * The exception are defined as above. 392 */ 393 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 394 395 EVENT_CONSTRAINT_END 396 }; 397 398 static struct extra_reg intel_rwc_extra_regs[] __read_mostly = { 399 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 400 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 401 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 402 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 403 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 404 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 405 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 406 EVENT_EXTRA_END 407 }; 408 409 static struct event_constraint intel_lnc_event_constraints[] = { 410 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 411 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 412 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 413 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 414 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 415 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 416 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 417 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 418 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 419 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 420 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 421 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 422 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 423 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 424 425 INTEL_EVENT_CONSTRAINT(0x20, 0xf), 426 427 INTEL_UEVENT_CONSTRAINT(0x012a, 0xf), 428 INTEL_UEVENT_CONSTRAINT(0x012b, 0xf), 429 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), 430 INTEL_UEVENT_CONSTRAINT(0x0175, 0x4), 431 432 INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff), 433 INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff), 434 435 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 436 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 437 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 438 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 439 INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1), 440 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8), 441 INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc), 442 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3), 443 444 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 445 446 INTEL_UEVENT_CONSTRAINT(0x00e0, 0xf), 447 448 EVENT_CONSTRAINT_END 449 }; 450 451 static struct extra_reg intel_lnc_extra_regs[] __read_mostly = { 452 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0), 453 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1), 454 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 455 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 456 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 457 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE), 458 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 459 EVENT_EXTRA_END 460 }; 461 462 static struct event_constraint intel_pnc_event_constraints[] = { 463 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 464 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 465 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 466 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 467 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 468 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 469 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 470 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 471 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 472 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 473 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 474 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 475 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 476 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 477 478 INTEL_EVENT_CONSTRAINT(0x20, 0xf), 479 INTEL_EVENT_CONSTRAINT(0x79, 0xf), 480 481 INTEL_UEVENT_CONSTRAINT(0x0275, 0xf), 482 INTEL_UEVENT_CONSTRAINT(0x0176, 0xf), 483 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 484 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 485 INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfc), 486 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3), 487 488 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), 489 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), 490 INTEL_EVENT_CONSTRAINT(0xd4, 0xf), 491 INTEL_EVENT_CONSTRAINT(0xd6, 0xf), 492 INTEL_EVENT_CONSTRAINT(0xdf, 0xf), 493 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 494 495 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8), 496 INTEL_UEVENT_CONSTRAINT(0x0847, 0xf), 497 INTEL_UEVENT_CONSTRAINT(0x0446, 0xf), 498 INTEL_UEVENT_CONSTRAINT(0x0846, 0xf), 499 INTEL_UEVENT_CONSTRAINT(0x0148, 0xf), 500 501 EVENT_CONSTRAINT_END 502 }; 503 504 static struct extra_reg intel_pnc_extra_regs[] __read_mostly = { 505 /* must define OMR_X first, see intel_alt_er() */ 506 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0), 507 INTEL_UEVENT_EXTRA_REG(0x022a, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1), 508 INTEL_UEVENT_EXTRA_REG(0x042a, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2), 509 INTEL_UEVENT_EXTRA_REG(0x082a, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3), 510 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 511 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 512 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 513 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE), 514 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 515 EVENT_EXTRA_END 516 }; 517 518 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 519 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 520 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 521 522 static struct attribute *nhm_mem_events_attrs[] = { 523 EVENT_PTR(mem_ld_nhm), 524 NULL, 525 }; 526 527 /* 528 * topdown events for Intel Core CPUs. 529 * 530 * The events are all in slots, which is a free slot in a 4 wide 531 * pipeline. Some events are already reported in slots, for cycle 532 * events we multiply by the pipeline width (4). 533 * 534 * With Hyper Threading on, topdown metrics are either summed or averaged 535 * between the threads of a core: (count_t0 + count_t1). 536 * 537 * For the average case the metric is always scaled to pipeline width, 538 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 539 */ 540 541 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 542 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 543 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 544 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 545 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 546 "event=0xe,umask=0x1"); /* uops_issued.any */ 547 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 548 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 549 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 550 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 551 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 552 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 553 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 554 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 555 "4", "2"); 556 557 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 558 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 559 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 560 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 561 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 562 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 563 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 564 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 565 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 566 567 static struct attribute *snb_events_attrs[] = { 568 EVENT_PTR(td_slots_issued), 569 EVENT_PTR(td_slots_retired), 570 EVENT_PTR(td_fetch_bubbles), 571 EVENT_PTR(td_total_slots), 572 EVENT_PTR(td_total_slots_scale), 573 EVENT_PTR(td_recovery_bubbles), 574 EVENT_PTR(td_recovery_bubbles_scale), 575 NULL, 576 }; 577 578 static struct attribute *snb_mem_events_attrs[] = { 579 EVENT_PTR(mem_ld_snb), 580 EVENT_PTR(mem_st_snb), 581 NULL, 582 }; 583 584 static struct event_constraint intel_hsw_event_constraints[] = { 585 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 586 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 587 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 588 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 589 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 590 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 591 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 592 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 593 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 594 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 595 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 596 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 597 598 /* 599 * When HT is off these events can only run on the bottom 4 counters 600 * When HT is on, they are impacted by the HT bug and require EXCL access 601 */ 602 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 603 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 604 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 605 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 606 607 EVENT_CONSTRAINT_END 608 }; 609 610 static struct event_constraint intel_bdw_event_constraints[] = { 611 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 612 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 613 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 614 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 615 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 616 /* 617 * when HT is off, these can only run on the bottom 4 counters 618 */ 619 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 620 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 621 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 622 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 623 EVENT_CONSTRAINT_END 624 }; 625 626 static u64 intel_pmu_event_map(int hw_event) 627 { 628 return intel_perfmon_event_map[hw_event]; 629 } 630 631 static __initconst const u64 glc_hw_cache_event_ids 632 [PERF_COUNT_HW_CACHE_MAX] 633 [PERF_COUNT_HW_CACHE_OP_MAX] 634 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 635 { 636 [ C(L1D ) ] = { 637 [ C(OP_READ) ] = { 638 [ C(RESULT_ACCESS) ] = 0x81d0, 639 [ C(RESULT_MISS) ] = 0xe124, 640 }, 641 [ C(OP_WRITE) ] = { 642 [ C(RESULT_ACCESS) ] = 0x82d0, 643 }, 644 }, 645 [ C(L1I ) ] = { 646 [ C(OP_READ) ] = { 647 [ C(RESULT_MISS) ] = 0xe424, 648 }, 649 [ C(OP_WRITE) ] = { 650 [ C(RESULT_ACCESS) ] = -1, 651 [ C(RESULT_MISS) ] = -1, 652 }, 653 }, 654 [ C(LL ) ] = { 655 [ C(OP_READ) ] = { 656 [ C(RESULT_ACCESS) ] = 0x12a, 657 [ C(RESULT_MISS) ] = 0x12a, 658 }, 659 [ C(OP_WRITE) ] = { 660 [ C(RESULT_ACCESS) ] = 0x12a, 661 [ C(RESULT_MISS) ] = 0x12a, 662 }, 663 }, 664 [ C(DTLB) ] = { 665 [ C(OP_READ) ] = { 666 [ C(RESULT_ACCESS) ] = 0x81d0, 667 [ C(RESULT_MISS) ] = 0xe12, 668 }, 669 [ C(OP_WRITE) ] = { 670 [ C(RESULT_ACCESS) ] = 0x82d0, 671 [ C(RESULT_MISS) ] = 0xe13, 672 }, 673 }, 674 [ C(ITLB) ] = { 675 [ C(OP_READ) ] = { 676 [ C(RESULT_ACCESS) ] = -1, 677 [ C(RESULT_MISS) ] = 0xe11, 678 }, 679 [ C(OP_WRITE) ] = { 680 [ C(RESULT_ACCESS) ] = -1, 681 [ C(RESULT_MISS) ] = -1, 682 }, 683 [ C(OP_PREFETCH) ] = { 684 [ C(RESULT_ACCESS) ] = -1, 685 [ C(RESULT_MISS) ] = -1, 686 }, 687 }, 688 [ C(BPU ) ] = { 689 [ C(OP_READ) ] = { 690 [ C(RESULT_ACCESS) ] = 0x4c4, 691 [ C(RESULT_MISS) ] = 0x4c5, 692 }, 693 [ C(OP_WRITE) ] = { 694 [ C(RESULT_ACCESS) ] = -1, 695 [ C(RESULT_MISS) ] = -1, 696 }, 697 [ C(OP_PREFETCH) ] = { 698 [ C(RESULT_ACCESS) ] = -1, 699 [ C(RESULT_MISS) ] = -1, 700 }, 701 }, 702 [ C(NODE) ] = { 703 [ C(OP_READ) ] = { 704 [ C(RESULT_ACCESS) ] = 0x12a, 705 [ C(RESULT_MISS) ] = 0x12a, 706 }, 707 }, 708 }; 709 710 static __initconst const u64 glc_hw_cache_extra_regs 711 [PERF_COUNT_HW_CACHE_MAX] 712 [PERF_COUNT_HW_CACHE_OP_MAX] 713 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 714 { 715 [ C(LL ) ] = { 716 [ C(OP_READ) ] = { 717 [ C(RESULT_ACCESS) ] = 0x10001, 718 [ C(RESULT_MISS) ] = 0x3fbfc00001, 719 }, 720 [ C(OP_WRITE) ] = { 721 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, 722 [ C(RESULT_MISS) ] = 0x3f3fc00002, 723 }, 724 }, 725 [ C(NODE) ] = { 726 [ C(OP_READ) ] = { 727 [ C(RESULT_ACCESS) ] = 0x10c000001, 728 [ C(RESULT_MISS) ] = 0x3fb3000001, 729 }, 730 }, 731 }; 732 733 static __initconst const u64 pnc_hw_cache_event_ids 734 [PERF_COUNT_HW_CACHE_MAX] 735 [PERF_COUNT_HW_CACHE_OP_MAX] 736 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 737 { 738 [ C(L1D ) ] = { 739 [ C(OP_READ) ] = { 740 [ C(RESULT_ACCESS) ] = 0x81d0, 741 [ C(RESULT_MISS) ] = 0xe124, 742 }, 743 [ C(OP_WRITE) ] = { 744 [ C(RESULT_ACCESS) ] = 0x82d0, 745 }, 746 }, 747 [ C(L1I ) ] = { 748 [ C(OP_READ) ] = { 749 [ C(RESULT_MISS) ] = 0xe424, 750 }, 751 [ C(OP_WRITE) ] = { 752 [ C(RESULT_ACCESS) ] = -1, 753 [ C(RESULT_MISS) ] = -1, 754 }, 755 }, 756 [ C(LL ) ] = { 757 [ C(OP_READ) ] = { 758 [ C(RESULT_ACCESS) ] = 0x12a, 759 [ C(RESULT_MISS) ] = 0x12a, 760 }, 761 [ C(OP_WRITE) ] = { 762 [ C(RESULT_ACCESS) ] = 0x12a, 763 [ C(RESULT_MISS) ] = 0x12a, 764 }, 765 }, 766 [ C(DTLB) ] = { 767 [ C(OP_READ) ] = { 768 [ C(RESULT_ACCESS) ] = 0x81d0, 769 [ C(RESULT_MISS) ] = 0xe12, 770 }, 771 [ C(OP_WRITE) ] = { 772 [ C(RESULT_ACCESS) ] = 0x82d0, 773 [ C(RESULT_MISS) ] = 0xe13, 774 }, 775 }, 776 [ C(ITLB) ] = { 777 [ C(OP_READ) ] = { 778 [ C(RESULT_ACCESS) ] = -1, 779 [ C(RESULT_MISS) ] = 0xe11, 780 }, 781 [ C(OP_WRITE) ] = { 782 [ C(RESULT_ACCESS) ] = -1, 783 [ C(RESULT_MISS) ] = -1, 784 }, 785 [ C(OP_PREFETCH) ] = { 786 [ C(RESULT_ACCESS) ] = -1, 787 [ C(RESULT_MISS) ] = -1, 788 }, 789 }, 790 [ C(BPU ) ] = { 791 [ C(OP_READ) ] = { 792 [ C(RESULT_ACCESS) ] = 0x4c4, 793 [ C(RESULT_MISS) ] = 0x4c5, 794 }, 795 [ C(OP_WRITE) ] = { 796 [ C(RESULT_ACCESS) ] = -1, 797 [ C(RESULT_MISS) ] = -1, 798 }, 799 [ C(OP_PREFETCH) ] = { 800 [ C(RESULT_ACCESS) ] = -1, 801 [ C(RESULT_MISS) ] = -1, 802 }, 803 }, 804 [ C(NODE) ] = { 805 [ C(OP_READ) ] = { 806 [ C(RESULT_ACCESS) ] = -1, 807 [ C(RESULT_MISS) ] = -1, 808 }, 809 }, 810 }; 811 812 static __initconst const u64 pnc_hw_cache_extra_regs 813 [PERF_COUNT_HW_CACHE_MAX] 814 [PERF_COUNT_HW_CACHE_OP_MAX] 815 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 816 { 817 [ C(LL ) ] = { 818 [ C(OP_READ) ] = { 819 [ C(RESULT_ACCESS) ] = 0x4000000000000001, 820 [ C(RESULT_MISS) ] = 0xFFFFF000000001, 821 }, 822 [ C(OP_WRITE) ] = { 823 [ C(RESULT_ACCESS) ] = 0x4000000000000002, 824 [ C(RESULT_MISS) ] = 0xFFFFF000000002, 825 }, 826 }, 827 }; 828 829 /* 830 * Notes on the events: 831 * - data reads do not include code reads (comparable to earlier tables) 832 * - data counts include speculative execution (except L1 write, dtlb, bpu) 833 * - remote node access includes remote memory, remote cache, remote mmio. 834 * - prefetches are not included in the counts. 835 * - icache miss does not include decoded icache 836 */ 837 838 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 839 #define SKL_DEMAND_RFO BIT_ULL(1) 840 #define SKL_ANY_RESPONSE BIT_ULL(16) 841 #define SKL_SUPPLIER_NONE BIT_ULL(17) 842 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 843 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 844 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 845 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 846 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 847 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 848 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 849 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 850 #define SKL_SPL_HIT BIT_ULL(30) 851 #define SKL_SNOOP_NONE BIT_ULL(31) 852 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 853 #define SKL_SNOOP_MISS BIT_ULL(33) 854 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 855 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 856 #define SKL_SNOOP_HITM BIT_ULL(36) 857 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 858 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 859 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 860 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 861 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 862 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 863 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 864 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 865 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 866 SKL_SNOOP_HITM|SKL_SPL_HIT) 867 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 868 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 869 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 870 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 871 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 872 873 static __initconst const u64 skl_hw_cache_event_ids 874 [PERF_COUNT_HW_CACHE_MAX] 875 [PERF_COUNT_HW_CACHE_OP_MAX] 876 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 877 { 878 [ C(L1D ) ] = { 879 [ C(OP_READ) ] = { 880 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 881 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 882 }, 883 [ C(OP_WRITE) ] = { 884 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 885 [ C(RESULT_MISS) ] = 0x0, 886 }, 887 [ C(OP_PREFETCH) ] = { 888 [ C(RESULT_ACCESS) ] = 0x0, 889 [ C(RESULT_MISS) ] = 0x0, 890 }, 891 }, 892 [ C(L1I ) ] = { 893 [ C(OP_READ) ] = { 894 [ C(RESULT_ACCESS) ] = 0x0, 895 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 896 }, 897 [ C(OP_WRITE) ] = { 898 [ C(RESULT_ACCESS) ] = -1, 899 [ C(RESULT_MISS) ] = -1, 900 }, 901 [ C(OP_PREFETCH) ] = { 902 [ C(RESULT_ACCESS) ] = 0x0, 903 [ C(RESULT_MISS) ] = 0x0, 904 }, 905 }, 906 [ C(LL ) ] = { 907 [ C(OP_READ) ] = { 908 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 909 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 910 }, 911 [ C(OP_WRITE) ] = { 912 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 913 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 914 }, 915 [ C(OP_PREFETCH) ] = { 916 [ C(RESULT_ACCESS) ] = 0x0, 917 [ C(RESULT_MISS) ] = 0x0, 918 }, 919 }, 920 [ C(DTLB) ] = { 921 [ C(OP_READ) ] = { 922 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 923 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 924 }, 925 [ C(OP_WRITE) ] = { 926 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 927 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 928 }, 929 [ C(OP_PREFETCH) ] = { 930 [ C(RESULT_ACCESS) ] = 0x0, 931 [ C(RESULT_MISS) ] = 0x0, 932 }, 933 }, 934 [ C(ITLB) ] = { 935 [ C(OP_READ) ] = { 936 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 937 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 938 }, 939 [ C(OP_WRITE) ] = { 940 [ C(RESULT_ACCESS) ] = -1, 941 [ C(RESULT_MISS) ] = -1, 942 }, 943 [ C(OP_PREFETCH) ] = { 944 [ C(RESULT_ACCESS) ] = -1, 945 [ C(RESULT_MISS) ] = -1, 946 }, 947 }, 948 [ C(BPU ) ] = { 949 [ C(OP_READ) ] = { 950 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 951 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 952 }, 953 [ C(OP_WRITE) ] = { 954 [ C(RESULT_ACCESS) ] = -1, 955 [ C(RESULT_MISS) ] = -1, 956 }, 957 [ C(OP_PREFETCH) ] = { 958 [ C(RESULT_ACCESS) ] = -1, 959 [ C(RESULT_MISS) ] = -1, 960 }, 961 }, 962 [ C(NODE) ] = { 963 [ C(OP_READ) ] = { 964 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 965 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 966 }, 967 [ C(OP_WRITE) ] = { 968 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 969 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 970 }, 971 [ C(OP_PREFETCH) ] = { 972 [ C(RESULT_ACCESS) ] = 0x0, 973 [ C(RESULT_MISS) ] = 0x0, 974 }, 975 }, 976 }; 977 978 static __initconst const u64 skl_hw_cache_extra_regs 979 [PERF_COUNT_HW_CACHE_MAX] 980 [PERF_COUNT_HW_CACHE_OP_MAX] 981 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 982 { 983 [ C(LL ) ] = { 984 [ C(OP_READ) ] = { 985 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 986 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 987 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 988 SKL_L3_MISS|SKL_ANY_SNOOP| 989 SKL_SUPPLIER_NONE, 990 }, 991 [ C(OP_WRITE) ] = { 992 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 993 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 994 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 995 SKL_L3_MISS|SKL_ANY_SNOOP| 996 SKL_SUPPLIER_NONE, 997 }, 998 [ C(OP_PREFETCH) ] = { 999 [ C(RESULT_ACCESS) ] = 0x0, 1000 [ C(RESULT_MISS) ] = 0x0, 1001 }, 1002 }, 1003 [ C(NODE) ] = { 1004 [ C(OP_READ) ] = { 1005 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 1006 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 1007 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 1008 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 1009 }, 1010 [ C(OP_WRITE) ] = { 1011 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 1012 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 1013 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 1014 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 1015 }, 1016 [ C(OP_PREFETCH) ] = { 1017 [ C(RESULT_ACCESS) ] = 0x0, 1018 [ C(RESULT_MISS) ] = 0x0, 1019 }, 1020 }, 1021 }; 1022 1023 #define SNB_DMND_DATA_RD (1ULL << 0) 1024 #define SNB_DMND_RFO (1ULL << 1) 1025 #define SNB_DMND_IFETCH (1ULL << 2) 1026 #define SNB_DMND_WB (1ULL << 3) 1027 #define SNB_PF_DATA_RD (1ULL << 4) 1028 #define SNB_PF_RFO (1ULL << 5) 1029 #define SNB_PF_IFETCH (1ULL << 6) 1030 #define SNB_LLC_DATA_RD (1ULL << 7) 1031 #define SNB_LLC_RFO (1ULL << 8) 1032 #define SNB_LLC_IFETCH (1ULL << 9) 1033 #define SNB_BUS_LOCKS (1ULL << 10) 1034 #define SNB_STRM_ST (1ULL << 11) 1035 #define SNB_OTHER (1ULL << 15) 1036 #define SNB_RESP_ANY (1ULL << 16) 1037 #define SNB_NO_SUPP (1ULL << 17) 1038 #define SNB_LLC_HITM (1ULL << 18) 1039 #define SNB_LLC_HITE (1ULL << 19) 1040 #define SNB_LLC_HITS (1ULL << 20) 1041 #define SNB_LLC_HITF (1ULL << 21) 1042 #define SNB_LOCAL (1ULL << 22) 1043 #define SNB_REMOTE (0xffULL << 23) 1044 #define SNB_SNP_NONE (1ULL << 31) 1045 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 1046 #define SNB_SNP_MISS (1ULL << 33) 1047 #define SNB_NO_FWD (1ULL << 34) 1048 #define SNB_SNP_FWD (1ULL << 35) 1049 #define SNB_HITM (1ULL << 36) 1050 #define SNB_NON_DRAM (1ULL << 37) 1051 1052 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 1053 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 1054 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1055 1056 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 1057 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 1058 SNB_HITM) 1059 1060 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 1061 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 1062 1063 #define SNB_L3_ACCESS SNB_RESP_ANY 1064 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 1065 1066 static __initconst const u64 snb_hw_cache_extra_regs 1067 [PERF_COUNT_HW_CACHE_MAX] 1068 [PERF_COUNT_HW_CACHE_OP_MAX] 1069 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1070 { 1071 [ C(LL ) ] = { 1072 [ C(OP_READ) ] = { 1073 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 1074 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 1075 }, 1076 [ C(OP_WRITE) ] = { 1077 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 1078 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 1079 }, 1080 [ C(OP_PREFETCH) ] = { 1081 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 1082 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 1083 }, 1084 }, 1085 [ C(NODE) ] = { 1086 [ C(OP_READ) ] = { 1087 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 1088 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 1089 }, 1090 [ C(OP_WRITE) ] = { 1091 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 1092 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 1093 }, 1094 [ C(OP_PREFETCH) ] = { 1095 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 1096 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 1097 }, 1098 }, 1099 }; 1100 1101 static __initconst const u64 snb_hw_cache_event_ids 1102 [PERF_COUNT_HW_CACHE_MAX] 1103 [PERF_COUNT_HW_CACHE_OP_MAX] 1104 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1105 { 1106 [ C(L1D) ] = { 1107 [ C(OP_READ) ] = { 1108 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 1109 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 1110 }, 1111 [ C(OP_WRITE) ] = { 1112 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 1113 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 1114 }, 1115 [ C(OP_PREFETCH) ] = { 1116 [ C(RESULT_ACCESS) ] = 0x0, 1117 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 1118 }, 1119 }, 1120 [ C(L1I ) ] = { 1121 [ C(OP_READ) ] = { 1122 [ C(RESULT_ACCESS) ] = 0x0, 1123 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 1124 }, 1125 [ C(OP_WRITE) ] = { 1126 [ C(RESULT_ACCESS) ] = -1, 1127 [ C(RESULT_MISS) ] = -1, 1128 }, 1129 [ C(OP_PREFETCH) ] = { 1130 [ C(RESULT_ACCESS) ] = 0x0, 1131 [ C(RESULT_MISS) ] = 0x0, 1132 }, 1133 }, 1134 [ C(LL ) ] = { 1135 [ C(OP_READ) ] = { 1136 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1137 [ C(RESULT_ACCESS) ] = 0x01b7, 1138 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1139 [ C(RESULT_MISS) ] = 0x01b7, 1140 }, 1141 [ C(OP_WRITE) ] = { 1142 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1143 [ C(RESULT_ACCESS) ] = 0x01b7, 1144 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1145 [ C(RESULT_MISS) ] = 0x01b7, 1146 }, 1147 [ C(OP_PREFETCH) ] = { 1148 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1149 [ C(RESULT_ACCESS) ] = 0x01b7, 1150 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1151 [ C(RESULT_MISS) ] = 0x01b7, 1152 }, 1153 }, 1154 [ C(DTLB) ] = { 1155 [ C(OP_READ) ] = { 1156 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 1157 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 1158 }, 1159 [ C(OP_WRITE) ] = { 1160 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 1161 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1162 }, 1163 [ C(OP_PREFETCH) ] = { 1164 [ C(RESULT_ACCESS) ] = 0x0, 1165 [ C(RESULT_MISS) ] = 0x0, 1166 }, 1167 }, 1168 [ C(ITLB) ] = { 1169 [ C(OP_READ) ] = { 1170 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 1171 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 1172 }, 1173 [ C(OP_WRITE) ] = { 1174 [ C(RESULT_ACCESS) ] = -1, 1175 [ C(RESULT_MISS) ] = -1, 1176 }, 1177 [ C(OP_PREFETCH) ] = { 1178 [ C(RESULT_ACCESS) ] = -1, 1179 [ C(RESULT_MISS) ] = -1, 1180 }, 1181 }, 1182 [ C(BPU ) ] = { 1183 [ C(OP_READ) ] = { 1184 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1185 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1186 }, 1187 [ C(OP_WRITE) ] = { 1188 [ C(RESULT_ACCESS) ] = -1, 1189 [ C(RESULT_MISS) ] = -1, 1190 }, 1191 [ C(OP_PREFETCH) ] = { 1192 [ C(RESULT_ACCESS) ] = -1, 1193 [ C(RESULT_MISS) ] = -1, 1194 }, 1195 }, 1196 [ C(NODE) ] = { 1197 [ C(OP_READ) ] = { 1198 [ C(RESULT_ACCESS) ] = 0x01b7, 1199 [ C(RESULT_MISS) ] = 0x01b7, 1200 }, 1201 [ C(OP_WRITE) ] = { 1202 [ C(RESULT_ACCESS) ] = 0x01b7, 1203 [ C(RESULT_MISS) ] = 0x01b7, 1204 }, 1205 [ C(OP_PREFETCH) ] = { 1206 [ C(RESULT_ACCESS) ] = 0x01b7, 1207 [ C(RESULT_MISS) ] = 0x01b7, 1208 }, 1209 }, 1210 1211 }; 1212 1213 /* 1214 * Notes on the events: 1215 * - data reads do not include code reads (comparable to earlier tables) 1216 * - data counts include speculative execution (except L1 write, dtlb, bpu) 1217 * - remote node access includes remote memory, remote cache, remote mmio. 1218 * - prefetches are not included in the counts because they are not 1219 * reliably counted. 1220 */ 1221 1222 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 1223 #define HSW_DEMAND_RFO BIT_ULL(1) 1224 #define HSW_ANY_RESPONSE BIT_ULL(16) 1225 #define HSW_SUPPLIER_NONE BIT_ULL(17) 1226 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 1227 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 1228 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 1229 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 1230 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 1231 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 1232 HSW_L3_MISS_REMOTE_HOP2P) 1233 #define HSW_SNOOP_NONE BIT_ULL(31) 1234 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 1235 #define HSW_SNOOP_MISS BIT_ULL(33) 1236 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 1237 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 1238 #define HSW_SNOOP_HITM BIT_ULL(36) 1239 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 1240 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 1241 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 1242 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 1243 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 1244 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 1245 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 1246 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 1247 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 1248 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 1249 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 1250 1251 #define BDW_L3_MISS_LOCAL BIT(26) 1252 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 1253 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 1254 HSW_L3_MISS_REMOTE_HOP2P) 1255 1256 1257 static __initconst const u64 hsw_hw_cache_event_ids 1258 [PERF_COUNT_HW_CACHE_MAX] 1259 [PERF_COUNT_HW_CACHE_OP_MAX] 1260 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1261 { 1262 [ C(L1D ) ] = { 1263 [ C(OP_READ) ] = { 1264 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1265 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 1266 }, 1267 [ C(OP_WRITE) ] = { 1268 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1269 [ C(RESULT_MISS) ] = 0x0, 1270 }, 1271 [ C(OP_PREFETCH) ] = { 1272 [ C(RESULT_ACCESS) ] = 0x0, 1273 [ C(RESULT_MISS) ] = 0x0, 1274 }, 1275 }, 1276 [ C(L1I ) ] = { 1277 [ C(OP_READ) ] = { 1278 [ C(RESULT_ACCESS) ] = 0x0, 1279 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 1280 }, 1281 [ C(OP_WRITE) ] = { 1282 [ C(RESULT_ACCESS) ] = -1, 1283 [ C(RESULT_MISS) ] = -1, 1284 }, 1285 [ C(OP_PREFETCH) ] = { 1286 [ C(RESULT_ACCESS) ] = 0x0, 1287 [ C(RESULT_MISS) ] = 0x0, 1288 }, 1289 }, 1290 [ C(LL ) ] = { 1291 [ C(OP_READ) ] = { 1292 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1293 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1294 }, 1295 [ C(OP_WRITE) ] = { 1296 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1297 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1298 }, 1299 [ C(OP_PREFETCH) ] = { 1300 [ C(RESULT_ACCESS) ] = 0x0, 1301 [ C(RESULT_MISS) ] = 0x0, 1302 }, 1303 }, 1304 [ C(DTLB) ] = { 1305 [ C(OP_READ) ] = { 1306 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1307 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1308 }, 1309 [ C(OP_WRITE) ] = { 1310 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1311 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1312 }, 1313 [ C(OP_PREFETCH) ] = { 1314 [ C(RESULT_ACCESS) ] = 0x0, 1315 [ C(RESULT_MISS) ] = 0x0, 1316 }, 1317 }, 1318 [ C(ITLB) ] = { 1319 [ C(OP_READ) ] = { 1320 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1321 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1322 }, 1323 [ C(OP_WRITE) ] = { 1324 [ C(RESULT_ACCESS) ] = -1, 1325 [ C(RESULT_MISS) ] = -1, 1326 }, 1327 [ C(OP_PREFETCH) ] = { 1328 [ C(RESULT_ACCESS) ] = -1, 1329 [ C(RESULT_MISS) ] = -1, 1330 }, 1331 }, 1332 [ C(BPU ) ] = { 1333 [ C(OP_READ) ] = { 1334 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1335 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1336 }, 1337 [ C(OP_WRITE) ] = { 1338 [ C(RESULT_ACCESS) ] = -1, 1339 [ C(RESULT_MISS) ] = -1, 1340 }, 1341 [ C(OP_PREFETCH) ] = { 1342 [ C(RESULT_ACCESS) ] = -1, 1343 [ C(RESULT_MISS) ] = -1, 1344 }, 1345 }, 1346 [ C(NODE) ] = { 1347 [ C(OP_READ) ] = { 1348 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1349 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1350 }, 1351 [ C(OP_WRITE) ] = { 1352 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1353 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1354 }, 1355 [ C(OP_PREFETCH) ] = { 1356 [ C(RESULT_ACCESS) ] = 0x0, 1357 [ C(RESULT_MISS) ] = 0x0, 1358 }, 1359 }, 1360 }; 1361 1362 static __initconst const u64 hsw_hw_cache_extra_regs 1363 [PERF_COUNT_HW_CACHE_MAX] 1364 [PERF_COUNT_HW_CACHE_OP_MAX] 1365 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1366 { 1367 [ C(LL ) ] = { 1368 [ C(OP_READ) ] = { 1369 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1370 HSW_LLC_ACCESS, 1371 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1372 HSW_L3_MISS|HSW_ANY_SNOOP, 1373 }, 1374 [ C(OP_WRITE) ] = { 1375 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1376 HSW_LLC_ACCESS, 1377 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1378 HSW_L3_MISS|HSW_ANY_SNOOP, 1379 }, 1380 [ C(OP_PREFETCH) ] = { 1381 [ C(RESULT_ACCESS) ] = 0x0, 1382 [ C(RESULT_MISS) ] = 0x0, 1383 }, 1384 }, 1385 [ C(NODE) ] = { 1386 [ C(OP_READ) ] = { 1387 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1388 HSW_L3_MISS_LOCAL_DRAM| 1389 HSW_SNOOP_DRAM, 1390 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1391 HSW_L3_MISS_REMOTE| 1392 HSW_SNOOP_DRAM, 1393 }, 1394 [ C(OP_WRITE) ] = { 1395 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1396 HSW_L3_MISS_LOCAL_DRAM| 1397 HSW_SNOOP_DRAM, 1398 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1399 HSW_L3_MISS_REMOTE| 1400 HSW_SNOOP_DRAM, 1401 }, 1402 [ C(OP_PREFETCH) ] = { 1403 [ C(RESULT_ACCESS) ] = 0x0, 1404 [ C(RESULT_MISS) ] = 0x0, 1405 }, 1406 }, 1407 }; 1408 1409 static __initconst const u64 westmere_hw_cache_event_ids 1410 [PERF_COUNT_HW_CACHE_MAX] 1411 [PERF_COUNT_HW_CACHE_OP_MAX] 1412 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1413 { 1414 [ C(L1D) ] = { 1415 [ C(OP_READ) ] = { 1416 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1417 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1418 }, 1419 [ C(OP_WRITE) ] = { 1420 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1421 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1422 }, 1423 [ C(OP_PREFETCH) ] = { 1424 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1425 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1426 }, 1427 }, 1428 [ C(L1I ) ] = { 1429 [ C(OP_READ) ] = { 1430 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1431 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1432 }, 1433 [ C(OP_WRITE) ] = { 1434 [ C(RESULT_ACCESS) ] = -1, 1435 [ C(RESULT_MISS) ] = -1, 1436 }, 1437 [ C(OP_PREFETCH) ] = { 1438 [ C(RESULT_ACCESS) ] = 0x0, 1439 [ C(RESULT_MISS) ] = 0x0, 1440 }, 1441 }, 1442 [ C(LL ) ] = { 1443 [ C(OP_READ) ] = { 1444 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1445 [ C(RESULT_ACCESS) ] = 0x01b7, 1446 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1447 [ C(RESULT_MISS) ] = 0x01b7, 1448 }, 1449 /* 1450 * Use RFO, not WRITEBACK, because a write miss would typically occur 1451 * on RFO. 1452 */ 1453 [ C(OP_WRITE) ] = { 1454 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1455 [ C(RESULT_ACCESS) ] = 0x01b7, 1456 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1457 [ C(RESULT_MISS) ] = 0x01b7, 1458 }, 1459 [ C(OP_PREFETCH) ] = { 1460 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1461 [ C(RESULT_ACCESS) ] = 0x01b7, 1462 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1463 [ C(RESULT_MISS) ] = 0x01b7, 1464 }, 1465 }, 1466 [ C(DTLB) ] = { 1467 [ C(OP_READ) ] = { 1468 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1469 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1470 }, 1471 [ C(OP_WRITE) ] = { 1472 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1473 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1474 }, 1475 [ C(OP_PREFETCH) ] = { 1476 [ C(RESULT_ACCESS) ] = 0x0, 1477 [ C(RESULT_MISS) ] = 0x0, 1478 }, 1479 }, 1480 [ C(ITLB) ] = { 1481 [ C(OP_READ) ] = { 1482 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1483 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1484 }, 1485 [ C(OP_WRITE) ] = { 1486 [ C(RESULT_ACCESS) ] = -1, 1487 [ C(RESULT_MISS) ] = -1, 1488 }, 1489 [ C(OP_PREFETCH) ] = { 1490 [ C(RESULT_ACCESS) ] = -1, 1491 [ C(RESULT_MISS) ] = -1, 1492 }, 1493 }, 1494 [ C(BPU ) ] = { 1495 [ C(OP_READ) ] = { 1496 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1497 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1498 }, 1499 [ C(OP_WRITE) ] = { 1500 [ C(RESULT_ACCESS) ] = -1, 1501 [ C(RESULT_MISS) ] = -1, 1502 }, 1503 [ C(OP_PREFETCH) ] = { 1504 [ C(RESULT_ACCESS) ] = -1, 1505 [ C(RESULT_MISS) ] = -1, 1506 }, 1507 }, 1508 [ C(NODE) ] = { 1509 [ C(OP_READ) ] = { 1510 [ C(RESULT_ACCESS) ] = 0x01b7, 1511 [ C(RESULT_MISS) ] = 0x01b7, 1512 }, 1513 [ C(OP_WRITE) ] = { 1514 [ C(RESULT_ACCESS) ] = 0x01b7, 1515 [ C(RESULT_MISS) ] = 0x01b7, 1516 }, 1517 [ C(OP_PREFETCH) ] = { 1518 [ C(RESULT_ACCESS) ] = 0x01b7, 1519 [ C(RESULT_MISS) ] = 0x01b7, 1520 }, 1521 }, 1522 }; 1523 1524 /* 1525 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1526 * See IA32 SDM Vol 3B 30.6.1.3 1527 */ 1528 1529 #define NHM_DMND_DATA_RD (1 << 0) 1530 #define NHM_DMND_RFO (1 << 1) 1531 #define NHM_DMND_IFETCH (1 << 2) 1532 #define NHM_DMND_WB (1 << 3) 1533 #define NHM_PF_DATA_RD (1 << 4) 1534 #define NHM_PF_DATA_RFO (1 << 5) 1535 #define NHM_PF_IFETCH (1 << 6) 1536 #define NHM_OFFCORE_OTHER (1 << 7) 1537 #define NHM_UNCORE_HIT (1 << 8) 1538 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1539 #define NHM_OTHER_CORE_HITM (1 << 10) 1540 /* reserved */ 1541 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1542 #define NHM_REMOTE_DRAM (1 << 13) 1543 #define NHM_LOCAL_DRAM (1 << 14) 1544 #define NHM_NON_DRAM (1 << 15) 1545 1546 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1547 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1548 1549 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1550 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1551 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1552 1553 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1554 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1555 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1556 1557 static __initconst const u64 nehalem_hw_cache_extra_regs 1558 [PERF_COUNT_HW_CACHE_MAX] 1559 [PERF_COUNT_HW_CACHE_OP_MAX] 1560 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1561 { 1562 [ C(LL ) ] = { 1563 [ C(OP_READ) ] = { 1564 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1565 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1566 }, 1567 [ C(OP_WRITE) ] = { 1568 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1569 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1570 }, 1571 [ C(OP_PREFETCH) ] = { 1572 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1573 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1574 }, 1575 }, 1576 [ C(NODE) ] = { 1577 [ C(OP_READ) ] = { 1578 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1579 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1580 }, 1581 [ C(OP_WRITE) ] = { 1582 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1583 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1584 }, 1585 [ C(OP_PREFETCH) ] = { 1586 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1587 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1588 }, 1589 }, 1590 }; 1591 1592 static __initconst const u64 nehalem_hw_cache_event_ids 1593 [PERF_COUNT_HW_CACHE_MAX] 1594 [PERF_COUNT_HW_CACHE_OP_MAX] 1595 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1596 { 1597 [ C(L1D) ] = { 1598 [ C(OP_READ) ] = { 1599 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1600 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1601 }, 1602 [ C(OP_WRITE) ] = { 1603 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1604 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1605 }, 1606 [ C(OP_PREFETCH) ] = { 1607 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1608 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1609 }, 1610 }, 1611 [ C(L1I ) ] = { 1612 [ C(OP_READ) ] = { 1613 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1614 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1615 }, 1616 [ C(OP_WRITE) ] = { 1617 [ C(RESULT_ACCESS) ] = -1, 1618 [ C(RESULT_MISS) ] = -1, 1619 }, 1620 [ C(OP_PREFETCH) ] = { 1621 [ C(RESULT_ACCESS) ] = 0x0, 1622 [ C(RESULT_MISS) ] = 0x0, 1623 }, 1624 }, 1625 [ C(LL ) ] = { 1626 [ C(OP_READ) ] = { 1627 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1628 [ C(RESULT_ACCESS) ] = 0x01b7, 1629 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1630 [ C(RESULT_MISS) ] = 0x01b7, 1631 }, 1632 /* 1633 * Use RFO, not WRITEBACK, because a write miss would typically occur 1634 * on RFO. 1635 */ 1636 [ C(OP_WRITE) ] = { 1637 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1638 [ C(RESULT_ACCESS) ] = 0x01b7, 1639 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1640 [ C(RESULT_MISS) ] = 0x01b7, 1641 }, 1642 [ C(OP_PREFETCH) ] = { 1643 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1644 [ C(RESULT_ACCESS) ] = 0x01b7, 1645 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1646 [ C(RESULT_MISS) ] = 0x01b7, 1647 }, 1648 }, 1649 [ C(DTLB) ] = { 1650 [ C(OP_READ) ] = { 1651 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1652 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1653 }, 1654 [ C(OP_WRITE) ] = { 1655 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1656 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1657 }, 1658 [ C(OP_PREFETCH) ] = { 1659 [ C(RESULT_ACCESS) ] = 0x0, 1660 [ C(RESULT_MISS) ] = 0x0, 1661 }, 1662 }, 1663 [ C(ITLB) ] = { 1664 [ C(OP_READ) ] = { 1665 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1666 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1667 }, 1668 [ C(OP_WRITE) ] = { 1669 [ C(RESULT_ACCESS) ] = -1, 1670 [ C(RESULT_MISS) ] = -1, 1671 }, 1672 [ C(OP_PREFETCH) ] = { 1673 [ C(RESULT_ACCESS) ] = -1, 1674 [ C(RESULT_MISS) ] = -1, 1675 }, 1676 }, 1677 [ C(BPU ) ] = { 1678 [ C(OP_READ) ] = { 1679 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1680 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1681 }, 1682 [ C(OP_WRITE) ] = { 1683 [ C(RESULT_ACCESS) ] = -1, 1684 [ C(RESULT_MISS) ] = -1, 1685 }, 1686 [ C(OP_PREFETCH) ] = { 1687 [ C(RESULT_ACCESS) ] = -1, 1688 [ C(RESULT_MISS) ] = -1, 1689 }, 1690 }, 1691 [ C(NODE) ] = { 1692 [ C(OP_READ) ] = { 1693 [ C(RESULT_ACCESS) ] = 0x01b7, 1694 [ C(RESULT_MISS) ] = 0x01b7, 1695 }, 1696 [ C(OP_WRITE) ] = { 1697 [ C(RESULT_ACCESS) ] = 0x01b7, 1698 [ C(RESULT_MISS) ] = 0x01b7, 1699 }, 1700 [ C(OP_PREFETCH) ] = { 1701 [ C(RESULT_ACCESS) ] = 0x01b7, 1702 [ C(RESULT_MISS) ] = 0x01b7, 1703 }, 1704 }, 1705 }; 1706 1707 static __initconst const u64 core2_hw_cache_event_ids 1708 [PERF_COUNT_HW_CACHE_MAX] 1709 [PERF_COUNT_HW_CACHE_OP_MAX] 1710 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1711 { 1712 [ C(L1D) ] = { 1713 [ C(OP_READ) ] = { 1714 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1715 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1716 }, 1717 [ C(OP_WRITE) ] = { 1718 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1719 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1720 }, 1721 [ C(OP_PREFETCH) ] = { 1722 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1723 [ C(RESULT_MISS) ] = 0, 1724 }, 1725 }, 1726 [ C(L1I ) ] = { 1727 [ C(OP_READ) ] = { 1728 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1729 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1730 }, 1731 [ C(OP_WRITE) ] = { 1732 [ C(RESULT_ACCESS) ] = -1, 1733 [ C(RESULT_MISS) ] = -1, 1734 }, 1735 [ C(OP_PREFETCH) ] = { 1736 [ C(RESULT_ACCESS) ] = 0, 1737 [ C(RESULT_MISS) ] = 0, 1738 }, 1739 }, 1740 [ C(LL ) ] = { 1741 [ C(OP_READ) ] = { 1742 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1743 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1744 }, 1745 [ C(OP_WRITE) ] = { 1746 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1747 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1748 }, 1749 [ C(OP_PREFETCH) ] = { 1750 [ C(RESULT_ACCESS) ] = 0, 1751 [ C(RESULT_MISS) ] = 0, 1752 }, 1753 }, 1754 [ C(DTLB) ] = { 1755 [ C(OP_READ) ] = { 1756 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1757 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1758 }, 1759 [ C(OP_WRITE) ] = { 1760 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1761 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1762 }, 1763 [ C(OP_PREFETCH) ] = { 1764 [ C(RESULT_ACCESS) ] = 0, 1765 [ C(RESULT_MISS) ] = 0, 1766 }, 1767 }, 1768 [ C(ITLB) ] = { 1769 [ C(OP_READ) ] = { 1770 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1771 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1772 }, 1773 [ C(OP_WRITE) ] = { 1774 [ C(RESULT_ACCESS) ] = -1, 1775 [ C(RESULT_MISS) ] = -1, 1776 }, 1777 [ C(OP_PREFETCH) ] = { 1778 [ C(RESULT_ACCESS) ] = -1, 1779 [ C(RESULT_MISS) ] = -1, 1780 }, 1781 }, 1782 [ C(BPU ) ] = { 1783 [ C(OP_READ) ] = { 1784 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1785 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1786 }, 1787 [ C(OP_WRITE) ] = { 1788 [ C(RESULT_ACCESS) ] = -1, 1789 [ C(RESULT_MISS) ] = -1, 1790 }, 1791 [ C(OP_PREFETCH) ] = { 1792 [ C(RESULT_ACCESS) ] = -1, 1793 [ C(RESULT_MISS) ] = -1, 1794 }, 1795 }, 1796 }; 1797 1798 static __initconst const u64 atom_hw_cache_event_ids 1799 [PERF_COUNT_HW_CACHE_MAX] 1800 [PERF_COUNT_HW_CACHE_OP_MAX] 1801 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1802 { 1803 [ C(L1D) ] = { 1804 [ C(OP_READ) ] = { 1805 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1806 [ C(RESULT_MISS) ] = 0, 1807 }, 1808 [ C(OP_WRITE) ] = { 1809 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1810 [ C(RESULT_MISS) ] = 0, 1811 }, 1812 [ C(OP_PREFETCH) ] = { 1813 [ C(RESULT_ACCESS) ] = 0x0, 1814 [ C(RESULT_MISS) ] = 0, 1815 }, 1816 }, 1817 [ C(L1I ) ] = { 1818 [ C(OP_READ) ] = { 1819 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1820 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1821 }, 1822 [ C(OP_WRITE) ] = { 1823 [ C(RESULT_ACCESS) ] = -1, 1824 [ C(RESULT_MISS) ] = -1, 1825 }, 1826 [ C(OP_PREFETCH) ] = { 1827 [ C(RESULT_ACCESS) ] = 0, 1828 [ C(RESULT_MISS) ] = 0, 1829 }, 1830 }, 1831 [ C(LL ) ] = { 1832 [ C(OP_READ) ] = { 1833 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1834 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1835 }, 1836 [ C(OP_WRITE) ] = { 1837 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1838 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1839 }, 1840 [ C(OP_PREFETCH) ] = { 1841 [ C(RESULT_ACCESS) ] = 0, 1842 [ C(RESULT_MISS) ] = 0, 1843 }, 1844 }, 1845 [ C(DTLB) ] = { 1846 [ C(OP_READ) ] = { 1847 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1848 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1849 }, 1850 [ C(OP_WRITE) ] = { 1851 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1852 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1853 }, 1854 [ C(OP_PREFETCH) ] = { 1855 [ C(RESULT_ACCESS) ] = 0, 1856 [ C(RESULT_MISS) ] = 0, 1857 }, 1858 }, 1859 [ C(ITLB) ] = { 1860 [ C(OP_READ) ] = { 1861 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1862 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1863 }, 1864 [ C(OP_WRITE) ] = { 1865 [ C(RESULT_ACCESS) ] = -1, 1866 [ C(RESULT_MISS) ] = -1, 1867 }, 1868 [ C(OP_PREFETCH) ] = { 1869 [ C(RESULT_ACCESS) ] = -1, 1870 [ C(RESULT_MISS) ] = -1, 1871 }, 1872 }, 1873 [ C(BPU ) ] = { 1874 [ C(OP_READ) ] = { 1875 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1876 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1877 }, 1878 [ C(OP_WRITE) ] = { 1879 [ C(RESULT_ACCESS) ] = -1, 1880 [ C(RESULT_MISS) ] = -1, 1881 }, 1882 [ C(OP_PREFETCH) ] = { 1883 [ C(RESULT_ACCESS) ] = -1, 1884 [ C(RESULT_MISS) ] = -1, 1885 }, 1886 }, 1887 }; 1888 1889 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1890 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1891 /* no_alloc_cycles.not_delivered */ 1892 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1893 "event=0xca,umask=0x50"); 1894 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1895 /* uops_retired.all */ 1896 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1897 "event=0xc2,umask=0x10"); 1898 /* uops_retired.all */ 1899 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1900 "event=0xc2,umask=0x10"); 1901 1902 static struct attribute *slm_events_attrs[] = { 1903 EVENT_PTR(td_total_slots_slm), 1904 EVENT_PTR(td_total_slots_scale_slm), 1905 EVENT_PTR(td_fetch_bubbles_slm), 1906 EVENT_PTR(td_fetch_bubbles_scale_slm), 1907 EVENT_PTR(td_slots_issued_slm), 1908 EVENT_PTR(td_slots_retired_slm), 1909 NULL 1910 }; 1911 1912 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1913 { 1914 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1915 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1916 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1917 EVENT_EXTRA_END 1918 }; 1919 1920 #define SLM_DMND_READ SNB_DMND_DATA_RD 1921 #define SLM_DMND_WRITE SNB_DMND_RFO 1922 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1923 1924 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1925 #define SLM_LLC_ACCESS SNB_RESP_ANY 1926 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1927 1928 static __initconst const u64 slm_hw_cache_extra_regs 1929 [PERF_COUNT_HW_CACHE_MAX] 1930 [PERF_COUNT_HW_CACHE_OP_MAX] 1931 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1932 { 1933 [ C(LL ) ] = { 1934 [ C(OP_READ) ] = { 1935 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1936 [ C(RESULT_MISS) ] = 0, 1937 }, 1938 [ C(OP_WRITE) ] = { 1939 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1940 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1941 }, 1942 [ C(OP_PREFETCH) ] = { 1943 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1944 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1945 }, 1946 }, 1947 }; 1948 1949 static __initconst const u64 slm_hw_cache_event_ids 1950 [PERF_COUNT_HW_CACHE_MAX] 1951 [PERF_COUNT_HW_CACHE_OP_MAX] 1952 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1953 { 1954 [ C(L1D) ] = { 1955 [ C(OP_READ) ] = { 1956 [ C(RESULT_ACCESS) ] = 0, 1957 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1958 }, 1959 [ C(OP_WRITE) ] = { 1960 [ C(RESULT_ACCESS) ] = 0, 1961 [ C(RESULT_MISS) ] = 0, 1962 }, 1963 [ C(OP_PREFETCH) ] = { 1964 [ C(RESULT_ACCESS) ] = 0, 1965 [ C(RESULT_MISS) ] = 0, 1966 }, 1967 }, 1968 [ C(L1I ) ] = { 1969 [ C(OP_READ) ] = { 1970 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1971 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1972 }, 1973 [ C(OP_WRITE) ] = { 1974 [ C(RESULT_ACCESS) ] = -1, 1975 [ C(RESULT_MISS) ] = -1, 1976 }, 1977 [ C(OP_PREFETCH) ] = { 1978 [ C(RESULT_ACCESS) ] = 0, 1979 [ C(RESULT_MISS) ] = 0, 1980 }, 1981 }, 1982 [ C(LL ) ] = { 1983 [ C(OP_READ) ] = { 1984 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1985 [ C(RESULT_ACCESS) ] = 0x01b7, 1986 [ C(RESULT_MISS) ] = 0, 1987 }, 1988 [ C(OP_WRITE) ] = { 1989 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1990 [ C(RESULT_ACCESS) ] = 0x01b7, 1991 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1992 [ C(RESULT_MISS) ] = 0x01b7, 1993 }, 1994 [ C(OP_PREFETCH) ] = { 1995 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1996 [ C(RESULT_ACCESS) ] = 0x01b7, 1997 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1998 [ C(RESULT_MISS) ] = 0x01b7, 1999 }, 2000 }, 2001 [ C(DTLB) ] = { 2002 [ C(OP_READ) ] = { 2003 [ C(RESULT_ACCESS) ] = 0, 2004 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 2005 }, 2006 [ C(OP_WRITE) ] = { 2007 [ C(RESULT_ACCESS) ] = 0, 2008 [ C(RESULT_MISS) ] = 0, 2009 }, 2010 [ C(OP_PREFETCH) ] = { 2011 [ C(RESULT_ACCESS) ] = 0, 2012 [ C(RESULT_MISS) ] = 0, 2013 }, 2014 }, 2015 [ C(ITLB) ] = { 2016 [ C(OP_READ) ] = { 2017 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 2018 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 2019 }, 2020 [ C(OP_WRITE) ] = { 2021 [ C(RESULT_ACCESS) ] = -1, 2022 [ C(RESULT_MISS) ] = -1, 2023 }, 2024 [ C(OP_PREFETCH) ] = { 2025 [ C(RESULT_ACCESS) ] = -1, 2026 [ C(RESULT_MISS) ] = -1, 2027 }, 2028 }, 2029 [ C(BPU ) ] = { 2030 [ C(OP_READ) ] = { 2031 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 2032 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 2033 }, 2034 [ C(OP_WRITE) ] = { 2035 [ C(RESULT_ACCESS) ] = -1, 2036 [ C(RESULT_MISS) ] = -1, 2037 }, 2038 [ C(OP_PREFETCH) ] = { 2039 [ C(RESULT_ACCESS) ] = -1, 2040 [ C(RESULT_MISS) ] = -1, 2041 }, 2042 }, 2043 }; 2044 2045 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 2046 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 2047 /* UOPS_NOT_DELIVERED.ANY */ 2048 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 2049 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 2050 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 2051 /* UOPS_RETIRED.ANY */ 2052 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 2053 /* UOPS_ISSUED.ANY */ 2054 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 2055 2056 static struct attribute *glm_events_attrs[] = { 2057 EVENT_PTR(td_total_slots_glm), 2058 EVENT_PTR(td_total_slots_scale_glm), 2059 EVENT_PTR(td_fetch_bubbles_glm), 2060 EVENT_PTR(td_recovery_bubbles_glm), 2061 EVENT_PTR(td_slots_issued_glm), 2062 EVENT_PTR(td_slots_retired_glm), 2063 NULL 2064 }; 2065 2066 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 2067 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2068 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 2069 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 2070 EVENT_EXTRA_END 2071 }; 2072 2073 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 2074 #define GLM_DEMAND_RFO BIT_ULL(1) 2075 #define GLM_ANY_RESPONSE BIT_ULL(16) 2076 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 2077 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 2078 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 2079 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 2080 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 2081 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 2082 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 2083 2084 static __initconst const u64 glm_hw_cache_event_ids 2085 [PERF_COUNT_HW_CACHE_MAX] 2086 [PERF_COUNT_HW_CACHE_OP_MAX] 2087 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2088 [C(L1D)] = { 2089 [C(OP_READ)] = { 2090 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2091 [C(RESULT_MISS)] = 0x0, 2092 }, 2093 [C(OP_WRITE)] = { 2094 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2095 [C(RESULT_MISS)] = 0x0, 2096 }, 2097 [C(OP_PREFETCH)] = { 2098 [C(RESULT_ACCESS)] = 0x0, 2099 [C(RESULT_MISS)] = 0x0, 2100 }, 2101 }, 2102 [C(L1I)] = { 2103 [C(OP_READ)] = { 2104 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 2105 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 2106 }, 2107 [C(OP_WRITE)] = { 2108 [C(RESULT_ACCESS)] = -1, 2109 [C(RESULT_MISS)] = -1, 2110 }, 2111 [C(OP_PREFETCH)] = { 2112 [C(RESULT_ACCESS)] = 0x0, 2113 [C(RESULT_MISS)] = 0x0, 2114 }, 2115 }, 2116 [C(LL)] = { 2117 [C(OP_READ)] = { 2118 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2119 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2120 }, 2121 [C(OP_WRITE)] = { 2122 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2123 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2124 }, 2125 [C(OP_PREFETCH)] = { 2126 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2127 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2128 }, 2129 }, 2130 [C(DTLB)] = { 2131 [C(OP_READ)] = { 2132 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2133 [C(RESULT_MISS)] = 0x0, 2134 }, 2135 [C(OP_WRITE)] = { 2136 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2137 [C(RESULT_MISS)] = 0x0, 2138 }, 2139 [C(OP_PREFETCH)] = { 2140 [C(RESULT_ACCESS)] = 0x0, 2141 [C(RESULT_MISS)] = 0x0, 2142 }, 2143 }, 2144 [C(ITLB)] = { 2145 [C(OP_READ)] = { 2146 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 2147 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 2148 }, 2149 [C(OP_WRITE)] = { 2150 [C(RESULT_ACCESS)] = -1, 2151 [C(RESULT_MISS)] = -1, 2152 }, 2153 [C(OP_PREFETCH)] = { 2154 [C(RESULT_ACCESS)] = -1, 2155 [C(RESULT_MISS)] = -1, 2156 }, 2157 }, 2158 [C(BPU)] = { 2159 [C(OP_READ)] = { 2160 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 2161 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 2162 }, 2163 [C(OP_WRITE)] = { 2164 [C(RESULT_ACCESS)] = -1, 2165 [C(RESULT_MISS)] = -1, 2166 }, 2167 [C(OP_PREFETCH)] = { 2168 [C(RESULT_ACCESS)] = -1, 2169 [C(RESULT_MISS)] = -1, 2170 }, 2171 }, 2172 }; 2173 2174 static __initconst const u64 glm_hw_cache_extra_regs 2175 [PERF_COUNT_HW_CACHE_MAX] 2176 [PERF_COUNT_HW_CACHE_OP_MAX] 2177 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2178 [C(LL)] = { 2179 [C(OP_READ)] = { 2180 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2181 GLM_LLC_ACCESS, 2182 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2183 GLM_LLC_MISS, 2184 }, 2185 [C(OP_WRITE)] = { 2186 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2187 GLM_LLC_ACCESS, 2188 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2189 GLM_LLC_MISS, 2190 }, 2191 [C(OP_PREFETCH)] = { 2192 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 2193 GLM_LLC_ACCESS, 2194 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 2195 GLM_LLC_MISS, 2196 }, 2197 }, 2198 }; 2199 2200 static __initconst const u64 glp_hw_cache_event_ids 2201 [PERF_COUNT_HW_CACHE_MAX] 2202 [PERF_COUNT_HW_CACHE_OP_MAX] 2203 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2204 [C(L1D)] = { 2205 [C(OP_READ)] = { 2206 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2207 [C(RESULT_MISS)] = 0x0, 2208 }, 2209 [C(OP_WRITE)] = { 2210 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2211 [C(RESULT_MISS)] = 0x0, 2212 }, 2213 [C(OP_PREFETCH)] = { 2214 [C(RESULT_ACCESS)] = 0x0, 2215 [C(RESULT_MISS)] = 0x0, 2216 }, 2217 }, 2218 [C(L1I)] = { 2219 [C(OP_READ)] = { 2220 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 2221 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 2222 }, 2223 [C(OP_WRITE)] = { 2224 [C(RESULT_ACCESS)] = -1, 2225 [C(RESULT_MISS)] = -1, 2226 }, 2227 [C(OP_PREFETCH)] = { 2228 [C(RESULT_ACCESS)] = 0x0, 2229 [C(RESULT_MISS)] = 0x0, 2230 }, 2231 }, 2232 [C(LL)] = { 2233 [C(OP_READ)] = { 2234 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2235 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2236 }, 2237 [C(OP_WRITE)] = { 2238 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2239 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2240 }, 2241 [C(OP_PREFETCH)] = { 2242 [C(RESULT_ACCESS)] = 0x0, 2243 [C(RESULT_MISS)] = 0x0, 2244 }, 2245 }, 2246 [C(DTLB)] = { 2247 [C(OP_READ)] = { 2248 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2249 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 2250 }, 2251 [C(OP_WRITE)] = { 2252 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2253 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 2254 }, 2255 [C(OP_PREFETCH)] = { 2256 [C(RESULT_ACCESS)] = 0x0, 2257 [C(RESULT_MISS)] = 0x0, 2258 }, 2259 }, 2260 [C(ITLB)] = { 2261 [C(OP_READ)] = { 2262 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 2263 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 2264 }, 2265 [C(OP_WRITE)] = { 2266 [C(RESULT_ACCESS)] = -1, 2267 [C(RESULT_MISS)] = -1, 2268 }, 2269 [C(OP_PREFETCH)] = { 2270 [C(RESULT_ACCESS)] = -1, 2271 [C(RESULT_MISS)] = -1, 2272 }, 2273 }, 2274 [C(BPU)] = { 2275 [C(OP_READ)] = { 2276 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 2277 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 2278 }, 2279 [C(OP_WRITE)] = { 2280 [C(RESULT_ACCESS)] = -1, 2281 [C(RESULT_MISS)] = -1, 2282 }, 2283 [C(OP_PREFETCH)] = { 2284 [C(RESULT_ACCESS)] = -1, 2285 [C(RESULT_MISS)] = -1, 2286 }, 2287 }, 2288 }; 2289 2290 static __initconst const u64 glp_hw_cache_extra_regs 2291 [PERF_COUNT_HW_CACHE_MAX] 2292 [PERF_COUNT_HW_CACHE_OP_MAX] 2293 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2294 [C(LL)] = { 2295 [C(OP_READ)] = { 2296 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2297 GLM_LLC_ACCESS, 2298 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2299 GLM_LLC_MISS, 2300 }, 2301 [C(OP_WRITE)] = { 2302 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2303 GLM_LLC_ACCESS, 2304 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2305 GLM_LLC_MISS, 2306 }, 2307 [C(OP_PREFETCH)] = { 2308 [C(RESULT_ACCESS)] = 0x0, 2309 [C(RESULT_MISS)] = 0x0, 2310 }, 2311 }, 2312 }; 2313 2314 #define TNT_LOCAL_DRAM BIT_ULL(26) 2315 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 2316 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 2317 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 2318 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 2319 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 2320 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 2321 2322 static __initconst const u64 tnt_hw_cache_extra_regs 2323 [PERF_COUNT_HW_CACHE_MAX] 2324 [PERF_COUNT_HW_CACHE_OP_MAX] 2325 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2326 [C(LL)] = { 2327 [C(OP_READ)] = { 2328 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 2329 TNT_LLC_ACCESS, 2330 [C(RESULT_MISS)] = TNT_DEMAND_READ| 2331 TNT_LLC_MISS, 2332 }, 2333 [C(OP_WRITE)] = { 2334 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 2335 TNT_LLC_ACCESS, 2336 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 2337 TNT_LLC_MISS, 2338 }, 2339 [C(OP_PREFETCH)] = { 2340 [C(RESULT_ACCESS)] = 0x0, 2341 [C(RESULT_MISS)] = 0x0, 2342 }, 2343 }, 2344 }; 2345 2346 static __initconst const u64 arw_hw_cache_extra_regs 2347 [PERF_COUNT_HW_CACHE_MAX] 2348 [PERF_COUNT_HW_CACHE_OP_MAX] 2349 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2350 [C(LL)] = { 2351 [C(OP_READ)] = { 2352 [C(RESULT_ACCESS)] = 0x4000000000000001, 2353 [C(RESULT_MISS)] = 0xFFFFF000000001, 2354 }, 2355 [C(OP_WRITE)] = { 2356 [C(RESULT_ACCESS)] = 0x4000000000000002, 2357 [C(RESULT_MISS)] = 0xFFFFF000000002, 2358 }, 2359 [C(OP_PREFETCH)] = { 2360 [C(RESULT_ACCESS)] = 0x0, 2361 [C(RESULT_MISS)] = 0x0, 2362 }, 2363 }, 2364 }; 2365 2366 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2367 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2368 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2369 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2370 2371 static struct attribute *tnt_events_attrs[] = { 2372 EVENT_PTR(td_fe_bound_tnt), 2373 EVENT_PTR(td_retiring_tnt), 2374 EVENT_PTR(td_bad_spec_tnt), 2375 EVENT_PTR(td_be_bound_tnt), 2376 NULL, 2377 }; 2378 2379 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 2380 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2381 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 2382 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 2383 EVENT_EXTRA_END 2384 }; 2385 2386 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3"); 2387 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6"); 2388 2389 static struct attribute *grt_mem_attrs[] = { 2390 EVENT_PTR(mem_ld_grt), 2391 EVENT_PTR(mem_st_grt), 2392 NULL 2393 }; 2394 2395 static struct extra_reg intel_grt_extra_regs[] __read_mostly = { 2396 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2397 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 2398 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 2399 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2400 EVENT_EXTRA_END 2401 }; 2402 2403 EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0"); 2404 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0"); 2405 2406 static struct attribute *cmt_events_attrs[] = { 2407 EVENT_PTR(td_fe_bound_tnt), 2408 EVENT_PTR(td_retiring_cmt), 2409 EVENT_PTR(td_bad_spec_cmt), 2410 EVENT_PTR(td_be_bound_tnt), 2411 NULL 2412 }; 2413 2414 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = { 2415 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2416 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0), 2417 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1), 2418 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2419 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0), 2420 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1), 2421 EVENT_EXTRA_END 2422 }; 2423 2424 static struct extra_reg intel_arw_extra_regs[] __read_mostly = { 2425 /* must define OMR_X first, see intel_alt_er() */ 2426 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0), 2427 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1), 2428 INTEL_UEVENT_EXTRA_REG(0x04b7, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2), 2429 INTEL_UEVENT_EXTRA_REG(0x08b7, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3), 2430 INTEL_UEVENT_EXTRA_REG(0x01d4, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0), 2431 INTEL_UEVENT_EXTRA_REG(0x02d4, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1), 2432 INTEL_UEVENT_EXTRA_REG(0x04d4, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2), 2433 INTEL_UEVENT_EXTRA_REG(0x08d4, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3), 2434 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2435 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0), 2436 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1), 2437 EVENT_EXTRA_END 2438 }; 2439 2440 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_skt, "event=0x9c,umask=0x01"); 2441 EVENT_ATTR_STR(topdown-retiring, td_retiring_skt, "event=0xc2,umask=0x02"); 2442 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_skt, "event=0xa4,umask=0x02"); 2443 2444 static struct attribute *skt_events_attrs[] = { 2445 EVENT_PTR(td_fe_bound_skt), 2446 EVENT_PTR(td_retiring_skt), 2447 EVENT_PTR(td_bad_spec_cmt), 2448 EVENT_PTR(td_be_bound_skt), 2449 NULL, 2450 }; 2451 2452 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2453 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2454 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 2455 #define KNL_MCDRAM_FAR BIT_ULL(22) 2456 #define KNL_DDR_LOCAL BIT_ULL(23) 2457 #define KNL_DDR_FAR BIT_ULL(24) 2458 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2459 KNL_DDR_LOCAL | KNL_DDR_FAR) 2460 #define KNL_L2_READ SLM_DMND_READ 2461 #define KNL_L2_WRITE SLM_DMND_WRITE 2462 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2463 #define KNL_L2_ACCESS SLM_LLC_ACCESS 2464 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2465 KNL_DRAM_ANY | SNB_SNP_ANY | \ 2466 SNB_NON_DRAM) 2467 2468 static __initconst const u64 knl_hw_cache_extra_regs 2469 [PERF_COUNT_HW_CACHE_MAX] 2470 [PERF_COUNT_HW_CACHE_OP_MAX] 2471 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2472 [C(LL)] = { 2473 [C(OP_READ)] = { 2474 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2475 [C(RESULT_MISS)] = 0, 2476 }, 2477 [C(OP_WRITE)] = { 2478 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2479 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2480 }, 2481 [C(OP_PREFETCH)] = { 2482 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2483 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2484 }, 2485 }, 2486 }; 2487 2488 /* 2489 * Used from PMIs where the LBRs are already disabled. 2490 * 2491 * This function could be called consecutively. It is required to remain in 2492 * disabled state if called consecutively. 2493 * 2494 * During consecutive calls, the same disable value will be written to related 2495 * registers, so the PMU state remains unchanged. 2496 * 2497 * intel_bts events don't coexist with intel PMU's BTS events because of 2498 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2499 * disabled around intel PMU's event batching etc, only inside the PMI handler. 2500 * 2501 * Avoid PEBS_ENABLE MSR access in PMIs. 2502 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 2503 * It doesn't matter if the PEBS is enabled or not. 2504 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 2505 * access PEBS_ENABLE MSR in disable_all()/enable_all(). 2506 * However, there are some cases which may change PEBS status, e.g. PMI 2507 * throttle. The PEBS_ENABLE should be updated where the status changes. 2508 */ 2509 static __always_inline void __intel_pmu_disable_all(bool bts) 2510 { 2511 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2512 2513 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2514 2515 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2516 intel_pmu_disable_bts(); 2517 } 2518 2519 static __always_inline void intel_pmu_disable_all(void) 2520 { 2521 __intel_pmu_disable_all(true); 2522 static_call_cond(x86_pmu_pebs_disable_all)(); 2523 intel_pmu_lbr_disable_all(); 2524 } 2525 2526 static void __intel_pmu_enable_all(int added, bool pmi) 2527 { 2528 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2529 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2530 2531 intel_pmu_lbr_enable_all(pmi); 2532 2533 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) { 2534 wrmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val); 2535 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val; 2536 } 2537 2538 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 2539 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2540 2541 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2542 struct perf_event *event = 2543 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2544 2545 if (WARN_ON_ONCE(!event)) 2546 return; 2547 2548 intel_pmu_enable_bts(event->hw.config); 2549 } 2550 } 2551 2552 static void intel_pmu_enable_all(int added) 2553 { 2554 static_call_cond(x86_pmu_pebs_enable_all)(); 2555 __intel_pmu_enable_all(added, false); 2556 } 2557 2558 static noinline int 2559 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, 2560 unsigned int cnt, unsigned long flags) 2561 { 2562 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2563 2564 intel_pmu_lbr_read(); 2565 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); 2566 2567 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); 2568 intel_pmu_enable_all(0); 2569 local_irq_restore(flags); 2570 return cnt; 2571 } 2572 2573 static int 2574 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2575 { 2576 unsigned long flags; 2577 2578 /* must not have branches... */ 2579 local_irq_save(flags); 2580 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2581 __intel_pmu_lbr_disable(); 2582 /* ... until here */ 2583 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2584 } 2585 2586 static int 2587 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2588 { 2589 unsigned long flags; 2590 2591 /* must not have branches... */ 2592 local_irq_save(flags); 2593 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2594 __intel_pmu_arch_lbr_disable(); 2595 /* ... until here */ 2596 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2597 } 2598 2599 /* 2600 * Workaround for: 2601 * Intel Errata AAK100 (model 26) 2602 * Intel Errata AAP53 (model 30) 2603 * Intel Errata BD53 (model 44) 2604 * 2605 * The official story: 2606 * These chips need to be 'reset' when adding counters by programming the 2607 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2608 * in sequence on the same PMC or on different PMCs. 2609 * 2610 * In practice it appears some of these events do in fact count, and 2611 * we need to program all 4 events. 2612 */ 2613 static void intel_pmu_nhm_workaround(void) 2614 { 2615 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2616 static const unsigned long nhm_magic[4] = { 2617 0x4300B5, 2618 0x4300D2, 2619 0x4300B1, 2620 0x4300B1 2621 }; 2622 struct perf_event *event; 2623 int i; 2624 2625 /* 2626 * The Errata requires below steps: 2627 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2628 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2629 * the corresponding PMCx; 2630 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2631 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2632 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2633 */ 2634 2635 /* 2636 * The real steps we choose are a little different from above. 2637 * A) To reduce MSR operations, we don't run step 1) as they 2638 * are already cleared before this function is called; 2639 * B) Call x86_perf_event_update to save PMCx before configuring 2640 * PERFEVTSELx with magic number; 2641 * C) With step 5), we do clear only when the PERFEVTSELx is 2642 * not used currently. 2643 * D) Call x86_perf_event_set_period to restore PMCx; 2644 */ 2645 2646 /* We always operate 4 pairs of PERF Counters */ 2647 for (i = 0; i < 4; i++) { 2648 event = cpuc->events[i]; 2649 if (event) 2650 static_call(x86_pmu_update)(event); 2651 } 2652 2653 for (i = 0; i < 4; i++) { 2654 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2655 wrmsrq(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2656 } 2657 2658 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2659 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2660 2661 for (i = 0; i < 4; i++) { 2662 event = cpuc->events[i]; 2663 2664 if (event) { 2665 static_call(x86_pmu_set_period)(event); 2666 __x86_pmu_enable_event(&event->hw, 2667 ARCH_PERFMON_EVENTSEL_ENABLE); 2668 } else 2669 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2670 } 2671 } 2672 2673 static void intel_pmu_nhm_enable_all(int added) 2674 { 2675 if (added) 2676 intel_pmu_nhm_workaround(); 2677 intel_pmu_enable_all(added); 2678 } 2679 2680 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2681 { 2682 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2683 2684 if (cpuc->tfa_shadow != val) { 2685 cpuc->tfa_shadow = val; 2686 wrmsrq(MSR_TSX_FORCE_ABORT, val); 2687 } 2688 } 2689 2690 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2691 { 2692 /* 2693 * We're going to use PMC3, make sure TFA is set before we touch it. 2694 */ 2695 if (cntr == 3) 2696 intel_set_tfa(cpuc, true); 2697 } 2698 2699 static void intel_tfa_pmu_enable_all(int added) 2700 { 2701 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2702 2703 /* 2704 * If we find PMC3 is no longer used when we enable the PMU, we can 2705 * clear TFA. 2706 */ 2707 if (!test_bit(3, cpuc->active_mask)) 2708 intel_set_tfa(cpuc, false); 2709 2710 intel_pmu_enable_all(added); 2711 } 2712 2713 static inline u64 intel_pmu_get_status(void) 2714 { 2715 u64 status; 2716 2717 rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status); 2718 2719 return status; 2720 } 2721 2722 static inline void intel_pmu_ack_status(u64 ack) 2723 { 2724 wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2725 } 2726 2727 static inline bool event_is_checkpointed(struct perf_event *event) 2728 { 2729 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2730 } 2731 2732 static inline void intel_set_masks(struct perf_event *event, int idx) 2733 { 2734 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2735 2736 if (event->attr.exclude_host) 2737 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2738 if (event->attr.exclude_guest) 2739 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2740 if (event_is_checkpointed(event)) 2741 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2742 } 2743 2744 static inline void intel_clear_masks(struct perf_event *event, int idx) 2745 { 2746 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2747 2748 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2749 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2750 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2751 } 2752 2753 static void intel_pmu_disable_fixed(struct perf_event *event) 2754 { 2755 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2756 struct hw_perf_event *hwc = &event->hw; 2757 int idx = hwc->idx; 2758 u64 mask; 2759 2760 if (is_topdown_idx(idx)) { 2761 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2762 2763 /* 2764 * When there are other active TopDown events, 2765 * don't disable the fixed counter 3. 2766 */ 2767 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2768 return; 2769 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2770 } 2771 2772 intel_clear_masks(event, idx); 2773 2774 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK); 2775 cpuc->fixed_ctrl_val &= ~mask; 2776 } 2777 2778 static inline void __intel_pmu_update_event_ext(int idx, u64 ext) 2779 { 2780 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2781 u32 msr; 2782 2783 if (idx < INTEL_PMC_IDX_FIXED) { 2784 msr = MSR_IA32_PMC_V6_GP0_CFG_C + 2785 x86_pmu.addr_offset(idx, false); 2786 } else { 2787 msr = MSR_IA32_PMC_V6_FX0_CFG_C + 2788 x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false); 2789 } 2790 2791 cpuc->cfg_c_val[idx] = ext; 2792 wrmsrq(msr, ext); 2793 } 2794 2795 static void intel_pmu_disable_event_ext(struct perf_event *event) 2796 { 2797 /* 2798 * Only clear CFG_C MSR for PEBS counter group events, 2799 * it avoids the HW counter's value to be added into 2800 * other PEBS records incorrectly after PEBS counter 2801 * group events are disabled. 2802 * 2803 * For other events, it's unnecessary to clear CFG_C MSRs 2804 * since CFG_C doesn't take effect if counter is in 2805 * disabled state. That helps to reduce the WRMSR overhead 2806 * in context switches. 2807 */ 2808 if (!is_pebs_counter_event_group(event)) 2809 return; 2810 2811 __intel_pmu_update_event_ext(event->hw.idx, 0); 2812 } 2813 2814 DEFINE_STATIC_CALL_NULL(intel_pmu_disable_event_ext, intel_pmu_disable_event_ext); 2815 2816 static void intel_pmu_disable_event(struct perf_event *event) 2817 { 2818 struct hw_perf_event *hwc = &event->hw; 2819 int idx = hwc->idx; 2820 2821 switch (idx) { 2822 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2823 intel_clear_masks(event, idx); 2824 static_call_cond(intel_pmu_disable_event_ext)(event); 2825 x86_pmu_disable_event(event); 2826 break; 2827 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2828 static_call_cond(intel_pmu_disable_event_ext)(event); 2829 fallthrough; 2830 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2831 intel_pmu_disable_fixed(event); 2832 break; 2833 case INTEL_PMC_IDX_FIXED_BTS: 2834 intel_pmu_disable_bts(); 2835 intel_pmu_drain_bts_buffer(); 2836 return; 2837 case INTEL_PMC_IDX_FIXED_VLBR: 2838 intel_clear_masks(event, idx); 2839 break; 2840 default: 2841 intel_clear_masks(event, idx); 2842 pr_warn("Failed to disable the event with invalid index %d\n", 2843 idx); 2844 return; 2845 } 2846 2847 /* 2848 * Needs to be called after x86_pmu_disable_event, 2849 * so we don't trigger the event without PEBS bit set. 2850 */ 2851 if (unlikely(event->attr.precise_ip)) 2852 static_call(x86_pmu_pebs_disable)(event); 2853 } 2854 2855 static void intel_pmu_assign_event(struct perf_event *event, int idx) 2856 { 2857 if (is_pebs_pt(event)) 2858 perf_report_aux_output_id(event, idx); 2859 } 2860 2861 static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event) 2862 { 2863 return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK; 2864 } 2865 2866 static void intel_pmu_del_event(struct perf_event *event) 2867 { 2868 if (intel_pmu_needs_branch_stack(event)) 2869 intel_pmu_lbr_del(event); 2870 if (event->attr.precise_ip) 2871 intel_pmu_pebs_del(event); 2872 if (is_pebs_counter_event_group(event) || 2873 is_acr_event_group(event)) 2874 this_cpu_ptr(&cpu_hw_events)->n_late_setup--; 2875 } 2876 2877 static int icl_set_topdown_event_period(struct perf_event *event) 2878 { 2879 struct hw_perf_event *hwc = &event->hw; 2880 s64 left = local64_read(&hwc->period_left); 2881 2882 /* 2883 * The values in PERF_METRICS MSR are derived from fixed counter 3. 2884 * Software should start both registers, PERF_METRICS and fixed 2885 * counter 3, from zero. 2886 * Clear PERF_METRICS and Fixed counter 3 in initialization. 2887 * After that, both MSRs will be cleared for each read. 2888 * Don't need to clear them again. 2889 */ 2890 if (left == x86_pmu.max_period) { 2891 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0); 2892 wrmsrq(MSR_PERF_METRICS, 0); 2893 hwc->saved_slots = 0; 2894 hwc->saved_metric = 0; 2895 } 2896 2897 if ((hwc->saved_slots) && is_slots_event(event)) { 2898 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2899 wrmsrq(MSR_PERF_METRICS, hwc->saved_metric); 2900 } 2901 2902 perf_event_update_userpage(event); 2903 2904 return 0; 2905 } 2906 2907 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period); 2908 2909 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 2910 { 2911 u32 val; 2912 2913 /* 2914 * The metric is reported as an 8bit integer fraction 2915 * summing up to 0xff. 2916 * slots-in-metric = (Metric / 0xff) * slots 2917 */ 2918 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 2919 return mul_u64_u32_div(slots, val, 0xff); 2920 } 2921 2922 static u64 icl_get_topdown_value(struct perf_event *event, 2923 u64 slots, u64 metrics) 2924 { 2925 int idx = event->hw.idx; 2926 u64 delta; 2927 2928 if (is_metric_idx(idx)) 2929 delta = icl_get_metrics_event_value(metrics, slots, idx); 2930 else 2931 delta = slots; 2932 2933 return delta; 2934 } 2935 2936 static void __icl_update_topdown_event(struct perf_event *event, 2937 u64 slots, u64 metrics, 2938 u64 last_slots, u64 last_metrics) 2939 { 2940 u64 delta, last = 0; 2941 2942 delta = icl_get_topdown_value(event, slots, metrics); 2943 if (last_slots) 2944 last = icl_get_topdown_value(event, last_slots, last_metrics); 2945 2946 /* 2947 * The 8bit integer fraction of metric may be not accurate, 2948 * especially when the changes is very small. 2949 * For example, if only a few bad_spec happens, the fraction 2950 * may be reduced from 1 to 0. If so, the bad_spec event value 2951 * will be 0 which is definitely less than the last value. 2952 * Avoid update event->count for this case. 2953 */ 2954 if (delta > last) { 2955 delta -= last; 2956 local64_add(delta, &event->count); 2957 } 2958 } 2959 2960 static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 2961 u64 metrics, int metric_end) 2962 { 2963 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2964 struct perf_event *other; 2965 int idx; 2966 2967 event->hw.saved_slots = slots; 2968 event->hw.saved_metric = metrics; 2969 2970 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2971 if (!is_topdown_idx(idx)) 2972 continue; 2973 other = cpuc->events[idx]; 2974 other->hw.saved_slots = slots; 2975 other->hw.saved_metric = metrics; 2976 } 2977 } 2978 2979 /* 2980 * Update all active Topdown events. 2981 * 2982 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 2983 * modify by a NMI. PMU has to be disabled before calling this function. 2984 */ 2985 2986 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end, u64 *val) 2987 { 2988 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2989 struct perf_event *other; 2990 u64 slots, metrics; 2991 bool reset = true; 2992 int idx; 2993 2994 if (!val) { 2995 /* read Fixed counter 3 */ 2996 slots = rdpmc(3 | INTEL_PMC_FIXED_RDPMC_BASE); 2997 if (!slots) 2998 return 0; 2999 3000 /* read PERF_METRICS */ 3001 metrics = rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS); 3002 } else { 3003 slots = val[0]; 3004 metrics = val[1]; 3005 /* 3006 * Don't reset the PERF_METRICS and Fixed counter 3 3007 * for each PEBS record read. Utilize the RDPMC metrics 3008 * clear mode. 3009 */ 3010 reset = false; 3011 } 3012 3013 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 3014 if (!is_topdown_idx(idx)) 3015 continue; 3016 other = cpuc->events[idx]; 3017 __icl_update_topdown_event(other, slots, metrics, 3018 event ? event->hw.saved_slots : 0, 3019 event ? event->hw.saved_metric : 0); 3020 } 3021 3022 /* 3023 * Check and update this event, which may have been cleared 3024 * in active_mask e.g. x86_pmu_stop() 3025 */ 3026 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 3027 __icl_update_topdown_event(event, slots, metrics, 3028 event->hw.saved_slots, 3029 event->hw.saved_metric); 3030 3031 /* 3032 * In x86_pmu_stop(), the event is cleared in active_mask first, 3033 * then drain the delta, which indicates context switch for 3034 * counting. 3035 * Save metric and slots for context switch. 3036 * Don't need to reset the PERF_METRICS and Fixed counter 3. 3037 * Because the values will be restored in next schedule in. 3038 */ 3039 update_saved_topdown_regs(event, slots, metrics, metric_end); 3040 reset = false; 3041 } 3042 3043 if (reset) { 3044 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 3045 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0); 3046 wrmsrq(MSR_PERF_METRICS, 0); 3047 if (event) 3048 update_saved_topdown_regs(event, 0, 0, metric_end); 3049 } 3050 3051 return slots; 3052 } 3053 3054 static u64 icl_update_topdown_event(struct perf_event *event, u64 *val) 3055 { 3056 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 3057 x86_pmu.num_topdown_events - 1, 3058 val); 3059 } 3060 3061 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, intel_pmu_topdown_event_update); 3062 3063 static void intel_pmu_read_event(struct perf_event *event) 3064 { 3065 if (event->hw.flags & (PERF_X86_EVENT_AUTO_RELOAD | PERF_X86_EVENT_TOPDOWN) || 3066 is_pebs_counter_event_group(event)) { 3067 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3068 bool pmu_enabled = cpuc->enabled; 3069 3070 /* Only need to call update_topdown_event() once for group read. */ 3071 if (is_metric_event(event) && (cpuc->txn_flags & PERF_PMU_TXN_READ)) 3072 return; 3073 3074 cpuc->enabled = 0; 3075 if (pmu_enabled) 3076 intel_pmu_disable_all(); 3077 3078 /* 3079 * If the PEBS counters snapshotting is enabled, 3080 * the topdown event is available in PEBS records. 3081 */ 3082 if (is_topdown_count(event) && !is_pebs_counter_event_group(event)) 3083 static_call(intel_pmu_update_topdown_event)(event, NULL); 3084 else 3085 intel_pmu_drain_pebs_buffer(); 3086 3087 cpuc->enabled = pmu_enabled; 3088 if (pmu_enabled) 3089 intel_pmu_enable_all(0); 3090 3091 return; 3092 } 3093 3094 x86_perf_event_update(event); 3095 } 3096 3097 static void intel_pmu_enable_fixed(struct perf_event *event) 3098 { 3099 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3100 struct hw_perf_event *hwc = &event->hw; 3101 int idx = hwc->idx; 3102 u64 bits = 0; 3103 3104 if (is_topdown_idx(idx)) { 3105 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3106 /* 3107 * When there are other active TopDown events, 3108 * don't enable the fixed counter 3 again. 3109 */ 3110 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 3111 return; 3112 3113 idx = INTEL_PMC_IDX_FIXED_SLOTS; 3114 3115 if (event->attr.config1 & INTEL_TD_CFG_METRIC_CLEAR) 3116 bits |= INTEL_FIXED_3_METRICS_CLEAR; 3117 } 3118 3119 intel_set_masks(event, idx); 3120 3121 /* 3122 * Enable IRQ generation (0x8), if not PEBS, 3123 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 3124 * if requested: 3125 */ 3126 if (!event->attr.precise_ip) 3127 bits |= INTEL_FIXED_0_ENABLE_PMI; 3128 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 3129 bits |= INTEL_FIXED_0_USER; 3130 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 3131 bits |= INTEL_FIXED_0_KERNEL; 3132 if (hwc->config & ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE) 3133 bits |= INTEL_FIXED_0_RDPMC_USER_DISABLE; 3134 3135 /* 3136 * ANY bit is supported in v3 and up 3137 */ 3138 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 3139 bits |= INTEL_FIXED_0_ANYTHREAD; 3140 3141 idx -= INTEL_PMC_IDX_FIXED; 3142 bits = intel_fixed_bits_by_idx(idx, bits); 3143 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) 3144 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); 3145 3146 cpuc->fixed_ctrl_val &= ~intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK); 3147 cpuc->fixed_ctrl_val |= bits; 3148 } 3149 3150 static void intel_pmu_config_acr(int idx, u64 mask, u32 reload) 3151 { 3152 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3153 int msr_b, msr_c; 3154 int msr_offset; 3155 3156 if (!mask && !cpuc->acr_cfg_b[idx]) 3157 return; 3158 3159 if (idx < INTEL_PMC_IDX_FIXED) { 3160 msr_b = MSR_IA32_PMC_V6_GP0_CFG_B; 3161 msr_c = MSR_IA32_PMC_V6_GP0_CFG_C; 3162 msr_offset = x86_pmu.addr_offset(idx, false); 3163 } else { 3164 msr_b = MSR_IA32_PMC_V6_FX0_CFG_B; 3165 msr_c = MSR_IA32_PMC_V6_FX0_CFG_C; 3166 msr_offset = x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false); 3167 } 3168 3169 if (cpuc->acr_cfg_b[idx] != mask) { 3170 wrmsrl(msr_b + msr_offset, mask); 3171 cpuc->acr_cfg_b[idx] = mask; 3172 } 3173 /* Only need to update the reload value when there is a valid config value. */ 3174 if (mask && cpuc->acr_cfg_c[idx] != reload) { 3175 wrmsrl(msr_c + msr_offset, reload); 3176 cpuc->acr_cfg_c[idx] = reload; 3177 } 3178 } 3179 3180 static void intel_pmu_enable_acr(struct perf_event *event) 3181 { 3182 struct hw_perf_event *hwc = &event->hw; 3183 3184 if (!is_acr_event_group(event) || !event->attr.config2) { 3185 /* 3186 * The disable doesn't clear the ACR CFG register. 3187 * Check and clear the ACR CFG register. 3188 */ 3189 intel_pmu_config_acr(hwc->idx, 0, 0); 3190 return; 3191 } 3192 3193 intel_pmu_config_acr(hwc->idx, hwc->config1, -hwc->sample_period); 3194 } 3195 3196 DEFINE_STATIC_CALL_NULL(intel_pmu_enable_acr_event, intel_pmu_enable_acr); 3197 3198 static void intel_pmu_enable_event_ext(struct perf_event *event) 3199 { 3200 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3201 struct hw_perf_event *hwc = &event->hw; 3202 union arch_pebs_index old, new; 3203 struct arch_pebs_cap cap; 3204 u64 ext = 0; 3205 3206 cap = hybrid(cpuc->pmu, arch_pebs_cap); 3207 3208 if (event->attr.precise_ip) { 3209 u64 pebs_data_cfg = intel_get_arch_pebs_data_config(event); 3210 3211 ext |= ARCH_PEBS_EN; 3212 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) 3213 ext |= (-hwc->sample_period) & ARCH_PEBS_RELOAD; 3214 3215 if (pebs_data_cfg && cap.caps) { 3216 if (pebs_data_cfg & PEBS_DATACFG_MEMINFO) 3217 ext |= ARCH_PEBS_AUX & cap.caps; 3218 3219 if (pebs_data_cfg & PEBS_DATACFG_GP) 3220 ext |= ARCH_PEBS_GPR & cap.caps; 3221 3222 if (pebs_data_cfg & PEBS_DATACFG_XMMS) 3223 ext |= ARCH_PEBS_VECR_XMM & cap.caps; 3224 3225 if (pebs_data_cfg & PEBS_DATACFG_LBRS) 3226 ext |= ARCH_PEBS_LBR & cap.caps; 3227 3228 if (pebs_data_cfg & 3229 (PEBS_DATACFG_CNTR_MASK << PEBS_DATACFG_CNTR_SHIFT)) 3230 ext |= ARCH_PEBS_CNTR_GP & cap.caps; 3231 3232 if (pebs_data_cfg & 3233 (PEBS_DATACFG_FIX_MASK << PEBS_DATACFG_FIX_SHIFT)) 3234 ext |= ARCH_PEBS_CNTR_FIXED & cap.caps; 3235 3236 if (pebs_data_cfg & PEBS_DATACFG_METRICS) 3237 ext |= ARCH_PEBS_CNTR_METRICS & cap.caps; 3238 } 3239 3240 if (cpuc->n_pebs == cpuc->n_large_pebs) 3241 new.thresh = ARCH_PEBS_THRESH_MULTI; 3242 else 3243 new.thresh = ARCH_PEBS_THRESH_SINGLE; 3244 3245 rdmsrq(MSR_IA32_PEBS_INDEX, old.whole); 3246 if (new.thresh != old.thresh || !old.en) { 3247 if (old.thresh == ARCH_PEBS_THRESH_MULTI && old.wr > 0) { 3248 /* 3249 * Large PEBS was enabled. 3250 * Drain PEBS buffer before applying the single PEBS. 3251 */ 3252 intel_pmu_drain_pebs_buffer(); 3253 } else { 3254 new.wr = 0; 3255 new.full = 0; 3256 new.en = 1; 3257 wrmsrq(MSR_IA32_PEBS_INDEX, new.whole); 3258 } 3259 } 3260 } 3261 3262 if (is_pebs_counter_event_group(event)) 3263 ext |= ARCH_PEBS_CNTR_ALLOW; 3264 3265 if (cpuc->cfg_c_val[hwc->idx] != ext) 3266 __intel_pmu_update_event_ext(hwc->idx, ext); 3267 } 3268 3269 static void intel_pmu_update_rdpmc_user_disable(struct perf_event *event) 3270 { 3271 if (!x86_pmu_has_rdpmc_user_disable(event->pmu)) 3272 return; 3273 3274 /* 3275 * Counter scope's user-space rdpmc is disabled by default 3276 * except two cases. 3277 * a. rdpmc = 2 (user space rdpmc enabled unconditionally) 3278 * b. rdpmc = 1 and the event is not a system-wide event. 3279 * The count of non-system-wide events would be cleared when 3280 * context switches, so no count data is leaked. 3281 */ 3282 if (x86_pmu.attr_rdpmc == X86_USER_RDPMC_ALWAYS_ENABLE || 3283 (x86_pmu.attr_rdpmc == X86_USER_RDPMC_CONDITIONAL_ENABLE && 3284 event->ctx->task)) 3285 event->hw.config &= ~ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE; 3286 else 3287 event->hw.config |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE; 3288 } 3289 3290 DEFINE_STATIC_CALL_NULL(intel_pmu_enable_event_ext, intel_pmu_enable_event_ext); 3291 3292 static void intel_pmu_enable_event(struct perf_event *event) 3293 { 3294 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE; 3295 struct hw_perf_event *hwc = &event->hw; 3296 int idx = hwc->idx; 3297 3298 intel_pmu_update_rdpmc_user_disable(event); 3299 3300 if (unlikely(event->attr.precise_ip)) 3301 static_call(x86_pmu_pebs_enable)(event); 3302 3303 switch (idx) { 3304 case 0 ... INTEL_PMC_IDX_FIXED - 1: 3305 if (branch_sample_counters(event)) 3306 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR; 3307 intel_set_masks(event, idx); 3308 static_call_cond(intel_pmu_enable_acr_event)(event); 3309 static_call_cond(intel_pmu_enable_event_ext)(event); 3310 __x86_pmu_enable_event(hwc, enable_mask); 3311 break; 3312 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 3313 static_call_cond(intel_pmu_enable_acr_event)(event); 3314 static_call_cond(intel_pmu_enable_event_ext)(event); 3315 fallthrough; 3316 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 3317 intel_pmu_enable_fixed(event); 3318 break; 3319 case INTEL_PMC_IDX_FIXED_BTS: 3320 if (!__this_cpu_read(cpu_hw_events.enabled)) 3321 return; 3322 intel_pmu_enable_bts(hwc->config); 3323 break; 3324 case INTEL_PMC_IDX_FIXED_VLBR: 3325 intel_set_masks(event, idx); 3326 break; 3327 default: 3328 pr_warn("Failed to enable the event with invalid index %d\n", 3329 idx); 3330 } 3331 } 3332 3333 static void intel_pmu_acr_late_setup(struct cpu_hw_events *cpuc) 3334 { 3335 struct perf_event *event, *leader; 3336 int i, j, idx; 3337 3338 for (i = 0; i < cpuc->n_events; i++) { 3339 leader = cpuc->event_list[i]; 3340 if (!is_acr_event_group(leader)) 3341 continue; 3342 3343 /* The ACR events must be contiguous. */ 3344 for (j = i; j < cpuc->n_events; j++) { 3345 event = cpuc->event_list[j]; 3346 if (event->group_leader != leader->group_leader) 3347 break; 3348 for_each_set_bit(idx, (unsigned long *)&event->attr.config2, X86_PMC_IDX_MAX) { 3349 if (i + idx >= cpuc->n_events || 3350 !is_acr_event_group(cpuc->event_list[i + idx])) 3351 return; 3352 __set_bit(cpuc->assign[i + idx], (unsigned long *)&event->hw.config1); 3353 } 3354 } 3355 i = j - 1; 3356 } 3357 } 3358 3359 void intel_pmu_late_setup(void) 3360 { 3361 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3362 3363 if (!cpuc->n_late_setup) 3364 return; 3365 3366 intel_pmu_pebs_late_setup(cpuc); 3367 intel_pmu_acr_late_setup(cpuc); 3368 } 3369 3370 static void intel_pmu_add_event(struct perf_event *event) 3371 { 3372 if (event->attr.precise_ip) 3373 intel_pmu_pebs_add(event); 3374 if (intel_pmu_needs_branch_stack(event)) 3375 intel_pmu_lbr_add(event); 3376 if (is_pebs_counter_event_group(event) || 3377 is_acr_event_group(event)) 3378 this_cpu_ptr(&cpu_hw_events)->n_late_setup++; 3379 } 3380 3381 /* 3382 * Save and restart an expired event. Called by NMI contexts, 3383 * so it has to be careful about preempting normal event ops: 3384 */ 3385 int intel_pmu_save_and_restart(struct perf_event *event) 3386 { 3387 static_call(x86_pmu_update)(event); 3388 /* 3389 * For a checkpointed counter always reset back to 0. This 3390 * avoids a situation where the counter overflows, aborts the 3391 * transaction and is then set back to shortly before the 3392 * overflow, and overflows and aborts again. 3393 */ 3394 if (unlikely(event_is_checkpointed(event))) { 3395 /* No race with NMIs because the counter should not be armed */ 3396 wrmsrq(event->hw.event_base, 0); 3397 local64_set(&event->hw.prev_count, 0); 3398 } 3399 return static_call(x86_pmu_set_period)(event); 3400 } 3401 3402 static int intel_pmu_set_period(struct perf_event *event) 3403 { 3404 if (unlikely(is_topdown_count(event))) 3405 return static_call(intel_pmu_set_topdown_event_period)(event); 3406 3407 return x86_perf_event_set_period(event); 3408 } 3409 3410 static u64 intel_pmu_update(struct perf_event *event) 3411 { 3412 if (unlikely(is_topdown_count(event))) 3413 return static_call(intel_pmu_update_topdown_event)(event, NULL); 3414 3415 return x86_perf_event_update(event); 3416 } 3417 3418 static void intel_pmu_reset(void) 3419 { 3420 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 3421 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3422 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask); 3423 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask); 3424 unsigned long flags; 3425 int idx; 3426 3427 if (!*(u64 *)cntr_mask) 3428 return; 3429 3430 local_irq_save(flags); 3431 3432 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 3433 3434 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) { 3435 wrmsrq_safe(x86_pmu_config_addr(idx), 0ull); 3436 wrmsrq_safe(x86_pmu_event_addr(idx), 0ull); 3437 } 3438 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) { 3439 if (fixed_counter_disabled(idx, cpuc->pmu)) 3440 continue; 3441 wrmsrq_safe(x86_pmu_fixed_ctr_addr(idx), 0ull); 3442 } 3443 3444 if (ds) 3445 ds->bts_index = ds->bts_buffer_base; 3446 3447 /* Ack all overflows and disable fixed counters */ 3448 if (x86_pmu.version >= 2) { 3449 intel_pmu_ack_status(intel_pmu_get_status()); 3450 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0); 3451 } 3452 3453 /* Reset LBRs and LBR freezing */ 3454 if (x86_pmu.lbr_nr) { 3455 update_debugctlmsr(get_debugctlmsr() & 3456 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 3457 } 3458 3459 local_irq_restore(flags); 3460 } 3461 3462 /* 3463 * We may be running with guest PEBS events created by KVM, and the 3464 * PEBS records are logged into the guest's DS and invisible to host. 3465 * 3466 * In the case of guest PEBS overflow, we only trigger a fake event 3467 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM. 3468 * The guest will then vm-entry and check the guest DS area to read 3469 * the guest PEBS records. 3470 * 3471 * The contents and other behavior of the guest event do not matter. 3472 */ 3473 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs, 3474 struct perf_sample_data *data) 3475 { 3476 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3477 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask; 3478 struct perf_event *event = NULL; 3479 int bit; 3480 3481 if (!unlikely(perf_guest_state())) 3482 return; 3483 3484 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active || 3485 !guest_pebs_idxs) 3486 return; 3487 3488 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) { 3489 event = cpuc->events[bit]; 3490 if (!event->attr.precise_ip) 3491 continue; 3492 3493 perf_sample_data_init(data, 0, event->hw.last_period); 3494 perf_event_overflow(event, data, regs); 3495 3496 /* Inject one fake event is enough. */ 3497 break; 3498 } 3499 } 3500 3501 static int handle_pmi_common(struct pt_regs *regs, u64 status) 3502 { 3503 struct perf_sample_data data; 3504 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3505 int bit; 3506 int handled = 0; 3507 3508 inc_irq_stat(apic_perf_irqs); 3509 3510 /* 3511 * Ignore a range of extra bits in status that do not indicate 3512 * overflow by themselves. 3513 */ 3514 status &= ~(GLOBAL_STATUS_COND_CHG | 3515 GLOBAL_STATUS_ASIF | 3516 GLOBAL_STATUS_LBRS_FROZEN); 3517 if (!status) 3518 return 0; 3519 /* 3520 * In case multiple PEBS events are sampled at the same time, 3521 * it is possible to have GLOBAL_STATUS bit 62 set indicating 3522 * PEBS buffer overflow and also seeing at most 3 PEBS counters 3523 * having their bits set in the status register. This is a sign 3524 * that there was at least one PEBS record pending at the time 3525 * of the PMU interrupt. PEBS counters must only be processed 3526 * via the drain_pebs() calls and not via the regular sample 3527 * processing loop coming after that the function, otherwise 3528 * phony regular samples may be generated in the sampling buffer 3529 * not marked with the EXACT tag. Another possibility is to have 3530 * one PEBS event and at least one non-PEBS event which overflows 3531 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 3532 * not be set, yet the overflow status bit for the PEBS counter will 3533 * be on Skylake. 3534 * 3535 * To avoid this problem, we systematically ignore the PEBS-enabled 3536 * counters from the GLOBAL_STATUS mask and we always process PEBS 3537 * events via drain_pebs(). 3538 */ 3539 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable); 3540 3541 /* 3542 * PEBS overflow sets bit 62 in the global status register 3543 */ 3544 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 3545 u64 pebs_enabled = cpuc->pebs_enabled; 3546 3547 handled++; 3548 x86_pmu_handle_guest_pebs(regs, &data); 3549 static_call(x86_pmu_drain_pebs)(regs, &data); 3550 3551 /* 3552 * PMI throttle may be triggered, which stops the PEBS event. 3553 * Although cpuc->pebs_enabled is updated accordingly, the 3554 * MSR_IA32_PEBS_ENABLE is not updated. Because the 3555 * cpuc->enabled has been forced to 0 in PMI. 3556 * Update the MSR if pebs_enabled is changed. 3557 */ 3558 if (pebs_enabled != cpuc->pebs_enabled) 3559 wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 3560 3561 /* 3562 * Above PEBS handler (PEBS counters snapshotting) has updated fixed 3563 * counter 3 and perf metrics counts if they are in counter group, 3564 * unnecessary to update again. 3565 */ 3566 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] && 3567 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS])) 3568 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT; 3569 } 3570 3571 /* 3572 * Arch PEBS sets bit 54 in the global status register 3573 */ 3574 if (__test_and_clear_bit(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT, 3575 (unsigned long *)&status)) { 3576 handled++; 3577 static_call(x86_pmu_drain_pebs)(regs, &data); 3578 3579 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] && 3580 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS])) 3581 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT; 3582 } 3583 3584 /* 3585 * Intel PT 3586 */ 3587 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 3588 handled++; 3589 if (!perf_guest_handle_intel_pt_intr()) 3590 intel_pt_interrupt(); 3591 } 3592 3593 /* 3594 * Intel Perf metrics 3595 */ 3596 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 3597 handled++; 3598 static_call(intel_pmu_update_topdown_event)(NULL, NULL); 3599 } 3600 3601 status &= hybrid(cpuc->pmu, intel_ctrl); 3602 3603 /* 3604 * Checkpointed counters can lead to 'spurious' PMIs because the 3605 * rollback caused by the PMI will have cleared the overflow status 3606 * bit. Therefore always force probe these counters. 3607 */ 3608 status |= cpuc->intel_cp_status; 3609 3610 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 3611 struct perf_event *event = cpuc->events[bit]; 3612 u64 last_period; 3613 3614 handled++; 3615 3616 if (!test_bit(bit, cpuc->active_mask)) 3617 continue; 3618 /* Event may have already been cleared: */ 3619 if (!event) 3620 continue; 3621 3622 /* 3623 * There may be unprocessed PEBS records in the PEBS buffer, 3624 * which still stores the previous values. 3625 * Process those records first before handling the latest value. 3626 * For example, 3627 * A is a regular counter 3628 * B is a PEBS event which reads A 3629 * C is a PEBS event 3630 * 3631 * The following can happen: 3632 * B-assist A=1 3633 * C A=2 3634 * B-assist A=3 3635 * A-overflow-PMI A=4 3636 * C-assist-PMI (PEBS buffer) A=5 3637 * 3638 * The PEBS buffer has to be drained before handling the A-PMI 3639 */ 3640 if (is_pebs_counter_event_group(event)) 3641 static_call(x86_pmu_drain_pebs)(regs, &data); 3642 3643 last_period = event->hw.last_period; 3644 3645 if (!intel_pmu_save_and_restart(event)) 3646 continue; 3647 3648 perf_sample_data_init(&data, 0, last_period); 3649 3650 if (has_branch_stack(event)) 3651 intel_pmu_lbr_save_brstack(&data, cpuc, event); 3652 3653 perf_event_overflow(event, &data, regs); 3654 } 3655 3656 return handled; 3657 } 3658 3659 /* 3660 * This handler is triggered by the local APIC, so the APIC IRQ handling 3661 * rules apply: 3662 */ 3663 static int intel_pmu_handle_irq(struct pt_regs *regs) 3664 { 3665 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3666 bool late_ack = hybrid_bit(cpuc->pmu, late_ack); 3667 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); 3668 int loops; 3669 u64 status; 3670 int handled; 3671 int pmu_enabled; 3672 3673 /* 3674 * Save the PMU state. 3675 * It needs to be restored when leaving the handler. 3676 */ 3677 pmu_enabled = cpuc->enabled; 3678 /* 3679 * In general, the early ACK is only applied for old platforms. 3680 * For the big core starts from Haswell, the late ACK should be 3681 * applied. 3682 * For the small core after Tremont, we have to do the ACK right 3683 * before re-enabling counters, which is in the middle of the 3684 * NMI handler. 3685 */ 3686 if (!late_ack && !mid_ack) 3687 apic_write(APIC_LVTPC, APIC_DM_NMI); 3688 intel_bts_disable_local(); 3689 cpuc->enabled = 0; 3690 __intel_pmu_disable_all(true); 3691 handled = intel_pmu_drain_bts_buffer(); 3692 handled += intel_bts_interrupt(); 3693 status = intel_pmu_get_status(); 3694 if (!status) 3695 goto done; 3696 3697 loops = 0; 3698 again: 3699 intel_pmu_lbr_read(); 3700 intel_pmu_ack_status(status); 3701 if (++loops > 100) { 3702 static bool warned; 3703 3704 if (!warned) { 3705 WARN(1, "perfevents: irq loop stuck!\n"); 3706 perf_event_print_debug(); 3707 warned = true; 3708 } 3709 intel_pmu_reset(); 3710 goto done; 3711 } 3712 3713 handled += handle_pmi_common(regs, status); 3714 3715 /* 3716 * Repeat if there is more work to be done: 3717 */ 3718 status = intel_pmu_get_status(); 3719 if (status) 3720 goto again; 3721 3722 done: 3723 if (mid_ack) 3724 apic_write(APIC_LVTPC, APIC_DM_NMI); 3725 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 3726 cpuc->enabled = pmu_enabled; 3727 if (pmu_enabled) 3728 __intel_pmu_enable_all(0, true); 3729 intel_bts_enable_local(); 3730 3731 /* 3732 * Only unmask the NMI after the overflow counters 3733 * have been reset. This avoids spurious NMIs on 3734 * Haswell CPUs. 3735 */ 3736 if (late_ack) 3737 apic_write(APIC_LVTPC, APIC_DM_NMI); 3738 return handled; 3739 } 3740 3741 static struct event_constraint * 3742 intel_bts_constraints(struct perf_event *event) 3743 { 3744 if (unlikely(intel_pmu_has_bts(event))) 3745 return &bts_constraint; 3746 3747 return NULL; 3748 } 3749 3750 /* 3751 * Note: matches a fake event, like Fixed2. 3752 */ 3753 static struct event_constraint * 3754 intel_vlbr_constraints(struct perf_event *event) 3755 { 3756 struct event_constraint *c = &vlbr_constraint; 3757 3758 if (unlikely(constraint_match(c, event->hw.config))) { 3759 event->hw.flags |= c->flags; 3760 return c; 3761 } 3762 3763 return NULL; 3764 } 3765 3766 static int intel_alt_er(struct cpu_hw_events *cpuc, 3767 int idx, u64 config) 3768 { 3769 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); 3770 int alt_idx = idx; 3771 3772 switch (idx) { 3773 case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1: 3774 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 3775 return idx; 3776 if (++alt_idx > EXTRA_REG_RSP_1) 3777 alt_idx = EXTRA_REG_RSP_0; 3778 if (config & ~extra_regs[alt_idx].valid_mask) 3779 return idx; 3780 break; 3781 3782 case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3: 3783 if (!(x86_pmu.flags & PMU_FL_HAS_OMR)) 3784 return idx; 3785 if (++alt_idx > EXTRA_REG_OMR_3) 3786 alt_idx = EXTRA_REG_OMR_0; 3787 /* 3788 * Subtracting EXTRA_REG_OMR_0 ensures to get correct 3789 * OMR extra_reg entries which start from 0. 3790 */ 3791 if (config & ~extra_regs[alt_idx - EXTRA_REG_OMR_0].valid_mask) 3792 return idx; 3793 break; 3794 3795 default: 3796 break; 3797 } 3798 3799 return alt_idx; 3800 } 3801 3802 static void intel_fixup_er(struct perf_event *event, int idx) 3803 { 3804 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); 3805 int er_idx; 3806 3807 event->hw.extra_reg.idx = idx; 3808 switch (idx) { 3809 case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1: 3810 er_idx = idx - EXTRA_REG_RSP_0; 3811 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3812 event->hw.config |= extra_regs[er_idx].event; 3813 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0 + er_idx; 3814 break; 3815 3816 case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3: 3817 er_idx = idx - EXTRA_REG_OMR_0; 3818 event->hw.config &= ~ARCH_PERFMON_EVENTSEL_UMASK; 3819 event->hw.config |= 1ULL << (8 + er_idx); 3820 event->hw.extra_reg.reg = MSR_OMR_0 + er_idx; 3821 break; 3822 3823 default: 3824 pr_warn("The extra reg idx %d is not supported.\n", idx); 3825 } 3826 } 3827 3828 /* 3829 * manage allocation of shared extra msr for certain events 3830 * 3831 * sharing can be: 3832 * per-cpu: to be shared between the various events on a single PMU 3833 * per-core: per-cpu + shared by HT threads 3834 */ 3835 static struct event_constraint * 3836 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 3837 struct perf_event *event, 3838 struct hw_perf_event_extra *reg) 3839 { 3840 struct event_constraint *c = &emptyconstraint; 3841 struct er_account *era; 3842 unsigned long flags; 3843 int idx = reg->idx; 3844 3845 /* 3846 * reg->alloc can be set due to existing state, so for fake cpuc we 3847 * need to ignore this, otherwise we might fail to allocate proper fake 3848 * state for this extra reg constraint. Also see the comment below. 3849 */ 3850 if (reg->alloc && !cpuc->is_fake) 3851 return NULL; /* call x86_get_event_constraint() */ 3852 3853 again: 3854 era = &cpuc->shared_regs->regs[idx]; 3855 /* 3856 * we use spin_lock_irqsave() to avoid lockdep issues when 3857 * passing a fake cpuc 3858 */ 3859 raw_spin_lock_irqsave(&era->lock, flags); 3860 3861 if (!atomic_read(&era->ref) || era->config == reg->config) { 3862 3863 /* 3864 * If its a fake cpuc -- as per validate_{group,event}() we 3865 * shouldn't touch event state and we can avoid doing so 3866 * since both will only call get_event_constraints() once 3867 * on each event, this avoids the need for reg->alloc. 3868 * 3869 * Not doing the ER fixup will only result in era->reg being 3870 * wrong, but since we won't actually try and program hardware 3871 * this isn't a problem either. 3872 */ 3873 if (!cpuc->is_fake) { 3874 if (idx != reg->idx) 3875 intel_fixup_er(event, idx); 3876 3877 /* 3878 * x86_schedule_events() can call get_event_constraints() 3879 * multiple times on events in the case of incremental 3880 * scheduling(). reg->alloc ensures we only do the ER 3881 * allocation once. 3882 */ 3883 reg->alloc = 1; 3884 } 3885 3886 /* lock in msr value */ 3887 era->config = reg->config; 3888 era->reg = reg->reg; 3889 3890 /* one more user */ 3891 atomic_inc(&era->ref); 3892 3893 /* 3894 * need to call x86_get_event_constraint() 3895 * to check if associated event has constraints 3896 */ 3897 c = NULL; 3898 } else { 3899 idx = intel_alt_er(cpuc, idx, reg->config); 3900 if (idx != reg->idx) { 3901 raw_spin_unlock_irqrestore(&era->lock, flags); 3902 goto again; 3903 } 3904 } 3905 raw_spin_unlock_irqrestore(&era->lock, flags); 3906 3907 return c; 3908 } 3909 3910 static void 3911 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3912 struct hw_perf_event_extra *reg) 3913 { 3914 struct er_account *era; 3915 3916 /* 3917 * Only put constraint if extra reg was actually allocated. Also takes 3918 * care of event which do not use an extra shared reg. 3919 * 3920 * Also, if this is a fake cpuc we shouldn't touch any event state 3921 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3922 * either since it'll be thrown out. 3923 */ 3924 if (!reg->alloc || cpuc->is_fake) 3925 return; 3926 3927 era = &cpuc->shared_regs->regs[reg->idx]; 3928 3929 /* one fewer user */ 3930 atomic_dec(&era->ref); 3931 3932 /* allocate again next time */ 3933 reg->alloc = 0; 3934 } 3935 3936 static struct event_constraint * 3937 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3938 struct perf_event *event) 3939 { 3940 struct event_constraint *c = NULL, *d; 3941 struct hw_perf_event_extra *xreg, *breg; 3942 3943 xreg = &event->hw.extra_reg; 3944 if (xreg->idx != EXTRA_REG_NONE) { 3945 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3946 if (c == &emptyconstraint) 3947 return c; 3948 } 3949 breg = &event->hw.branch_reg; 3950 if (breg->idx != EXTRA_REG_NONE) { 3951 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3952 if (d == &emptyconstraint) { 3953 __intel_shared_reg_put_constraints(cpuc, xreg); 3954 c = d; 3955 } 3956 } 3957 return c; 3958 } 3959 3960 struct event_constraint * 3961 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3962 struct perf_event *event) 3963 { 3964 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); 3965 struct event_constraint *c; 3966 3967 if (event_constraints) { 3968 for_each_event_constraint(c, event_constraints) { 3969 if (constraint_match(c, event->hw.config)) { 3970 event->hw.flags |= c->flags; 3971 return c; 3972 } 3973 } 3974 } 3975 3976 return &hybrid_var(cpuc->pmu, unconstrained); 3977 } 3978 3979 static struct event_constraint * 3980 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3981 struct perf_event *event) 3982 { 3983 struct event_constraint *c; 3984 3985 c = intel_vlbr_constraints(event); 3986 if (c) 3987 return c; 3988 3989 c = intel_bts_constraints(event); 3990 if (c) 3991 return c; 3992 3993 c = intel_shared_regs_constraints(cpuc, event); 3994 if (c) 3995 return c; 3996 3997 c = intel_pebs_constraints(event); 3998 if (c) 3999 return c; 4000 4001 return x86_get_event_constraints(cpuc, idx, event); 4002 } 4003 4004 static void 4005 intel_start_scheduling(struct cpu_hw_events *cpuc) 4006 { 4007 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 4008 struct intel_excl_states *xl; 4009 int tid = cpuc->excl_thread_id; 4010 4011 /* 4012 * nothing needed if in group validation mode 4013 */ 4014 if (cpuc->is_fake || !is_ht_workaround_enabled()) 4015 return; 4016 4017 /* 4018 * no exclusion needed 4019 */ 4020 if (WARN_ON_ONCE(!excl_cntrs)) 4021 return; 4022 4023 xl = &excl_cntrs->states[tid]; 4024 4025 xl->sched_started = true; 4026 /* 4027 * lock shared state until we are done scheduling 4028 * in stop_event_scheduling() 4029 * makes scheduling appear as a transaction 4030 */ 4031 raw_spin_lock(&excl_cntrs->lock); 4032 } 4033 4034 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 4035 { 4036 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 4037 struct event_constraint *c = cpuc->event_constraint[idx]; 4038 struct intel_excl_states *xl; 4039 int tid = cpuc->excl_thread_id; 4040 4041 if (cpuc->is_fake || !is_ht_workaround_enabled()) 4042 return; 4043 4044 if (WARN_ON_ONCE(!excl_cntrs)) 4045 return; 4046 4047 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 4048 return; 4049 4050 xl = &excl_cntrs->states[tid]; 4051 4052 lockdep_assert_held(&excl_cntrs->lock); 4053 4054 if (c->flags & PERF_X86_EVENT_EXCL) 4055 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 4056 else 4057 xl->state[cntr] = INTEL_EXCL_SHARED; 4058 } 4059 4060 static void 4061 intel_stop_scheduling(struct cpu_hw_events *cpuc) 4062 { 4063 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 4064 struct intel_excl_states *xl; 4065 int tid = cpuc->excl_thread_id; 4066 4067 /* 4068 * nothing needed if in group validation mode 4069 */ 4070 if (cpuc->is_fake || !is_ht_workaround_enabled()) 4071 return; 4072 /* 4073 * no exclusion needed 4074 */ 4075 if (WARN_ON_ONCE(!excl_cntrs)) 4076 return; 4077 4078 xl = &excl_cntrs->states[tid]; 4079 4080 xl->sched_started = false; 4081 /* 4082 * release shared state lock (acquired in intel_start_scheduling()) 4083 */ 4084 raw_spin_unlock(&excl_cntrs->lock); 4085 } 4086 4087 static struct event_constraint * 4088 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 4089 { 4090 WARN_ON_ONCE(!cpuc->constraint_list); 4091 4092 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 4093 struct event_constraint *cx; 4094 4095 /* 4096 * grab pre-allocated constraint entry 4097 */ 4098 cx = &cpuc->constraint_list[idx]; 4099 4100 /* 4101 * initialize dynamic constraint 4102 * with static constraint 4103 */ 4104 *cx = *c; 4105 4106 /* 4107 * mark constraint as dynamic 4108 */ 4109 cx->flags |= PERF_X86_EVENT_DYNAMIC; 4110 c = cx; 4111 } 4112 4113 return c; 4114 } 4115 4116 static struct event_constraint * 4117 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 4118 int idx, struct event_constraint *c) 4119 { 4120 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 4121 struct intel_excl_states *xlo; 4122 int tid = cpuc->excl_thread_id; 4123 int is_excl, i, w; 4124 4125 /* 4126 * validating a group does not require 4127 * enforcing cross-thread exclusion 4128 */ 4129 if (cpuc->is_fake || !is_ht_workaround_enabled()) 4130 return c; 4131 4132 /* 4133 * no exclusion needed 4134 */ 4135 if (WARN_ON_ONCE(!excl_cntrs)) 4136 return c; 4137 4138 /* 4139 * because we modify the constraint, we need 4140 * to make a copy. Static constraints come 4141 * from static const tables. 4142 * 4143 * only needed when constraint has not yet 4144 * been cloned (marked dynamic) 4145 */ 4146 c = dyn_constraint(cpuc, c, idx); 4147 4148 /* 4149 * From here on, the constraint is dynamic. 4150 * Either it was just allocated above, or it 4151 * was allocated during a earlier invocation 4152 * of this function 4153 */ 4154 4155 /* 4156 * state of sibling HT 4157 */ 4158 xlo = &excl_cntrs->states[tid ^ 1]; 4159 4160 /* 4161 * event requires exclusive counter access 4162 * across HT threads 4163 */ 4164 is_excl = c->flags & PERF_X86_EVENT_EXCL; 4165 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 4166 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 4167 if (!cpuc->n_excl++) 4168 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 4169 } 4170 4171 /* 4172 * Modify static constraint with current dynamic 4173 * state of thread 4174 * 4175 * EXCLUSIVE: sibling counter measuring exclusive event 4176 * SHARED : sibling counter measuring non-exclusive event 4177 * UNUSED : sibling counter unused 4178 */ 4179 w = c->weight; 4180 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 4181 /* 4182 * exclusive event in sibling counter 4183 * our corresponding counter cannot be used 4184 * regardless of our event 4185 */ 4186 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 4187 __clear_bit(i, c->idxmsk); 4188 w--; 4189 continue; 4190 } 4191 /* 4192 * if measuring an exclusive event, sibling 4193 * measuring non-exclusive, then counter cannot 4194 * be used 4195 */ 4196 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 4197 __clear_bit(i, c->idxmsk); 4198 w--; 4199 continue; 4200 } 4201 } 4202 4203 /* 4204 * if we return an empty mask, then switch 4205 * back to static empty constraint to avoid 4206 * the cost of freeing later on 4207 */ 4208 if (!w) 4209 c = &emptyconstraint; 4210 4211 c->weight = w; 4212 4213 return c; 4214 } 4215 4216 static struct event_constraint * 4217 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4218 struct perf_event *event) 4219 { 4220 struct event_constraint *c1, *c2; 4221 4222 c1 = cpuc->event_constraint[idx]; 4223 4224 /* 4225 * first time only 4226 * - static constraint: no change across incremental scheduling calls 4227 * - dynamic constraint: handled by intel_get_excl_constraints() 4228 */ 4229 c2 = __intel_get_event_constraints(cpuc, idx, event); 4230 if (c1) { 4231 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 4232 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 4233 c1->weight = c2->weight; 4234 c2 = c1; 4235 } 4236 4237 if (cpuc->excl_cntrs) 4238 return intel_get_excl_constraints(cpuc, event, idx, c2); 4239 4240 if (event->hw.dyn_constraint != ~0ULL) { 4241 c2 = dyn_constraint(cpuc, c2, idx); 4242 c2->idxmsk64 &= event->hw.dyn_constraint; 4243 c2->weight = hweight64(c2->idxmsk64); 4244 } 4245 4246 return c2; 4247 } 4248 4249 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 4250 struct perf_event *event) 4251 { 4252 struct hw_perf_event *hwc = &event->hw; 4253 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 4254 int tid = cpuc->excl_thread_id; 4255 struct intel_excl_states *xl; 4256 4257 /* 4258 * nothing needed if in group validation mode 4259 */ 4260 if (cpuc->is_fake) 4261 return; 4262 4263 if (WARN_ON_ONCE(!excl_cntrs)) 4264 return; 4265 4266 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 4267 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 4268 if (!--cpuc->n_excl) 4269 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 4270 } 4271 4272 /* 4273 * If event was actually assigned, then mark the counter state as 4274 * unused now. 4275 */ 4276 if (hwc->idx >= 0) { 4277 xl = &excl_cntrs->states[tid]; 4278 4279 /* 4280 * put_constraint may be called from x86_schedule_events() 4281 * which already has the lock held so here make locking 4282 * conditional. 4283 */ 4284 if (!xl->sched_started) 4285 raw_spin_lock(&excl_cntrs->lock); 4286 4287 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 4288 4289 if (!xl->sched_started) 4290 raw_spin_unlock(&excl_cntrs->lock); 4291 } 4292 } 4293 4294 static void 4295 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 4296 struct perf_event *event) 4297 { 4298 struct hw_perf_event_extra *reg; 4299 4300 reg = &event->hw.extra_reg; 4301 if (reg->idx != EXTRA_REG_NONE) 4302 __intel_shared_reg_put_constraints(cpuc, reg); 4303 4304 reg = &event->hw.branch_reg; 4305 if (reg->idx != EXTRA_REG_NONE) 4306 __intel_shared_reg_put_constraints(cpuc, reg); 4307 } 4308 4309 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 4310 struct perf_event *event) 4311 { 4312 intel_put_shared_regs_event_constraints(cpuc, event); 4313 4314 /* 4315 * is PMU has exclusive counter restrictions, then 4316 * all events are subject to and must call the 4317 * put_excl_constraints() routine 4318 */ 4319 if (cpuc->excl_cntrs) 4320 intel_put_excl_constraints(cpuc, event); 4321 } 4322 4323 static void intel_pebs_aliases_core2(struct perf_event *event) 4324 { 4325 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 4326 /* 4327 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 4328 * (0x003c) so that we can use it with PEBS. 4329 * 4330 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 4331 * PEBS capable. However we can use INST_RETIRED.ANY_P 4332 * (0x00c0), which is a PEBS capable event, to get the same 4333 * count. 4334 * 4335 * INST_RETIRED.ANY_P counts the number of cycles that retires 4336 * CNTMASK instructions. By setting CNTMASK to a value (16) 4337 * larger than the maximum number of instructions that can be 4338 * retired per cycle (4) and then inverting the condition, we 4339 * count all cycles that retire 16 or less instructions, which 4340 * is every cycle. 4341 * 4342 * Thereby we gain a PEBS capable cycle counter. 4343 */ 4344 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 4345 4346 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 4347 event->hw.config = alt_config; 4348 } 4349 } 4350 4351 static void intel_pebs_aliases_snb(struct perf_event *event) 4352 { 4353 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 4354 /* 4355 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 4356 * (0x003c) so that we can use it with PEBS. 4357 * 4358 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 4359 * PEBS capable. However we can use UOPS_RETIRED.ALL 4360 * (0x01c2), which is a PEBS capable event, to get the same 4361 * count. 4362 * 4363 * UOPS_RETIRED.ALL counts the number of cycles that retires 4364 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 4365 * larger than the maximum number of micro-ops that can be 4366 * retired per cycle (4) and then inverting the condition, we 4367 * count all cycles that retire 16 or less micro-ops, which 4368 * is every cycle. 4369 * 4370 * Thereby we gain a PEBS capable cycle counter. 4371 */ 4372 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 4373 4374 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 4375 event->hw.config = alt_config; 4376 } 4377 } 4378 4379 static void intel_pebs_aliases_precdist(struct perf_event *event) 4380 { 4381 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 4382 /* 4383 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 4384 * (0x003c) so that we can use it with PEBS. 4385 * 4386 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 4387 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 4388 * (0x01c0), which is a PEBS capable event, to get the same 4389 * count. 4390 * 4391 * The PREC_DIST event has special support to minimize sample 4392 * shadowing effects. One drawback is that it can be 4393 * only programmed on counter 1, but that seems like an 4394 * acceptable trade off. 4395 */ 4396 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 4397 4398 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 4399 event->hw.config = alt_config; 4400 } 4401 } 4402 4403 static void intel_pebs_aliases_ivb(struct perf_event *event) 4404 { 4405 if (event->attr.precise_ip < 3) 4406 return intel_pebs_aliases_snb(event); 4407 return intel_pebs_aliases_precdist(event); 4408 } 4409 4410 static void intel_pebs_aliases_skl(struct perf_event *event) 4411 { 4412 if (event->attr.precise_ip < 3) 4413 return intel_pebs_aliases_core2(event); 4414 return intel_pebs_aliases_precdist(event); 4415 } 4416 4417 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 4418 { 4419 unsigned long flags = x86_pmu.large_pebs_flags; 4420 4421 if (event->attr.use_clockid) 4422 flags &= ~PERF_SAMPLE_TIME; 4423 if (!event->attr.exclude_kernel) 4424 flags &= ~PERF_SAMPLE_REGS_USER; 4425 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 4426 flags &= ~PERF_SAMPLE_REGS_USER; 4427 if (event->attr.sample_regs_intr & ~PEBS_GP_REGS) 4428 flags &= ~PERF_SAMPLE_REGS_INTR; 4429 return flags; 4430 } 4431 4432 static int intel_pmu_bts_config(struct perf_event *event) 4433 { 4434 struct perf_event_attr *attr = &event->attr; 4435 4436 if (unlikely(intel_pmu_has_bts(event))) { 4437 /* BTS is not supported by this architecture. */ 4438 if (!x86_pmu.bts_active) 4439 return -EOPNOTSUPP; 4440 4441 /* BTS is currently only allowed for user-mode. */ 4442 if (!attr->exclude_kernel) 4443 return -EOPNOTSUPP; 4444 4445 /* BTS is not allowed for precise events. */ 4446 if (attr->precise_ip) 4447 return -EOPNOTSUPP; 4448 4449 /* disallow bts if conflicting events are present */ 4450 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 4451 return -EBUSY; 4452 4453 event->destroy = hw_perf_lbr_event_destroy; 4454 } 4455 4456 return 0; 4457 } 4458 4459 static int core_pmu_hw_config(struct perf_event *event) 4460 { 4461 int ret = x86_pmu_hw_config(event); 4462 4463 if (ret) 4464 return ret; 4465 4466 return intel_pmu_bts_config(event); 4467 } 4468 4469 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 4470 ((x86_pmu.num_topdown_events - 1) << 8)) 4471 4472 static bool is_available_metric_event(struct perf_event *event) 4473 { 4474 return is_metric_event(event) && 4475 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 4476 } 4477 4478 static inline bool is_mem_loads_event(struct perf_event *event) 4479 { 4480 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 4481 } 4482 4483 static inline bool is_mem_loads_aux_event(struct perf_event *event) 4484 { 4485 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 4486 } 4487 4488 static inline bool require_mem_loads_aux_event(struct perf_event *event) 4489 { 4490 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) 4491 return false; 4492 4493 if (is_hybrid()) 4494 return hybrid_pmu(event->pmu)->pmu_type == hybrid_big; 4495 4496 return true; 4497 } 4498 4499 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) 4500 { 4501 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); 4502 4503 return test_bit(idx, (unsigned long *)&intel_cap->capabilities); 4504 } 4505 4506 static u64 intel_pmu_freq_start_period(struct perf_event *event) 4507 { 4508 int type = event->attr.type; 4509 u64 config, factor; 4510 s64 start; 4511 4512 /* 4513 * The 127 is the lowest possible recommended SAV (sample after value) 4514 * for a 4000 freq (default freq), according to the event list JSON file. 4515 * Also, assume the workload is idle 50% time. 4516 */ 4517 factor = 64 * 4000; 4518 if (type != PERF_TYPE_HARDWARE && type != PERF_TYPE_HW_CACHE) 4519 goto end; 4520 4521 /* 4522 * The estimation of the start period in the freq mode is 4523 * based on the below assumption. 4524 * 4525 * For a cycles or an instructions event, 1GHZ of the 4526 * underlying platform, 1 IPC. The workload is idle 50% time. 4527 * The start period = 1,000,000,000 * 1 / freq / 2. 4528 * = 500,000,000 / freq 4529 * 4530 * Usually, the branch-related events occur less than the 4531 * instructions event. According to the Intel event list JSON 4532 * file, the SAV (sample after value) of a branch-related event 4533 * is usually 1/4 of an instruction event. 4534 * The start period of branch-related events = 125,000,000 / freq. 4535 * 4536 * The cache-related events occurs even less. The SAV is usually 4537 * 1/20 of an instruction event. 4538 * The start period of cache-related events = 25,000,000 / freq. 4539 */ 4540 config = event->attr.config & PERF_HW_EVENT_MASK; 4541 if (type == PERF_TYPE_HARDWARE) { 4542 switch (config) { 4543 case PERF_COUNT_HW_CPU_CYCLES: 4544 case PERF_COUNT_HW_INSTRUCTIONS: 4545 case PERF_COUNT_HW_BUS_CYCLES: 4546 case PERF_COUNT_HW_STALLED_CYCLES_FRONTEND: 4547 case PERF_COUNT_HW_STALLED_CYCLES_BACKEND: 4548 case PERF_COUNT_HW_REF_CPU_CYCLES: 4549 factor = 500000000; 4550 break; 4551 case PERF_COUNT_HW_BRANCH_INSTRUCTIONS: 4552 case PERF_COUNT_HW_BRANCH_MISSES: 4553 factor = 125000000; 4554 break; 4555 case PERF_COUNT_HW_CACHE_REFERENCES: 4556 case PERF_COUNT_HW_CACHE_MISSES: 4557 factor = 25000000; 4558 break; 4559 default: 4560 goto end; 4561 } 4562 } 4563 4564 if (type == PERF_TYPE_HW_CACHE) 4565 factor = 25000000; 4566 end: 4567 /* 4568 * Usually, a prime or a number with less factors (close to prime) 4569 * is chosen as an SAV, which makes it less likely that the sampling 4570 * period synchronizes with some periodic event in the workload. 4571 * Minus 1 to make it at least avoiding values near power of twos 4572 * for the default freq. 4573 */ 4574 start = DIV_ROUND_UP_ULL(factor, event->attr.sample_freq) - 1; 4575 4576 if (start > x86_pmu.max_period) 4577 start = x86_pmu.max_period; 4578 4579 if (x86_pmu.limit_period) 4580 x86_pmu.limit_period(event, &start); 4581 4582 return start; 4583 } 4584 4585 static inline bool intel_pmu_has_acr(struct pmu *pmu) 4586 { 4587 return !!hybrid(pmu, acr_cause_mask64); 4588 } 4589 4590 static bool intel_pmu_is_acr_group(struct perf_event *event) 4591 { 4592 /* The group leader has the ACR flag set */ 4593 if (is_acr_event_group(event)) 4594 return true; 4595 4596 /* The acr_mask is set */ 4597 if (event->attr.config2) 4598 return true; 4599 4600 return false; 4601 } 4602 4603 static inline bool intel_pmu_has_pebs_counter_group(struct pmu *pmu) 4604 { 4605 u64 caps; 4606 4607 if (x86_pmu.intel_cap.pebs_format >= 6 && x86_pmu.intel_cap.pebs_baseline) 4608 return true; 4609 4610 caps = hybrid(pmu, arch_pebs_cap).caps; 4611 if (x86_pmu.arch_pebs && (caps & ARCH_PEBS_CNTR_MASK)) 4612 return true; 4613 4614 return false; 4615 } 4616 4617 static inline void intel_pmu_set_acr_cntr_constr(struct perf_event *event, 4618 u64 *cause_mask, int *num) 4619 { 4620 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cntr_mask64); 4621 *cause_mask |= event->attr.config2; 4622 *num += 1; 4623 } 4624 4625 static inline void intel_pmu_set_acr_caused_constr(struct perf_event *event, 4626 int idx, u64 cause_mask) 4627 { 4628 if (test_bit(idx, (unsigned long *)&cause_mask)) 4629 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cause_mask64); 4630 } 4631 4632 static inline int intel_set_branch_counter_constr(struct perf_event *event, 4633 int *num) 4634 { 4635 if (branch_sample_call_stack(event)) 4636 return -EINVAL; 4637 if (branch_sample_counters(event)) { 4638 (*num)++; 4639 event->hw.dyn_constraint &= x86_pmu.lbr_counters; 4640 } 4641 4642 return 0; 4643 } 4644 4645 static int intel_pmu_hw_config(struct perf_event *event) 4646 { 4647 int ret = x86_pmu_hw_config(event); 4648 4649 if (ret) 4650 return ret; 4651 4652 ret = intel_pmu_bts_config(event); 4653 if (ret) 4654 return ret; 4655 4656 if (event->attr.freq && event->attr.sample_freq) { 4657 event->hw.sample_period = intel_pmu_freq_start_period(event); 4658 event->hw.last_period = event->hw.sample_period; 4659 local64_set(&event->hw.period_left, event->hw.sample_period); 4660 } 4661 4662 if (event->attr.precise_ip) { 4663 struct arch_pebs_cap pebs_cap = hybrid(event->pmu, arch_pebs_cap); 4664 4665 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) 4666 return -EINVAL; 4667 4668 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 4669 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 4670 if (!(event->attr.sample_type & ~intel_pmu_large_pebs_flags(event)) && 4671 !has_aux_action(event)) { 4672 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 4673 event->attach_state |= PERF_ATTACH_SCHED_CB; 4674 } 4675 } 4676 if (x86_pmu.pebs_aliases) 4677 x86_pmu.pebs_aliases(event); 4678 4679 if (x86_pmu.arch_pebs) { 4680 u64 cntr_mask = hybrid(event->pmu, intel_ctrl) & 4681 ~GLOBAL_CTRL_EN_PERF_METRICS; 4682 u64 pebs_mask = event->attr.precise_ip >= 3 ? 4683 pebs_cap.pdists : pebs_cap.counters; 4684 if (cntr_mask != pebs_mask) 4685 event->hw.dyn_constraint &= pebs_mask; 4686 } 4687 } 4688 4689 if (needs_branch_stack(event)) { 4690 /* Avoid branch stack setup for counting events in SAMPLE READ */ 4691 if (is_sampling_event(event) || 4692 !(event->attr.sample_type & PERF_SAMPLE_READ)) 4693 event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK; 4694 } 4695 4696 if (branch_sample_counters(event)) { 4697 struct perf_event *leader, *sibling; 4698 int num = 0; 4699 4700 if (!(x86_pmu.flags & PMU_FL_BR_CNTR) || 4701 (event->attr.config & ~INTEL_ARCH_EVENT_MASK)) 4702 return -EINVAL; 4703 4704 /* 4705 * The branch counter logging is not supported in the call stack 4706 * mode yet, since we cannot simply flush the LBR during e.g., 4707 * multiplexing. Also, there is no obvious usage with the call 4708 * stack mode. Simply forbids it for now. 4709 * 4710 * If any events in the group enable the branch counter logging 4711 * feature, the group is treated as a branch counter logging 4712 * group, which requires the extra space to store the counters. 4713 */ 4714 leader = event->group_leader; 4715 if (intel_set_branch_counter_constr(leader, &num)) 4716 return -EINVAL; 4717 leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS; 4718 4719 for_each_sibling_event(sibling, leader) { 4720 if (intel_set_branch_counter_constr(sibling, &num)) 4721 return -EINVAL; 4722 } 4723 4724 /* event isn't installed as a sibling yet. */ 4725 if (event != leader) { 4726 if (intel_set_branch_counter_constr(event, &num)) 4727 return -EINVAL; 4728 } 4729 4730 if (num > fls(x86_pmu.lbr_counters)) 4731 return -EINVAL; 4732 /* 4733 * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't 4734 * require any branch stack setup. 4735 * Clear the bit to avoid unnecessary branch stack setup. 4736 */ 4737 if (0 == (event->attr.branch_sample_type & 4738 ~(PERF_SAMPLE_BRANCH_PLM_ALL | 4739 PERF_SAMPLE_BRANCH_COUNTERS))) 4740 event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK; 4741 4742 /* 4743 * Force the leader to be a LBR event. So LBRs can be reset 4744 * with the leader event. See intel_pmu_lbr_del() for details. 4745 */ 4746 if (!intel_pmu_needs_branch_stack(leader)) 4747 return -EINVAL; 4748 } 4749 4750 if (intel_pmu_needs_branch_stack(event)) { 4751 ret = intel_pmu_setup_lbr_filter(event); 4752 if (ret) 4753 return ret; 4754 event->attach_state |= PERF_ATTACH_SCHED_CB; 4755 4756 /* 4757 * BTS is set up earlier in this path, so don't account twice 4758 */ 4759 if (!unlikely(intel_pmu_has_bts(event))) { 4760 /* disallow lbr if conflicting events are present */ 4761 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 4762 return -EBUSY; 4763 4764 event->destroy = hw_perf_lbr_event_destroy; 4765 } 4766 } 4767 4768 if (event->attr.aux_output) { 4769 if (!event->attr.precise_ip) 4770 return -EINVAL; 4771 4772 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 4773 } 4774 4775 if ((event->attr.sample_type & PERF_SAMPLE_READ) && 4776 intel_pmu_has_pebs_counter_group(event->pmu) && 4777 is_sampling_event(event) && 4778 event->attr.precise_ip) 4779 event->group_leader->hw.flags |= PERF_X86_EVENT_PEBS_CNTR; 4780 4781 if (intel_pmu_has_acr(event->pmu) && intel_pmu_is_acr_group(event)) { 4782 struct perf_event *sibling, *leader = event->group_leader; 4783 struct pmu *pmu = event->pmu; 4784 bool has_sw_event = false; 4785 int num = 0, idx = 0; 4786 u64 cause_mask = 0; 4787 4788 /* Not support perf metrics */ 4789 if (is_metric_event(event)) 4790 return -EINVAL; 4791 4792 /* Not support freq mode */ 4793 if (event->attr.freq) 4794 return -EINVAL; 4795 4796 /* PDist is not supported */ 4797 if (event->attr.config2 && event->attr.precise_ip > 2) 4798 return -EINVAL; 4799 4800 /* The reload value cannot exceeds the max period */ 4801 if (event->attr.sample_period > x86_pmu.max_period) 4802 return -EINVAL; 4803 /* 4804 * The counter-constraints of each event cannot be finalized 4805 * unless the whole group is scanned. However, it's hard 4806 * to know whether the event is the last one of the group. 4807 * Recalculate the counter-constraints for each event when 4808 * adding a new event. 4809 * 4810 * The group is traversed twice, which may be optimized later. 4811 * In the first round, 4812 * - Find all events which do reload when other events 4813 * overflow and set the corresponding counter-constraints 4814 * - Add all events, which can cause other events reload, 4815 * in the cause_mask 4816 * - Error out if the number of events exceeds the HW limit 4817 * - The ACR events must be contiguous. 4818 * Error out if there are non-X86 events between ACR events. 4819 * This is not a HW limit, but a SW limit. 4820 * With the assumption, the intel_pmu_acr_late_setup() can 4821 * easily convert the event idx to counter idx without 4822 * traversing the whole event list. 4823 */ 4824 if (!is_x86_event(leader)) 4825 return -EINVAL; 4826 4827 if (leader->attr.config2) 4828 intel_pmu_set_acr_cntr_constr(leader, &cause_mask, &num); 4829 4830 if (leader->nr_siblings) { 4831 for_each_sibling_event(sibling, leader) { 4832 if (!is_x86_event(sibling)) { 4833 has_sw_event = true; 4834 continue; 4835 } 4836 if (!sibling->attr.config2) 4837 continue; 4838 if (has_sw_event) 4839 return -EINVAL; 4840 intel_pmu_set_acr_cntr_constr(sibling, &cause_mask, &num); 4841 } 4842 } 4843 if (leader != event && event->attr.config2) { 4844 if (has_sw_event) 4845 return -EINVAL; 4846 intel_pmu_set_acr_cntr_constr(event, &cause_mask, &num); 4847 } 4848 4849 if (hweight64(cause_mask) > hweight64(hybrid(pmu, acr_cause_mask64)) || 4850 num > hweight64(hybrid(event->pmu, acr_cntr_mask64))) 4851 return -EINVAL; 4852 /* 4853 * In the second round, apply the counter-constraints for 4854 * the events which can cause other events reload. 4855 */ 4856 intel_pmu_set_acr_caused_constr(leader, idx++, cause_mask); 4857 4858 if (leader->nr_siblings) { 4859 for_each_sibling_event(sibling, leader) { 4860 if (is_x86_event(sibling)) 4861 intel_pmu_set_acr_caused_constr(sibling, idx++, cause_mask); 4862 } 4863 } 4864 4865 if (leader != event) 4866 intel_pmu_set_acr_caused_constr(event, idx, cause_mask); 4867 4868 leader->hw.flags |= PERF_X86_EVENT_ACR; 4869 } 4870 4871 if ((event->attr.type == PERF_TYPE_HARDWARE) || 4872 (event->attr.type == PERF_TYPE_HW_CACHE)) 4873 return 0; 4874 4875 /* 4876 * Config Topdown slots and metric events 4877 * 4878 * The slots event on Fixed Counter 3 can support sampling, 4879 * which will be handled normally in x86_perf_event_update(). 4880 * 4881 * Metric events don't support sampling and require being paired 4882 * with a slots event as group leader. When the slots event 4883 * is used in a metrics group, it too cannot support sampling. 4884 */ 4885 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { 4886 /* The metrics_clear can only be set for the slots event */ 4887 if (event->attr.config1 && 4888 (!is_slots_event(event) || (event->attr.config1 & ~INTEL_TD_CFG_METRIC_CLEAR))) 4889 return -EINVAL; 4890 4891 if (event->attr.config2) 4892 return -EINVAL; 4893 4894 /* 4895 * The TopDown metrics events and slots event don't 4896 * support any filters. 4897 */ 4898 if (event->attr.config & X86_ALL_EVENT_FLAGS) 4899 return -EINVAL; 4900 4901 if (is_available_metric_event(event)) { 4902 struct perf_event *leader = event->group_leader; 4903 4904 /* The metric events don't support sampling. */ 4905 if (is_sampling_event(event)) 4906 return -EINVAL; 4907 4908 /* The metric events require a slots group leader. */ 4909 if (!is_slots_event(leader)) 4910 return -EINVAL; 4911 4912 /* 4913 * The leader/SLOTS must not be a sampling event for 4914 * metric use; hardware requires it starts at 0 when used 4915 * in conjunction with MSR_PERF_METRICS. 4916 */ 4917 if (is_sampling_event(leader)) 4918 return -EINVAL; 4919 4920 event->event_caps |= PERF_EV_CAP_SIBLING; 4921 /* 4922 * Only once we have a METRICs sibling do we 4923 * need TopDown magic. 4924 */ 4925 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 4926 event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 4927 } 4928 } 4929 4930 /* 4931 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 4932 * doesn't function quite right. As a work-around it needs to always be 4933 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 4934 * The actual count of this second event is irrelevant it just needs 4935 * to be active to make the first event function correctly. 4936 * 4937 * In a group, the auxiliary event must be in front of the load latency 4938 * event. The rule is to simplify the implementation of the check. 4939 * That's because perf cannot have a complete group at the moment. 4940 */ 4941 if (require_mem_loads_aux_event(event) && 4942 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 4943 is_mem_loads_event(event)) { 4944 struct perf_event *leader = event->group_leader; 4945 struct perf_event *sibling = NULL; 4946 4947 /* 4948 * When this memload event is also the first event (no group 4949 * exists yet), then there is no aux event before it. 4950 */ 4951 if (leader == event) 4952 return -ENODATA; 4953 4954 if (!is_mem_loads_aux_event(leader)) { 4955 for_each_sibling_event(sibling, leader) { 4956 if (is_mem_loads_aux_event(sibling)) 4957 break; 4958 } 4959 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 4960 return -ENODATA; 4961 } 4962 } 4963 4964 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 4965 return 0; 4966 4967 if (x86_pmu.version < 3) 4968 return -EINVAL; 4969 4970 ret = perf_allow_cpu(); 4971 if (ret) 4972 return ret; 4973 4974 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 4975 4976 return 0; 4977 } 4978 4979 /* 4980 * Currently, the only caller of this function is the atomic_switch_perf_msrs(). 4981 * The host perf context helps to prepare the values of the real hardware for 4982 * a set of msrs that need to be switched atomically in a vmx transaction. 4983 * 4984 * For example, the pseudocode needed to add a new msr should look like: 4985 * 4986 * arr[(*nr)++] = (struct perf_guest_switch_msr){ 4987 * .msr = the hardware msr address, 4988 * .host = the value the hardware has when it doesn't run a guest, 4989 * .guest = the value the hardware has when it runs a guest, 4990 * }; 4991 * 4992 * These values have nothing to do with the emulated values the guest sees 4993 * when it uses {RD,WR}MSR, which should be handled by the KVM context, 4994 * specifically in the intel_pmu_{get,set}_msr(). 4995 */ 4996 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) 4997 { 4998 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4999 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 5000 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data; 5001 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 5002 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; 5003 int global_ctrl, pebs_enable; 5004 5005 /* 5006 * In addition to obeying exclude_guest/exclude_host, remove bits being 5007 * used for PEBS when running a guest, because PEBS writes to virtual 5008 * addresses (not physical addresses). 5009 */ 5010 *nr = 0; 5011 global_ctrl = (*nr)++; 5012 arr[global_ctrl] = (struct perf_guest_switch_msr){ 5013 .msr = MSR_CORE_PERF_GLOBAL_CTRL, 5014 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask, 5015 .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask, 5016 }; 5017 5018 if (!x86_pmu.ds_pebs) 5019 return arr; 5020 5021 /* 5022 * If PMU counter has PEBS enabled it is not enough to 5023 * disable counter on a guest entry since PEBS memory 5024 * write can overshoot guest entry and corrupt guest 5025 * memory. Disabling PEBS solves the problem. 5026 * 5027 * Don't do this if the CPU already enforces it. 5028 */ 5029 if (x86_pmu.pebs_no_isolation) { 5030 arr[(*nr)++] = (struct perf_guest_switch_msr){ 5031 .msr = MSR_IA32_PEBS_ENABLE, 5032 .host = cpuc->pebs_enabled, 5033 .guest = 0, 5034 }; 5035 return arr; 5036 } 5037 5038 if (!kvm_pmu || !x86_pmu.pebs_ept) 5039 return arr; 5040 5041 arr[(*nr)++] = (struct perf_guest_switch_msr){ 5042 .msr = MSR_IA32_DS_AREA, 5043 .host = (unsigned long)cpuc->ds, 5044 .guest = kvm_pmu->ds_area, 5045 }; 5046 5047 if (x86_pmu.intel_cap.pebs_baseline) { 5048 arr[(*nr)++] = (struct perf_guest_switch_msr){ 5049 .msr = MSR_PEBS_DATA_CFG, 5050 .host = cpuc->active_pebs_data_cfg, 5051 .guest = kvm_pmu->pebs_data_cfg, 5052 }; 5053 } 5054 5055 pebs_enable = (*nr)++; 5056 arr[pebs_enable] = (struct perf_guest_switch_msr){ 5057 .msr = MSR_IA32_PEBS_ENABLE, 5058 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask, 5059 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask & kvm_pmu->pebs_enable, 5060 }; 5061 5062 if (arr[pebs_enable].host) { 5063 /* Disable guest PEBS if host PEBS is enabled. */ 5064 arr[pebs_enable].guest = 0; 5065 } else { 5066 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */ 5067 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask; 5068 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask; 5069 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ 5070 arr[global_ctrl].guest |= arr[pebs_enable].guest; 5071 } 5072 5073 return arr; 5074 } 5075 5076 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data) 5077 { 5078 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5079 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 5080 int idx; 5081 5082 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { 5083 struct perf_event *event = cpuc->events[idx]; 5084 5085 arr[idx].msr = x86_pmu_config_addr(idx); 5086 arr[idx].host = arr[idx].guest = 0; 5087 5088 if (!test_bit(idx, cpuc->active_mask)) 5089 continue; 5090 5091 arr[idx].host = arr[idx].guest = 5092 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 5093 5094 if (event->attr.exclude_host) 5095 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 5096 else if (event->attr.exclude_guest) 5097 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 5098 } 5099 5100 *nr = x86_pmu_max_num_counters(cpuc->pmu); 5101 return arr; 5102 } 5103 5104 static void core_pmu_enable_event(struct perf_event *event) 5105 { 5106 if (!event->attr.exclude_host) 5107 x86_pmu_enable_event(event); 5108 } 5109 5110 static void core_pmu_enable_all(int added) 5111 { 5112 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5113 int idx; 5114 5115 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { 5116 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 5117 5118 if (!test_bit(idx, cpuc->active_mask) || 5119 cpuc->events[idx]->attr.exclude_host) 5120 continue; 5121 5122 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 5123 } 5124 } 5125 5126 static int hsw_hw_config(struct perf_event *event) 5127 { 5128 int ret = intel_pmu_hw_config(event); 5129 5130 if (ret) 5131 return ret; 5132 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 5133 return 0; 5134 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 5135 5136 /* 5137 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 5138 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 5139 * this combination. 5140 */ 5141 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 5142 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 5143 event->attr.precise_ip > 0)) 5144 return -EOPNOTSUPP; 5145 5146 if (event_is_checkpointed(event)) { 5147 /* 5148 * Sampling of checkpointed events can cause situations where 5149 * the CPU constantly aborts because of a overflow, which is 5150 * then checkpointed back and ignored. Forbid checkpointing 5151 * for sampling. 5152 * 5153 * But still allow a long sampling period, so that perf stat 5154 * from KVM works. 5155 */ 5156 if (event->attr.sample_period > 0 && 5157 event->attr.sample_period < 0x7fffffff) 5158 return -EOPNOTSUPP; 5159 } 5160 return 0; 5161 } 5162 5163 static struct event_constraint counter0_constraint = 5164 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 5165 5166 static struct event_constraint counter1_constraint = 5167 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2); 5168 5169 static struct event_constraint counter0_1_constraint = 5170 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3); 5171 5172 static struct event_constraint counter2_constraint = 5173 EVENT_CONSTRAINT(0, 0x4, 0); 5174 5175 static struct event_constraint fixed0_constraint = 5176 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 5177 5178 static struct event_constraint fixed0_counter0_constraint = 5179 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 5180 5181 static struct event_constraint fixed0_counter0_1_constraint = 5182 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL); 5183 5184 static struct event_constraint counters_1_7_constraint = 5185 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL); 5186 5187 static struct event_constraint * 5188 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5189 struct perf_event *event) 5190 { 5191 struct event_constraint *c; 5192 5193 c = intel_get_event_constraints(cpuc, idx, event); 5194 5195 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 5196 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 5197 if (c->idxmsk64 & (1U << 2)) 5198 return &counter2_constraint; 5199 return &emptyconstraint; 5200 } 5201 5202 return c; 5203 } 5204 5205 static struct event_constraint * 5206 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5207 struct perf_event *event) 5208 { 5209 /* 5210 * Fixed counter 0 has less skid. 5211 * Force instruction:ppp in Fixed counter 0 5212 */ 5213 if ((event->attr.precise_ip == 3) && 5214 constraint_match(&fixed0_constraint, event->hw.config)) 5215 return &fixed0_constraint; 5216 5217 return hsw_get_event_constraints(cpuc, idx, event); 5218 } 5219 5220 static struct event_constraint * 5221 glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5222 struct perf_event *event) 5223 { 5224 struct event_constraint *c; 5225 5226 c = icl_get_event_constraints(cpuc, idx, event); 5227 5228 /* 5229 * The :ppp indicates the Precise Distribution (PDist) facility, which 5230 * is only supported on the GP counter 0. If a :ppp event which is not 5231 * available on the GP counter 0, error out. 5232 * Exception: Instruction PDIR is only available on the fixed counter 0. 5233 */ 5234 if ((event->attr.precise_ip == 3) && 5235 !constraint_match(&fixed0_constraint, event->hw.config)) { 5236 if (c->idxmsk64 & BIT_ULL(0)) 5237 return &counter0_constraint; 5238 5239 return &emptyconstraint; 5240 } 5241 5242 return c; 5243 } 5244 5245 static struct event_constraint * 5246 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5247 struct perf_event *event) 5248 { 5249 struct event_constraint *c; 5250 5251 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 5252 if (event->attr.precise_ip == 3) 5253 return &counter0_constraint; 5254 5255 c = intel_get_event_constraints(cpuc, idx, event); 5256 5257 return c; 5258 } 5259 5260 static struct event_constraint * 5261 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5262 struct perf_event *event) 5263 { 5264 struct event_constraint *c; 5265 5266 c = intel_get_event_constraints(cpuc, idx, event); 5267 5268 /* 5269 * :ppp means to do reduced skid PEBS, 5270 * which is available on PMC0 and fixed counter 0. 5271 */ 5272 if (event->attr.precise_ip == 3) { 5273 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 5274 if (constraint_match(&fixed0_constraint, event->hw.config)) 5275 return &fixed0_counter0_constraint; 5276 5277 return &counter0_constraint; 5278 } 5279 5280 return c; 5281 } 5282 5283 static bool allow_tsx_force_abort = true; 5284 5285 static struct event_constraint * 5286 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5287 struct perf_event *event) 5288 { 5289 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 5290 5291 /* 5292 * Without TFA we must not use PMC3. 5293 */ 5294 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 5295 c = dyn_constraint(cpuc, c, idx); 5296 c->idxmsk64 &= ~(1ULL << 3); 5297 c->weight--; 5298 } 5299 5300 return c; 5301 } 5302 5303 static struct event_constraint * 5304 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5305 struct perf_event *event) 5306 { 5307 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5308 5309 if (pmu->pmu_type == hybrid_big) 5310 return glc_get_event_constraints(cpuc, idx, event); 5311 else if (pmu->pmu_type == hybrid_small) 5312 return tnt_get_event_constraints(cpuc, idx, event); 5313 5314 WARN_ON(1); 5315 return &emptyconstraint; 5316 } 5317 5318 static struct event_constraint * 5319 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5320 struct perf_event *event) 5321 { 5322 struct event_constraint *c; 5323 5324 c = intel_get_event_constraints(cpuc, idx, event); 5325 5326 /* 5327 * The :ppp indicates the Precise Distribution (PDist) facility, which 5328 * is only supported on the GP counter 0 & 1 and Fixed counter 0. 5329 * If a :ppp event which is not available on the above eligible counters, 5330 * error out. 5331 */ 5332 if (event->attr.precise_ip == 3) { 5333 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */ 5334 if (constraint_match(&fixed0_constraint, event->hw.config)) { 5335 /* The fixed counter 0 doesn't support LBR event logging. */ 5336 if (branch_sample_counters(event)) 5337 return &counter0_1_constraint; 5338 else 5339 return &fixed0_counter0_1_constraint; 5340 } 5341 5342 switch (c->idxmsk64 & 0x3ull) { 5343 case 0x1: 5344 return &counter0_constraint; 5345 case 0x2: 5346 return &counter1_constraint; 5347 case 0x3: 5348 return &counter0_1_constraint; 5349 } 5350 return &emptyconstraint; 5351 } 5352 5353 return c; 5354 } 5355 5356 static struct event_constraint * 5357 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5358 struct perf_event *event) 5359 { 5360 struct event_constraint *c; 5361 5362 c = glc_get_event_constraints(cpuc, idx, event); 5363 5364 /* The Retire Latency is not supported by the fixed counter 0. */ 5365 if (event->attr.precise_ip && 5366 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) && 5367 constraint_match(&fixed0_constraint, event->hw.config)) { 5368 /* 5369 * The Instruction PDIR is only available 5370 * on the fixed counter 0. Error out for this case. 5371 */ 5372 if (event->attr.precise_ip == 3) 5373 return &emptyconstraint; 5374 return &counters_1_7_constraint; 5375 } 5376 5377 return c; 5378 } 5379 5380 static struct event_constraint * 5381 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5382 struct perf_event *event) 5383 { 5384 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5385 5386 if (pmu->pmu_type == hybrid_big) 5387 return rwc_get_event_constraints(cpuc, idx, event); 5388 if (pmu->pmu_type == hybrid_small) 5389 return cmt_get_event_constraints(cpuc, idx, event); 5390 5391 WARN_ON(1); 5392 return &emptyconstraint; 5393 } 5394 5395 static int adl_hw_config(struct perf_event *event) 5396 { 5397 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5398 5399 if (pmu->pmu_type == hybrid_big) 5400 return hsw_hw_config(event); 5401 else if (pmu->pmu_type == hybrid_small) 5402 return intel_pmu_hw_config(event); 5403 5404 WARN_ON(1); 5405 return -EOPNOTSUPP; 5406 } 5407 5408 static enum intel_cpu_type adl_get_hybrid_cpu_type(void) 5409 { 5410 return INTEL_CPU_TYPE_CORE; 5411 } 5412 5413 static inline bool erratum_hsw11(struct perf_event *event) 5414 { 5415 return (event->hw.config & INTEL_ARCH_EVENT_MASK) == 5416 X86_CONFIG(.event=0xc0, .umask=0x01); 5417 } 5418 5419 static struct event_constraint * 5420 arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5421 struct perf_event *event) 5422 { 5423 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5424 5425 if (pmu->pmu_type == hybrid_tiny) 5426 return cmt_get_event_constraints(cpuc, idx, event); 5427 5428 return mtl_get_event_constraints(cpuc, idx, event); 5429 } 5430 5431 static int arl_h_hw_config(struct perf_event *event) 5432 { 5433 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5434 5435 if (pmu->pmu_type == hybrid_tiny) 5436 return intel_pmu_hw_config(event); 5437 5438 return adl_hw_config(event); 5439 } 5440 5441 /* 5442 * The HSW11 requires a period larger than 100 which is the same as the BDM11. 5443 * A minimum period of 128 is enforced as well for the INST_RETIRED.ALL. 5444 * 5445 * The message 'interrupt took too long' can be observed on any counter which 5446 * was armed with a period < 32 and two events expired in the same NMI. 5447 * A minimum period of 32 is enforced for the rest of the events. 5448 */ 5449 static void hsw_limit_period(struct perf_event *event, s64 *left) 5450 { 5451 *left = max(*left, erratum_hsw11(event) ? 128 : 32); 5452 } 5453 5454 /* 5455 * Broadwell: 5456 * 5457 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 5458 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 5459 * the two to enforce a minimum period of 128 (the smallest value that has bits 5460 * 0-5 cleared and >= 100). 5461 * 5462 * Because of how the code in x86_perf_event_set_period() works, the truncation 5463 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 5464 * to make up for the 'lost' events due to carrying the 'error' in period_left. 5465 * 5466 * Therefore the effective (average) period matches the requested period, 5467 * despite coarser hardware granularity. 5468 */ 5469 static void bdw_limit_period(struct perf_event *event, s64 *left) 5470 { 5471 if (erratum_hsw11(event)) { 5472 if (*left < 128) 5473 *left = 128; 5474 *left &= ~0x3fULL; 5475 } 5476 } 5477 5478 static void nhm_limit_period(struct perf_event *event, s64 *left) 5479 { 5480 *left = max(*left, 32LL); 5481 } 5482 5483 static void glc_limit_period(struct perf_event *event, s64 *left) 5484 { 5485 if (event->attr.precise_ip == 3) 5486 *left = max(*left, 128LL); 5487 } 5488 5489 PMU_FORMAT_ATTR(event, "config:0-7" ); 5490 PMU_FORMAT_ATTR(umask, "config:8-15" ); 5491 PMU_FORMAT_ATTR(edge, "config:18" ); 5492 PMU_FORMAT_ATTR(pc, "config:19" ); 5493 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 5494 PMU_FORMAT_ATTR(inv, "config:23" ); 5495 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 5496 PMU_FORMAT_ATTR(in_tx, "config:32" ); 5497 PMU_FORMAT_ATTR(in_tx_cp, "config:33" ); 5498 PMU_FORMAT_ATTR(eq, "config:36" ); /* v6 + */ 5499 5500 PMU_FORMAT_ATTR(metrics_clear, "config1:0"); /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */ 5501 5502 static ssize_t umask2_show(struct device *dev, 5503 struct device_attribute *attr, 5504 char *page) 5505 { 5506 u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2; 5507 5508 if (mask == ARCH_PERFMON_EVENTSEL_UMASK2) 5509 return sprintf(page, "config:8-15,40-47\n"); 5510 5511 /* Roll back to the old format if umask2 is not supported. */ 5512 return sprintf(page, "config:8-15\n"); 5513 } 5514 5515 static struct device_attribute format_attr_umask2 = 5516 __ATTR(umask, 0444, umask2_show, NULL); 5517 5518 static struct attribute *format_evtsel_ext_attrs[] = { 5519 &format_attr_umask2.attr, 5520 &format_attr_eq.attr, 5521 &format_attr_metrics_clear.attr, 5522 NULL 5523 }; 5524 5525 static umode_t 5526 evtsel_ext_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5527 { 5528 struct device *dev = kobj_to_dev(kobj); 5529 u64 mask; 5530 5531 /* 5532 * The umask and umask2 have different formats but share the 5533 * same attr name. In update mode, the previous value of the 5534 * umask is unconditionally removed before is_visible. If 5535 * umask2 format is not enumerated, it's impossible to roll 5536 * back to the old format. 5537 * Does the check in umask2_show rather than is_visible. 5538 */ 5539 if (i == 0) 5540 return attr->mode; 5541 5542 mask = hybrid(dev_get_drvdata(dev), config_mask); 5543 if (i == 1) 5544 return (mask & ARCH_PERFMON_EVENTSEL_EQ) ? attr->mode : 0; 5545 5546 /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */ 5547 if (i == 2) { 5548 union perf_capabilities intel_cap = hybrid(dev_get_drvdata(dev), intel_cap); 5549 5550 return intel_cap.rdpmc_metrics_clear ? attr->mode : 0; 5551 } 5552 5553 return 0; 5554 } 5555 5556 static struct attribute *intel_arch_formats_attr[] = { 5557 &format_attr_event.attr, 5558 &format_attr_umask.attr, 5559 &format_attr_edge.attr, 5560 &format_attr_pc.attr, 5561 &format_attr_inv.attr, 5562 &format_attr_cmask.attr, 5563 NULL, 5564 }; 5565 5566 ssize_t intel_event_sysfs_show(char *page, u64 config) 5567 { 5568 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 5569 5570 return x86_event_sysfs_show(page, config, event); 5571 } 5572 5573 static struct intel_shared_regs *allocate_shared_regs(int cpu) 5574 { 5575 struct intel_shared_regs *regs; 5576 int i; 5577 5578 regs = kzalloc_node(sizeof(struct intel_shared_regs), 5579 GFP_KERNEL, cpu_to_node(cpu)); 5580 if (regs) { 5581 /* 5582 * initialize the locks to keep lockdep happy 5583 */ 5584 for (i = 0; i < EXTRA_REG_MAX; i++) 5585 raw_spin_lock_init(®s->regs[i].lock); 5586 5587 regs->core_id = -1; 5588 } 5589 return regs; 5590 } 5591 5592 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 5593 { 5594 struct intel_excl_cntrs *c; 5595 5596 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 5597 GFP_KERNEL, cpu_to_node(cpu)); 5598 if (c) { 5599 raw_spin_lock_init(&c->lock); 5600 c->core_id = -1; 5601 } 5602 return c; 5603 } 5604 5605 5606 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 5607 { 5608 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 5609 5610 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 5611 cpuc->shared_regs = allocate_shared_regs(cpu); 5612 if (!cpuc->shared_regs) 5613 goto err; 5614 } 5615 5616 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_DYN_CONSTRAINT)) { 5617 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 5618 5619 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 5620 if (!cpuc->constraint_list) 5621 goto err_shared_regs; 5622 } 5623 5624 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 5625 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 5626 if (!cpuc->excl_cntrs) 5627 goto err_constraint_list; 5628 5629 cpuc->excl_thread_id = 0; 5630 } 5631 5632 return 0; 5633 5634 err_constraint_list: 5635 kfree(cpuc->constraint_list); 5636 cpuc->constraint_list = NULL; 5637 5638 err_shared_regs: 5639 kfree(cpuc->shared_regs); 5640 cpuc->shared_regs = NULL; 5641 5642 err: 5643 return -ENOMEM; 5644 } 5645 5646 static int intel_pmu_cpu_prepare(int cpu) 5647 { 5648 int ret; 5649 5650 ret = intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 5651 if (ret) 5652 return ret; 5653 5654 return alloc_arch_pebs_buf_on_cpu(cpu); 5655 } 5656 5657 static void flip_smm_bit(void *data) 5658 { 5659 unsigned long set = *(unsigned long *)data; 5660 5661 if (set > 0) { 5662 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 5663 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 5664 } else { 5665 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 5666 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 5667 } 5668 } 5669 5670 static void intel_pmu_check_counters_mask(u64 *cntr_mask, 5671 u64 *fixed_cntr_mask, 5672 u64 *intel_ctrl) 5673 { 5674 unsigned int bit; 5675 5676 bit = fls64(*cntr_mask); 5677 if (bit > INTEL_PMC_MAX_GENERIC) { 5678 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5679 bit, INTEL_PMC_MAX_GENERIC); 5680 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); 5681 } 5682 *intel_ctrl = *cntr_mask; 5683 5684 bit = fls64(*fixed_cntr_mask); 5685 if (bit > INTEL_PMC_MAX_FIXED) { 5686 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5687 bit, INTEL_PMC_MAX_FIXED); 5688 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0); 5689 } 5690 5691 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED; 5692 } 5693 5694 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 5695 u64 cntr_mask, 5696 u64 fixed_cntr_mask, 5697 u64 intel_ctrl); 5698 5699 enum dyn_constr_type { 5700 DYN_CONSTR_NONE, 5701 DYN_CONSTR_BR_CNTR, 5702 DYN_CONSTR_ACR_CNTR, 5703 DYN_CONSTR_ACR_CAUSE, 5704 DYN_CONSTR_PEBS, 5705 DYN_CONSTR_PDIST, 5706 5707 DYN_CONSTR_MAX, 5708 }; 5709 5710 static const char * const dyn_constr_type_name[] = { 5711 [DYN_CONSTR_NONE] = "a normal event", 5712 [DYN_CONSTR_BR_CNTR] = "a branch counter logging event", 5713 [DYN_CONSTR_ACR_CNTR] = "an auto-counter reload event", 5714 [DYN_CONSTR_ACR_CAUSE] = "an auto-counter reload cause event", 5715 [DYN_CONSTR_PEBS] = "a PEBS event", 5716 [DYN_CONSTR_PDIST] = "a PEBS PDIST event", 5717 }; 5718 5719 static void __intel_pmu_check_dyn_constr(struct event_constraint *constr, 5720 enum dyn_constr_type type, u64 mask) 5721 { 5722 struct event_constraint *c1, *c2; 5723 int new_weight, check_weight; 5724 u64 new_mask, check_mask; 5725 5726 for_each_event_constraint(c1, constr) { 5727 new_mask = c1->idxmsk64 & mask; 5728 new_weight = hweight64(new_mask); 5729 5730 /* ignore topdown perf metrics event */ 5731 if (c1->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) 5732 continue; 5733 5734 if (!new_weight && fls64(c1->idxmsk64) < INTEL_PMC_IDX_FIXED) { 5735 pr_info("The event 0x%llx is not supported as %s.\n", 5736 c1->code, dyn_constr_type_name[type]); 5737 } 5738 5739 if (new_weight <= 1) 5740 continue; 5741 5742 for_each_event_constraint(c2, c1 + 1) { 5743 bool check_fail = false; 5744 5745 check_mask = c2->idxmsk64 & mask; 5746 check_weight = hweight64(check_mask); 5747 5748 if (c2->idxmsk64 & INTEL_PMC_MSK_TOPDOWN || 5749 !check_weight) 5750 continue; 5751 5752 /* The same constraints or no overlap */ 5753 if (new_mask == check_mask || 5754 (new_mask ^ check_mask) == (new_mask | check_mask)) 5755 continue; 5756 5757 /* 5758 * A scheduler issue may be triggered in the following cases. 5759 * - Two overlap constraints have the same weight. 5760 * E.g., A constraints: 0x3, B constraints: 0x6 5761 * event counter failure case 5762 * B PMC[2:1] 1 5763 * A PMC[1:0] 0 5764 * A PMC[1:0] FAIL 5765 * - Two overlap constraints have different weight. 5766 * The constraint has a low weight, but has high last bit. 5767 * E.g., A constraints: 0x7, B constraints: 0xC 5768 * event counter failure case 5769 * B PMC[3:2] 2 5770 * A PMC[2:0] 0 5771 * A PMC[2:0] 1 5772 * A PMC[2:0] FAIL 5773 */ 5774 if (new_weight == check_weight) { 5775 check_fail = true; 5776 } else if (new_weight < check_weight) { 5777 if ((new_mask | check_mask) != check_mask && 5778 fls64(new_mask) > fls64(check_mask)) 5779 check_fail = true; 5780 } else { 5781 if ((new_mask | check_mask) != new_mask && 5782 fls64(new_mask) < fls64(check_mask)) 5783 check_fail = true; 5784 } 5785 5786 if (check_fail) { 5787 pr_warn("The two events 0x%llx and 0x%llx may not be " 5788 "fully scheduled under some circumstances as " 5789 "%s.\n", 5790 c1->code, c2->code, dyn_constr_type_name[type]); 5791 } 5792 } 5793 } 5794 } 5795 5796 static void intel_pmu_check_dyn_constr(struct pmu *pmu, 5797 struct event_constraint *constr, 5798 u64 cntr_mask) 5799 { 5800 u64 gp_mask = GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); 5801 enum dyn_constr_type i; 5802 u64 mask; 5803 5804 for (i = DYN_CONSTR_NONE; i < DYN_CONSTR_MAX; i++) { 5805 mask = 0; 5806 switch (i) { 5807 case DYN_CONSTR_NONE: 5808 mask = cntr_mask; 5809 break; 5810 case DYN_CONSTR_BR_CNTR: 5811 if (x86_pmu.flags & PMU_FL_BR_CNTR) 5812 mask = x86_pmu.lbr_counters; 5813 break; 5814 case DYN_CONSTR_ACR_CNTR: 5815 mask = hybrid(pmu, acr_cntr_mask64) & gp_mask; 5816 break; 5817 case DYN_CONSTR_ACR_CAUSE: 5818 if (hybrid(pmu, acr_cntr_mask64) == 5819 hybrid(pmu, acr_cause_mask64)) 5820 continue; 5821 mask = hybrid(pmu, acr_cause_mask64) & gp_mask; 5822 break; 5823 case DYN_CONSTR_PEBS: 5824 if (x86_pmu.arch_pebs) { 5825 mask = hybrid(pmu, arch_pebs_cap).counters & 5826 gp_mask; 5827 } 5828 break; 5829 case DYN_CONSTR_PDIST: 5830 if (x86_pmu.arch_pebs) { 5831 mask = hybrid(pmu, arch_pebs_cap).pdists & 5832 gp_mask; 5833 } 5834 break; 5835 default: 5836 pr_warn("Unsupported dynamic constraint type %d\n", i); 5837 } 5838 5839 if (mask) 5840 __intel_pmu_check_dyn_constr(constr, i, mask); 5841 } 5842 } 5843 5844 static void intel_pmu_check_event_constraints_all(struct pmu *pmu) 5845 { 5846 struct event_constraint *event_constraints = hybrid(pmu, event_constraints); 5847 struct event_constraint *pebs_constraints = hybrid(pmu, pebs_constraints); 5848 u64 cntr_mask = hybrid(pmu, cntr_mask64); 5849 u64 fixed_cntr_mask = hybrid(pmu, fixed_cntr_mask64); 5850 u64 intel_ctrl = hybrid(pmu, intel_ctrl); 5851 5852 intel_pmu_check_event_constraints(event_constraints, cntr_mask, 5853 fixed_cntr_mask, intel_ctrl); 5854 5855 if (event_constraints) 5856 intel_pmu_check_dyn_constr(pmu, event_constraints, cntr_mask); 5857 5858 if (pebs_constraints) 5859 intel_pmu_check_dyn_constr(pmu, pebs_constraints, cntr_mask); 5860 } 5861 5862 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs); 5863 5864 static inline bool intel_pmu_broken_perf_cap(void) 5865 { 5866 /* The Perf Metric (Bit 15) is always cleared */ 5867 if (boot_cpu_data.x86_vfm == INTEL_METEORLAKE || 5868 boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L) 5869 return true; 5870 5871 return false; 5872 } 5873 5874 static inline void __intel_update_pmu_caps(struct pmu *pmu) 5875 { 5876 struct pmu *dest_pmu = pmu ? pmu : x86_get_pmu(smp_processor_id()); 5877 5878 if (hybrid(pmu, arch_pebs_cap).caps & ARCH_PEBS_VECR_XMM) 5879 dest_pmu->capabilities |= PERF_PMU_CAP_EXTENDED_REGS; 5880 } 5881 5882 static inline void __intel_update_large_pebs_flags(struct pmu *pmu) 5883 { 5884 u64 caps = hybrid(pmu, arch_pebs_cap).caps; 5885 5886 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME; 5887 if (caps & ARCH_PEBS_LBR) 5888 x86_pmu.large_pebs_flags |= PERF_SAMPLE_BRANCH_STACK; 5889 if (caps & ARCH_PEBS_CNTR_MASK) 5890 x86_pmu.large_pebs_flags |= PERF_SAMPLE_READ; 5891 5892 if (!(caps & ARCH_PEBS_AUX)) 5893 x86_pmu.large_pebs_flags &= ~PERF_SAMPLE_DATA_SRC; 5894 if (!(caps & ARCH_PEBS_GPR)) { 5895 x86_pmu.large_pebs_flags &= 5896 ~(PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER); 5897 } 5898 } 5899 5900 #define counter_mask(_gp, _fixed) ((_gp) | ((u64)(_fixed) << INTEL_PMC_IDX_FIXED)) 5901 5902 static void update_pmu_cap(struct pmu *pmu) 5903 { 5904 unsigned int eax, ebx, ecx, edx; 5905 union cpuid35_eax eax_0; 5906 union cpuid35_ebx ebx_0; 5907 u64 cntrs_mask = 0; 5908 u64 pebs_mask = 0; 5909 u64 pdists_mask = 0; 5910 5911 cpuid(ARCH_PERFMON_EXT_LEAF, &eax_0.full, &ebx_0.full, &ecx, &edx); 5912 5913 if (ebx_0.split.umask2) 5914 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_UMASK2; 5915 if (ebx_0.split.eq) 5916 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_EQ; 5917 if (ebx_0.split.rdpmc_user_disable) 5918 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE; 5919 5920 if (eax_0.split.cntr_subleaf) { 5921 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF, 5922 &eax, &ebx, &ecx, &edx); 5923 hybrid(pmu, cntr_mask64) = eax; 5924 hybrid(pmu, fixed_cntr_mask64) = ebx; 5925 cntrs_mask = counter_mask(eax, ebx); 5926 } 5927 5928 if (eax_0.split.acr_subleaf) { 5929 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_ACR_LEAF, 5930 &eax, &ebx, &ecx, &edx); 5931 /* The mask of the counters which can be reloaded */ 5932 hybrid(pmu, acr_cntr_mask64) = counter_mask(eax, ebx); 5933 /* The mask of the counters which can cause a reload of reloadable counters */ 5934 hybrid(pmu, acr_cause_mask64) = counter_mask(ecx, edx); 5935 } 5936 5937 /* Bits[5:4] should be set simultaneously if arch-PEBS is supported */ 5938 if (eax_0.split.pebs_caps_subleaf && eax_0.split.pebs_cnts_subleaf) { 5939 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_CAP_LEAF, 5940 &eax, &ebx, &ecx, &edx); 5941 hybrid(pmu, arch_pebs_cap).caps = (u64)ebx << 32; 5942 5943 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_COUNTER_LEAF, 5944 &eax, &ebx, &ecx, &edx); 5945 pebs_mask = counter_mask(eax, ecx); 5946 pdists_mask = counter_mask(ebx, edx); 5947 hybrid(pmu, arch_pebs_cap).counters = pebs_mask; 5948 hybrid(pmu, arch_pebs_cap).pdists = pdists_mask; 5949 5950 if (WARN_ON((pebs_mask | pdists_mask) & ~cntrs_mask)) { 5951 x86_pmu.arch_pebs = 0; 5952 } else { 5953 __intel_update_pmu_caps(pmu); 5954 __intel_update_large_pebs_flags(pmu); 5955 } 5956 } else { 5957 WARN_ON(x86_pmu.arch_pebs == 1); 5958 x86_pmu.arch_pebs = 0; 5959 } 5960 5961 if (!intel_pmu_broken_perf_cap()) { 5962 /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */ 5963 rdmsrq(MSR_IA32_PERF_CAPABILITIES, hybrid(pmu, intel_cap).capabilities); 5964 } 5965 } 5966 5967 static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu) 5968 { 5969 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64, 5970 &pmu->intel_ctrl); 5971 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 5972 pmu->unconstrained = (struct event_constraint) 5973 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 5974 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 5975 5976 if (pmu->intel_cap.perf_metrics) 5977 pmu->intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS; 5978 else 5979 pmu->intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS; 5980 5981 pmu->pmu.capabilities |= PERF_PMU_CAP_MEDIATED_VPMU; 5982 5983 intel_pmu_check_event_constraints_all(&pmu->pmu); 5984 5985 intel_pmu_check_extra_regs(pmu->extra_regs); 5986 } 5987 5988 static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void) 5989 { 5990 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 5991 enum intel_cpu_type cpu_type = c->topo.intel_type; 5992 int i; 5993 5994 /* 5995 * This is running on a CPU model that is known to have hybrid 5996 * configurations. But the CPU told us it is not hybrid, shame 5997 * on it. There should be a fixup function provided for these 5998 * troublesome CPUs (->get_hybrid_cpu_type). 5999 */ 6000 if (cpu_type == INTEL_CPU_TYPE_UNKNOWN) { 6001 if (x86_pmu.get_hybrid_cpu_type) 6002 cpu_type = x86_pmu.get_hybrid_cpu_type(); 6003 else 6004 return NULL; 6005 } 6006 6007 /* 6008 * This essentially just maps between the 'hybrid_cpu_type' 6009 * and 'hybrid_pmu_type' enums except for ARL-H processor 6010 * which needs to compare atom uarch native id since ARL-H 6011 * contains two different atom uarchs. 6012 */ 6013 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 6014 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type; 6015 u32 native_id; 6016 6017 if (cpu_type == INTEL_CPU_TYPE_CORE && pmu_type == hybrid_big) 6018 return &x86_pmu.hybrid_pmu[i]; 6019 if (cpu_type == INTEL_CPU_TYPE_ATOM) { 6020 if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small) 6021 return &x86_pmu.hybrid_pmu[i]; 6022 6023 native_id = c->topo.intel_native_model_id; 6024 if (native_id == INTEL_ATOM_SKT_NATIVE_ID && pmu_type == hybrid_small) 6025 return &x86_pmu.hybrid_pmu[i]; 6026 if (native_id == INTEL_ATOM_CMT_NATIVE_ID && pmu_type == hybrid_tiny) 6027 return &x86_pmu.hybrid_pmu[i]; 6028 } 6029 } 6030 6031 return NULL; 6032 } 6033 6034 static bool init_hybrid_pmu(int cpu) 6035 { 6036 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 6037 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu(); 6038 6039 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { 6040 cpuc->pmu = NULL; 6041 return false; 6042 } 6043 6044 /* Only check and dump the PMU information for the first CPU */ 6045 if (!cpumask_empty(&pmu->supported_cpus)) 6046 goto end; 6047 6048 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) 6049 update_pmu_cap(&pmu->pmu); 6050 6051 intel_pmu_check_hybrid_pmus(pmu); 6052 6053 if (!check_hw_exists(&pmu->pmu, pmu->cntr_mask, pmu->fixed_cntr_mask)) 6054 return false; 6055 6056 pr_info("%s PMU driver: ", pmu->name); 6057 6058 pr_cont("\n"); 6059 6060 x86_pmu_show_pmu_cap(&pmu->pmu); 6061 6062 end: 6063 cpumask_set_cpu(cpu, &pmu->supported_cpus); 6064 cpuc->pmu = &pmu->pmu; 6065 6066 return true; 6067 } 6068 6069 static void intel_pmu_cpu_starting(int cpu) 6070 { 6071 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 6072 int core_id = topology_core_id(cpu); 6073 int i; 6074 6075 if (is_hybrid() && !init_hybrid_pmu(cpu)) 6076 return; 6077 6078 init_debug_store_on_cpu(cpu); 6079 init_arch_pebs_on_cpu(cpu); 6080 /* 6081 * Deal with CPUs that don't clear their LBRs on power-up, and that may 6082 * even boot with LBRs enabled. 6083 */ 6084 if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr) 6085 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT); 6086 intel_pmu_lbr_reset(); 6087 6088 cpuc->lbr_sel = NULL; 6089 6090 if (x86_pmu.flags & PMU_FL_TFA) { 6091 WARN_ON_ONCE(cpuc->tfa_shadow); 6092 cpuc->tfa_shadow = ~0ULL; 6093 intel_set_tfa(cpuc, false); 6094 } 6095 6096 if (x86_pmu.version > 1) 6097 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 6098 6099 /* 6100 * Disable perf metrics if any added CPU doesn't support it. 6101 * 6102 * Turn off the check for a hybrid architecture, because the 6103 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate 6104 * the architecture features. The perf metrics is a model-specific 6105 * feature for now. The corresponding bit should always be 0 on 6106 * a hybrid platform, e.g., Alder Lake. 6107 */ 6108 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 6109 union perf_capabilities perf_cap; 6110 6111 rdmsrq(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 6112 if (!perf_cap.perf_metrics) { 6113 x86_pmu.intel_cap.perf_metrics = 0; 6114 x86_pmu.intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS; 6115 } 6116 } 6117 6118 __intel_update_pmu_caps(cpuc->pmu); 6119 6120 if (!cpuc->shared_regs) 6121 return; 6122 6123 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 6124 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 6125 struct intel_shared_regs *pc; 6126 6127 pc = per_cpu(cpu_hw_events, i).shared_regs; 6128 if (pc && pc->core_id == core_id) { 6129 cpuc->kfree_on_online[0] = cpuc->shared_regs; 6130 cpuc->shared_regs = pc; 6131 break; 6132 } 6133 } 6134 cpuc->shared_regs->core_id = core_id; 6135 cpuc->shared_regs->refcnt++; 6136 } 6137 6138 if (x86_pmu.lbr_sel_map) 6139 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 6140 6141 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 6142 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 6143 struct cpu_hw_events *sibling; 6144 struct intel_excl_cntrs *c; 6145 6146 sibling = &per_cpu(cpu_hw_events, i); 6147 c = sibling->excl_cntrs; 6148 if (c && c->core_id == core_id) { 6149 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 6150 cpuc->excl_cntrs = c; 6151 if (!sibling->excl_thread_id) 6152 cpuc->excl_thread_id = 1; 6153 break; 6154 } 6155 } 6156 cpuc->excl_cntrs->core_id = core_id; 6157 cpuc->excl_cntrs->refcnt++; 6158 } 6159 } 6160 6161 static void free_excl_cntrs(struct cpu_hw_events *cpuc) 6162 { 6163 struct intel_excl_cntrs *c; 6164 6165 c = cpuc->excl_cntrs; 6166 if (c) { 6167 if (c->core_id == -1 || --c->refcnt == 0) 6168 kfree(c); 6169 cpuc->excl_cntrs = NULL; 6170 } 6171 6172 kfree(cpuc->constraint_list); 6173 cpuc->constraint_list = NULL; 6174 } 6175 6176 static void intel_pmu_cpu_dying(int cpu) 6177 { 6178 fini_debug_store_on_cpu(cpu); 6179 fini_arch_pebs_on_cpu(cpu); 6180 } 6181 6182 void intel_cpuc_finish(struct cpu_hw_events *cpuc) 6183 { 6184 struct intel_shared_regs *pc; 6185 6186 pc = cpuc->shared_regs; 6187 if (pc) { 6188 if (pc->core_id == -1 || --pc->refcnt == 0) 6189 kfree(pc); 6190 cpuc->shared_regs = NULL; 6191 } 6192 6193 free_excl_cntrs(cpuc); 6194 } 6195 6196 static void intel_pmu_cpu_dead(int cpu) 6197 { 6198 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 6199 6200 release_arch_pebs_buf_on_cpu(cpu); 6201 intel_cpuc_finish(cpuc); 6202 6203 if (is_hybrid() && cpuc->pmu) 6204 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); 6205 } 6206 6207 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, 6208 struct task_struct *task, bool sched_in) 6209 { 6210 intel_pmu_pebs_sched_task(pmu_ctx, sched_in); 6211 intel_pmu_lbr_sched_task(pmu_ctx, task, sched_in); 6212 } 6213 6214 static int intel_pmu_check_period(struct perf_event *event, u64 value) 6215 { 6216 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 6217 } 6218 6219 static void intel_aux_output_init(void) 6220 { 6221 /* Refer also intel_pmu_aux_output_match() */ 6222 if (x86_pmu.intel_cap.pebs_output_pt_available) 6223 x86_pmu.assign = intel_pmu_assign_event; 6224 } 6225 6226 static int intel_pmu_aux_output_match(struct perf_event *event) 6227 { 6228 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */ 6229 if (!x86_pmu.intel_cap.pebs_output_pt_available) 6230 return 0; 6231 6232 return is_intel_pt_event(event); 6233 } 6234 6235 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret) 6236 { 6237 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu); 6238 6239 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus); 6240 } 6241 6242 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 6243 6244 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 6245 6246 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 6247 6248 PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63"); 6249 6250 static struct attribute *intel_arch3_formats_attr[] = { 6251 &format_attr_event.attr, 6252 &format_attr_umask.attr, 6253 &format_attr_edge.attr, 6254 &format_attr_pc.attr, 6255 &format_attr_any.attr, 6256 &format_attr_inv.attr, 6257 &format_attr_cmask.attr, 6258 NULL, 6259 }; 6260 6261 static struct attribute *hsw_format_attr[] = { 6262 &format_attr_in_tx.attr, 6263 &format_attr_in_tx_cp.attr, 6264 &format_attr_offcore_rsp.attr, 6265 &format_attr_ldlat.attr, 6266 NULL 6267 }; 6268 6269 static struct attribute *nhm_format_attr[] = { 6270 &format_attr_offcore_rsp.attr, 6271 &format_attr_ldlat.attr, 6272 NULL 6273 }; 6274 6275 static struct attribute *slm_format_attr[] = { 6276 &format_attr_offcore_rsp.attr, 6277 NULL 6278 }; 6279 6280 static struct attribute *cmt_format_attr[] = { 6281 &format_attr_offcore_rsp.attr, 6282 &format_attr_ldlat.attr, 6283 &format_attr_snoop_rsp.attr, 6284 NULL 6285 }; 6286 6287 static struct attribute *skl_format_attr[] = { 6288 &format_attr_frontend.attr, 6289 NULL, 6290 }; 6291 6292 static __initconst const struct x86_pmu core_pmu = { 6293 .name = "core", 6294 .handle_irq = x86_pmu_handle_irq, 6295 .disable_all = x86_pmu_disable_all, 6296 .enable_all = core_pmu_enable_all, 6297 .enable = core_pmu_enable_event, 6298 .disable = x86_pmu_disable_event, 6299 .hw_config = core_pmu_hw_config, 6300 .schedule_events = x86_schedule_events, 6301 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 6302 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 6303 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0, 6304 .event_map = intel_pmu_event_map, 6305 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 6306 .apic = 1, 6307 .large_pebs_flags = LARGE_PEBS_FLAGS, 6308 6309 /* 6310 * Intel PMCs cannot be accessed sanely above 32-bit width, 6311 * so we install an artificial 1<<31 period regardless of 6312 * the generic event period: 6313 */ 6314 .max_period = (1ULL<<31) - 1, 6315 .get_event_constraints = intel_get_event_constraints, 6316 .put_event_constraints = intel_put_event_constraints, 6317 .event_constraints = intel_core_event_constraints, 6318 .guest_get_msrs = core_guest_get_msrs, 6319 .format_attrs = intel_arch_formats_attr, 6320 .events_sysfs_show = intel_event_sysfs_show, 6321 6322 /* 6323 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 6324 * together with PMU version 1 and thus be using core_pmu with 6325 * shared_regs. We need following callbacks here to allocate 6326 * it properly. 6327 */ 6328 .cpu_prepare = intel_pmu_cpu_prepare, 6329 .cpu_starting = intel_pmu_cpu_starting, 6330 .cpu_dying = intel_pmu_cpu_dying, 6331 .cpu_dead = intel_pmu_cpu_dead, 6332 6333 .check_period = intel_pmu_check_period, 6334 6335 .lbr_reset = intel_pmu_lbr_reset_64, 6336 .lbr_read = intel_pmu_lbr_read_64, 6337 .lbr_save = intel_pmu_lbr_save, 6338 .lbr_restore = intel_pmu_lbr_restore, 6339 }; 6340 6341 static __initconst const struct x86_pmu intel_pmu = { 6342 .name = "Intel", 6343 .handle_irq = intel_pmu_handle_irq, 6344 .disable_all = intel_pmu_disable_all, 6345 .enable_all = intel_pmu_enable_all, 6346 .enable = intel_pmu_enable_event, 6347 .disable = intel_pmu_disable_event, 6348 .add = intel_pmu_add_event, 6349 .del = intel_pmu_del_event, 6350 .read = intel_pmu_read_event, 6351 .set_period = intel_pmu_set_period, 6352 .update = intel_pmu_update, 6353 .hw_config = intel_pmu_hw_config, 6354 .schedule_events = x86_schedule_events, 6355 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 6356 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 6357 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0, 6358 .event_map = intel_pmu_event_map, 6359 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 6360 .apic = 1, 6361 .large_pebs_flags = LARGE_PEBS_FLAGS, 6362 /* 6363 * Intel PMCs cannot be accessed sanely above 32 bit width, 6364 * so we install an artificial 1<<31 period regardless of 6365 * the generic event period: 6366 */ 6367 .max_period = (1ULL << 31) - 1, 6368 .get_event_constraints = intel_get_event_constraints, 6369 .put_event_constraints = intel_put_event_constraints, 6370 .pebs_aliases = intel_pebs_aliases_core2, 6371 6372 .format_attrs = intel_arch3_formats_attr, 6373 .events_sysfs_show = intel_event_sysfs_show, 6374 6375 .cpu_prepare = intel_pmu_cpu_prepare, 6376 .cpu_starting = intel_pmu_cpu_starting, 6377 .cpu_dying = intel_pmu_cpu_dying, 6378 .cpu_dead = intel_pmu_cpu_dead, 6379 6380 .guest_get_msrs = intel_guest_get_msrs, 6381 .sched_task = intel_pmu_sched_task, 6382 6383 .check_period = intel_pmu_check_period, 6384 6385 .aux_output_match = intel_pmu_aux_output_match, 6386 6387 .lbr_reset = intel_pmu_lbr_reset_64, 6388 .lbr_read = intel_pmu_lbr_read_64, 6389 .lbr_save = intel_pmu_lbr_save, 6390 .lbr_restore = intel_pmu_lbr_restore, 6391 6392 /* 6393 * SMM has access to all 4 rings and while traditionally SMM code only 6394 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM. 6395 * 6396 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction 6397 * between SMM or not, this results in what should be pure userspace 6398 * counters including SMM data. 6399 * 6400 * This is a clear privilege issue, therefore globally disable 6401 * counting SMM by default. 6402 */ 6403 .attr_freeze_on_smi = 1, 6404 }; 6405 6406 static __init void intel_clovertown_quirk(void) 6407 { 6408 /* 6409 * PEBS is unreliable due to: 6410 * 6411 * AJ67 - PEBS may experience CPL leaks 6412 * AJ68 - PEBS PMI may be delayed by one event 6413 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 6414 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 6415 * 6416 * AJ67 could be worked around by restricting the OS/USR flags. 6417 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 6418 * 6419 * AJ106 could possibly be worked around by not allowing LBR 6420 * usage from PEBS, including the fixup. 6421 * AJ68 could possibly be worked around by always programming 6422 * a pebs_event_reset[0] value and coping with the lost events. 6423 * 6424 * But taken together it might just make sense to not enable PEBS on 6425 * these chips. 6426 */ 6427 pr_warn("PEBS disabled due to CPU errata\n"); 6428 x86_pmu.ds_pebs = 0; 6429 x86_pmu.pebs_constraints = NULL; 6430 } 6431 6432 static const struct x86_cpu_id isolation_ucodes[] = { 6433 X86_MATCH_VFM_STEPS(INTEL_HASWELL, 3, 3, 0x0000001f), 6434 X86_MATCH_VFM_STEPS(INTEL_HASWELL_L, 1, 1, 0x0000001e), 6435 X86_MATCH_VFM_STEPS(INTEL_HASWELL_G, 1, 1, 0x00000015), 6436 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 2, 2, 0x00000037), 6437 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 4, 4, 0x0000000a), 6438 X86_MATCH_VFM_STEPS(INTEL_BROADWELL, 4, 4, 0x00000023), 6439 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_G, 1, 1, 0x00000014), 6440 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 2, 2, 0x00000010), 6441 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 3, 3, 0x07000009), 6442 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 4, 4, 0x0f000009), 6443 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 5, 5, 0x0e000002), 6444 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_X, 1, 1, 0x0b000014), 6445 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 3, 3, 0x00000021), 6446 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 4, 7, 0x00000000), 6447 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 11, 11, 0x00000000), 6448 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_L, 3, 3, 0x0000007c), 6449 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE, 3, 3, 0x0000007c), 6450 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE, 9, 13, 0x0000004e), 6451 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE_L, 9, 12, 0x0000004e), 6452 {} 6453 }; 6454 6455 static void intel_check_pebs_isolation(void) 6456 { 6457 x86_pmu.pebs_no_isolation = !x86_match_min_microcode_rev(isolation_ucodes); 6458 } 6459 6460 static __init void intel_pebs_isolation_quirk(void) 6461 { 6462 WARN_ON_ONCE(x86_pmu.check_microcode); 6463 x86_pmu.check_microcode = intel_check_pebs_isolation; 6464 intel_check_pebs_isolation(); 6465 } 6466 6467 static const struct x86_cpu_id pebs_ucodes[] = { 6468 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE, 7, 7, 0x00000028), 6469 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 6, 6, 0x00000618), 6470 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 7, 7, 0x0000070c), 6471 {} 6472 }; 6473 6474 static bool intel_snb_pebs_broken(void) 6475 { 6476 return !x86_match_min_microcode_rev(pebs_ucodes); 6477 } 6478 6479 static void intel_snb_check_microcode(void) 6480 { 6481 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 6482 return; 6483 6484 /* 6485 * Serialized by the microcode lock.. 6486 */ 6487 if (x86_pmu.pebs_broken) { 6488 pr_info("PEBS enabled due to microcode update\n"); 6489 x86_pmu.pebs_broken = 0; 6490 } else { 6491 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 6492 x86_pmu.pebs_broken = 1; 6493 } 6494 } 6495 6496 static bool is_lbr_from(unsigned long msr) 6497 { 6498 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 6499 6500 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 6501 } 6502 6503 /* 6504 * Under certain circumstances, access certain MSR may cause #GP. 6505 * The function tests if the input MSR can be safely accessed. 6506 */ 6507 static bool check_msr(unsigned long msr, u64 mask) 6508 { 6509 u64 val_old, val_new, val_tmp; 6510 6511 /* 6512 * Disable the check for real HW, so we don't 6513 * mess with potentially enabled registers: 6514 */ 6515 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 6516 return true; 6517 6518 /* 6519 * Read the current value, change it and read it back to see if it 6520 * matches, this is needed to detect certain hardware emulators 6521 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 6522 */ 6523 if (rdmsrq_safe(msr, &val_old)) 6524 return false; 6525 6526 /* 6527 * Only change the bits which can be updated by wrmsrq. 6528 */ 6529 val_tmp = val_old ^ mask; 6530 6531 if (is_lbr_from(msr)) 6532 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 6533 6534 if (wrmsrq_safe(msr, val_tmp) || 6535 rdmsrq_safe(msr, &val_new)) 6536 return false; 6537 6538 /* 6539 * Quirk only affects validation in wrmsr(), so wrmsrq()'s value 6540 * should equal rdmsrq()'s even with the quirk. 6541 */ 6542 if (val_new != val_tmp) 6543 return false; 6544 6545 if (is_lbr_from(msr)) 6546 val_old = lbr_from_signext_quirk_wr(val_old); 6547 6548 /* Here it's sure that the MSR can be safely accessed. 6549 * Restore the old value and return. 6550 */ 6551 wrmsrq(msr, val_old); 6552 6553 return true; 6554 } 6555 6556 static __init void intel_sandybridge_quirk(void) 6557 { 6558 x86_pmu.check_microcode = intel_snb_check_microcode; 6559 cpus_read_lock(); 6560 intel_snb_check_microcode(); 6561 cpus_read_unlock(); 6562 } 6563 6564 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 6565 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 6566 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 6567 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 6568 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 6569 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 6570 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 6571 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 6572 }; 6573 6574 static __init void intel_arch_events_quirk(void) 6575 { 6576 int bit; 6577 6578 /* disable event that reported as not present by cpuid */ 6579 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 6580 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 6581 pr_warn("CPUID marked event: \'%s\' unavailable\n", 6582 intel_arch_events_map[bit].name); 6583 } 6584 } 6585 6586 static __init void intel_nehalem_quirk(void) 6587 { 6588 union cpuid10_ebx ebx; 6589 6590 ebx.full = x86_pmu.events_maskl; 6591 if (ebx.split.no_branch_misses_retired) { 6592 /* 6593 * Erratum AAJ80 detected, we work it around by using 6594 * the BR_MISP_EXEC.ANY event. This will over-count 6595 * branch-misses, but it's still much better than the 6596 * architectural event which is often completely bogus: 6597 */ 6598 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 6599 ebx.split.no_branch_misses_retired = 0; 6600 x86_pmu.events_maskl = ebx.full; 6601 pr_info("CPU erratum AAJ80 worked around\n"); 6602 } 6603 } 6604 6605 /* 6606 * enable software workaround for errata: 6607 * SNB: BJ122 6608 * IVB: BV98 6609 * HSW: HSD29 6610 * 6611 * Only needed when HT is enabled. However detecting 6612 * if HT is enabled is difficult (model specific). So instead, 6613 * we enable the workaround in the early boot, and verify if 6614 * it is needed in a later initcall phase once we have valid 6615 * topology information to check if HT is actually enabled 6616 */ 6617 static __init void intel_ht_bug(void) 6618 { 6619 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 6620 6621 x86_pmu.start_scheduling = intel_start_scheduling; 6622 x86_pmu.commit_scheduling = intel_commit_scheduling; 6623 x86_pmu.stop_scheduling = intel_stop_scheduling; 6624 } 6625 6626 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 6627 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 6628 6629 /* Haswell special events */ 6630 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 6631 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 6632 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 6633 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 6634 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 6635 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 6636 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 6637 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 6638 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 6639 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 6640 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 6641 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 6642 6643 static struct attribute *hsw_events_attrs[] = { 6644 EVENT_PTR(td_slots_issued), 6645 EVENT_PTR(td_slots_retired), 6646 EVENT_PTR(td_fetch_bubbles), 6647 EVENT_PTR(td_total_slots), 6648 EVENT_PTR(td_total_slots_scale), 6649 EVENT_PTR(td_recovery_bubbles), 6650 EVENT_PTR(td_recovery_bubbles_scale), 6651 NULL 6652 }; 6653 6654 static struct attribute *hsw_mem_events_attrs[] = { 6655 EVENT_PTR(mem_ld_hsw), 6656 EVENT_PTR(mem_st_hsw), 6657 NULL, 6658 }; 6659 6660 static struct attribute *hsw_tsx_events_attrs[] = { 6661 EVENT_PTR(tx_start), 6662 EVENT_PTR(tx_commit), 6663 EVENT_PTR(tx_abort), 6664 EVENT_PTR(tx_capacity), 6665 EVENT_PTR(tx_conflict), 6666 EVENT_PTR(el_start), 6667 EVENT_PTR(el_commit), 6668 EVENT_PTR(el_abort), 6669 EVENT_PTR(el_capacity), 6670 EVENT_PTR(el_conflict), 6671 EVENT_PTR(cycles_t), 6672 EVENT_PTR(cycles_ct), 6673 NULL 6674 }; 6675 6676 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 6677 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 6678 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 6679 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 6680 6681 static struct attribute *icl_events_attrs[] = { 6682 EVENT_PTR(mem_ld_hsw), 6683 EVENT_PTR(mem_st_hsw), 6684 NULL, 6685 }; 6686 6687 static struct attribute *icl_td_events_attrs[] = { 6688 EVENT_PTR(slots), 6689 EVENT_PTR(td_retiring), 6690 EVENT_PTR(td_bad_spec), 6691 EVENT_PTR(td_fe_bound), 6692 EVENT_PTR(td_be_bound), 6693 NULL, 6694 }; 6695 6696 static struct attribute *icl_tsx_events_attrs[] = { 6697 EVENT_PTR(tx_start), 6698 EVENT_PTR(tx_abort), 6699 EVENT_PTR(tx_commit), 6700 EVENT_PTR(tx_capacity_read), 6701 EVENT_PTR(tx_capacity_write), 6702 EVENT_PTR(tx_conflict), 6703 EVENT_PTR(el_start), 6704 EVENT_PTR(el_abort), 6705 EVENT_PTR(el_commit), 6706 EVENT_PTR(el_capacity_read), 6707 EVENT_PTR(el_capacity_write), 6708 EVENT_PTR(el_conflict), 6709 EVENT_PTR(cycles_t), 6710 EVENT_PTR(cycles_ct), 6711 NULL, 6712 }; 6713 6714 6715 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 6716 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 6717 6718 static struct attribute *glc_events_attrs[] = { 6719 EVENT_PTR(mem_ld_hsw), 6720 EVENT_PTR(mem_st_spr), 6721 EVENT_PTR(mem_ld_aux), 6722 NULL, 6723 }; 6724 6725 static struct attribute *glc_td_events_attrs[] = { 6726 EVENT_PTR(slots), 6727 EVENT_PTR(td_retiring), 6728 EVENT_PTR(td_bad_spec), 6729 EVENT_PTR(td_fe_bound), 6730 EVENT_PTR(td_be_bound), 6731 EVENT_PTR(td_heavy_ops), 6732 EVENT_PTR(td_br_mispredict), 6733 EVENT_PTR(td_fetch_lat), 6734 EVENT_PTR(td_mem_bound), 6735 NULL, 6736 }; 6737 6738 static struct attribute *glc_tsx_events_attrs[] = { 6739 EVENT_PTR(tx_start), 6740 EVENT_PTR(tx_abort), 6741 EVENT_PTR(tx_commit), 6742 EVENT_PTR(tx_capacity_read), 6743 EVENT_PTR(tx_capacity_write), 6744 EVENT_PTR(tx_conflict), 6745 EVENT_PTR(cycles_t), 6746 EVENT_PTR(cycles_ct), 6747 NULL, 6748 }; 6749 6750 static ssize_t freeze_on_smi_show(struct device *cdev, 6751 struct device_attribute *attr, 6752 char *buf) 6753 { 6754 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 6755 } 6756 6757 static DEFINE_MUTEX(freeze_on_smi_mutex); 6758 6759 static ssize_t freeze_on_smi_store(struct device *cdev, 6760 struct device_attribute *attr, 6761 const char *buf, size_t count) 6762 { 6763 unsigned long val; 6764 ssize_t ret; 6765 6766 ret = kstrtoul(buf, 0, &val); 6767 if (ret) 6768 return ret; 6769 6770 if (val > 1) 6771 return -EINVAL; 6772 6773 mutex_lock(&freeze_on_smi_mutex); 6774 6775 if (x86_pmu.attr_freeze_on_smi == val) 6776 goto done; 6777 6778 x86_pmu.attr_freeze_on_smi = val; 6779 6780 cpus_read_lock(); 6781 on_each_cpu(flip_smm_bit, &val, 1); 6782 cpus_read_unlock(); 6783 done: 6784 mutex_unlock(&freeze_on_smi_mutex); 6785 6786 return count; 6787 } 6788 6789 static void update_tfa_sched(void *ignored) 6790 { 6791 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 6792 6793 /* 6794 * check if PMC3 is used 6795 * and if so force schedule out for all event types all contexts 6796 */ 6797 if (test_bit(3, cpuc->active_mask)) 6798 perf_pmu_resched(x86_get_pmu(smp_processor_id())); 6799 } 6800 6801 static ssize_t show_sysctl_tfa(struct device *cdev, 6802 struct device_attribute *attr, 6803 char *buf) 6804 { 6805 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 6806 } 6807 6808 static ssize_t set_sysctl_tfa(struct device *cdev, 6809 struct device_attribute *attr, 6810 const char *buf, size_t count) 6811 { 6812 bool val; 6813 ssize_t ret; 6814 6815 ret = kstrtobool(buf, &val); 6816 if (ret) 6817 return ret; 6818 6819 /* no change */ 6820 if (val == allow_tsx_force_abort) 6821 return count; 6822 6823 allow_tsx_force_abort = val; 6824 6825 cpus_read_lock(); 6826 on_each_cpu(update_tfa_sched, NULL, 1); 6827 cpus_read_unlock(); 6828 6829 return count; 6830 } 6831 6832 6833 static DEVICE_ATTR_RW(freeze_on_smi); 6834 6835 static ssize_t branches_show(struct device *cdev, 6836 struct device_attribute *attr, 6837 char *buf) 6838 { 6839 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 6840 } 6841 6842 static DEVICE_ATTR_RO(branches); 6843 6844 static ssize_t branch_counter_nr_show(struct device *cdev, 6845 struct device_attribute *attr, 6846 char *buf) 6847 { 6848 return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_counters)); 6849 } 6850 6851 static DEVICE_ATTR_RO(branch_counter_nr); 6852 6853 static ssize_t branch_counter_width_show(struct device *cdev, 6854 struct device_attribute *attr, 6855 char *buf) 6856 { 6857 return snprintf(buf, PAGE_SIZE, "%d\n", LBR_INFO_BR_CNTR_BITS); 6858 } 6859 6860 static DEVICE_ATTR_RO(branch_counter_width); 6861 6862 static struct attribute *lbr_attrs[] = { 6863 &dev_attr_branches.attr, 6864 &dev_attr_branch_counter_nr.attr, 6865 &dev_attr_branch_counter_width.attr, 6866 NULL 6867 }; 6868 6869 static umode_t 6870 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6871 { 6872 /* branches */ 6873 if (i == 0) 6874 return x86_pmu.lbr_nr ? attr->mode : 0; 6875 6876 return (x86_pmu.flags & PMU_FL_BR_CNTR) ? attr->mode : 0; 6877 } 6878 6879 static char pmu_name_str[30]; 6880 6881 static DEVICE_STRING_ATTR_RO(pmu_name, 0444, pmu_name_str); 6882 6883 static struct attribute *intel_pmu_caps_attrs[] = { 6884 &dev_attr_pmu_name.attr.attr, 6885 NULL 6886 }; 6887 6888 static DEVICE_ATTR(allow_tsx_force_abort, 0644, 6889 show_sysctl_tfa, 6890 set_sysctl_tfa); 6891 6892 static struct attribute *intel_pmu_attrs[] = { 6893 &dev_attr_freeze_on_smi.attr, 6894 &dev_attr_allow_tsx_force_abort.attr, 6895 NULL, 6896 }; 6897 6898 static umode_t 6899 default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6900 { 6901 if (attr == &dev_attr_allow_tsx_force_abort.attr) 6902 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 6903 6904 return attr->mode; 6905 } 6906 6907 static umode_t 6908 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6909 { 6910 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 6911 } 6912 6913 static umode_t 6914 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6915 { 6916 return intel_pmu_has_pebs() ? attr->mode : 0; 6917 } 6918 6919 static umode_t 6920 mem_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6921 { 6922 if (attr == &event_attr_mem_ld_aux.attr.attr) 6923 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0; 6924 6925 return pebs_is_visible(kobj, attr, i); 6926 } 6927 6928 static umode_t 6929 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6930 { 6931 return x86_pmu.version >= 2 ? attr->mode : 0; 6932 } 6933 6934 static umode_t 6935 td_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6936 { 6937 /* 6938 * Hide the perf metrics topdown events 6939 * if the feature is not enumerated. 6940 */ 6941 if (x86_pmu.num_topdown_events) 6942 return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0; 6943 6944 return attr->mode; 6945 } 6946 6947 PMU_FORMAT_ATTR(acr_mask, "config2:0-63"); 6948 6949 static struct attribute *format_acr_attrs[] = { 6950 &format_attr_acr_mask.attr, 6951 NULL 6952 }; 6953 6954 static umode_t 6955 acr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6956 { 6957 struct device *dev = kobj_to_dev(kobj); 6958 6959 return intel_pmu_has_acr(dev_get_drvdata(dev)) ? attr->mode : 0; 6960 } 6961 6962 static struct attribute_group group_events_td = { 6963 .name = "events", 6964 .is_visible = td_is_visible, 6965 }; 6966 6967 static struct attribute_group group_events_mem = { 6968 .name = "events", 6969 .is_visible = mem_is_visible, 6970 }; 6971 6972 static struct attribute_group group_events_tsx = { 6973 .name = "events", 6974 .is_visible = tsx_is_visible, 6975 }; 6976 6977 static struct attribute_group group_caps_gen = { 6978 .name = "caps", 6979 .attrs = intel_pmu_caps_attrs, 6980 }; 6981 6982 static struct attribute_group group_caps_lbr = { 6983 .name = "caps", 6984 .attrs = lbr_attrs, 6985 .is_visible = lbr_is_visible, 6986 }; 6987 6988 static struct attribute_group group_format_extra = { 6989 .name = "format", 6990 .is_visible = exra_is_visible, 6991 }; 6992 6993 static struct attribute_group group_format_extra_skl = { 6994 .name = "format", 6995 .is_visible = exra_is_visible, 6996 }; 6997 6998 static struct attribute_group group_format_evtsel_ext = { 6999 .name = "format", 7000 .attrs = format_evtsel_ext_attrs, 7001 .is_visible = evtsel_ext_is_visible, 7002 }; 7003 7004 static struct attribute_group group_format_acr = { 7005 .name = "format", 7006 .attrs = format_acr_attrs, 7007 .is_visible = acr_is_visible, 7008 }; 7009 7010 static struct attribute_group group_default = { 7011 .attrs = intel_pmu_attrs, 7012 .is_visible = default_is_visible, 7013 }; 7014 7015 static const struct attribute_group *attr_update[] = { 7016 &group_events_td, 7017 &group_events_mem, 7018 &group_events_tsx, 7019 &group_caps_gen, 7020 &group_caps_lbr, 7021 &group_format_extra, 7022 &group_format_extra_skl, 7023 &group_format_evtsel_ext, 7024 &group_format_acr, 7025 &group_default, 7026 NULL, 7027 }; 7028 7029 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); 7030 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); 7031 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); 7032 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); 7033 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); 7034 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); 7035 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); 7036 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); 7037 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); 7038 7039 static struct attribute *adl_hybrid_events_attrs[] = { 7040 EVENT_PTR(slots_adl), 7041 EVENT_PTR(td_retiring_adl), 7042 EVENT_PTR(td_bad_spec_adl), 7043 EVENT_PTR(td_fe_bound_adl), 7044 EVENT_PTR(td_be_bound_adl), 7045 EVENT_PTR(td_heavy_ops_adl), 7046 EVENT_PTR(td_br_mis_adl), 7047 EVENT_PTR(td_fetch_lat_adl), 7048 EVENT_PTR(td_mem_bound_adl), 7049 NULL, 7050 }; 7051 7052 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_lnl, "event=0xc2,umask=0x02;event=0x00,umask=0x80", hybrid_big_small); 7053 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_lnl, "event=0x9c,umask=0x01;event=0x00,umask=0x82", hybrid_big_small); 7054 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_lnl, "event=0xa4,umask=0x02;event=0x00,umask=0x83", hybrid_big_small); 7055 7056 static struct attribute *lnl_hybrid_events_attrs[] = { 7057 EVENT_PTR(slots_adl), 7058 EVENT_PTR(td_retiring_lnl), 7059 EVENT_PTR(td_bad_spec_adl), 7060 EVENT_PTR(td_fe_bound_lnl), 7061 EVENT_PTR(td_be_bound_lnl), 7062 EVENT_PTR(td_heavy_ops_adl), 7063 EVENT_PTR(td_br_mis_adl), 7064 EVENT_PTR(td_fetch_lat_adl), 7065 EVENT_PTR(td_mem_bound_adl), 7066 NULL 7067 }; 7068 7069 /* The event string must be in PMU IDX order. */ 7070 EVENT_ATTR_STR_HYBRID(topdown-retiring, 7071 td_retiring_arl_h, 7072 "event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0", 7073 hybrid_big_small_tiny); 7074 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, 7075 td_bad_spec_arl_h, 7076 "event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0", 7077 hybrid_big_small_tiny); 7078 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, 7079 td_fe_bound_arl_h, 7080 "event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0", 7081 hybrid_big_small_tiny); 7082 EVENT_ATTR_STR_HYBRID(topdown-be-bound, 7083 td_be_bound_arl_h, 7084 "event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0", 7085 hybrid_big_small_tiny); 7086 7087 static struct attribute *arl_h_hybrid_events_attrs[] = { 7088 EVENT_PTR(slots_adl), 7089 EVENT_PTR(td_retiring_arl_h), 7090 EVENT_PTR(td_bad_spec_arl_h), 7091 EVENT_PTR(td_fe_bound_arl_h), 7092 EVENT_PTR(td_be_bound_arl_h), 7093 EVENT_PTR(td_heavy_ops_adl), 7094 EVENT_PTR(td_br_mis_adl), 7095 EVENT_PTR(td_fetch_lat_adl), 7096 EVENT_PTR(td_mem_bound_adl), 7097 NULL, 7098 }; 7099 7100 /* Must be in IDX order */ 7101 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); 7102 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); 7103 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); 7104 7105 static struct attribute *adl_hybrid_mem_attrs[] = { 7106 EVENT_PTR(mem_ld_adl), 7107 EVENT_PTR(mem_st_adl), 7108 EVENT_PTR(mem_ld_aux_adl), 7109 NULL, 7110 }; 7111 7112 static struct attribute *mtl_hybrid_mem_attrs[] = { 7113 EVENT_PTR(mem_ld_adl), 7114 EVENT_PTR(mem_st_adl), 7115 NULL 7116 }; 7117 7118 EVENT_ATTR_STR_HYBRID(mem-loads, 7119 mem_ld_arl_h, 7120 "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3", 7121 hybrid_big_small_tiny); 7122 EVENT_ATTR_STR_HYBRID(mem-stores, 7123 mem_st_arl_h, 7124 "event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6", 7125 hybrid_big_small_tiny); 7126 7127 static struct attribute *arl_h_hybrid_mem_attrs[] = { 7128 EVENT_PTR(mem_ld_arl_h), 7129 EVENT_PTR(mem_st_arl_h), 7130 NULL, 7131 }; 7132 7133 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); 7134 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); 7135 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); 7136 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); 7137 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); 7138 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); 7139 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); 7140 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); 7141 7142 static struct attribute *adl_hybrid_tsx_attrs[] = { 7143 EVENT_PTR(tx_start_adl), 7144 EVENT_PTR(tx_abort_adl), 7145 EVENT_PTR(tx_commit_adl), 7146 EVENT_PTR(tx_capacity_read_adl), 7147 EVENT_PTR(tx_capacity_write_adl), 7148 EVENT_PTR(tx_conflict_adl), 7149 EVENT_PTR(cycles_t_adl), 7150 EVENT_PTR(cycles_ct_adl), 7151 NULL, 7152 }; 7153 7154 FORMAT_ATTR_HYBRID(in_tx, hybrid_big); 7155 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); 7156 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny); 7157 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny); 7158 FORMAT_ATTR_HYBRID(frontend, hybrid_big); 7159 7160 #define ADL_HYBRID_RTM_FORMAT_ATTR \ 7161 FORMAT_HYBRID_PTR(in_tx), \ 7162 FORMAT_HYBRID_PTR(in_tx_cp) 7163 7164 #define ADL_HYBRID_FORMAT_ATTR \ 7165 FORMAT_HYBRID_PTR(offcore_rsp), \ 7166 FORMAT_HYBRID_PTR(ldlat), \ 7167 FORMAT_HYBRID_PTR(frontend) 7168 7169 static struct attribute *adl_hybrid_extra_attr_rtm[] = { 7170 ADL_HYBRID_RTM_FORMAT_ATTR, 7171 ADL_HYBRID_FORMAT_ATTR, 7172 NULL 7173 }; 7174 7175 static struct attribute *adl_hybrid_extra_attr[] = { 7176 ADL_HYBRID_FORMAT_ATTR, 7177 NULL 7178 }; 7179 7180 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_tiny); 7181 7182 static struct attribute *mtl_hybrid_extra_attr_rtm[] = { 7183 ADL_HYBRID_RTM_FORMAT_ATTR, 7184 ADL_HYBRID_FORMAT_ATTR, 7185 FORMAT_HYBRID_PTR(snoop_rsp), 7186 NULL 7187 }; 7188 7189 static struct attribute *mtl_hybrid_extra_attr[] = { 7190 ADL_HYBRID_FORMAT_ATTR, 7191 FORMAT_HYBRID_PTR(snoop_rsp), 7192 NULL 7193 }; 7194 7195 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) 7196 { 7197 struct device *dev = kobj_to_dev(kobj); 7198 struct x86_hybrid_pmu *pmu = 7199 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 7200 struct perf_pmu_events_hybrid_attr *pmu_attr = 7201 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); 7202 7203 return pmu->pmu_type & pmu_attr->pmu_type; 7204 } 7205 7206 static umode_t hybrid_events_is_visible(struct kobject *kobj, 7207 struct attribute *attr, int i) 7208 { 7209 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; 7210 } 7211 7212 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) 7213 { 7214 int cpu = cpumask_first(&pmu->supported_cpus); 7215 7216 return (cpu >= nr_cpu_ids) ? -1 : cpu; 7217 } 7218 7219 static umode_t hybrid_tsx_is_visible(struct kobject *kobj, 7220 struct attribute *attr, int i) 7221 { 7222 struct device *dev = kobj_to_dev(kobj); 7223 struct x86_hybrid_pmu *pmu = 7224 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 7225 int cpu = hybrid_find_supported_cpu(pmu); 7226 7227 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; 7228 } 7229 7230 static umode_t hybrid_format_is_visible(struct kobject *kobj, 7231 struct attribute *attr, int i) 7232 { 7233 struct device *dev = kobj_to_dev(kobj); 7234 struct x86_hybrid_pmu *pmu = 7235 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 7236 struct perf_pmu_format_hybrid_attr *pmu_attr = 7237 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); 7238 int cpu = hybrid_find_supported_cpu(pmu); 7239 7240 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0; 7241 } 7242 7243 static umode_t hybrid_td_is_visible(struct kobject *kobj, 7244 struct attribute *attr, int i) 7245 { 7246 struct device *dev = kobj_to_dev(kobj); 7247 struct x86_hybrid_pmu *pmu = 7248 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 7249 7250 if (!is_attr_for_this_pmu(kobj, attr)) 7251 return 0; 7252 7253 7254 /* Only the big core supports perf metrics */ 7255 if (pmu->pmu_type == hybrid_big) 7256 return pmu->intel_cap.perf_metrics ? attr->mode : 0; 7257 7258 return attr->mode; 7259 } 7260 7261 static struct attribute_group hybrid_group_events_td = { 7262 .name = "events", 7263 .is_visible = hybrid_td_is_visible, 7264 }; 7265 7266 static struct attribute_group hybrid_group_events_mem = { 7267 .name = "events", 7268 .is_visible = hybrid_events_is_visible, 7269 }; 7270 7271 static struct attribute_group hybrid_group_events_tsx = { 7272 .name = "events", 7273 .is_visible = hybrid_tsx_is_visible, 7274 }; 7275 7276 static struct attribute_group hybrid_group_format_extra = { 7277 .name = "format", 7278 .is_visible = hybrid_format_is_visible, 7279 }; 7280 7281 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, 7282 struct device_attribute *attr, 7283 char *buf) 7284 { 7285 struct x86_hybrid_pmu *pmu = 7286 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 7287 7288 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus); 7289 } 7290 7291 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); 7292 static struct attribute *intel_hybrid_cpus_attrs[] = { 7293 &dev_attr_cpus.attr, 7294 NULL, 7295 }; 7296 7297 static struct attribute_group hybrid_group_cpus = { 7298 .attrs = intel_hybrid_cpus_attrs, 7299 }; 7300 7301 static const struct attribute_group *hybrid_attr_update[] = { 7302 &hybrid_group_events_td, 7303 &hybrid_group_events_mem, 7304 &hybrid_group_events_tsx, 7305 &group_caps_gen, 7306 &group_caps_lbr, 7307 &hybrid_group_format_extra, 7308 &group_format_evtsel_ext, 7309 &group_format_acr, 7310 &group_default, 7311 &hybrid_group_cpus, 7312 NULL, 7313 }; 7314 7315 static struct attribute *empty_attrs; 7316 7317 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 7318 u64 cntr_mask, 7319 u64 fixed_cntr_mask, 7320 u64 intel_ctrl) 7321 { 7322 struct event_constraint *c; 7323 7324 if (!event_constraints) 7325 return; 7326 7327 /* 7328 * event on fixed counter2 (REF_CYCLES) only works on this 7329 * counter, so do not extend mask to generic counters 7330 */ 7331 for_each_event_constraint(c, event_constraints) { 7332 /* 7333 * Don't extend the topdown slots and metrics 7334 * events to the generic counters. 7335 */ 7336 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 7337 /* 7338 * Disable topdown slots and metrics events, 7339 * if slots event is not in CPUID. 7340 */ 7341 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) 7342 c->idxmsk64 = 0; 7343 c->weight = hweight64(c->idxmsk64); 7344 continue; 7345 } 7346 7347 if (c->cmask == FIXED_EVENT_FLAGS) { 7348 /* Disabled fixed counters which are not in CPUID */ 7349 c->idxmsk64 &= intel_ctrl; 7350 7351 /* 7352 * Don't extend the pseudo-encoding to the 7353 * generic counters 7354 */ 7355 if (!use_fixed_pseudo_encoding(c->code)) 7356 c->idxmsk64 |= cntr_mask; 7357 } 7358 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED); 7359 c->weight = hweight64(c->idxmsk64); 7360 } 7361 } 7362 7363 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) 7364 { 7365 struct extra_reg *er; 7366 7367 /* 7368 * Access extra MSR may cause #GP under certain circumstances. 7369 * E.g. KVM doesn't support offcore event 7370 * Check all extra_regs here. 7371 */ 7372 if (!extra_regs) 7373 return; 7374 7375 for (er = extra_regs; er->msr; er++) { 7376 er->extra_msr_access = check_msr(er->msr, 0x11UL); 7377 /* Disable LBR select mapping */ 7378 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 7379 x86_pmu.lbr_sel_map = NULL; 7380 } 7381 } 7382 7383 static inline int intel_pmu_v6_addr_offset(int index, bool eventsel) 7384 { 7385 return MSR_IA32_PMC_V6_STEP * index; 7386 } 7387 7388 static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = { 7389 { hybrid_small, "cpu_atom" }, 7390 { hybrid_big, "cpu_core" }, 7391 { hybrid_tiny, "cpu_lowpower" }, 7392 }; 7393 7394 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus) 7395 { 7396 unsigned long pmus_mask = pmus; 7397 struct x86_hybrid_pmu *pmu; 7398 int idx = 0, bit; 7399 7400 x86_pmu.num_hybrid_pmus = hweight_long(pmus_mask); 7401 x86_pmu.hybrid_pmu = kzalloc_objs(struct x86_hybrid_pmu, 7402 x86_pmu.num_hybrid_pmus); 7403 if (!x86_pmu.hybrid_pmu) 7404 return -ENOMEM; 7405 7406 static_branch_enable(&perf_is_hybrid); 7407 x86_pmu.filter = intel_pmu_filter; 7408 7409 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) { 7410 pmu = &x86_pmu.hybrid_pmu[idx++]; 7411 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id; 7412 pmu->name = intel_hybrid_pmu_type_map[bit].name; 7413 7414 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 7415 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 7416 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 7417 pmu->config_mask = X86_RAW_EVENT_MASK; 7418 pmu->unconstrained = (struct event_constraint) 7419 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 7420 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 7421 7422 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 7423 if (pmu->pmu_type & hybrid_small_tiny) { 7424 pmu->intel_cap.perf_metrics = 0; 7425 pmu->mid_ack = true; 7426 } else if (pmu->pmu_type & hybrid_big) { 7427 pmu->intel_cap.perf_metrics = 1; 7428 pmu->late_ack = true; 7429 } 7430 } 7431 7432 return 0; 7433 } 7434 7435 static __always_inline void intel_pmu_ref_cycles_ext(void) 7436 { 7437 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED))) 7438 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c; 7439 } 7440 7441 static __always_inline void intel_pmu_init_glc(struct pmu *pmu) 7442 { 7443 x86_pmu.late_ack = true; 7444 x86_pmu.limit_period = glc_limit_period; 7445 x86_pmu.pebs_aliases = NULL; 7446 x86_pmu.pebs_prec_dist = true; 7447 x86_pmu.pebs_block = true; 7448 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7449 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7450 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 7451 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 7452 x86_pmu.lbr_pt_coexist = true; 7453 x86_pmu.num_topdown_events = 8; 7454 static_call_update(intel_pmu_update_topdown_event, 7455 &icl_update_topdown_event); 7456 static_call_update(intel_pmu_set_topdown_event_period, 7457 &icl_set_topdown_event_period); 7458 7459 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7460 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7461 hybrid(pmu, event_constraints) = intel_glc_event_constraints; 7462 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints; 7463 7464 intel_pmu_ref_cycles_ext(); 7465 } 7466 7467 static __always_inline void intel_pmu_init_grt(struct pmu *pmu) 7468 { 7469 x86_pmu.mid_ack = true; 7470 x86_pmu.limit_period = glc_limit_period; 7471 x86_pmu.pebs_aliases = NULL; 7472 x86_pmu.pebs_prec_dist = true; 7473 x86_pmu.pebs_block = true; 7474 x86_pmu.lbr_pt_coexist = true; 7475 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7476 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 7477 7478 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7479 memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7480 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 7481 hybrid(pmu, event_constraints) = intel_grt_event_constraints; 7482 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints; 7483 hybrid(pmu, extra_regs) = intel_grt_extra_regs; 7484 7485 intel_pmu_ref_cycles_ext(); 7486 } 7487 7488 static __always_inline void intel_pmu_init_lnc(struct pmu *pmu) 7489 { 7490 intel_pmu_init_glc(pmu); 7491 hybrid(pmu, event_constraints) = intel_lnc_event_constraints; 7492 hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints; 7493 hybrid(pmu, extra_regs) = intel_lnc_extra_regs; 7494 } 7495 7496 static __always_inline void intel_pmu_init_pnc(struct pmu *pmu) 7497 { 7498 intel_pmu_init_glc(pmu); 7499 x86_pmu.flags &= ~PMU_FL_HAS_RSP_1; 7500 x86_pmu.flags |= PMU_FL_HAS_OMR; 7501 memcpy(hybrid_var(pmu, hw_cache_event_ids), 7502 pnc_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7503 memcpy(hybrid_var(pmu, hw_cache_extra_regs), 7504 pnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7505 hybrid(pmu, event_constraints) = intel_pnc_event_constraints; 7506 hybrid(pmu, pebs_constraints) = intel_pnc_pebs_event_constraints; 7507 hybrid(pmu, extra_regs) = intel_pnc_extra_regs; 7508 } 7509 7510 static __always_inline void intel_pmu_init_skt(struct pmu *pmu) 7511 { 7512 intel_pmu_init_grt(pmu); 7513 hybrid(pmu, event_constraints) = intel_skt_event_constraints; 7514 hybrid(pmu, extra_regs) = intel_cmt_extra_regs; 7515 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); 7516 } 7517 7518 static __always_inline void intel_pmu_init_arw(struct pmu *pmu) 7519 { 7520 intel_pmu_init_grt(pmu); 7521 x86_pmu.flags &= ~PMU_FL_HAS_RSP_1; 7522 x86_pmu.flags |= PMU_FL_HAS_OMR; 7523 memcpy(hybrid_var(pmu, hw_cache_extra_regs), 7524 arw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7525 hybrid(pmu, event_constraints) = intel_arw_event_constraints; 7526 hybrid(pmu, pebs_constraints) = intel_arw_pebs_event_constraints; 7527 hybrid(pmu, extra_regs) = intel_arw_extra_regs; 7528 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); 7529 } 7530 7531 __init int intel_pmu_init(void) 7532 { 7533 struct attribute **extra_skl_attr = &empty_attrs; 7534 struct attribute **extra_attr = &empty_attrs; 7535 struct attribute **td_attr = &empty_attrs; 7536 struct attribute **mem_attr = &empty_attrs; 7537 struct attribute **tsx_attr = &empty_attrs; 7538 union cpuid10_edx edx; 7539 union cpuid10_eax eax; 7540 union cpuid10_ebx ebx; 7541 unsigned int fixed_mask; 7542 bool pmem = false; 7543 int version, i; 7544 char *name; 7545 struct x86_hybrid_pmu *pmu; 7546 7547 /* Architectural Perfmon was introduced starting with Core "Yonah" */ 7548 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 7549 switch (boot_cpu_data.x86) { 7550 case 6: 7551 if (boot_cpu_data.x86_vfm < INTEL_CORE_YONAH) 7552 return p6_pmu_init(); 7553 break; 7554 case 11: 7555 return knc_pmu_init(); 7556 case 15: 7557 return p4_pmu_init(); 7558 } 7559 7560 pr_cont("unsupported CPU family %d model %d ", 7561 boot_cpu_data.x86, boot_cpu_data.x86_model); 7562 return -ENODEV; 7563 } 7564 7565 /* 7566 * Check whether the Architectural PerfMon supports 7567 * Branch Misses Retired hw_event or not. 7568 */ 7569 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); 7570 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 7571 return -ENODEV; 7572 7573 version = eax.split.version_id; 7574 if (version < 2) 7575 x86_pmu = core_pmu; 7576 else 7577 x86_pmu = intel_pmu; 7578 7579 x86_pmu.version = version; 7580 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0); 7581 x86_pmu.cntval_bits = eax.split.bit_width; 7582 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 7583 7584 x86_pmu.events_maskl = ebx.full; 7585 x86_pmu.events_mask_len = eax.split.mask_length; 7586 7587 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64); 7588 x86_pmu.pebs_capable = PEBS_COUNTER_MASK; 7589 x86_pmu.config_mask = X86_RAW_EVENT_MASK; 7590 7591 /* 7592 * Quirk: v2 perfmon does not report fixed-purpose events, so 7593 * assume at least 3 events, when not running in a hypervisor: 7594 */ 7595 if (version > 1 && version < 5) { 7596 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 7597 7598 x86_pmu.fixed_cntr_mask64 = 7599 GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0); 7600 } else if (version >= 5) 7601 x86_pmu.fixed_cntr_mask64 = fixed_mask; 7602 7603 if (boot_cpu_has(X86_FEATURE_PDCM)) { 7604 u64 capabilities; 7605 7606 rdmsrq(MSR_IA32_PERF_CAPABILITIES, capabilities); 7607 x86_pmu.intel_cap.capabilities = capabilities; 7608 } 7609 7610 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 7611 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 7612 x86_pmu.lbr_read = intel_pmu_lbr_read_32; 7613 } 7614 7615 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 7616 intel_pmu_arch_lbr_init(); 7617 7618 intel_pebs_init(); 7619 7620 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 7621 7622 if (version >= 5) { 7623 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 7624 if (x86_pmu.intel_cap.anythread_deprecated) 7625 pr_cont(" AnyThread deprecated, "); 7626 } 7627 7628 /* The perf side of core PMU is ready to support the mediated vPMU. */ 7629 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_MEDIATED_VPMU; 7630 7631 /* 7632 * Many features on and after V6 require dynamic constraint, 7633 * e.g., Arch PEBS, ACR. 7634 */ 7635 if (version >= 6) { 7636 x86_pmu.flags |= PMU_FL_DYN_CONSTRAINT; 7637 x86_pmu.late_setup = intel_pmu_late_setup; 7638 } 7639 7640 /* 7641 * Install the hw-cache-events table: 7642 */ 7643 switch (boot_cpu_data.x86_vfm) { 7644 case INTEL_CORE_YONAH: 7645 pr_cont("Core events, "); 7646 name = "core"; 7647 break; 7648 7649 case INTEL_CORE2_MEROM: 7650 x86_add_quirk(intel_clovertown_quirk); 7651 fallthrough; 7652 7653 case INTEL_CORE2_MEROM_L: 7654 case INTEL_CORE2_PENRYN: 7655 case INTEL_CORE2_DUNNINGTON: 7656 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 7657 sizeof(hw_cache_event_ids)); 7658 7659 intel_pmu_lbr_init_core(); 7660 7661 x86_pmu.event_constraints = intel_core2_event_constraints; 7662 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 7663 pr_cont("Core2 events, "); 7664 name = "core2"; 7665 break; 7666 7667 case INTEL_NEHALEM: 7668 case INTEL_NEHALEM_EP: 7669 case INTEL_NEHALEM_EX: 7670 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 7671 sizeof(hw_cache_event_ids)); 7672 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 7673 sizeof(hw_cache_extra_regs)); 7674 7675 intel_pmu_lbr_init_nhm(); 7676 7677 x86_pmu.event_constraints = intel_nehalem_event_constraints; 7678 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 7679 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 7680 x86_pmu.extra_regs = intel_nehalem_extra_regs; 7681 x86_pmu.limit_period = nhm_limit_period; 7682 7683 mem_attr = nhm_mem_events_attrs; 7684 7685 /* UOPS_ISSUED.STALLED_CYCLES */ 7686 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 7687 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 7688 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 7689 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 7690 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 7691 7692 intel_pmu_pebs_data_source_nhm(); 7693 x86_add_quirk(intel_nehalem_quirk); 7694 x86_pmu.pebs_no_tlb = 1; 7695 extra_attr = nhm_format_attr; 7696 7697 pr_cont("Nehalem events, "); 7698 name = "nehalem"; 7699 break; 7700 7701 case INTEL_ATOM_BONNELL: 7702 case INTEL_ATOM_BONNELL_MID: 7703 case INTEL_ATOM_SALTWELL: 7704 case INTEL_ATOM_SALTWELL_MID: 7705 case INTEL_ATOM_SALTWELL_TABLET: 7706 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 7707 sizeof(hw_cache_event_ids)); 7708 7709 intel_pmu_lbr_init_atom(); 7710 7711 x86_pmu.event_constraints = intel_gen_event_constraints; 7712 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 7713 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 7714 pr_cont("Atom events, "); 7715 name = "bonnell"; 7716 break; 7717 7718 case INTEL_ATOM_SILVERMONT: 7719 case INTEL_ATOM_SILVERMONT_D: 7720 case INTEL_ATOM_SILVERMONT_MID: 7721 case INTEL_ATOM_AIRMONT: 7722 case INTEL_ATOM_AIRMONT_NP: 7723 case INTEL_ATOM_SILVERMONT_MID2: 7724 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 7725 sizeof(hw_cache_event_ids)); 7726 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 7727 sizeof(hw_cache_extra_regs)); 7728 7729 intel_pmu_lbr_init_slm(); 7730 7731 x86_pmu.event_constraints = intel_slm_event_constraints; 7732 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 7733 x86_pmu.extra_regs = intel_slm_extra_regs; 7734 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7735 td_attr = slm_events_attrs; 7736 extra_attr = slm_format_attr; 7737 pr_cont("Silvermont events, "); 7738 name = "silvermont"; 7739 break; 7740 7741 case INTEL_ATOM_GOLDMONT: 7742 case INTEL_ATOM_GOLDMONT_D: 7743 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 7744 sizeof(hw_cache_event_ids)); 7745 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 7746 sizeof(hw_cache_extra_regs)); 7747 7748 intel_pmu_lbr_init_skl(); 7749 7750 x86_pmu.event_constraints = intel_slm_event_constraints; 7751 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 7752 x86_pmu.extra_regs = intel_glm_extra_regs; 7753 /* 7754 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 7755 * for precise cycles. 7756 * :pp is identical to :ppp 7757 */ 7758 x86_pmu.pebs_aliases = NULL; 7759 x86_pmu.pebs_prec_dist = true; 7760 x86_pmu.lbr_pt_coexist = true; 7761 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7762 td_attr = glm_events_attrs; 7763 extra_attr = slm_format_attr; 7764 pr_cont("Goldmont events, "); 7765 name = "goldmont"; 7766 break; 7767 7768 case INTEL_ATOM_GOLDMONT_PLUS: 7769 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 7770 sizeof(hw_cache_event_ids)); 7771 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 7772 sizeof(hw_cache_extra_regs)); 7773 7774 intel_pmu_lbr_init_skl(); 7775 7776 x86_pmu.event_constraints = intel_slm_event_constraints; 7777 x86_pmu.extra_regs = intel_glm_extra_regs; 7778 /* 7779 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 7780 * for precise cycles. 7781 */ 7782 x86_pmu.pebs_aliases = NULL; 7783 x86_pmu.pebs_prec_dist = true; 7784 x86_pmu.lbr_pt_coexist = true; 7785 x86_pmu.pebs_capable = ~0ULL; 7786 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7787 x86_pmu.flags |= PMU_FL_PEBS_ALL; 7788 x86_pmu.get_event_constraints = glp_get_event_constraints; 7789 td_attr = glm_events_attrs; 7790 /* Goldmont Plus has 4-wide pipeline */ 7791 event_attr_td_total_slots_scale_glm.event_str = "4"; 7792 extra_attr = slm_format_attr; 7793 pr_cont("Goldmont plus events, "); 7794 name = "goldmont_plus"; 7795 break; 7796 7797 case INTEL_ATOM_TREMONT_D: 7798 case INTEL_ATOM_TREMONT: 7799 case INTEL_ATOM_TREMONT_L: 7800 x86_pmu.late_ack = true; 7801 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 7802 sizeof(hw_cache_event_ids)); 7803 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 7804 sizeof(hw_cache_extra_regs)); 7805 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 7806 7807 intel_pmu_lbr_init_skl(); 7808 7809 x86_pmu.event_constraints = intel_slm_event_constraints; 7810 x86_pmu.extra_regs = intel_tnt_extra_regs; 7811 /* 7812 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 7813 * for precise cycles. 7814 */ 7815 x86_pmu.pebs_aliases = NULL; 7816 x86_pmu.pebs_prec_dist = true; 7817 x86_pmu.lbr_pt_coexist = true; 7818 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7819 x86_pmu.get_event_constraints = tnt_get_event_constraints; 7820 td_attr = tnt_events_attrs; 7821 extra_attr = slm_format_attr; 7822 pr_cont("Tremont events, "); 7823 name = "Tremont"; 7824 break; 7825 7826 case INTEL_ATOM_GRACEMONT: 7827 intel_pmu_init_grt(NULL); 7828 intel_pmu_pebs_data_source_grt(); 7829 x86_pmu.pebs_latency_data = grt_latency_data; 7830 x86_pmu.get_event_constraints = tnt_get_event_constraints; 7831 td_attr = tnt_events_attrs; 7832 mem_attr = grt_mem_attrs; 7833 extra_attr = nhm_format_attr; 7834 pr_cont("Gracemont events, "); 7835 name = "gracemont"; 7836 break; 7837 7838 case INTEL_ATOM_CRESTMONT: 7839 case INTEL_ATOM_CRESTMONT_X: 7840 intel_pmu_init_grt(NULL); 7841 x86_pmu.extra_regs = intel_cmt_extra_regs; 7842 intel_pmu_pebs_data_source_cmt(); 7843 x86_pmu.pebs_latency_data = cmt_latency_data; 7844 x86_pmu.get_event_constraints = cmt_get_event_constraints; 7845 td_attr = cmt_events_attrs; 7846 mem_attr = grt_mem_attrs; 7847 extra_attr = cmt_format_attr; 7848 pr_cont("Crestmont events, "); 7849 name = "crestmont"; 7850 break; 7851 7852 case INTEL_ATOM_DARKMONT_X: 7853 intel_pmu_init_skt(NULL); 7854 intel_pmu_pebs_data_source_cmt(); 7855 x86_pmu.pebs_latency_data = cmt_latency_data; 7856 x86_pmu.get_event_constraints = cmt_get_event_constraints; 7857 td_attr = skt_events_attrs; 7858 mem_attr = grt_mem_attrs; 7859 extra_attr = cmt_format_attr; 7860 pr_cont("Darkmont events, "); 7861 name = "darkmont"; 7862 break; 7863 7864 case INTEL_WESTMERE: 7865 case INTEL_WESTMERE_EP: 7866 case INTEL_WESTMERE_EX: 7867 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 7868 sizeof(hw_cache_event_ids)); 7869 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 7870 sizeof(hw_cache_extra_regs)); 7871 7872 intel_pmu_lbr_init_nhm(); 7873 7874 x86_pmu.event_constraints = intel_westmere_event_constraints; 7875 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 7876 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 7877 x86_pmu.extra_regs = intel_westmere_extra_regs; 7878 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7879 7880 mem_attr = nhm_mem_events_attrs; 7881 7882 /* UOPS_ISSUED.STALLED_CYCLES */ 7883 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 7884 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 7885 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 7886 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 7887 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 7888 7889 intel_pmu_pebs_data_source_nhm(); 7890 extra_attr = nhm_format_attr; 7891 pr_cont("Westmere events, "); 7892 name = "westmere"; 7893 break; 7894 7895 case INTEL_SANDYBRIDGE: 7896 case INTEL_SANDYBRIDGE_X: 7897 x86_add_quirk(intel_sandybridge_quirk); 7898 x86_add_quirk(intel_ht_bug); 7899 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 7900 sizeof(hw_cache_event_ids)); 7901 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 7902 sizeof(hw_cache_extra_regs)); 7903 7904 intel_pmu_lbr_init_snb(); 7905 7906 x86_pmu.event_constraints = intel_snb_event_constraints; 7907 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 7908 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 7909 if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X) 7910 x86_pmu.extra_regs = intel_snbep_extra_regs; 7911 else 7912 x86_pmu.extra_regs = intel_snb_extra_regs; 7913 7914 7915 /* all extra regs are per-cpu when HT is on */ 7916 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7917 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7918 7919 td_attr = snb_events_attrs; 7920 mem_attr = snb_mem_events_attrs; 7921 7922 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 7923 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 7924 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 7925 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 7926 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 7927 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 7928 7929 extra_attr = nhm_format_attr; 7930 7931 pr_cont("SandyBridge events, "); 7932 name = "sandybridge"; 7933 break; 7934 7935 case INTEL_IVYBRIDGE: 7936 case INTEL_IVYBRIDGE_X: 7937 x86_add_quirk(intel_ht_bug); 7938 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 7939 sizeof(hw_cache_event_ids)); 7940 /* dTLB-load-misses on IVB is different than SNB */ 7941 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 7942 7943 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 7944 sizeof(hw_cache_extra_regs)); 7945 7946 intel_pmu_lbr_init_snb(); 7947 7948 x86_pmu.event_constraints = intel_ivb_event_constraints; 7949 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 7950 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 7951 x86_pmu.pebs_prec_dist = true; 7952 if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X) 7953 x86_pmu.extra_regs = intel_snbep_extra_regs; 7954 else 7955 x86_pmu.extra_regs = intel_snb_extra_regs; 7956 /* all extra regs are per-cpu when HT is on */ 7957 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7958 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7959 7960 td_attr = snb_events_attrs; 7961 mem_attr = snb_mem_events_attrs; 7962 7963 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 7964 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 7965 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 7966 7967 extra_attr = nhm_format_attr; 7968 7969 pr_cont("IvyBridge events, "); 7970 name = "ivybridge"; 7971 break; 7972 7973 7974 case INTEL_HASWELL: 7975 case INTEL_HASWELL_X: 7976 case INTEL_HASWELL_L: 7977 case INTEL_HASWELL_G: 7978 x86_add_quirk(intel_ht_bug); 7979 x86_add_quirk(intel_pebs_isolation_quirk); 7980 x86_pmu.late_ack = true; 7981 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7982 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7983 7984 intel_pmu_lbr_init_hsw(); 7985 7986 x86_pmu.event_constraints = intel_hsw_event_constraints; 7987 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 7988 x86_pmu.extra_regs = intel_snbep_extra_regs; 7989 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 7990 x86_pmu.pebs_prec_dist = true; 7991 /* all extra regs are per-cpu when HT is on */ 7992 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7993 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7994 7995 x86_pmu.hw_config = hsw_hw_config; 7996 x86_pmu.get_event_constraints = hsw_get_event_constraints; 7997 x86_pmu.limit_period = hsw_limit_period; 7998 x86_pmu.lbr_double_abort = true; 7999 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8000 hsw_format_attr : nhm_format_attr; 8001 td_attr = hsw_events_attrs; 8002 mem_attr = hsw_mem_events_attrs; 8003 tsx_attr = hsw_tsx_events_attrs; 8004 pr_cont("Haswell events, "); 8005 name = "haswell"; 8006 break; 8007 8008 case INTEL_BROADWELL: 8009 case INTEL_BROADWELL_D: 8010 case INTEL_BROADWELL_G: 8011 case INTEL_BROADWELL_X: 8012 x86_add_quirk(intel_pebs_isolation_quirk); 8013 x86_pmu.late_ack = true; 8014 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 8015 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 8016 8017 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 8018 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 8019 BDW_L3_MISS|HSW_SNOOP_DRAM; 8020 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 8021 HSW_SNOOP_DRAM; 8022 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 8023 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 8024 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 8025 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 8026 8027 intel_pmu_lbr_init_hsw(); 8028 8029 x86_pmu.event_constraints = intel_bdw_event_constraints; 8030 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 8031 x86_pmu.extra_regs = intel_snbep_extra_regs; 8032 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 8033 x86_pmu.pebs_prec_dist = true; 8034 /* all extra regs are per-cpu when HT is on */ 8035 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8036 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 8037 8038 x86_pmu.hw_config = hsw_hw_config; 8039 x86_pmu.get_event_constraints = hsw_get_event_constraints; 8040 x86_pmu.limit_period = bdw_limit_period; 8041 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8042 hsw_format_attr : nhm_format_attr; 8043 td_attr = hsw_events_attrs; 8044 mem_attr = hsw_mem_events_attrs; 8045 tsx_attr = hsw_tsx_events_attrs; 8046 pr_cont("Broadwell events, "); 8047 name = "broadwell"; 8048 break; 8049 8050 case INTEL_XEON_PHI_KNL: 8051 case INTEL_XEON_PHI_KNM: 8052 memcpy(hw_cache_event_ids, 8053 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 8054 memcpy(hw_cache_extra_regs, 8055 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 8056 intel_pmu_lbr_init_knl(); 8057 8058 x86_pmu.event_constraints = intel_slm_event_constraints; 8059 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 8060 x86_pmu.extra_regs = intel_knl_extra_regs; 8061 8062 /* all extra regs are per-cpu when HT is on */ 8063 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8064 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 8065 extra_attr = slm_format_attr; 8066 pr_cont("Knights Landing/Mill events, "); 8067 name = "knights-landing"; 8068 break; 8069 8070 case INTEL_SKYLAKE_X: 8071 pmem = true; 8072 fallthrough; 8073 case INTEL_SKYLAKE_L: 8074 case INTEL_SKYLAKE: 8075 case INTEL_KABYLAKE_L: 8076 case INTEL_KABYLAKE: 8077 case INTEL_COMETLAKE_L: 8078 case INTEL_COMETLAKE: 8079 x86_add_quirk(intel_pebs_isolation_quirk); 8080 x86_pmu.late_ack = true; 8081 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 8082 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 8083 intel_pmu_lbr_init_skl(); 8084 8085 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 8086 event_attr_td_recovery_bubbles.event_str_noht = 8087 "event=0xd,umask=0x1,cmask=1"; 8088 event_attr_td_recovery_bubbles.event_str_ht = 8089 "event=0xd,umask=0x1,cmask=1,any=1"; 8090 8091 x86_pmu.event_constraints = intel_skl_event_constraints; 8092 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 8093 x86_pmu.extra_regs = intel_skl_extra_regs; 8094 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 8095 x86_pmu.pebs_prec_dist = true; 8096 /* all extra regs are per-cpu when HT is on */ 8097 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8098 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 8099 8100 x86_pmu.hw_config = hsw_hw_config; 8101 x86_pmu.get_event_constraints = hsw_get_event_constraints; 8102 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8103 hsw_format_attr : nhm_format_attr; 8104 extra_skl_attr = skl_format_attr; 8105 td_attr = hsw_events_attrs; 8106 mem_attr = hsw_mem_events_attrs; 8107 tsx_attr = hsw_tsx_events_attrs; 8108 intel_pmu_pebs_data_source_skl(pmem); 8109 8110 /* 8111 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. 8112 * TSX force abort hooks are not required on these systems. Only deploy 8113 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. 8114 */ 8115 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && 8116 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { 8117 x86_pmu.flags |= PMU_FL_TFA; 8118 x86_pmu.get_event_constraints = tfa_get_event_constraints; 8119 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 8120 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 8121 } 8122 8123 pr_cont("Skylake events, "); 8124 name = "skylake"; 8125 break; 8126 8127 case INTEL_ICELAKE_X: 8128 case INTEL_ICELAKE_D: 8129 x86_pmu.pebs_ept = 1; 8130 pmem = true; 8131 fallthrough; 8132 case INTEL_ICELAKE_L: 8133 case INTEL_ICELAKE: 8134 case INTEL_TIGERLAKE_L: 8135 case INTEL_TIGERLAKE: 8136 case INTEL_ROCKETLAKE: 8137 x86_pmu.late_ack = true; 8138 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 8139 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 8140 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 8141 intel_pmu_lbr_init_skl(); 8142 8143 x86_pmu.event_constraints = intel_icl_event_constraints; 8144 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 8145 x86_pmu.extra_regs = intel_icl_extra_regs; 8146 x86_pmu.pebs_aliases = NULL; 8147 x86_pmu.pebs_prec_dist = true; 8148 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8149 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 8150 8151 x86_pmu.hw_config = hsw_hw_config; 8152 x86_pmu.get_event_constraints = icl_get_event_constraints; 8153 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8154 hsw_format_attr : nhm_format_attr; 8155 extra_skl_attr = skl_format_attr; 8156 mem_attr = icl_events_attrs; 8157 td_attr = icl_td_events_attrs; 8158 tsx_attr = icl_tsx_events_attrs; 8159 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 8160 x86_pmu.lbr_pt_coexist = true; 8161 intel_pmu_pebs_data_source_skl(pmem); 8162 x86_pmu.num_topdown_events = 4; 8163 static_call_update(intel_pmu_update_topdown_event, 8164 &icl_update_topdown_event); 8165 static_call_update(intel_pmu_set_topdown_event_period, 8166 &icl_set_topdown_event_period); 8167 pr_cont("Icelake events, "); 8168 name = "icelake"; 8169 break; 8170 8171 case INTEL_SAPPHIRERAPIDS_X: 8172 case INTEL_EMERALDRAPIDS_X: 8173 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 8174 x86_pmu.extra_regs = intel_glc_extra_regs; 8175 pr_cont("Sapphire Rapids events, "); 8176 name = "sapphire_rapids"; 8177 goto glc_common; 8178 8179 case INTEL_GRANITERAPIDS_X: 8180 case INTEL_GRANITERAPIDS_D: 8181 x86_pmu.extra_regs = intel_rwc_extra_regs; 8182 pr_cont("Granite Rapids events, "); 8183 name = "granite_rapids"; 8184 goto glc_common; 8185 8186 case INTEL_DIAMONDRAPIDS_X: 8187 intel_pmu_init_pnc(NULL); 8188 x86_pmu.pebs_latency_data = pnc_latency_data; 8189 8190 pr_cont("Panthercove events, "); 8191 name = "panthercove"; 8192 goto glc_base; 8193 8194 glc_common: 8195 intel_pmu_init_glc(NULL); 8196 intel_pmu_pebs_data_source_skl(true); 8197 8198 glc_base: 8199 x86_pmu.pebs_ept = 1; 8200 x86_pmu.hw_config = hsw_hw_config; 8201 x86_pmu.get_event_constraints = glc_get_event_constraints; 8202 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8203 hsw_format_attr : nhm_format_attr; 8204 extra_skl_attr = skl_format_attr; 8205 mem_attr = glc_events_attrs; 8206 td_attr = glc_td_events_attrs; 8207 tsx_attr = glc_tsx_events_attrs; 8208 break; 8209 8210 case INTEL_ALDERLAKE: 8211 case INTEL_ALDERLAKE_L: 8212 case INTEL_RAPTORLAKE: 8213 case INTEL_RAPTORLAKE_P: 8214 case INTEL_RAPTORLAKE_S: 8215 /* 8216 * Alder Lake has 2 types of CPU, core and atom. 8217 * 8218 * Initialize the common PerfMon capabilities here. 8219 */ 8220 intel_pmu_init_hybrid(hybrid_big_small); 8221 8222 x86_pmu.pebs_latency_data = grt_latency_data; 8223 x86_pmu.get_event_constraints = adl_get_event_constraints; 8224 x86_pmu.hw_config = adl_hw_config; 8225 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; 8226 8227 td_attr = adl_hybrid_events_attrs; 8228 mem_attr = adl_hybrid_mem_attrs; 8229 tsx_attr = adl_hybrid_tsx_attrs; 8230 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8231 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; 8232 8233 /* Initialize big core specific PerfMon capabilities.*/ 8234 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 8235 intel_pmu_init_glc(&pmu->pmu); 8236 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 8237 pmu->cntr_mask64 <<= 2; 8238 pmu->cntr_mask64 |= 0x3; 8239 pmu->fixed_cntr_mask64 <<= 1; 8240 pmu->fixed_cntr_mask64 |= 0x1; 8241 } else { 8242 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 8243 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 8244 } 8245 8246 /* 8247 * Quirk: For some Alder Lake machine, when all E-cores are disabled in 8248 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However, 8249 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will 8250 * mistakenly add extra counters for P-cores. Correct the number of 8251 * counters here. 8252 */ 8253 if ((x86_pmu_num_counters(&pmu->pmu) > 8) || (x86_pmu_num_counters_fixed(&pmu->pmu) > 4)) { 8254 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 8255 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 8256 } 8257 8258 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 8259 pmu->unconstrained = (struct event_constraint) 8260 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 8261 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 8262 8263 pmu->extra_regs = intel_glc_extra_regs; 8264 8265 /* Initialize Atom core specific PerfMon capabilities.*/ 8266 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 8267 intel_pmu_init_grt(&pmu->pmu); 8268 8269 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 8270 intel_pmu_pebs_data_source_adl(); 8271 pr_cont("Alderlake Hybrid events, "); 8272 name = "alderlake_hybrid"; 8273 break; 8274 8275 case INTEL_METEORLAKE: 8276 case INTEL_METEORLAKE_L: 8277 case INTEL_ARROWLAKE_U: 8278 intel_pmu_init_hybrid(hybrid_big_small); 8279 8280 x86_pmu.pebs_latency_data = cmt_latency_data; 8281 x86_pmu.get_event_constraints = mtl_get_event_constraints; 8282 x86_pmu.hw_config = adl_hw_config; 8283 8284 td_attr = adl_hybrid_events_attrs; 8285 mem_attr = mtl_hybrid_mem_attrs; 8286 tsx_attr = adl_hybrid_tsx_attrs; 8287 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8288 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 8289 8290 /* Initialize big core specific PerfMon capabilities.*/ 8291 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 8292 intel_pmu_init_glc(&pmu->pmu); 8293 pmu->extra_regs = intel_rwc_extra_regs; 8294 8295 /* Initialize Atom core specific PerfMon capabilities.*/ 8296 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 8297 intel_pmu_init_grt(&pmu->pmu); 8298 pmu->extra_regs = intel_cmt_extra_regs; 8299 8300 intel_pmu_pebs_data_source_mtl(); 8301 pr_cont("Meteorlake Hybrid events, "); 8302 name = "meteorlake_hybrid"; 8303 break; 8304 8305 case INTEL_PANTHERLAKE_L: 8306 case INTEL_WILDCATLAKE_L: 8307 pr_cont("Pantherlake Hybrid events, "); 8308 name = "pantherlake_hybrid"; 8309 goto lnl_common; 8310 8311 case INTEL_LUNARLAKE_M: 8312 case INTEL_ARROWLAKE: 8313 pr_cont("Lunarlake Hybrid events, "); 8314 name = "lunarlake_hybrid"; 8315 8316 lnl_common: 8317 intel_pmu_init_hybrid(hybrid_big_small); 8318 8319 x86_pmu.pebs_latency_data = lnl_latency_data; 8320 x86_pmu.get_event_constraints = mtl_get_event_constraints; 8321 x86_pmu.hw_config = adl_hw_config; 8322 8323 td_attr = lnl_hybrid_events_attrs; 8324 mem_attr = mtl_hybrid_mem_attrs; 8325 tsx_attr = adl_hybrid_tsx_attrs; 8326 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8327 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 8328 8329 /* Initialize big core specific PerfMon capabilities.*/ 8330 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 8331 intel_pmu_init_lnc(&pmu->pmu); 8332 8333 /* Initialize Atom core specific PerfMon capabilities.*/ 8334 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 8335 intel_pmu_init_skt(&pmu->pmu); 8336 8337 intel_pmu_pebs_data_source_lnl(); 8338 break; 8339 8340 case INTEL_ARROWLAKE_H: 8341 intel_pmu_init_hybrid(hybrid_big_small_tiny); 8342 8343 x86_pmu.pebs_latency_data = arl_h_latency_data; 8344 x86_pmu.get_event_constraints = arl_h_get_event_constraints; 8345 x86_pmu.hw_config = arl_h_hw_config; 8346 8347 td_attr = arl_h_hybrid_events_attrs; 8348 mem_attr = arl_h_hybrid_mem_attrs; 8349 tsx_attr = adl_hybrid_tsx_attrs; 8350 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8351 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 8352 8353 /* Initialize big core specific PerfMon capabilities. */ 8354 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 8355 intel_pmu_init_lnc(&pmu->pmu); 8356 8357 /* Initialize Atom core specific PerfMon capabilities. */ 8358 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 8359 intel_pmu_init_skt(&pmu->pmu); 8360 8361 /* Initialize Lower Power Atom specific PerfMon capabilities. */ 8362 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX]; 8363 intel_pmu_init_grt(&pmu->pmu); 8364 pmu->extra_regs = intel_cmt_extra_regs; 8365 8366 intel_pmu_pebs_data_source_arl_h(); 8367 pr_cont("ArrowLake-H Hybrid events, "); 8368 name = "arrowlake_h_hybrid"; 8369 break; 8370 8371 case INTEL_NOVALAKE: 8372 case INTEL_NOVALAKE_L: 8373 pr_cont("Novalake Hybrid events, "); 8374 name = "novalake_hybrid"; 8375 intel_pmu_init_hybrid(hybrid_big_small); 8376 8377 x86_pmu.pebs_latency_data = nvl_latency_data; 8378 x86_pmu.get_event_constraints = mtl_get_event_constraints; 8379 x86_pmu.hw_config = adl_hw_config; 8380 8381 td_attr = lnl_hybrid_events_attrs; 8382 mem_attr = mtl_hybrid_mem_attrs; 8383 tsx_attr = adl_hybrid_tsx_attrs; 8384 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8385 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 8386 8387 /* Initialize big core specific PerfMon capabilities.*/ 8388 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 8389 intel_pmu_init_pnc(&pmu->pmu); 8390 8391 /* Initialize Atom core specific PerfMon capabilities.*/ 8392 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 8393 intel_pmu_init_arw(&pmu->pmu); 8394 8395 intel_pmu_pebs_data_source_lnl(); 8396 break; 8397 8398 default: 8399 switch (x86_pmu.version) { 8400 case 1: 8401 x86_pmu.event_constraints = intel_v1_event_constraints; 8402 pr_cont("generic architected perfmon v1, "); 8403 name = "generic_arch_v1"; 8404 break; 8405 case 2: 8406 case 3: 8407 case 4: 8408 /* 8409 * default constraints for v2 and up 8410 */ 8411 x86_pmu.event_constraints = intel_gen_event_constraints; 8412 pr_cont("generic architected perfmon, "); 8413 name = "generic_arch_v2+"; 8414 break; 8415 default: 8416 /* 8417 * The default constraints for v5 and up can support up to 8418 * 16 fixed counters. For the fixed counters 4 and later, 8419 * the pseudo-encoding is applied. 8420 * The constraints may be cut according to the CPUID enumeration 8421 * by inserting the EVENT_CONSTRAINT_END. 8422 */ 8423 if (fls64(x86_pmu.fixed_cntr_mask64) > INTEL_PMC_MAX_FIXED) 8424 x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0); 8425 intel_v5_gen_event_constraints[fls64(x86_pmu.fixed_cntr_mask64)].weight = -1; 8426 x86_pmu.event_constraints = intel_v5_gen_event_constraints; 8427 pr_cont("generic architected perfmon, "); 8428 name = "generic_arch_v5+"; 8429 break; 8430 } 8431 } 8432 8433 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 8434 8435 if (!is_hybrid()) { 8436 group_events_td.attrs = td_attr; 8437 group_events_mem.attrs = mem_attr; 8438 group_events_tsx.attrs = tsx_attr; 8439 group_format_extra.attrs = extra_attr; 8440 group_format_extra_skl.attrs = extra_skl_attr; 8441 8442 x86_pmu.attr_update = attr_update; 8443 } else { 8444 hybrid_group_events_td.attrs = td_attr; 8445 hybrid_group_events_mem.attrs = mem_attr; 8446 hybrid_group_events_tsx.attrs = tsx_attr; 8447 hybrid_group_format_extra.attrs = extra_attr; 8448 8449 x86_pmu.attr_update = hybrid_attr_update; 8450 } 8451 8452 /* 8453 * The archPerfmonExt (0x23) includes an enhanced enumeration of 8454 * PMU architectural features with a per-core view. For non-hybrid, 8455 * each core has the same PMU capabilities. It's good enough to 8456 * update the x86_pmu from the booting CPU. For hybrid, the x86_pmu 8457 * is used to keep the common capabilities. Still keep the values 8458 * from the leaf 0xa. The core specific update will be done later 8459 * when a new type is online. 8460 */ 8461 if (!is_hybrid() && boot_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) 8462 update_pmu_cap(NULL); 8463 8464 if (x86_pmu.arch_pebs) { 8465 static_call_update(intel_pmu_disable_event_ext, 8466 intel_pmu_disable_event_ext); 8467 static_call_update(intel_pmu_enable_event_ext, 8468 intel_pmu_enable_event_ext); 8469 pr_cont("Architectural PEBS, "); 8470 } 8471 8472 intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64, 8473 &x86_pmu.fixed_cntr_mask64, 8474 &x86_pmu.intel_ctrl); 8475 8476 /* AnyThread may be deprecated on arch perfmon v5 or later */ 8477 if (x86_pmu.intel_cap.anythread_deprecated) 8478 x86_pmu.format_attrs = intel_arch_formats_attr; 8479 8480 intel_pmu_check_event_constraints_all(NULL); 8481 8482 /* 8483 * Access LBR MSR may cause #GP under certain circumstances. 8484 * Check all LBR MSR here. 8485 * Disable LBR access if any LBR MSRs can not be accessed. 8486 */ 8487 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 8488 x86_pmu.lbr_nr = 0; 8489 for (i = 0; i < x86_pmu.lbr_nr; i++) { 8490 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 8491 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 8492 x86_pmu.lbr_nr = 0; 8493 } 8494 8495 if (x86_pmu.lbr_nr) { 8496 intel_pmu_lbr_init(); 8497 8498 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 8499 8500 /* only support branch_stack snapshot for perfmon >= v2 */ 8501 if (x86_pmu.disable_all == intel_pmu_disable_all) { 8502 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) { 8503 static_call_update(perf_snapshot_branch_stack, 8504 intel_pmu_snapshot_arch_branch_stack); 8505 } else { 8506 static_call_update(perf_snapshot_branch_stack, 8507 intel_pmu_snapshot_branch_stack); 8508 } 8509 } 8510 } 8511 8512 intel_pmu_check_extra_regs(x86_pmu.extra_regs); 8513 8514 /* Support full width counters using alternative MSR range */ 8515 if (x86_pmu.intel_cap.full_width_write) { 8516 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 8517 x86_pmu.perfctr = MSR_IA32_PMC0; 8518 pr_cont("full-width counters, "); 8519 } 8520 8521 /* Support V6+ MSR Aliasing */ 8522 if (x86_pmu.version >= 6) { 8523 x86_pmu.perfctr = MSR_IA32_PMC_V6_GP0_CTR; 8524 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A; 8525 x86_pmu.fixedctr = MSR_IA32_PMC_V6_FX0_CTR; 8526 x86_pmu.addr_offset = intel_pmu_v6_addr_offset; 8527 } 8528 8529 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 8530 x86_pmu.intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS; 8531 8532 if (x86_pmu.intel_cap.pebs_timing_info) 8533 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY; 8534 8535 intel_aux_output_init(); 8536 8537 return 0; 8538 } 8539 8540 /* 8541 * HT bug: phase 2 init 8542 * Called once we have valid topology information to check 8543 * whether or not HT is enabled 8544 * If HT is off, then we disable the workaround 8545 */ 8546 static __init int fixup_ht_bug(void) 8547 { 8548 int c; 8549 /* 8550 * problem not present on this CPU model, nothing to do 8551 */ 8552 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 8553 return 0; 8554 8555 if (topology_max_smt_threads() > 1) { 8556 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 8557 return 0; 8558 } 8559 8560 cpus_read_lock(); 8561 8562 hardlockup_detector_perf_stop(); 8563 8564 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 8565 8566 x86_pmu.start_scheduling = NULL; 8567 x86_pmu.commit_scheduling = NULL; 8568 x86_pmu.stop_scheduling = NULL; 8569 8570 hardlockup_detector_perf_restart(); 8571 8572 for_each_online_cpu(c) 8573 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 8574 8575 cpus_read_unlock(); 8576 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 8577 return 0; 8578 } 8579 subsys_initcall(fixup_ht_bug) 8580