1 /* 2 * Per core/cpu state 3 * 4 * Used to coordinate shared registers between HT threads or 5 * among events on a single PMU. 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/stddef.h> 11 #include <linux/types.h> 12 #include <linux/init.h> 13 #include <linux/slab.h> 14 #include <linux/export.h> 15 #include <linux/nmi.h> 16 17 #include <asm/cpufeature.h> 18 #include <asm/hardirq.h> 19 #include <asm/intel-family.h> 20 #include <asm/apic.h> 21 22 #include "../perf_event.h" 23 24 /* 25 * Intel PerfMon, used on Core and later. 26 */ 27 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 28 { 29 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 30 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 31 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 32 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 33 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 34 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 35 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 36 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 37 }; 38 39 static struct event_constraint intel_core_event_constraints[] __read_mostly = 40 { 41 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 42 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 43 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 44 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 45 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 46 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 47 EVENT_CONSTRAINT_END 48 }; 49 50 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 51 { 52 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 53 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 54 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 55 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 56 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 57 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 58 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 59 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 60 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 61 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 62 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 63 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 64 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 65 EVENT_CONSTRAINT_END 66 }; 67 68 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 69 { 70 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 71 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 72 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 73 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 74 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 75 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 76 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 77 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 78 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 79 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 80 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 81 EVENT_CONSTRAINT_END 82 }; 83 84 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 85 { 86 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 87 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 88 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 89 EVENT_EXTRA_END 90 }; 91 92 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 93 { 94 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 95 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 96 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 97 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 98 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 99 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 100 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 101 EVENT_CONSTRAINT_END 102 }; 103 104 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 105 { 106 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 107 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 108 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 109 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 110 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 111 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 112 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 113 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 114 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 115 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 116 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 117 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 118 119 /* 120 * When HT is off these events can only run on the bottom 4 counters 121 * When HT is on, they are impacted by the HT bug and require EXCL access 122 */ 123 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 124 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 125 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 126 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 127 128 EVENT_CONSTRAINT_END 129 }; 130 131 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 132 { 133 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 134 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 135 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 136 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 137 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */ 138 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 139 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 140 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 141 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 142 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 143 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 144 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 145 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 146 147 /* 148 * When HT is off these events can only run on the bottom 4 counters 149 * When HT is on, they are impacted by the HT bug and require EXCL access 150 */ 151 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 152 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 153 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 154 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 155 156 EVENT_CONSTRAINT_END 157 }; 158 159 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 160 { 161 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 162 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 163 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 164 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 165 EVENT_EXTRA_END 166 }; 167 168 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 169 { 170 EVENT_CONSTRAINT_END 171 }; 172 173 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 174 { 175 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 176 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 177 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 178 EVENT_CONSTRAINT_END 179 }; 180 181 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 182 { 183 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 184 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 185 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 186 EVENT_CONSTRAINT_END 187 }; 188 189 static struct event_constraint intel_skl_event_constraints[] = { 190 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 191 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 192 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 193 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 194 195 /* 196 * when HT is off, these can only run on the bottom 4 counters 197 */ 198 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 199 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 200 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 201 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 202 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 203 204 EVENT_CONSTRAINT_END 205 }; 206 207 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 208 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 209 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 210 EVENT_EXTRA_END 211 }; 212 213 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 214 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 215 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 216 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 217 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 218 EVENT_EXTRA_END 219 }; 220 221 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 222 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 223 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 224 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 225 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 226 EVENT_EXTRA_END 227 }; 228 229 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 230 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 231 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 232 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 233 /* 234 * Note the low 8 bits eventsel code is not a continuous field, containing 235 * some #GPing bits. These are masked out. 236 */ 237 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 238 EVENT_EXTRA_END 239 }; 240 241 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 242 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 243 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 244 245 static struct attribute *nhm_mem_events_attrs[] = { 246 EVENT_PTR(mem_ld_nhm), 247 NULL, 248 }; 249 250 /* 251 * topdown events for Intel Core CPUs. 252 * 253 * The events are all in slots, which is a free slot in a 4 wide 254 * pipeline. Some events are already reported in slots, for cycle 255 * events we multiply by the pipeline width (4). 256 * 257 * With Hyper Threading on, topdown metrics are either summed or averaged 258 * between the threads of a core: (count_t0 + count_t1). 259 * 260 * For the average case the metric is always scaled to pipeline width, 261 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 262 */ 263 264 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 265 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 266 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 267 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 268 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 269 "event=0xe,umask=0x1"); /* uops_issued.any */ 270 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 271 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 272 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 273 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 274 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 275 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 276 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 277 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 278 "4", "2"); 279 280 static struct attribute *snb_events_attrs[] = { 281 EVENT_PTR(td_slots_issued), 282 EVENT_PTR(td_slots_retired), 283 EVENT_PTR(td_fetch_bubbles), 284 EVENT_PTR(td_total_slots), 285 EVENT_PTR(td_total_slots_scale), 286 EVENT_PTR(td_recovery_bubbles), 287 EVENT_PTR(td_recovery_bubbles_scale), 288 NULL, 289 }; 290 291 static struct attribute *snb_mem_events_attrs[] = { 292 EVENT_PTR(mem_ld_snb), 293 EVENT_PTR(mem_st_snb), 294 NULL, 295 }; 296 297 static struct event_constraint intel_hsw_event_constraints[] = { 298 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 299 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 300 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 301 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 302 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 303 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 304 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 305 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 306 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 307 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 308 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 309 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 310 311 /* 312 * When HT is off these events can only run on the bottom 4 counters 313 * When HT is on, they are impacted by the HT bug and require EXCL access 314 */ 315 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 316 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 317 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 318 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 319 320 EVENT_CONSTRAINT_END 321 }; 322 323 static struct event_constraint intel_bdw_event_constraints[] = { 324 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 325 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 326 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 327 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 328 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 329 /* 330 * when HT is off, these can only run on the bottom 4 counters 331 */ 332 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 333 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 334 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 335 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 336 EVENT_CONSTRAINT_END 337 }; 338 339 static u64 intel_pmu_event_map(int hw_event) 340 { 341 return intel_perfmon_event_map[hw_event]; 342 } 343 344 /* 345 * Notes on the events: 346 * - data reads do not include code reads (comparable to earlier tables) 347 * - data counts include speculative execution (except L1 write, dtlb, bpu) 348 * - remote node access includes remote memory, remote cache, remote mmio. 349 * - prefetches are not included in the counts. 350 * - icache miss does not include decoded icache 351 */ 352 353 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 354 #define SKL_DEMAND_RFO BIT_ULL(1) 355 #define SKL_ANY_RESPONSE BIT_ULL(16) 356 #define SKL_SUPPLIER_NONE BIT_ULL(17) 357 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 358 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 359 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 360 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 361 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 362 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 363 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 364 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 365 #define SKL_SPL_HIT BIT_ULL(30) 366 #define SKL_SNOOP_NONE BIT_ULL(31) 367 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 368 #define SKL_SNOOP_MISS BIT_ULL(33) 369 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 370 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 371 #define SKL_SNOOP_HITM BIT_ULL(36) 372 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 373 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 374 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 375 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 376 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 377 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 378 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 379 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 380 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 381 SKL_SNOOP_HITM|SKL_SPL_HIT) 382 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 383 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 384 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 385 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 386 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 387 388 static __initconst const u64 skl_hw_cache_event_ids 389 [PERF_COUNT_HW_CACHE_MAX] 390 [PERF_COUNT_HW_CACHE_OP_MAX] 391 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 392 { 393 [ C(L1D ) ] = { 394 [ C(OP_READ) ] = { 395 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 396 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 397 }, 398 [ C(OP_WRITE) ] = { 399 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 400 [ C(RESULT_MISS) ] = 0x0, 401 }, 402 [ C(OP_PREFETCH) ] = { 403 [ C(RESULT_ACCESS) ] = 0x0, 404 [ C(RESULT_MISS) ] = 0x0, 405 }, 406 }, 407 [ C(L1I ) ] = { 408 [ C(OP_READ) ] = { 409 [ C(RESULT_ACCESS) ] = 0x0, 410 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 411 }, 412 [ C(OP_WRITE) ] = { 413 [ C(RESULT_ACCESS) ] = -1, 414 [ C(RESULT_MISS) ] = -1, 415 }, 416 [ C(OP_PREFETCH) ] = { 417 [ C(RESULT_ACCESS) ] = 0x0, 418 [ C(RESULT_MISS) ] = 0x0, 419 }, 420 }, 421 [ C(LL ) ] = { 422 [ C(OP_READ) ] = { 423 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 424 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 425 }, 426 [ C(OP_WRITE) ] = { 427 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 428 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 429 }, 430 [ C(OP_PREFETCH) ] = { 431 [ C(RESULT_ACCESS) ] = 0x0, 432 [ C(RESULT_MISS) ] = 0x0, 433 }, 434 }, 435 [ C(DTLB) ] = { 436 [ C(OP_READ) ] = { 437 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 438 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 439 }, 440 [ C(OP_WRITE) ] = { 441 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 442 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 443 }, 444 [ C(OP_PREFETCH) ] = { 445 [ C(RESULT_ACCESS) ] = 0x0, 446 [ C(RESULT_MISS) ] = 0x0, 447 }, 448 }, 449 [ C(ITLB) ] = { 450 [ C(OP_READ) ] = { 451 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 452 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 453 }, 454 [ C(OP_WRITE) ] = { 455 [ C(RESULT_ACCESS) ] = -1, 456 [ C(RESULT_MISS) ] = -1, 457 }, 458 [ C(OP_PREFETCH) ] = { 459 [ C(RESULT_ACCESS) ] = -1, 460 [ C(RESULT_MISS) ] = -1, 461 }, 462 }, 463 [ C(BPU ) ] = { 464 [ C(OP_READ) ] = { 465 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 466 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 467 }, 468 [ C(OP_WRITE) ] = { 469 [ C(RESULT_ACCESS) ] = -1, 470 [ C(RESULT_MISS) ] = -1, 471 }, 472 [ C(OP_PREFETCH) ] = { 473 [ C(RESULT_ACCESS) ] = -1, 474 [ C(RESULT_MISS) ] = -1, 475 }, 476 }, 477 [ C(NODE) ] = { 478 [ C(OP_READ) ] = { 479 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 480 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 481 }, 482 [ C(OP_WRITE) ] = { 483 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 484 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 485 }, 486 [ C(OP_PREFETCH) ] = { 487 [ C(RESULT_ACCESS) ] = 0x0, 488 [ C(RESULT_MISS) ] = 0x0, 489 }, 490 }, 491 }; 492 493 static __initconst const u64 skl_hw_cache_extra_regs 494 [PERF_COUNT_HW_CACHE_MAX] 495 [PERF_COUNT_HW_CACHE_OP_MAX] 496 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 497 { 498 [ C(LL ) ] = { 499 [ C(OP_READ) ] = { 500 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 501 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 502 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 503 SKL_L3_MISS|SKL_ANY_SNOOP| 504 SKL_SUPPLIER_NONE, 505 }, 506 [ C(OP_WRITE) ] = { 507 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 508 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 509 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 510 SKL_L3_MISS|SKL_ANY_SNOOP| 511 SKL_SUPPLIER_NONE, 512 }, 513 [ C(OP_PREFETCH) ] = { 514 [ C(RESULT_ACCESS) ] = 0x0, 515 [ C(RESULT_MISS) ] = 0x0, 516 }, 517 }, 518 [ C(NODE) ] = { 519 [ C(OP_READ) ] = { 520 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 521 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 522 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 523 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 524 }, 525 [ C(OP_WRITE) ] = { 526 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 527 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 528 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 529 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 530 }, 531 [ C(OP_PREFETCH) ] = { 532 [ C(RESULT_ACCESS) ] = 0x0, 533 [ C(RESULT_MISS) ] = 0x0, 534 }, 535 }, 536 }; 537 538 #define SNB_DMND_DATA_RD (1ULL << 0) 539 #define SNB_DMND_RFO (1ULL << 1) 540 #define SNB_DMND_IFETCH (1ULL << 2) 541 #define SNB_DMND_WB (1ULL << 3) 542 #define SNB_PF_DATA_RD (1ULL << 4) 543 #define SNB_PF_RFO (1ULL << 5) 544 #define SNB_PF_IFETCH (1ULL << 6) 545 #define SNB_LLC_DATA_RD (1ULL << 7) 546 #define SNB_LLC_RFO (1ULL << 8) 547 #define SNB_LLC_IFETCH (1ULL << 9) 548 #define SNB_BUS_LOCKS (1ULL << 10) 549 #define SNB_STRM_ST (1ULL << 11) 550 #define SNB_OTHER (1ULL << 15) 551 #define SNB_RESP_ANY (1ULL << 16) 552 #define SNB_NO_SUPP (1ULL << 17) 553 #define SNB_LLC_HITM (1ULL << 18) 554 #define SNB_LLC_HITE (1ULL << 19) 555 #define SNB_LLC_HITS (1ULL << 20) 556 #define SNB_LLC_HITF (1ULL << 21) 557 #define SNB_LOCAL (1ULL << 22) 558 #define SNB_REMOTE (0xffULL << 23) 559 #define SNB_SNP_NONE (1ULL << 31) 560 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 561 #define SNB_SNP_MISS (1ULL << 33) 562 #define SNB_NO_FWD (1ULL << 34) 563 #define SNB_SNP_FWD (1ULL << 35) 564 #define SNB_HITM (1ULL << 36) 565 #define SNB_NON_DRAM (1ULL << 37) 566 567 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 568 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 569 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 570 571 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 572 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 573 SNB_HITM) 574 575 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 576 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 577 578 #define SNB_L3_ACCESS SNB_RESP_ANY 579 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 580 581 static __initconst const u64 snb_hw_cache_extra_regs 582 [PERF_COUNT_HW_CACHE_MAX] 583 [PERF_COUNT_HW_CACHE_OP_MAX] 584 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 585 { 586 [ C(LL ) ] = { 587 [ C(OP_READ) ] = { 588 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 589 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 590 }, 591 [ C(OP_WRITE) ] = { 592 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 593 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 594 }, 595 [ C(OP_PREFETCH) ] = { 596 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 597 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 598 }, 599 }, 600 [ C(NODE) ] = { 601 [ C(OP_READ) ] = { 602 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 603 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 604 }, 605 [ C(OP_WRITE) ] = { 606 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 607 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 608 }, 609 [ C(OP_PREFETCH) ] = { 610 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 611 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 612 }, 613 }, 614 }; 615 616 static __initconst const u64 snb_hw_cache_event_ids 617 [PERF_COUNT_HW_CACHE_MAX] 618 [PERF_COUNT_HW_CACHE_OP_MAX] 619 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 620 { 621 [ C(L1D) ] = { 622 [ C(OP_READ) ] = { 623 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 624 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 625 }, 626 [ C(OP_WRITE) ] = { 627 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 628 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 629 }, 630 [ C(OP_PREFETCH) ] = { 631 [ C(RESULT_ACCESS) ] = 0x0, 632 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 633 }, 634 }, 635 [ C(L1I ) ] = { 636 [ C(OP_READ) ] = { 637 [ C(RESULT_ACCESS) ] = 0x0, 638 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 639 }, 640 [ C(OP_WRITE) ] = { 641 [ C(RESULT_ACCESS) ] = -1, 642 [ C(RESULT_MISS) ] = -1, 643 }, 644 [ C(OP_PREFETCH) ] = { 645 [ C(RESULT_ACCESS) ] = 0x0, 646 [ C(RESULT_MISS) ] = 0x0, 647 }, 648 }, 649 [ C(LL ) ] = { 650 [ C(OP_READ) ] = { 651 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 652 [ C(RESULT_ACCESS) ] = 0x01b7, 653 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 654 [ C(RESULT_MISS) ] = 0x01b7, 655 }, 656 [ C(OP_WRITE) ] = { 657 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 658 [ C(RESULT_ACCESS) ] = 0x01b7, 659 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 660 [ C(RESULT_MISS) ] = 0x01b7, 661 }, 662 [ C(OP_PREFETCH) ] = { 663 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 664 [ C(RESULT_ACCESS) ] = 0x01b7, 665 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 666 [ C(RESULT_MISS) ] = 0x01b7, 667 }, 668 }, 669 [ C(DTLB) ] = { 670 [ C(OP_READ) ] = { 671 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 672 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 673 }, 674 [ C(OP_WRITE) ] = { 675 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 676 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 677 }, 678 [ C(OP_PREFETCH) ] = { 679 [ C(RESULT_ACCESS) ] = 0x0, 680 [ C(RESULT_MISS) ] = 0x0, 681 }, 682 }, 683 [ C(ITLB) ] = { 684 [ C(OP_READ) ] = { 685 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 686 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 687 }, 688 [ C(OP_WRITE) ] = { 689 [ C(RESULT_ACCESS) ] = -1, 690 [ C(RESULT_MISS) ] = -1, 691 }, 692 [ C(OP_PREFETCH) ] = { 693 [ C(RESULT_ACCESS) ] = -1, 694 [ C(RESULT_MISS) ] = -1, 695 }, 696 }, 697 [ C(BPU ) ] = { 698 [ C(OP_READ) ] = { 699 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 700 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 701 }, 702 [ C(OP_WRITE) ] = { 703 [ C(RESULT_ACCESS) ] = -1, 704 [ C(RESULT_MISS) ] = -1, 705 }, 706 [ C(OP_PREFETCH) ] = { 707 [ C(RESULT_ACCESS) ] = -1, 708 [ C(RESULT_MISS) ] = -1, 709 }, 710 }, 711 [ C(NODE) ] = { 712 [ C(OP_READ) ] = { 713 [ C(RESULT_ACCESS) ] = 0x01b7, 714 [ C(RESULT_MISS) ] = 0x01b7, 715 }, 716 [ C(OP_WRITE) ] = { 717 [ C(RESULT_ACCESS) ] = 0x01b7, 718 [ C(RESULT_MISS) ] = 0x01b7, 719 }, 720 [ C(OP_PREFETCH) ] = { 721 [ C(RESULT_ACCESS) ] = 0x01b7, 722 [ C(RESULT_MISS) ] = 0x01b7, 723 }, 724 }, 725 726 }; 727 728 /* 729 * Notes on the events: 730 * - data reads do not include code reads (comparable to earlier tables) 731 * - data counts include speculative execution (except L1 write, dtlb, bpu) 732 * - remote node access includes remote memory, remote cache, remote mmio. 733 * - prefetches are not included in the counts because they are not 734 * reliably counted. 735 */ 736 737 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 738 #define HSW_DEMAND_RFO BIT_ULL(1) 739 #define HSW_ANY_RESPONSE BIT_ULL(16) 740 #define HSW_SUPPLIER_NONE BIT_ULL(17) 741 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 742 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 743 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 744 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 745 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 746 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 747 HSW_L3_MISS_REMOTE_HOP2P) 748 #define HSW_SNOOP_NONE BIT_ULL(31) 749 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 750 #define HSW_SNOOP_MISS BIT_ULL(33) 751 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 752 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 753 #define HSW_SNOOP_HITM BIT_ULL(36) 754 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 755 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 756 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 757 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 758 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 759 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 760 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 761 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 762 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 763 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 764 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 765 766 #define BDW_L3_MISS_LOCAL BIT(26) 767 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 768 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 769 HSW_L3_MISS_REMOTE_HOP2P) 770 771 772 static __initconst const u64 hsw_hw_cache_event_ids 773 [PERF_COUNT_HW_CACHE_MAX] 774 [PERF_COUNT_HW_CACHE_OP_MAX] 775 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 776 { 777 [ C(L1D ) ] = { 778 [ C(OP_READ) ] = { 779 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 780 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 781 }, 782 [ C(OP_WRITE) ] = { 783 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 784 [ C(RESULT_MISS) ] = 0x0, 785 }, 786 [ C(OP_PREFETCH) ] = { 787 [ C(RESULT_ACCESS) ] = 0x0, 788 [ C(RESULT_MISS) ] = 0x0, 789 }, 790 }, 791 [ C(L1I ) ] = { 792 [ C(OP_READ) ] = { 793 [ C(RESULT_ACCESS) ] = 0x0, 794 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 795 }, 796 [ C(OP_WRITE) ] = { 797 [ C(RESULT_ACCESS) ] = -1, 798 [ C(RESULT_MISS) ] = -1, 799 }, 800 [ C(OP_PREFETCH) ] = { 801 [ C(RESULT_ACCESS) ] = 0x0, 802 [ C(RESULT_MISS) ] = 0x0, 803 }, 804 }, 805 [ C(LL ) ] = { 806 [ C(OP_READ) ] = { 807 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 808 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 809 }, 810 [ C(OP_WRITE) ] = { 811 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 812 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 813 }, 814 [ C(OP_PREFETCH) ] = { 815 [ C(RESULT_ACCESS) ] = 0x0, 816 [ C(RESULT_MISS) ] = 0x0, 817 }, 818 }, 819 [ C(DTLB) ] = { 820 [ C(OP_READ) ] = { 821 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 822 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 823 }, 824 [ C(OP_WRITE) ] = { 825 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 826 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 827 }, 828 [ C(OP_PREFETCH) ] = { 829 [ C(RESULT_ACCESS) ] = 0x0, 830 [ C(RESULT_MISS) ] = 0x0, 831 }, 832 }, 833 [ C(ITLB) ] = { 834 [ C(OP_READ) ] = { 835 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 836 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 837 }, 838 [ C(OP_WRITE) ] = { 839 [ C(RESULT_ACCESS) ] = -1, 840 [ C(RESULT_MISS) ] = -1, 841 }, 842 [ C(OP_PREFETCH) ] = { 843 [ C(RESULT_ACCESS) ] = -1, 844 [ C(RESULT_MISS) ] = -1, 845 }, 846 }, 847 [ C(BPU ) ] = { 848 [ C(OP_READ) ] = { 849 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 850 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 851 }, 852 [ C(OP_WRITE) ] = { 853 [ C(RESULT_ACCESS) ] = -1, 854 [ C(RESULT_MISS) ] = -1, 855 }, 856 [ C(OP_PREFETCH) ] = { 857 [ C(RESULT_ACCESS) ] = -1, 858 [ C(RESULT_MISS) ] = -1, 859 }, 860 }, 861 [ C(NODE) ] = { 862 [ C(OP_READ) ] = { 863 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 864 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 865 }, 866 [ C(OP_WRITE) ] = { 867 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 868 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 869 }, 870 [ C(OP_PREFETCH) ] = { 871 [ C(RESULT_ACCESS) ] = 0x0, 872 [ C(RESULT_MISS) ] = 0x0, 873 }, 874 }, 875 }; 876 877 static __initconst const u64 hsw_hw_cache_extra_regs 878 [PERF_COUNT_HW_CACHE_MAX] 879 [PERF_COUNT_HW_CACHE_OP_MAX] 880 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 881 { 882 [ C(LL ) ] = { 883 [ C(OP_READ) ] = { 884 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 885 HSW_LLC_ACCESS, 886 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 887 HSW_L3_MISS|HSW_ANY_SNOOP, 888 }, 889 [ C(OP_WRITE) ] = { 890 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 891 HSW_LLC_ACCESS, 892 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 893 HSW_L3_MISS|HSW_ANY_SNOOP, 894 }, 895 [ C(OP_PREFETCH) ] = { 896 [ C(RESULT_ACCESS) ] = 0x0, 897 [ C(RESULT_MISS) ] = 0x0, 898 }, 899 }, 900 [ C(NODE) ] = { 901 [ C(OP_READ) ] = { 902 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 903 HSW_L3_MISS_LOCAL_DRAM| 904 HSW_SNOOP_DRAM, 905 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 906 HSW_L3_MISS_REMOTE| 907 HSW_SNOOP_DRAM, 908 }, 909 [ C(OP_WRITE) ] = { 910 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 911 HSW_L3_MISS_LOCAL_DRAM| 912 HSW_SNOOP_DRAM, 913 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 914 HSW_L3_MISS_REMOTE| 915 HSW_SNOOP_DRAM, 916 }, 917 [ C(OP_PREFETCH) ] = { 918 [ C(RESULT_ACCESS) ] = 0x0, 919 [ C(RESULT_MISS) ] = 0x0, 920 }, 921 }, 922 }; 923 924 static __initconst const u64 westmere_hw_cache_event_ids 925 [PERF_COUNT_HW_CACHE_MAX] 926 [PERF_COUNT_HW_CACHE_OP_MAX] 927 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 928 { 929 [ C(L1D) ] = { 930 [ C(OP_READ) ] = { 931 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 932 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 933 }, 934 [ C(OP_WRITE) ] = { 935 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 936 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 937 }, 938 [ C(OP_PREFETCH) ] = { 939 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 940 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 941 }, 942 }, 943 [ C(L1I ) ] = { 944 [ C(OP_READ) ] = { 945 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 946 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 947 }, 948 [ C(OP_WRITE) ] = { 949 [ C(RESULT_ACCESS) ] = -1, 950 [ C(RESULT_MISS) ] = -1, 951 }, 952 [ C(OP_PREFETCH) ] = { 953 [ C(RESULT_ACCESS) ] = 0x0, 954 [ C(RESULT_MISS) ] = 0x0, 955 }, 956 }, 957 [ C(LL ) ] = { 958 [ C(OP_READ) ] = { 959 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 960 [ C(RESULT_ACCESS) ] = 0x01b7, 961 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 962 [ C(RESULT_MISS) ] = 0x01b7, 963 }, 964 /* 965 * Use RFO, not WRITEBACK, because a write miss would typically occur 966 * on RFO. 967 */ 968 [ C(OP_WRITE) ] = { 969 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 970 [ C(RESULT_ACCESS) ] = 0x01b7, 971 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 972 [ C(RESULT_MISS) ] = 0x01b7, 973 }, 974 [ C(OP_PREFETCH) ] = { 975 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 976 [ C(RESULT_ACCESS) ] = 0x01b7, 977 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 978 [ C(RESULT_MISS) ] = 0x01b7, 979 }, 980 }, 981 [ C(DTLB) ] = { 982 [ C(OP_READ) ] = { 983 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 984 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 985 }, 986 [ C(OP_WRITE) ] = { 987 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 988 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 989 }, 990 [ C(OP_PREFETCH) ] = { 991 [ C(RESULT_ACCESS) ] = 0x0, 992 [ C(RESULT_MISS) ] = 0x0, 993 }, 994 }, 995 [ C(ITLB) ] = { 996 [ C(OP_READ) ] = { 997 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 998 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 999 }, 1000 [ C(OP_WRITE) ] = { 1001 [ C(RESULT_ACCESS) ] = -1, 1002 [ C(RESULT_MISS) ] = -1, 1003 }, 1004 [ C(OP_PREFETCH) ] = { 1005 [ C(RESULT_ACCESS) ] = -1, 1006 [ C(RESULT_MISS) ] = -1, 1007 }, 1008 }, 1009 [ C(BPU ) ] = { 1010 [ C(OP_READ) ] = { 1011 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1012 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1013 }, 1014 [ C(OP_WRITE) ] = { 1015 [ C(RESULT_ACCESS) ] = -1, 1016 [ C(RESULT_MISS) ] = -1, 1017 }, 1018 [ C(OP_PREFETCH) ] = { 1019 [ C(RESULT_ACCESS) ] = -1, 1020 [ C(RESULT_MISS) ] = -1, 1021 }, 1022 }, 1023 [ C(NODE) ] = { 1024 [ C(OP_READ) ] = { 1025 [ C(RESULT_ACCESS) ] = 0x01b7, 1026 [ C(RESULT_MISS) ] = 0x01b7, 1027 }, 1028 [ C(OP_WRITE) ] = { 1029 [ C(RESULT_ACCESS) ] = 0x01b7, 1030 [ C(RESULT_MISS) ] = 0x01b7, 1031 }, 1032 [ C(OP_PREFETCH) ] = { 1033 [ C(RESULT_ACCESS) ] = 0x01b7, 1034 [ C(RESULT_MISS) ] = 0x01b7, 1035 }, 1036 }, 1037 }; 1038 1039 /* 1040 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1041 * See IA32 SDM Vol 3B 30.6.1.3 1042 */ 1043 1044 #define NHM_DMND_DATA_RD (1 << 0) 1045 #define NHM_DMND_RFO (1 << 1) 1046 #define NHM_DMND_IFETCH (1 << 2) 1047 #define NHM_DMND_WB (1 << 3) 1048 #define NHM_PF_DATA_RD (1 << 4) 1049 #define NHM_PF_DATA_RFO (1 << 5) 1050 #define NHM_PF_IFETCH (1 << 6) 1051 #define NHM_OFFCORE_OTHER (1 << 7) 1052 #define NHM_UNCORE_HIT (1 << 8) 1053 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1054 #define NHM_OTHER_CORE_HITM (1 << 10) 1055 /* reserved */ 1056 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1057 #define NHM_REMOTE_DRAM (1 << 13) 1058 #define NHM_LOCAL_DRAM (1 << 14) 1059 #define NHM_NON_DRAM (1 << 15) 1060 1061 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1062 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1063 1064 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1065 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1066 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1067 1068 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1069 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1070 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1071 1072 static __initconst const u64 nehalem_hw_cache_extra_regs 1073 [PERF_COUNT_HW_CACHE_MAX] 1074 [PERF_COUNT_HW_CACHE_OP_MAX] 1075 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1076 { 1077 [ C(LL ) ] = { 1078 [ C(OP_READ) ] = { 1079 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1080 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1081 }, 1082 [ C(OP_WRITE) ] = { 1083 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1084 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1085 }, 1086 [ C(OP_PREFETCH) ] = { 1087 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1088 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1089 }, 1090 }, 1091 [ C(NODE) ] = { 1092 [ C(OP_READ) ] = { 1093 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1094 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1095 }, 1096 [ C(OP_WRITE) ] = { 1097 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1098 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1099 }, 1100 [ C(OP_PREFETCH) ] = { 1101 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1102 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1103 }, 1104 }, 1105 }; 1106 1107 static __initconst const u64 nehalem_hw_cache_event_ids 1108 [PERF_COUNT_HW_CACHE_MAX] 1109 [PERF_COUNT_HW_CACHE_OP_MAX] 1110 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1111 { 1112 [ C(L1D) ] = { 1113 [ C(OP_READ) ] = { 1114 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1115 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1116 }, 1117 [ C(OP_WRITE) ] = { 1118 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1119 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1120 }, 1121 [ C(OP_PREFETCH) ] = { 1122 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1123 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1124 }, 1125 }, 1126 [ C(L1I ) ] = { 1127 [ C(OP_READ) ] = { 1128 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1129 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1130 }, 1131 [ C(OP_WRITE) ] = { 1132 [ C(RESULT_ACCESS) ] = -1, 1133 [ C(RESULT_MISS) ] = -1, 1134 }, 1135 [ C(OP_PREFETCH) ] = { 1136 [ C(RESULT_ACCESS) ] = 0x0, 1137 [ C(RESULT_MISS) ] = 0x0, 1138 }, 1139 }, 1140 [ C(LL ) ] = { 1141 [ C(OP_READ) ] = { 1142 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1143 [ C(RESULT_ACCESS) ] = 0x01b7, 1144 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1145 [ C(RESULT_MISS) ] = 0x01b7, 1146 }, 1147 /* 1148 * Use RFO, not WRITEBACK, because a write miss would typically occur 1149 * on RFO. 1150 */ 1151 [ C(OP_WRITE) ] = { 1152 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1153 [ C(RESULT_ACCESS) ] = 0x01b7, 1154 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1155 [ C(RESULT_MISS) ] = 0x01b7, 1156 }, 1157 [ C(OP_PREFETCH) ] = { 1158 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1159 [ C(RESULT_ACCESS) ] = 0x01b7, 1160 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1161 [ C(RESULT_MISS) ] = 0x01b7, 1162 }, 1163 }, 1164 [ C(DTLB) ] = { 1165 [ C(OP_READ) ] = { 1166 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1167 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1168 }, 1169 [ C(OP_WRITE) ] = { 1170 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1171 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1172 }, 1173 [ C(OP_PREFETCH) ] = { 1174 [ C(RESULT_ACCESS) ] = 0x0, 1175 [ C(RESULT_MISS) ] = 0x0, 1176 }, 1177 }, 1178 [ C(ITLB) ] = { 1179 [ C(OP_READ) ] = { 1180 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1181 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1182 }, 1183 [ C(OP_WRITE) ] = { 1184 [ C(RESULT_ACCESS) ] = -1, 1185 [ C(RESULT_MISS) ] = -1, 1186 }, 1187 [ C(OP_PREFETCH) ] = { 1188 [ C(RESULT_ACCESS) ] = -1, 1189 [ C(RESULT_MISS) ] = -1, 1190 }, 1191 }, 1192 [ C(BPU ) ] = { 1193 [ C(OP_READ) ] = { 1194 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1195 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1196 }, 1197 [ C(OP_WRITE) ] = { 1198 [ C(RESULT_ACCESS) ] = -1, 1199 [ C(RESULT_MISS) ] = -1, 1200 }, 1201 [ C(OP_PREFETCH) ] = { 1202 [ C(RESULT_ACCESS) ] = -1, 1203 [ C(RESULT_MISS) ] = -1, 1204 }, 1205 }, 1206 [ C(NODE) ] = { 1207 [ C(OP_READ) ] = { 1208 [ C(RESULT_ACCESS) ] = 0x01b7, 1209 [ C(RESULT_MISS) ] = 0x01b7, 1210 }, 1211 [ C(OP_WRITE) ] = { 1212 [ C(RESULT_ACCESS) ] = 0x01b7, 1213 [ C(RESULT_MISS) ] = 0x01b7, 1214 }, 1215 [ C(OP_PREFETCH) ] = { 1216 [ C(RESULT_ACCESS) ] = 0x01b7, 1217 [ C(RESULT_MISS) ] = 0x01b7, 1218 }, 1219 }, 1220 }; 1221 1222 static __initconst const u64 core2_hw_cache_event_ids 1223 [PERF_COUNT_HW_CACHE_MAX] 1224 [PERF_COUNT_HW_CACHE_OP_MAX] 1225 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1226 { 1227 [ C(L1D) ] = { 1228 [ C(OP_READ) ] = { 1229 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1230 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1231 }, 1232 [ C(OP_WRITE) ] = { 1233 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1234 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1235 }, 1236 [ C(OP_PREFETCH) ] = { 1237 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1238 [ C(RESULT_MISS) ] = 0, 1239 }, 1240 }, 1241 [ C(L1I ) ] = { 1242 [ C(OP_READ) ] = { 1243 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1244 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1245 }, 1246 [ C(OP_WRITE) ] = { 1247 [ C(RESULT_ACCESS) ] = -1, 1248 [ C(RESULT_MISS) ] = -1, 1249 }, 1250 [ C(OP_PREFETCH) ] = { 1251 [ C(RESULT_ACCESS) ] = 0, 1252 [ C(RESULT_MISS) ] = 0, 1253 }, 1254 }, 1255 [ C(LL ) ] = { 1256 [ C(OP_READ) ] = { 1257 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1258 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1259 }, 1260 [ C(OP_WRITE) ] = { 1261 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1262 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1263 }, 1264 [ C(OP_PREFETCH) ] = { 1265 [ C(RESULT_ACCESS) ] = 0, 1266 [ C(RESULT_MISS) ] = 0, 1267 }, 1268 }, 1269 [ C(DTLB) ] = { 1270 [ C(OP_READ) ] = { 1271 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1272 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1273 }, 1274 [ C(OP_WRITE) ] = { 1275 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1276 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1277 }, 1278 [ C(OP_PREFETCH) ] = { 1279 [ C(RESULT_ACCESS) ] = 0, 1280 [ C(RESULT_MISS) ] = 0, 1281 }, 1282 }, 1283 [ C(ITLB) ] = { 1284 [ C(OP_READ) ] = { 1285 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1286 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1287 }, 1288 [ C(OP_WRITE) ] = { 1289 [ C(RESULT_ACCESS) ] = -1, 1290 [ C(RESULT_MISS) ] = -1, 1291 }, 1292 [ C(OP_PREFETCH) ] = { 1293 [ C(RESULT_ACCESS) ] = -1, 1294 [ C(RESULT_MISS) ] = -1, 1295 }, 1296 }, 1297 [ C(BPU ) ] = { 1298 [ C(OP_READ) ] = { 1299 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1300 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1301 }, 1302 [ C(OP_WRITE) ] = { 1303 [ C(RESULT_ACCESS) ] = -1, 1304 [ C(RESULT_MISS) ] = -1, 1305 }, 1306 [ C(OP_PREFETCH) ] = { 1307 [ C(RESULT_ACCESS) ] = -1, 1308 [ C(RESULT_MISS) ] = -1, 1309 }, 1310 }, 1311 }; 1312 1313 static __initconst const u64 atom_hw_cache_event_ids 1314 [PERF_COUNT_HW_CACHE_MAX] 1315 [PERF_COUNT_HW_CACHE_OP_MAX] 1316 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1317 { 1318 [ C(L1D) ] = { 1319 [ C(OP_READ) ] = { 1320 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1321 [ C(RESULT_MISS) ] = 0, 1322 }, 1323 [ C(OP_WRITE) ] = { 1324 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1325 [ C(RESULT_MISS) ] = 0, 1326 }, 1327 [ C(OP_PREFETCH) ] = { 1328 [ C(RESULT_ACCESS) ] = 0x0, 1329 [ C(RESULT_MISS) ] = 0, 1330 }, 1331 }, 1332 [ C(L1I ) ] = { 1333 [ C(OP_READ) ] = { 1334 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1335 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1336 }, 1337 [ C(OP_WRITE) ] = { 1338 [ C(RESULT_ACCESS) ] = -1, 1339 [ C(RESULT_MISS) ] = -1, 1340 }, 1341 [ C(OP_PREFETCH) ] = { 1342 [ C(RESULT_ACCESS) ] = 0, 1343 [ C(RESULT_MISS) ] = 0, 1344 }, 1345 }, 1346 [ C(LL ) ] = { 1347 [ C(OP_READ) ] = { 1348 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1349 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1350 }, 1351 [ C(OP_WRITE) ] = { 1352 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1353 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1354 }, 1355 [ C(OP_PREFETCH) ] = { 1356 [ C(RESULT_ACCESS) ] = 0, 1357 [ C(RESULT_MISS) ] = 0, 1358 }, 1359 }, 1360 [ C(DTLB) ] = { 1361 [ C(OP_READ) ] = { 1362 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1363 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1364 }, 1365 [ C(OP_WRITE) ] = { 1366 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1367 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1368 }, 1369 [ C(OP_PREFETCH) ] = { 1370 [ C(RESULT_ACCESS) ] = 0, 1371 [ C(RESULT_MISS) ] = 0, 1372 }, 1373 }, 1374 [ C(ITLB) ] = { 1375 [ C(OP_READ) ] = { 1376 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1377 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1378 }, 1379 [ C(OP_WRITE) ] = { 1380 [ C(RESULT_ACCESS) ] = -1, 1381 [ C(RESULT_MISS) ] = -1, 1382 }, 1383 [ C(OP_PREFETCH) ] = { 1384 [ C(RESULT_ACCESS) ] = -1, 1385 [ C(RESULT_MISS) ] = -1, 1386 }, 1387 }, 1388 [ C(BPU ) ] = { 1389 [ C(OP_READ) ] = { 1390 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1391 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1392 }, 1393 [ C(OP_WRITE) ] = { 1394 [ C(RESULT_ACCESS) ] = -1, 1395 [ C(RESULT_MISS) ] = -1, 1396 }, 1397 [ C(OP_PREFETCH) ] = { 1398 [ C(RESULT_ACCESS) ] = -1, 1399 [ C(RESULT_MISS) ] = -1, 1400 }, 1401 }, 1402 }; 1403 1404 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1405 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1406 /* no_alloc_cycles.not_delivered */ 1407 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1408 "event=0xca,umask=0x50"); 1409 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1410 /* uops_retired.all */ 1411 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1412 "event=0xc2,umask=0x10"); 1413 /* uops_retired.all */ 1414 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1415 "event=0xc2,umask=0x10"); 1416 1417 static struct attribute *slm_events_attrs[] = { 1418 EVENT_PTR(td_total_slots_slm), 1419 EVENT_PTR(td_total_slots_scale_slm), 1420 EVENT_PTR(td_fetch_bubbles_slm), 1421 EVENT_PTR(td_fetch_bubbles_scale_slm), 1422 EVENT_PTR(td_slots_issued_slm), 1423 EVENT_PTR(td_slots_retired_slm), 1424 NULL 1425 }; 1426 1427 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1428 { 1429 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1430 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1431 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1432 EVENT_EXTRA_END 1433 }; 1434 1435 #define SLM_DMND_READ SNB_DMND_DATA_RD 1436 #define SLM_DMND_WRITE SNB_DMND_RFO 1437 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1438 1439 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1440 #define SLM_LLC_ACCESS SNB_RESP_ANY 1441 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1442 1443 static __initconst const u64 slm_hw_cache_extra_regs 1444 [PERF_COUNT_HW_CACHE_MAX] 1445 [PERF_COUNT_HW_CACHE_OP_MAX] 1446 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1447 { 1448 [ C(LL ) ] = { 1449 [ C(OP_READ) ] = { 1450 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1451 [ C(RESULT_MISS) ] = 0, 1452 }, 1453 [ C(OP_WRITE) ] = { 1454 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1455 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1456 }, 1457 [ C(OP_PREFETCH) ] = { 1458 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1459 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1460 }, 1461 }, 1462 }; 1463 1464 static __initconst const u64 slm_hw_cache_event_ids 1465 [PERF_COUNT_HW_CACHE_MAX] 1466 [PERF_COUNT_HW_CACHE_OP_MAX] 1467 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1468 { 1469 [ C(L1D) ] = { 1470 [ C(OP_READ) ] = { 1471 [ C(RESULT_ACCESS) ] = 0, 1472 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1473 }, 1474 [ C(OP_WRITE) ] = { 1475 [ C(RESULT_ACCESS) ] = 0, 1476 [ C(RESULT_MISS) ] = 0, 1477 }, 1478 [ C(OP_PREFETCH) ] = { 1479 [ C(RESULT_ACCESS) ] = 0, 1480 [ C(RESULT_MISS) ] = 0, 1481 }, 1482 }, 1483 [ C(L1I ) ] = { 1484 [ C(OP_READ) ] = { 1485 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1486 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1487 }, 1488 [ C(OP_WRITE) ] = { 1489 [ C(RESULT_ACCESS) ] = -1, 1490 [ C(RESULT_MISS) ] = -1, 1491 }, 1492 [ C(OP_PREFETCH) ] = { 1493 [ C(RESULT_ACCESS) ] = 0, 1494 [ C(RESULT_MISS) ] = 0, 1495 }, 1496 }, 1497 [ C(LL ) ] = { 1498 [ C(OP_READ) ] = { 1499 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1500 [ C(RESULT_ACCESS) ] = 0x01b7, 1501 [ C(RESULT_MISS) ] = 0, 1502 }, 1503 [ C(OP_WRITE) ] = { 1504 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1505 [ C(RESULT_ACCESS) ] = 0x01b7, 1506 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1507 [ C(RESULT_MISS) ] = 0x01b7, 1508 }, 1509 [ C(OP_PREFETCH) ] = { 1510 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1511 [ C(RESULT_ACCESS) ] = 0x01b7, 1512 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1513 [ C(RESULT_MISS) ] = 0x01b7, 1514 }, 1515 }, 1516 [ C(DTLB) ] = { 1517 [ C(OP_READ) ] = { 1518 [ C(RESULT_ACCESS) ] = 0, 1519 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1520 }, 1521 [ C(OP_WRITE) ] = { 1522 [ C(RESULT_ACCESS) ] = 0, 1523 [ C(RESULT_MISS) ] = 0, 1524 }, 1525 [ C(OP_PREFETCH) ] = { 1526 [ C(RESULT_ACCESS) ] = 0, 1527 [ C(RESULT_MISS) ] = 0, 1528 }, 1529 }, 1530 [ C(ITLB) ] = { 1531 [ C(OP_READ) ] = { 1532 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1533 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1534 }, 1535 [ C(OP_WRITE) ] = { 1536 [ C(RESULT_ACCESS) ] = -1, 1537 [ C(RESULT_MISS) ] = -1, 1538 }, 1539 [ C(OP_PREFETCH) ] = { 1540 [ C(RESULT_ACCESS) ] = -1, 1541 [ C(RESULT_MISS) ] = -1, 1542 }, 1543 }, 1544 [ C(BPU ) ] = { 1545 [ C(OP_READ) ] = { 1546 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1547 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1548 }, 1549 [ C(OP_WRITE) ] = { 1550 [ C(RESULT_ACCESS) ] = -1, 1551 [ C(RESULT_MISS) ] = -1, 1552 }, 1553 [ C(OP_PREFETCH) ] = { 1554 [ C(RESULT_ACCESS) ] = -1, 1555 [ C(RESULT_MISS) ] = -1, 1556 }, 1557 }, 1558 }; 1559 1560 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1561 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1562 /* UOPS_NOT_DELIVERED.ANY */ 1563 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1564 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1565 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1566 /* UOPS_RETIRED.ANY */ 1567 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1568 /* UOPS_ISSUED.ANY */ 1569 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1570 1571 static struct attribute *glm_events_attrs[] = { 1572 EVENT_PTR(td_total_slots_glm), 1573 EVENT_PTR(td_total_slots_scale_glm), 1574 EVENT_PTR(td_fetch_bubbles_glm), 1575 EVENT_PTR(td_recovery_bubbles_glm), 1576 EVENT_PTR(td_slots_issued_glm), 1577 EVENT_PTR(td_slots_retired_glm), 1578 NULL 1579 }; 1580 1581 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1582 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1583 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1584 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1585 EVENT_EXTRA_END 1586 }; 1587 1588 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 1589 #define GLM_DEMAND_RFO BIT_ULL(1) 1590 #define GLM_ANY_RESPONSE BIT_ULL(16) 1591 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1592 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1593 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1594 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1595 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1596 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1597 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1598 1599 static __initconst const u64 glm_hw_cache_event_ids 1600 [PERF_COUNT_HW_CACHE_MAX] 1601 [PERF_COUNT_HW_CACHE_OP_MAX] 1602 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1603 [C(L1D)] = { 1604 [C(OP_READ)] = { 1605 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1606 [C(RESULT_MISS)] = 0x0, 1607 }, 1608 [C(OP_WRITE)] = { 1609 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1610 [C(RESULT_MISS)] = 0x0, 1611 }, 1612 [C(OP_PREFETCH)] = { 1613 [C(RESULT_ACCESS)] = 0x0, 1614 [C(RESULT_MISS)] = 0x0, 1615 }, 1616 }, 1617 [C(L1I)] = { 1618 [C(OP_READ)] = { 1619 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1620 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1621 }, 1622 [C(OP_WRITE)] = { 1623 [C(RESULT_ACCESS)] = -1, 1624 [C(RESULT_MISS)] = -1, 1625 }, 1626 [C(OP_PREFETCH)] = { 1627 [C(RESULT_ACCESS)] = 0x0, 1628 [C(RESULT_MISS)] = 0x0, 1629 }, 1630 }, 1631 [C(LL)] = { 1632 [C(OP_READ)] = { 1633 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1634 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1635 }, 1636 [C(OP_WRITE)] = { 1637 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1638 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1639 }, 1640 [C(OP_PREFETCH)] = { 1641 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1642 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1643 }, 1644 }, 1645 [C(DTLB)] = { 1646 [C(OP_READ)] = { 1647 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1648 [C(RESULT_MISS)] = 0x0, 1649 }, 1650 [C(OP_WRITE)] = { 1651 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1652 [C(RESULT_MISS)] = 0x0, 1653 }, 1654 [C(OP_PREFETCH)] = { 1655 [C(RESULT_ACCESS)] = 0x0, 1656 [C(RESULT_MISS)] = 0x0, 1657 }, 1658 }, 1659 [C(ITLB)] = { 1660 [C(OP_READ)] = { 1661 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1662 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1663 }, 1664 [C(OP_WRITE)] = { 1665 [C(RESULT_ACCESS)] = -1, 1666 [C(RESULT_MISS)] = -1, 1667 }, 1668 [C(OP_PREFETCH)] = { 1669 [C(RESULT_ACCESS)] = -1, 1670 [C(RESULT_MISS)] = -1, 1671 }, 1672 }, 1673 [C(BPU)] = { 1674 [C(OP_READ)] = { 1675 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1676 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1677 }, 1678 [C(OP_WRITE)] = { 1679 [C(RESULT_ACCESS)] = -1, 1680 [C(RESULT_MISS)] = -1, 1681 }, 1682 [C(OP_PREFETCH)] = { 1683 [C(RESULT_ACCESS)] = -1, 1684 [C(RESULT_MISS)] = -1, 1685 }, 1686 }, 1687 }; 1688 1689 static __initconst const u64 glm_hw_cache_extra_regs 1690 [PERF_COUNT_HW_CACHE_MAX] 1691 [PERF_COUNT_HW_CACHE_OP_MAX] 1692 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1693 [C(LL)] = { 1694 [C(OP_READ)] = { 1695 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1696 GLM_LLC_ACCESS, 1697 [C(RESULT_MISS)] = GLM_DEMAND_READ| 1698 GLM_LLC_MISS, 1699 }, 1700 [C(OP_WRITE)] = { 1701 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1702 GLM_LLC_ACCESS, 1703 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1704 GLM_LLC_MISS, 1705 }, 1706 [C(OP_PREFETCH)] = { 1707 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 1708 GLM_LLC_ACCESS, 1709 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 1710 GLM_LLC_MISS, 1711 }, 1712 }, 1713 }; 1714 1715 static __initconst const u64 glp_hw_cache_event_ids 1716 [PERF_COUNT_HW_CACHE_MAX] 1717 [PERF_COUNT_HW_CACHE_OP_MAX] 1718 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1719 [C(L1D)] = { 1720 [C(OP_READ)] = { 1721 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1722 [C(RESULT_MISS)] = 0x0, 1723 }, 1724 [C(OP_WRITE)] = { 1725 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1726 [C(RESULT_MISS)] = 0x0, 1727 }, 1728 [C(OP_PREFETCH)] = { 1729 [C(RESULT_ACCESS)] = 0x0, 1730 [C(RESULT_MISS)] = 0x0, 1731 }, 1732 }, 1733 [C(L1I)] = { 1734 [C(OP_READ)] = { 1735 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1736 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1737 }, 1738 [C(OP_WRITE)] = { 1739 [C(RESULT_ACCESS)] = -1, 1740 [C(RESULT_MISS)] = -1, 1741 }, 1742 [C(OP_PREFETCH)] = { 1743 [C(RESULT_ACCESS)] = 0x0, 1744 [C(RESULT_MISS)] = 0x0, 1745 }, 1746 }, 1747 [C(LL)] = { 1748 [C(OP_READ)] = { 1749 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1750 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1751 }, 1752 [C(OP_WRITE)] = { 1753 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1754 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1755 }, 1756 [C(OP_PREFETCH)] = { 1757 [C(RESULT_ACCESS)] = 0x0, 1758 [C(RESULT_MISS)] = 0x0, 1759 }, 1760 }, 1761 [C(DTLB)] = { 1762 [C(OP_READ)] = { 1763 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1764 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1765 }, 1766 [C(OP_WRITE)] = { 1767 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1768 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1769 }, 1770 [C(OP_PREFETCH)] = { 1771 [C(RESULT_ACCESS)] = 0x0, 1772 [C(RESULT_MISS)] = 0x0, 1773 }, 1774 }, 1775 [C(ITLB)] = { 1776 [C(OP_READ)] = { 1777 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1778 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1779 }, 1780 [C(OP_WRITE)] = { 1781 [C(RESULT_ACCESS)] = -1, 1782 [C(RESULT_MISS)] = -1, 1783 }, 1784 [C(OP_PREFETCH)] = { 1785 [C(RESULT_ACCESS)] = -1, 1786 [C(RESULT_MISS)] = -1, 1787 }, 1788 }, 1789 [C(BPU)] = { 1790 [C(OP_READ)] = { 1791 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1792 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1793 }, 1794 [C(OP_WRITE)] = { 1795 [C(RESULT_ACCESS)] = -1, 1796 [C(RESULT_MISS)] = -1, 1797 }, 1798 [C(OP_PREFETCH)] = { 1799 [C(RESULT_ACCESS)] = -1, 1800 [C(RESULT_MISS)] = -1, 1801 }, 1802 }, 1803 }; 1804 1805 static __initconst const u64 glp_hw_cache_extra_regs 1806 [PERF_COUNT_HW_CACHE_MAX] 1807 [PERF_COUNT_HW_CACHE_OP_MAX] 1808 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1809 [C(LL)] = { 1810 [C(OP_READ)] = { 1811 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1812 GLM_LLC_ACCESS, 1813 [C(RESULT_MISS)] = GLM_DEMAND_READ| 1814 GLM_LLC_MISS, 1815 }, 1816 [C(OP_WRITE)] = { 1817 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1818 GLM_LLC_ACCESS, 1819 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1820 GLM_LLC_MISS, 1821 }, 1822 [C(OP_PREFETCH)] = { 1823 [C(RESULT_ACCESS)] = 0x0, 1824 [C(RESULT_MISS)] = 0x0, 1825 }, 1826 }, 1827 }; 1828 1829 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 1830 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 1831 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 1832 #define KNL_MCDRAM_FAR BIT_ULL(22) 1833 #define KNL_DDR_LOCAL BIT_ULL(23) 1834 #define KNL_DDR_FAR BIT_ULL(24) 1835 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 1836 KNL_DDR_LOCAL | KNL_DDR_FAR) 1837 #define KNL_L2_READ SLM_DMND_READ 1838 #define KNL_L2_WRITE SLM_DMND_WRITE 1839 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 1840 #define KNL_L2_ACCESS SLM_LLC_ACCESS 1841 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 1842 KNL_DRAM_ANY | SNB_SNP_ANY | \ 1843 SNB_NON_DRAM) 1844 1845 static __initconst const u64 knl_hw_cache_extra_regs 1846 [PERF_COUNT_HW_CACHE_MAX] 1847 [PERF_COUNT_HW_CACHE_OP_MAX] 1848 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1849 [C(LL)] = { 1850 [C(OP_READ)] = { 1851 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 1852 [C(RESULT_MISS)] = 0, 1853 }, 1854 [C(OP_WRITE)] = { 1855 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 1856 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 1857 }, 1858 [C(OP_PREFETCH)] = { 1859 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 1860 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 1861 }, 1862 }, 1863 }; 1864 1865 /* 1866 * Used from PMIs where the LBRs are already disabled. 1867 * 1868 * This function could be called consecutively. It is required to remain in 1869 * disabled state if called consecutively. 1870 * 1871 * During consecutive calls, the same disable value will be written to related 1872 * registers, so the PMU state remains unchanged. 1873 * 1874 * intel_bts events don't coexist with intel PMU's BTS events because of 1875 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 1876 * disabled around intel PMU's event batching etc, only inside the PMI handler. 1877 */ 1878 static void __intel_pmu_disable_all(void) 1879 { 1880 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1881 1882 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 1883 1884 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 1885 intel_pmu_disable_bts(); 1886 1887 intel_pmu_pebs_disable_all(); 1888 } 1889 1890 static void intel_pmu_disable_all(void) 1891 { 1892 __intel_pmu_disable_all(); 1893 intel_pmu_lbr_disable_all(); 1894 } 1895 1896 static void __intel_pmu_enable_all(int added, bool pmi) 1897 { 1898 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1899 1900 intel_pmu_pebs_enable_all(); 1901 intel_pmu_lbr_enable_all(pmi); 1902 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 1903 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 1904 1905 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 1906 struct perf_event *event = 1907 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 1908 1909 if (WARN_ON_ONCE(!event)) 1910 return; 1911 1912 intel_pmu_enable_bts(event->hw.config); 1913 } 1914 } 1915 1916 static void intel_pmu_enable_all(int added) 1917 { 1918 __intel_pmu_enable_all(added, false); 1919 } 1920 1921 /* 1922 * Workaround for: 1923 * Intel Errata AAK100 (model 26) 1924 * Intel Errata AAP53 (model 30) 1925 * Intel Errata BD53 (model 44) 1926 * 1927 * The official story: 1928 * These chips need to be 'reset' when adding counters by programming the 1929 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 1930 * in sequence on the same PMC or on different PMCs. 1931 * 1932 * In practise it appears some of these events do in fact count, and 1933 * we need to programm all 4 events. 1934 */ 1935 static void intel_pmu_nhm_workaround(void) 1936 { 1937 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1938 static const unsigned long nhm_magic[4] = { 1939 0x4300B5, 1940 0x4300D2, 1941 0x4300B1, 1942 0x4300B1 1943 }; 1944 struct perf_event *event; 1945 int i; 1946 1947 /* 1948 * The Errata requires below steps: 1949 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 1950 * 2) Configure 4 PERFEVTSELx with the magic events and clear 1951 * the corresponding PMCx; 1952 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 1953 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 1954 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 1955 */ 1956 1957 /* 1958 * The real steps we choose are a little different from above. 1959 * A) To reduce MSR operations, we don't run step 1) as they 1960 * are already cleared before this function is called; 1961 * B) Call x86_perf_event_update to save PMCx before configuring 1962 * PERFEVTSELx with magic number; 1963 * C) With step 5), we do clear only when the PERFEVTSELx is 1964 * not used currently. 1965 * D) Call x86_perf_event_set_period to restore PMCx; 1966 */ 1967 1968 /* We always operate 4 pairs of PERF Counters */ 1969 for (i = 0; i < 4; i++) { 1970 event = cpuc->events[i]; 1971 if (event) 1972 x86_perf_event_update(event); 1973 } 1974 1975 for (i = 0; i < 4; i++) { 1976 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 1977 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 1978 } 1979 1980 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 1981 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 1982 1983 for (i = 0; i < 4; i++) { 1984 event = cpuc->events[i]; 1985 1986 if (event) { 1987 x86_perf_event_set_period(event); 1988 __x86_pmu_enable_event(&event->hw, 1989 ARCH_PERFMON_EVENTSEL_ENABLE); 1990 } else 1991 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 1992 } 1993 } 1994 1995 static void intel_pmu_nhm_enable_all(int added) 1996 { 1997 if (added) 1998 intel_pmu_nhm_workaround(); 1999 intel_pmu_enable_all(added); 2000 } 2001 2002 static void enable_counter_freeze(void) 2003 { 2004 update_debugctlmsr(get_debugctlmsr() | 2005 DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI); 2006 } 2007 2008 static void disable_counter_freeze(void) 2009 { 2010 update_debugctlmsr(get_debugctlmsr() & 2011 ~DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI); 2012 } 2013 2014 static inline u64 intel_pmu_get_status(void) 2015 { 2016 u64 status; 2017 2018 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2019 2020 return status; 2021 } 2022 2023 static inline void intel_pmu_ack_status(u64 ack) 2024 { 2025 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2026 } 2027 2028 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc) 2029 { 2030 int idx = hwc->idx - INTEL_PMC_IDX_FIXED; 2031 u64 ctrl_val, mask; 2032 2033 mask = 0xfULL << (idx * 4); 2034 2035 rdmsrl(hwc->config_base, ctrl_val); 2036 ctrl_val &= ~mask; 2037 wrmsrl(hwc->config_base, ctrl_val); 2038 } 2039 2040 static inline bool event_is_checkpointed(struct perf_event *event) 2041 { 2042 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2043 } 2044 2045 static void intel_pmu_disable_event(struct perf_event *event) 2046 { 2047 struct hw_perf_event *hwc = &event->hw; 2048 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2049 2050 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { 2051 intel_pmu_disable_bts(); 2052 intel_pmu_drain_bts_buffer(); 2053 return; 2054 } 2055 2056 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx); 2057 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx); 2058 cpuc->intel_cp_status &= ~(1ull << hwc->idx); 2059 2060 if (unlikely(event->attr.precise_ip)) 2061 intel_pmu_pebs_disable(event); 2062 2063 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { 2064 intel_pmu_disable_fixed(hwc); 2065 return; 2066 } 2067 2068 x86_pmu_disable_event(event); 2069 } 2070 2071 static void intel_pmu_del_event(struct perf_event *event) 2072 { 2073 if (needs_branch_stack(event)) 2074 intel_pmu_lbr_del(event); 2075 if (event->attr.precise_ip) 2076 intel_pmu_pebs_del(event); 2077 } 2078 2079 static void intel_pmu_read_event(struct perf_event *event) 2080 { 2081 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2082 intel_pmu_auto_reload_read(event); 2083 else 2084 x86_perf_event_update(event); 2085 } 2086 2087 static void intel_pmu_enable_fixed(struct perf_event *event) 2088 { 2089 struct hw_perf_event *hwc = &event->hw; 2090 int idx = hwc->idx - INTEL_PMC_IDX_FIXED; 2091 u64 ctrl_val, mask, bits = 0; 2092 2093 /* 2094 * Enable IRQ generation (0x8), if not PEBS, 2095 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2096 * if requested: 2097 */ 2098 if (!event->attr.precise_ip) 2099 bits |= 0x8; 2100 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2101 bits |= 0x2; 2102 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2103 bits |= 0x1; 2104 2105 /* 2106 * ANY bit is supported in v3 and up 2107 */ 2108 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2109 bits |= 0x4; 2110 2111 bits <<= (idx * 4); 2112 mask = 0xfULL << (idx * 4); 2113 2114 rdmsrl(hwc->config_base, ctrl_val); 2115 ctrl_val &= ~mask; 2116 ctrl_val |= bits; 2117 wrmsrl(hwc->config_base, ctrl_val); 2118 } 2119 2120 static void intel_pmu_enable_event(struct perf_event *event) 2121 { 2122 struct hw_perf_event *hwc = &event->hw; 2123 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2124 2125 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { 2126 if (!__this_cpu_read(cpu_hw_events.enabled)) 2127 return; 2128 2129 intel_pmu_enable_bts(hwc->config); 2130 return; 2131 } 2132 2133 if (event->attr.exclude_host) 2134 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx); 2135 if (event->attr.exclude_guest) 2136 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx); 2137 2138 if (unlikely(event_is_checkpointed(event))) 2139 cpuc->intel_cp_status |= (1ull << hwc->idx); 2140 2141 if (unlikely(event->attr.precise_ip)) 2142 intel_pmu_pebs_enable(event); 2143 2144 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { 2145 intel_pmu_enable_fixed(event); 2146 return; 2147 } 2148 2149 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 2150 } 2151 2152 static void intel_pmu_add_event(struct perf_event *event) 2153 { 2154 if (event->attr.precise_ip) 2155 intel_pmu_pebs_add(event); 2156 if (needs_branch_stack(event)) 2157 intel_pmu_lbr_add(event); 2158 } 2159 2160 /* 2161 * Save and restart an expired event. Called by NMI contexts, 2162 * so it has to be careful about preempting normal event ops: 2163 */ 2164 int intel_pmu_save_and_restart(struct perf_event *event) 2165 { 2166 x86_perf_event_update(event); 2167 /* 2168 * For a checkpointed counter always reset back to 0. This 2169 * avoids a situation where the counter overflows, aborts the 2170 * transaction and is then set back to shortly before the 2171 * overflow, and overflows and aborts again. 2172 */ 2173 if (unlikely(event_is_checkpointed(event))) { 2174 /* No race with NMIs because the counter should not be armed */ 2175 wrmsrl(event->hw.event_base, 0); 2176 local64_set(&event->hw.prev_count, 0); 2177 } 2178 return x86_perf_event_set_period(event); 2179 } 2180 2181 static void intel_pmu_reset(void) 2182 { 2183 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2184 unsigned long flags; 2185 int idx; 2186 2187 if (!x86_pmu.num_counters) 2188 return; 2189 2190 local_irq_save(flags); 2191 2192 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2193 2194 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 2195 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2196 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2197 } 2198 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) 2199 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2200 2201 if (ds) 2202 ds->bts_index = ds->bts_buffer_base; 2203 2204 /* Ack all overflows and disable fixed counters */ 2205 if (x86_pmu.version >= 2) { 2206 intel_pmu_ack_status(intel_pmu_get_status()); 2207 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2208 } 2209 2210 /* Reset LBRs and LBR freezing */ 2211 if (x86_pmu.lbr_nr) { 2212 update_debugctlmsr(get_debugctlmsr() & 2213 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2214 } 2215 2216 local_irq_restore(flags); 2217 } 2218 2219 static int handle_pmi_common(struct pt_regs *regs, u64 status) 2220 { 2221 struct perf_sample_data data; 2222 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2223 int bit; 2224 int handled = 0; 2225 2226 inc_irq_stat(apic_perf_irqs); 2227 2228 /* 2229 * Ignore a range of extra bits in status that do not indicate 2230 * overflow by themselves. 2231 */ 2232 status &= ~(GLOBAL_STATUS_COND_CHG | 2233 GLOBAL_STATUS_ASIF | 2234 GLOBAL_STATUS_LBRS_FROZEN); 2235 if (!status) 2236 return 0; 2237 /* 2238 * In case multiple PEBS events are sampled at the same time, 2239 * it is possible to have GLOBAL_STATUS bit 62 set indicating 2240 * PEBS buffer overflow and also seeing at most 3 PEBS counters 2241 * having their bits set in the status register. This is a sign 2242 * that there was at least one PEBS record pending at the time 2243 * of the PMU interrupt. PEBS counters must only be processed 2244 * via the drain_pebs() calls and not via the regular sample 2245 * processing loop coming after that the function, otherwise 2246 * phony regular samples may be generated in the sampling buffer 2247 * not marked with the EXACT tag. Another possibility is to have 2248 * one PEBS event and at least one non-PEBS event whic hoverflows 2249 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2250 * not be set, yet the overflow status bit for the PEBS counter will 2251 * be on Skylake. 2252 * 2253 * To avoid this problem, we systematically ignore the PEBS-enabled 2254 * counters from the GLOBAL_STATUS mask and we always process PEBS 2255 * events via drain_pebs(). 2256 */ 2257 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 2258 status &= ~cpuc->pebs_enabled; 2259 else 2260 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 2261 2262 /* 2263 * PEBS overflow sets bit 62 in the global status register 2264 */ 2265 if (__test_and_clear_bit(62, (unsigned long *)&status)) { 2266 handled++; 2267 x86_pmu.drain_pebs(regs); 2268 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 2269 } 2270 2271 /* 2272 * Intel PT 2273 */ 2274 if (__test_and_clear_bit(55, (unsigned long *)&status)) { 2275 handled++; 2276 intel_pt_interrupt(); 2277 } 2278 2279 /* 2280 * Checkpointed counters can lead to 'spurious' PMIs because the 2281 * rollback caused by the PMI will have cleared the overflow status 2282 * bit. Therefore always force probe these counters. 2283 */ 2284 status |= cpuc->intel_cp_status; 2285 2286 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 2287 struct perf_event *event = cpuc->events[bit]; 2288 2289 handled++; 2290 2291 if (!test_bit(bit, cpuc->active_mask)) 2292 continue; 2293 2294 if (!intel_pmu_save_and_restart(event)) 2295 continue; 2296 2297 perf_sample_data_init(&data, 0, event->hw.last_period); 2298 2299 if (has_branch_stack(event)) 2300 data.br_stack = &cpuc->lbr_stack; 2301 2302 if (perf_event_overflow(event, &data, regs)) 2303 x86_pmu_stop(event, 0); 2304 } 2305 2306 return handled; 2307 } 2308 2309 static bool disable_counter_freezing = true; 2310 static int __init intel_perf_counter_freezing_setup(char *s) 2311 { 2312 bool res; 2313 2314 if (kstrtobool(s, &res)) 2315 return -EINVAL; 2316 2317 disable_counter_freezing = !res; 2318 return 1; 2319 } 2320 __setup("perf_v4_pmi=", intel_perf_counter_freezing_setup); 2321 2322 /* 2323 * Simplified handler for Arch Perfmon v4: 2324 * - We rely on counter freezing/unfreezing to enable/disable the PMU. 2325 * This is done automatically on PMU ack. 2326 * - Ack the PMU only after the APIC. 2327 */ 2328 2329 static int intel_pmu_handle_irq_v4(struct pt_regs *regs) 2330 { 2331 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2332 int handled = 0; 2333 bool bts = false; 2334 u64 status; 2335 int pmu_enabled = cpuc->enabled; 2336 int loops = 0; 2337 2338 /* PMU has been disabled because of counter freezing */ 2339 cpuc->enabled = 0; 2340 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2341 bts = true; 2342 intel_bts_disable_local(); 2343 handled = intel_pmu_drain_bts_buffer(); 2344 handled += intel_bts_interrupt(); 2345 } 2346 status = intel_pmu_get_status(); 2347 if (!status) 2348 goto done; 2349 again: 2350 intel_pmu_lbr_read(); 2351 if (++loops > 100) { 2352 static bool warned; 2353 2354 if (!warned) { 2355 WARN(1, "perfevents: irq loop stuck!\n"); 2356 perf_event_print_debug(); 2357 warned = true; 2358 } 2359 intel_pmu_reset(); 2360 goto done; 2361 } 2362 2363 2364 handled += handle_pmi_common(regs, status); 2365 done: 2366 /* Ack the PMI in the APIC */ 2367 apic_write(APIC_LVTPC, APIC_DM_NMI); 2368 2369 /* 2370 * The counters start counting immediately while ack the status. 2371 * Make it as close as possible to IRET. This avoids bogus 2372 * freezing on Skylake CPUs. 2373 */ 2374 if (status) { 2375 intel_pmu_ack_status(status); 2376 } else { 2377 /* 2378 * CPU may issues two PMIs very close to each other. 2379 * When the PMI handler services the first one, the 2380 * GLOBAL_STATUS is already updated to reflect both. 2381 * When it IRETs, the second PMI is immediately 2382 * handled and it sees clear status. At the meantime, 2383 * there may be a third PMI, because the freezing bit 2384 * isn't set since the ack in first PMI handlers. 2385 * Double check if there is more work to be done. 2386 */ 2387 status = intel_pmu_get_status(); 2388 if (status) 2389 goto again; 2390 } 2391 2392 if (bts) 2393 intel_bts_enable_local(); 2394 cpuc->enabled = pmu_enabled; 2395 return handled; 2396 } 2397 2398 /* 2399 * This handler is triggered by the local APIC, so the APIC IRQ handling 2400 * rules apply: 2401 */ 2402 static int intel_pmu_handle_irq(struct pt_regs *regs) 2403 { 2404 struct cpu_hw_events *cpuc; 2405 int loops; 2406 u64 status; 2407 int handled; 2408 int pmu_enabled; 2409 2410 cpuc = this_cpu_ptr(&cpu_hw_events); 2411 2412 /* 2413 * Save the PMU state. 2414 * It needs to be restored when leaving the handler. 2415 */ 2416 pmu_enabled = cpuc->enabled; 2417 /* 2418 * No known reason to not always do late ACK, 2419 * but just in case do it opt-in. 2420 */ 2421 if (!x86_pmu.late_ack) 2422 apic_write(APIC_LVTPC, APIC_DM_NMI); 2423 intel_bts_disable_local(); 2424 cpuc->enabled = 0; 2425 __intel_pmu_disable_all(); 2426 handled = intel_pmu_drain_bts_buffer(); 2427 handled += intel_bts_interrupt(); 2428 status = intel_pmu_get_status(); 2429 if (!status) 2430 goto done; 2431 2432 loops = 0; 2433 again: 2434 intel_pmu_lbr_read(); 2435 intel_pmu_ack_status(status); 2436 if (++loops > 100) { 2437 static bool warned; 2438 2439 if (!warned) { 2440 WARN(1, "perfevents: irq loop stuck!\n"); 2441 perf_event_print_debug(); 2442 warned = true; 2443 } 2444 intel_pmu_reset(); 2445 goto done; 2446 } 2447 2448 handled += handle_pmi_common(regs, status); 2449 2450 /* 2451 * Repeat if there is more work to be done: 2452 */ 2453 status = intel_pmu_get_status(); 2454 if (status) 2455 goto again; 2456 2457 done: 2458 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 2459 cpuc->enabled = pmu_enabled; 2460 if (pmu_enabled) 2461 __intel_pmu_enable_all(0, true); 2462 intel_bts_enable_local(); 2463 2464 /* 2465 * Only unmask the NMI after the overflow counters 2466 * have been reset. This avoids spurious NMIs on 2467 * Haswell CPUs. 2468 */ 2469 if (x86_pmu.late_ack) 2470 apic_write(APIC_LVTPC, APIC_DM_NMI); 2471 return handled; 2472 } 2473 2474 static struct event_constraint * 2475 intel_bts_constraints(struct perf_event *event) 2476 { 2477 struct hw_perf_event *hwc = &event->hw; 2478 unsigned int hw_event, bts_event; 2479 2480 if (event->attr.freq) 2481 return NULL; 2482 2483 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 2484 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 2485 2486 if (unlikely(hw_event == bts_event && hwc->sample_period == 1)) 2487 return &bts_constraint; 2488 2489 return NULL; 2490 } 2491 2492 static int intel_alt_er(int idx, u64 config) 2493 { 2494 int alt_idx = idx; 2495 2496 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 2497 return idx; 2498 2499 if (idx == EXTRA_REG_RSP_0) 2500 alt_idx = EXTRA_REG_RSP_1; 2501 2502 if (idx == EXTRA_REG_RSP_1) 2503 alt_idx = EXTRA_REG_RSP_0; 2504 2505 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask) 2506 return idx; 2507 2508 return alt_idx; 2509 } 2510 2511 static void intel_fixup_er(struct perf_event *event, int idx) 2512 { 2513 event->hw.extra_reg.idx = idx; 2514 2515 if (idx == EXTRA_REG_RSP_0) { 2516 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2517 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event; 2518 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 2519 } else if (idx == EXTRA_REG_RSP_1) { 2520 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2521 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event; 2522 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 2523 } 2524 } 2525 2526 /* 2527 * manage allocation of shared extra msr for certain events 2528 * 2529 * sharing can be: 2530 * per-cpu: to be shared between the various events on a single PMU 2531 * per-core: per-cpu + shared by HT threads 2532 */ 2533 static struct event_constraint * 2534 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 2535 struct perf_event *event, 2536 struct hw_perf_event_extra *reg) 2537 { 2538 struct event_constraint *c = &emptyconstraint; 2539 struct er_account *era; 2540 unsigned long flags; 2541 int idx = reg->idx; 2542 2543 /* 2544 * reg->alloc can be set due to existing state, so for fake cpuc we 2545 * need to ignore this, otherwise we might fail to allocate proper fake 2546 * state for this extra reg constraint. Also see the comment below. 2547 */ 2548 if (reg->alloc && !cpuc->is_fake) 2549 return NULL; /* call x86_get_event_constraint() */ 2550 2551 again: 2552 era = &cpuc->shared_regs->regs[idx]; 2553 /* 2554 * we use spin_lock_irqsave() to avoid lockdep issues when 2555 * passing a fake cpuc 2556 */ 2557 raw_spin_lock_irqsave(&era->lock, flags); 2558 2559 if (!atomic_read(&era->ref) || era->config == reg->config) { 2560 2561 /* 2562 * If its a fake cpuc -- as per validate_{group,event}() we 2563 * shouldn't touch event state and we can avoid doing so 2564 * since both will only call get_event_constraints() once 2565 * on each event, this avoids the need for reg->alloc. 2566 * 2567 * Not doing the ER fixup will only result in era->reg being 2568 * wrong, but since we won't actually try and program hardware 2569 * this isn't a problem either. 2570 */ 2571 if (!cpuc->is_fake) { 2572 if (idx != reg->idx) 2573 intel_fixup_er(event, idx); 2574 2575 /* 2576 * x86_schedule_events() can call get_event_constraints() 2577 * multiple times on events in the case of incremental 2578 * scheduling(). reg->alloc ensures we only do the ER 2579 * allocation once. 2580 */ 2581 reg->alloc = 1; 2582 } 2583 2584 /* lock in msr value */ 2585 era->config = reg->config; 2586 era->reg = reg->reg; 2587 2588 /* one more user */ 2589 atomic_inc(&era->ref); 2590 2591 /* 2592 * need to call x86_get_event_constraint() 2593 * to check if associated event has constraints 2594 */ 2595 c = NULL; 2596 } else { 2597 idx = intel_alt_er(idx, reg->config); 2598 if (idx != reg->idx) { 2599 raw_spin_unlock_irqrestore(&era->lock, flags); 2600 goto again; 2601 } 2602 } 2603 raw_spin_unlock_irqrestore(&era->lock, flags); 2604 2605 return c; 2606 } 2607 2608 static void 2609 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 2610 struct hw_perf_event_extra *reg) 2611 { 2612 struct er_account *era; 2613 2614 /* 2615 * Only put constraint if extra reg was actually allocated. Also takes 2616 * care of event which do not use an extra shared reg. 2617 * 2618 * Also, if this is a fake cpuc we shouldn't touch any event state 2619 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 2620 * either since it'll be thrown out. 2621 */ 2622 if (!reg->alloc || cpuc->is_fake) 2623 return; 2624 2625 era = &cpuc->shared_regs->regs[reg->idx]; 2626 2627 /* one fewer user */ 2628 atomic_dec(&era->ref); 2629 2630 /* allocate again next time */ 2631 reg->alloc = 0; 2632 } 2633 2634 static struct event_constraint * 2635 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 2636 struct perf_event *event) 2637 { 2638 struct event_constraint *c = NULL, *d; 2639 struct hw_perf_event_extra *xreg, *breg; 2640 2641 xreg = &event->hw.extra_reg; 2642 if (xreg->idx != EXTRA_REG_NONE) { 2643 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 2644 if (c == &emptyconstraint) 2645 return c; 2646 } 2647 breg = &event->hw.branch_reg; 2648 if (breg->idx != EXTRA_REG_NONE) { 2649 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 2650 if (d == &emptyconstraint) { 2651 __intel_shared_reg_put_constraints(cpuc, xreg); 2652 c = d; 2653 } 2654 } 2655 return c; 2656 } 2657 2658 struct event_constraint * 2659 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2660 struct perf_event *event) 2661 { 2662 struct event_constraint *c; 2663 2664 if (x86_pmu.event_constraints) { 2665 for_each_event_constraint(c, x86_pmu.event_constraints) { 2666 if ((event->hw.config & c->cmask) == c->code) { 2667 event->hw.flags |= c->flags; 2668 return c; 2669 } 2670 } 2671 } 2672 2673 return &unconstrained; 2674 } 2675 2676 static struct event_constraint * 2677 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2678 struct perf_event *event) 2679 { 2680 struct event_constraint *c; 2681 2682 c = intel_bts_constraints(event); 2683 if (c) 2684 return c; 2685 2686 c = intel_shared_regs_constraints(cpuc, event); 2687 if (c) 2688 return c; 2689 2690 c = intel_pebs_constraints(event); 2691 if (c) 2692 return c; 2693 2694 return x86_get_event_constraints(cpuc, idx, event); 2695 } 2696 2697 static void 2698 intel_start_scheduling(struct cpu_hw_events *cpuc) 2699 { 2700 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2701 struct intel_excl_states *xl; 2702 int tid = cpuc->excl_thread_id; 2703 2704 /* 2705 * nothing needed if in group validation mode 2706 */ 2707 if (cpuc->is_fake || !is_ht_workaround_enabled()) 2708 return; 2709 2710 /* 2711 * no exclusion needed 2712 */ 2713 if (WARN_ON_ONCE(!excl_cntrs)) 2714 return; 2715 2716 xl = &excl_cntrs->states[tid]; 2717 2718 xl->sched_started = true; 2719 /* 2720 * lock shared state until we are done scheduling 2721 * in stop_event_scheduling() 2722 * makes scheduling appear as a transaction 2723 */ 2724 raw_spin_lock(&excl_cntrs->lock); 2725 } 2726 2727 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2728 { 2729 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2730 struct event_constraint *c = cpuc->event_constraint[idx]; 2731 struct intel_excl_states *xl; 2732 int tid = cpuc->excl_thread_id; 2733 2734 if (cpuc->is_fake || !is_ht_workaround_enabled()) 2735 return; 2736 2737 if (WARN_ON_ONCE(!excl_cntrs)) 2738 return; 2739 2740 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 2741 return; 2742 2743 xl = &excl_cntrs->states[tid]; 2744 2745 lockdep_assert_held(&excl_cntrs->lock); 2746 2747 if (c->flags & PERF_X86_EVENT_EXCL) 2748 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 2749 else 2750 xl->state[cntr] = INTEL_EXCL_SHARED; 2751 } 2752 2753 static void 2754 intel_stop_scheduling(struct cpu_hw_events *cpuc) 2755 { 2756 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2757 struct intel_excl_states *xl; 2758 int tid = cpuc->excl_thread_id; 2759 2760 /* 2761 * nothing needed if in group validation mode 2762 */ 2763 if (cpuc->is_fake || !is_ht_workaround_enabled()) 2764 return; 2765 /* 2766 * no exclusion needed 2767 */ 2768 if (WARN_ON_ONCE(!excl_cntrs)) 2769 return; 2770 2771 xl = &excl_cntrs->states[tid]; 2772 2773 xl->sched_started = false; 2774 /* 2775 * release shared state lock (acquired in intel_start_scheduling()) 2776 */ 2777 raw_spin_unlock(&excl_cntrs->lock); 2778 } 2779 2780 static struct event_constraint * 2781 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 2782 int idx, struct event_constraint *c) 2783 { 2784 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2785 struct intel_excl_states *xlo; 2786 int tid = cpuc->excl_thread_id; 2787 int is_excl, i; 2788 2789 /* 2790 * validating a group does not require 2791 * enforcing cross-thread exclusion 2792 */ 2793 if (cpuc->is_fake || !is_ht_workaround_enabled()) 2794 return c; 2795 2796 /* 2797 * no exclusion needed 2798 */ 2799 if (WARN_ON_ONCE(!excl_cntrs)) 2800 return c; 2801 2802 /* 2803 * because we modify the constraint, we need 2804 * to make a copy. Static constraints come 2805 * from static const tables. 2806 * 2807 * only needed when constraint has not yet 2808 * been cloned (marked dynamic) 2809 */ 2810 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 2811 struct event_constraint *cx; 2812 2813 /* 2814 * grab pre-allocated constraint entry 2815 */ 2816 cx = &cpuc->constraint_list[idx]; 2817 2818 /* 2819 * initialize dynamic constraint 2820 * with static constraint 2821 */ 2822 *cx = *c; 2823 2824 /* 2825 * mark constraint as dynamic, so we 2826 * can free it later on 2827 */ 2828 cx->flags |= PERF_X86_EVENT_DYNAMIC; 2829 c = cx; 2830 } 2831 2832 /* 2833 * From here on, the constraint is dynamic. 2834 * Either it was just allocated above, or it 2835 * was allocated during a earlier invocation 2836 * of this function 2837 */ 2838 2839 /* 2840 * state of sibling HT 2841 */ 2842 xlo = &excl_cntrs->states[tid ^ 1]; 2843 2844 /* 2845 * event requires exclusive counter access 2846 * across HT threads 2847 */ 2848 is_excl = c->flags & PERF_X86_EVENT_EXCL; 2849 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 2850 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 2851 if (!cpuc->n_excl++) 2852 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 2853 } 2854 2855 /* 2856 * Modify static constraint with current dynamic 2857 * state of thread 2858 * 2859 * EXCLUSIVE: sibling counter measuring exclusive event 2860 * SHARED : sibling counter measuring non-exclusive event 2861 * UNUSED : sibling counter unused 2862 */ 2863 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 2864 /* 2865 * exclusive event in sibling counter 2866 * our corresponding counter cannot be used 2867 * regardless of our event 2868 */ 2869 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) 2870 __clear_bit(i, c->idxmsk); 2871 /* 2872 * if measuring an exclusive event, sibling 2873 * measuring non-exclusive, then counter cannot 2874 * be used 2875 */ 2876 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) 2877 __clear_bit(i, c->idxmsk); 2878 } 2879 2880 /* 2881 * recompute actual bit weight for scheduling algorithm 2882 */ 2883 c->weight = hweight64(c->idxmsk64); 2884 2885 /* 2886 * if we return an empty mask, then switch 2887 * back to static empty constraint to avoid 2888 * the cost of freeing later on 2889 */ 2890 if (c->weight == 0) 2891 c = &emptyconstraint; 2892 2893 return c; 2894 } 2895 2896 static struct event_constraint * 2897 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2898 struct perf_event *event) 2899 { 2900 struct event_constraint *c1 = NULL; 2901 struct event_constraint *c2; 2902 2903 if (idx >= 0) /* fake does < 0 */ 2904 c1 = cpuc->event_constraint[idx]; 2905 2906 /* 2907 * first time only 2908 * - static constraint: no change across incremental scheduling calls 2909 * - dynamic constraint: handled by intel_get_excl_constraints() 2910 */ 2911 c2 = __intel_get_event_constraints(cpuc, idx, event); 2912 if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) { 2913 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 2914 c1->weight = c2->weight; 2915 c2 = c1; 2916 } 2917 2918 if (cpuc->excl_cntrs) 2919 return intel_get_excl_constraints(cpuc, event, idx, c2); 2920 2921 return c2; 2922 } 2923 2924 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 2925 struct perf_event *event) 2926 { 2927 struct hw_perf_event *hwc = &event->hw; 2928 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2929 int tid = cpuc->excl_thread_id; 2930 struct intel_excl_states *xl; 2931 2932 /* 2933 * nothing needed if in group validation mode 2934 */ 2935 if (cpuc->is_fake) 2936 return; 2937 2938 if (WARN_ON_ONCE(!excl_cntrs)) 2939 return; 2940 2941 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 2942 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 2943 if (!--cpuc->n_excl) 2944 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 2945 } 2946 2947 /* 2948 * If event was actually assigned, then mark the counter state as 2949 * unused now. 2950 */ 2951 if (hwc->idx >= 0) { 2952 xl = &excl_cntrs->states[tid]; 2953 2954 /* 2955 * put_constraint may be called from x86_schedule_events() 2956 * which already has the lock held so here make locking 2957 * conditional. 2958 */ 2959 if (!xl->sched_started) 2960 raw_spin_lock(&excl_cntrs->lock); 2961 2962 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 2963 2964 if (!xl->sched_started) 2965 raw_spin_unlock(&excl_cntrs->lock); 2966 } 2967 } 2968 2969 static void 2970 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 2971 struct perf_event *event) 2972 { 2973 struct hw_perf_event_extra *reg; 2974 2975 reg = &event->hw.extra_reg; 2976 if (reg->idx != EXTRA_REG_NONE) 2977 __intel_shared_reg_put_constraints(cpuc, reg); 2978 2979 reg = &event->hw.branch_reg; 2980 if (reg->idx != EXTRA_REG_NONE) 2981 __intel_shared_reg_put_constraints(cpuc, reg); 2982 } 2983 2984 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 2985 struct perf_event *event) 2986 { 2987 intel_put_shared_regs_event_constraints(cpuc, event); 2988 2989 /* 2990 * is PMU has exclusive counter restrictions, then 2991 * all events are subject to and must call the 2992 * put_excl_constraints() routine 2993 */ 2994 if (cpuc->excl_cntrs) 2995 intel_put_excl_constraints(cpuc, event); 2996 } 2997 2998 static void intel_pebs_aliases_core2(struct perf_event *event) 2999 { 3000 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3001 /* 3002 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3003 * (0x003c) so that we can use it with PEBS. 3004 * 3005 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3006 * PEBS capable. However we can use INST_RETIRED.ANY_P 3007 * (0x00c0), which is a PEBS capable event, to get the same 3008 * count. 3009 * 3010 * INST_RETIRED.ANY_P counts the number of cycles that retires 3011 * CNTMASK instructions. By setting CNTMASK to a value (16) 3012 * larger than the maximum number of instructions that can be 3013 * retired per cycle (4) and then inverting the condition, we 3014 * count all cycles that retire 16 or less instructions, which 3015 * is every cycle. 3016 * 3017 * Thereby we gain a PEBS capable cycle counter. 3018 */ 3019 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3020 3021 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3022 event->hw.config = alt_config; 3023 } 3024 } 3025 3026 static void intel_pebs_aliases_snb(struct perf_event *event) 3027 { 3028 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3029 /* 3030 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3031 * (0x003c) so that we can use it with PEBS. 3032 * 3033 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3034 * PEBS capable. However we can use UOPS_RETIRED.ALL 3035 * (0x01c2), which is a PEBS capable event, to get the same 3036 * count. 3037 * 3038 * UOPS_RETIRED.ALL counts the number of cycles that retires 3039 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3040 * larger than the maximum number of micro-ops that can be 3041 * retired per cycle (4) and then inverting the condition, we 3042 * count all cycles that retire 16 or less micro-ops, which 3043 * is every cycle. 3044 * 3045 * Thereby we gain a PEBS capable cycle counter. 3046 */ 3047 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3048 3049 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3050 event->hw.config = alt_config; 3051 } 3052 } 3053 3054 static void intel_pebs_aliases_precdist(struct perf_event *event) 3055 { 3056 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3057 /* 3058 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3059 * (0x003c) so that we can use it with PEBS. 3060 * 3061 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3062 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3063 * (0x01c0), which is a PEBS capable event, to get the same 3064 * count. 3065 * 3066 * The PREC_DIST event has special support to minimize sample 3067 * shadowing effects. One drawback is that it can be 3068 * only programmed on counter 1, but that seems like an 3069 * acceptable trade off. 3070 */ 3071 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3072 3073 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3074 event->hw.config = alt_config; 3075 } 3076 } 3077 3078 static void intel_pebs_aliases_ivb(struct perf_event *event) 3079 { 3080 if (event->attr.precise_ip < 3) 3081 return intel_pebs_aliases_snb(event); 3082 return intel_pebs_aliases_precdist(event); 3083 } 3084 3085 static void intel_pebs_aliases_skl(struct perf_event *event) 3086 { 3087 if (event->attr.precise_ip < 3) 3088 return intel_pebs_aliases_core2(event); 3089 return intel_pebs_aliases_precdist(event); 3090 } 3091 3092 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3093 { 3094 unsigned long flags = x86_pmu.large_pebs_flags; 3095 3096 if (event->attr.use_clockid) 3097 flags &= ~PERF_SAMPLE_TIME; 3098 if (!event->attr.exclude_kernel) 3099 flags &= ~PERF_SAMPLE_REGS_USER; 3100 if (event->attr.sample_regs_user & ~PEBS_REGS) 3101 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3102 return flags; 3103 } 3104 3105 static int intel_pmu_hw_config(struct perf_event *event) 3106 { 3107 int ret = x86_pmu_hw_config(event); 3108 3109 if (ret) 3110 return ret; 3111 3112 if (event->attr.precise_ip) { 3113 if (!event->attr.freq) { 3114 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3115 if (!(event->attr.sample_type & 3116 ~intel_pmu_large_pebs_flags(event))) 3117 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3118 } 3119 if (x86_pmu.pebs_aliases) 3120 x86_pmu.pebs_aliases(event); 3121 3122 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) 3123 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY; 3124 } 3125 3126 if (needs_branch_stack(event)) { 3127 ret = intel_pmu_setup_lbr_filter(event); 3128 if (ret) 3129 return ret; 3130 3131 /* 3132 * BTS is set up earlier in this path, so don't account twice 3133 */ 3134 if (!intel_pmu_has_bts(event)) { 3135 /* disallow lbr if conflicting events are present */ 3136 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3137 return -EBUSY; 3138 3139 event->destroy = hw_perf_lbr_event_destroy; 3140 } 3141 } 3142 3143 if (event->attr.type != PERF_TYPE_RAW) 3144 return 0; 3145 3146 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 3147 return 0; 3148 3149 if (x86_pmu.version < 3) 3150 return -EINVAL; 3151 3152 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN)) 3153 return -EACCES; 3154 3155 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 3156 3157 return 0; 3158 } 3159 3160 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr) 3161 { 3162 if (x86_pmu.guest_get_msrs) 3163 return x86_pmu.guest_get_msrs(nr); 3164 *nr = 0; 3165 return NULL; 3166 } 3167 EXPORT_SYMBOL_GPL(perf_guest_get_msrs); 3168 3169 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) 3170 { 3171 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3172 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3173 3174 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; 3175 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; 3176 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; 3177 /* 3178 * If PMU counter has PEBS enabled it is not enough to disable counter 3179 * on a guest entry since PEBS memory write can overshoot guest entry 3180 * and corrupt guest memory. Disabling PEBS solves the problem. 3181 */ 3182 arr[1].msr = MSR_IA32_PEBS_ENABLE; 3183 arr[1].host = cpuc->pebs_enabled; 3184 arr[1].guest = 0; 3185 3186 *nr = 2; 3187 return arr; 3188 } 3189 3190 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) 3191 { 3192 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3193 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3194 int idx; 3195 3196 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3197 struct perf_event *event = cpuc->events[idx]; 3198 3199 arr[idx].msr = x86_pmu_config_addr(idx); 3200 arr[idx].host = arr[idx].guest = 0; 3201 3202 if (!test_bit(idx, cpuc->active_mask)) 3203 continue; 3204 3205 arr[idx].host = arr[idx].guest = 3206 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 3207 3208 if (event->attr.exclude_host) 3209 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3210 else if (event->attr.exclude_guest) 3211 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3212 } 3213 3214 *nr = x86_pmu.num_counters; 3215 return arr; 3216 } 3217 3218 static void core_pmu_enable_event(struct perf_event *event) 3219 { 3220 if (!event->attr.exclude_host) 3221 x86_pmu_enable_event(event); 3222 } 3223 3224 static void core_pmu_enable_all(int added) 3225 { 3226 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3227 int idx; 3228 3229 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3230 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 3231 3232 if (!test_bit(idx, cpuc->active_mask) || 3233 cpuc->events[idx]->attr.exclude_host) 3234 continue; 3235 3236 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 3237 } 3238 } 3239 3240 static int hsw_hw_config(struct perf_event *event) 3241 { 3242 int ret = intel_pmu_hw_config(event); 3243 3244 if (ret) 3245 return ret; 3246 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 3247 return 0; 3248 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 3249 3250 /* 3251 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 3252 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 3253 * this combination. 3254 */ 3255 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 3256 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 3257 event->attr.precise_ip > 0)) 3258 return -EOPNOTSUPP; 3259 3260 if (event_is_checkpointed(event)) { 3261 /* 3262 * Sampling of checkpointed events can cause situations where 3263 * the CPU constantly aborts because of a overflow, which is 3264 * then checkpointed back and ignored. Forbid checkpointing 3265 * for sampling. 3266 * 3267 * But still allow a long sampling period, so that perf stat 3268 * from KVM works. 3269 */ 3270 if (event->attr.sample_period > 0 && 3271 event->attr.sample_period < 0x7fffffff) 3272 return -EOPNOTSUPP; 3273 } 3274 return 0; 3275 } 3276 3277 static struct event_constraint counter0_constraint = 3278 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 3279 3280 static struct event_constraint counter2_constraint = 3281 EVENT_CONSTRAINT(0, 0x4, 0); 3282 3283 static struct event_constraint * 3284 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3285 struct perf_event *event) 3286 { 3287 struct event_constraint *c; 3288 3289 c = intel_get_event_constraints(cpuc, idx, event); 3290 3291 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 3292 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 3293 if (c->idxmsk64 & (1U << 2)) 3294 return &counter2_constraint; 3295 return &emptyconstraint; 3296 } 3297 3298 return c; 3299 } 3300 3301 static struct event_constraint * 3302 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3303 struct perf_event *event) 3304 { 3305 struct event_constraint *c; 3306 3307 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 3308 if (event->attr.precise_ip == 3) 3309 return &counter0_constraint; 3310 3311 c = intel_get_event_constraints(cpuc, idx, event); 3312 3313 return c; 3314 } 3315 3316 /* 3317 * Broadwell: 3318 * 3319 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 3320 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 3321 * the two to enforce a minimum period of 128 (the smallest value that has bits 3322 * 0-5 cleared and >= 100). 3323 * 3324 * Because of how the code in x86_perf_event_set_period() works, the truncation 3325 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 3326 * to make up for the 'lost' events due to carrying the 'error' in period_left. 3327 * 3328 * Therefore the effective (average) period matches the requested period, 3329 * despite coarser hardware granularity. 3330 */ 3331 static u64 bdw_limit_period(struct perf_event *event, u64 left) 3332 { 3333 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 3334 X86_CONFIG(.event=0xc0, .umask=0x01)) { 3335 if (left < 128) 3336 left = 128; 3337 left &= ~0x3fULL; 3338 } 3339 return left; 3340 } 3341 3342 PMU_FORMAT_ATTR(event, "config:0-7" ); 3343 PMU_FORMAT_ATTR(umask, "config:8-15" ); 3344 PMU_FORMAT_ATTR(edge, "config:18" ); 3345 PMU_FORMAT_ATTR(pc, "config:19" ); 3346 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 3347 PMU_FORMAT_ATTR(inv, "config:23" ); 3348 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 3349 PMU_FORMAT_ATTR(in_tx, "config:32"); 3350 PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 3351 3352 static struct attribute *intel_arch_formats_attr[] = { 3353 &format_attr_event.attr, 3354 &format_attr_umask.attr, 3355 &format_attr_edge.attr, 3356 &format_attr_pc.attr, 3357 &format_attr_inv.attr, 3358 &format_attr_cmask.attr, 3359 NULL, 3360 }; 3361 3362 ssize_t intel_event_sysfs_show(char *page, u64 config) 3363 { 3364 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 3365 3366 return x86_event_sysfs_show(page, config, event); 3367 } 3368 3369 struct intel_shared_regs *allocate_shared_regs(int cpu) 3370 { 3371 struct intel_shared_regs *regs; 3372 int i; 3373 3374 regs = kzalloc_node(sizeof(struct intel_shared_regs), 3375 GFP_KERNEL, cpu_to_node(cpu)); 3376 if (regs) { 3377 /* 3378 * initialize the locks to keep lockdep happy 3379 */ 3380 for (i = 0; i < EXTRA_REG_MAX; i++) 3381 raw_spin_lock_init(®s->regs[i].lock); 3382 3383 regs->core_id = -1; 3384 } 3385 return regs; 3386 } 3387 3388 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 3389 { 3390 struct intel_excl_cntrs *c; 3391 3392 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 3393 GFP_KERNEL, cpu_to_node(cpu)); 3394 if (c) { 3395 raw_spin_lock_init(&c->lock); 3396 c->core_id = -1; 3397 } 3398 return c; 3399 } 3400 3401 static int intel_pmu_cpu_prepare(int cpu) 3402 { 3403 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3404 3405 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 3406 cpuc->shared_regs = allocate_shared_regs(cpu); 3407 if (!cpuc->shared_regs) 3408 goto err; 3409 } 3410 3411 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 3412 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 3413 3414 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL); 3415 if (!cpuc->constraint_list) 3416 goto err_shared_regs; 3417 3418 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 3419 if (!cpuc->excl_cntrs) 3420 goto err_constraint_list; 3421 3422 cpuc->excl_thread_id = 0; 3423 } 3424 3425 return 0; 3426 3427 err_constraint_list: 3428 kfree(cpuc->constraint_list); 3429 cpuc->constraint_list = NULL; 3430 3431 err_shared_regs: 3432 kfree(cpuc->shared_regs); 3433 cpuc->shared_regs = NULL; 3434 3435 err: 3436 return -ENOMEM; 3437 } 3438 3439 static void flip_smm_bit(void *data) 3440 { 3441 unsigned long set = *(unsigned long *)data; 3442 3443 if (set > 0) { 3444 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 3445 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 3446 } else { 3447 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 3448 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 3449 } 3450 } 3451 3452 static void intel_pmu_cpu_starting(int cpu) 3453 { 3454 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3455 int core_id = topology_core_id(cpu); 3456 int i; 3457 3458 init_debug_store_on_cpu(cpu); 3459 /* 3460 * Deal with CPUs that don't clear their LBRs on power-up. 3461 */ 3462 intel_pmu_lbr_reset(); 3463 3464 cpuc->lbr_sel = NULL; 3465 3466 if (x86_pmu.version > 1) 3467 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 3468 3469 if (x86_pmu.counter_freezing) 3470 enable_counter_freeze(); 3471 3472 if (!cpuc->shared_regs) 3473 return; 3474 3475 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 3476 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 3477 struct intel_shared_regs *pc; 3478 3479 pc = per_cpu(cpu_hw_events, i).shared_regs; 3480 if (pc && pc->core_id == core_id) { 3481 cpuc->kfree_on_online[0] = cpuc->shared_regs; 3482 cpuc->shared_regs = pc; 3483 break; 3484 } 3485 } 3486 cpuc->shared_regs->core_id = core_id; 3487 cpuc->shared_regs->refcnt++; 3488 } 3489 3490 if (x86_pmu.lbr_sel_map) 3491 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 3492 3493 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 3494 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 3495 struct cpu_hw_events *sibling; 3496 struct intel_excl_cntrs *c; 3497 3498 sibling = &per_cpu(cpu_hw_events, i); 3499 c = sibling->excl_cntrs; 3500 if (c && c->core_id == core_id) { 3501 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 3502 cpuc->excl_cntrs = c; 3503 if (!sibling->excl_thread_id) 3504 cpuc->excl_thread_id = 1; 3505 break; 3506 } 3507 } 3508 cpuc->excl_cntrs->core_id = core_id; 3509 cpuc->excl_cntrs->refcnt++; 3510 } 3511 } 3512 3513 static void free_excl_cntrs(int cpu) 3514 { 3515 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3516 struct intel_excl_cntrs *c; 3517 3518 c = cpuc->excl_cntrs; 3519 if (c) { 3520 if (c->core_id == -1 || --c->refcnt == 0) 3521 kfree(c); 3522 cpuc->excl_cntrs = NULL; 3523 kfree(cpuc->constraint_list); 3524 cpuc->constraint_list = NULL; 3525 } 3526 } 3527 3528 static void intel_pmu_cpu_dying(int cpu) 3529 { 3530 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3531 struct intel_shared_regs *pc; 3532 3533 pc = cpuc->shared_regs; 3534 if (pc) { 3535 if (pc->core_id == -1 || --pc->refcnt == 0) 3536 kfree(pc); 3537 cpuc->shared_regs = NULL; 3538 } 3539 3540 free_excl_cntrs(cpu); 3541 3542 fini_debug_store_on_cpu(cpu); 3543 3544 if (x86_pmu.counter_freezing) 3545 disable_counter_freeze(); 3546 } 3547 3548 static void intel_pmu_sched_task(struct perf_event_context *ctx, 3549 bool sched_in) 3550 { 3551 intel_pmu_pebs_sched_task(ctx, sched_in); 3552 intel_pmu_lbr_sched_task(ctx, sched_in); 3553 } 3554 3555 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 3556 3557 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 3558 3559 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 3560 3561 static struct attribute *intel_arch3_formats_attr[] = { 3562 &format_attr_event.attr, 3563 &format_attr_umask.attr, 3564 &format_attr_edge.attr, 3565 &format_attr_pc.attr, 3566 &format_attr_any.attr, 3567 &format_attr_inv.attr, 3568 &format_attr_cmask.attr, 3569 NULL, 3570 }; 3571 3572 static struct attribute *hsw_format_attr[] = { 3573 &format_attr_in_tx.attr, 3574 &format_attr_in_tx_cp.attr, 3575 &format_attr_offcore_rsp.attr, 3576 &format_attr_ldlat.attr, 3577 NULL 3578 }; 3579 3580 static struct attribute *nhm_format_attr[] = { 3581 &format_attr_offcore_rsp.attr, 3582 &format_attr_ldlat.attr, 3583 NULL 3584 }; 3585 3586 static struct attribute *slm_format_attr[] = { 3587 &format_attr_offcore_rsp.attr, 3588 NULL 3589 }; 3590 3591 static struct attribute *skl_format_attr[] = { 3592 &format_attr_frontend.attr, 3593 NULL, 3594 }; 3595 3596 static __initconst const struct x86_pmu core_pmu = { 3597 .name = "core", 3598 .handle_irq = x86_pmu_handle_irq, 3599 .disable_all = x86_pmu_disable_all, 3600 .enable_all = core_pmu_enable_all, 3601 .enable = core_pmu_enable_event, 3602 .disable = x86_pmu_disable_event, 3603 .hw_config = x86_pmu_hw_config, 3604 .schedule_events = x86_schedule_events, 3605 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 3606 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 3607 .event_map = intel_pmu_event_map, 3608 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3609 .apic = 1, 3610 .large_pebs_flags = LARGE_PEBS_FLAGS, 3611 3612 /* 3613 * Intel PMCs cannot be accessed sanely above 32-bit width, 3614 * so we install an artificial 1<<31 period regardless of 3615 * the generic event period: 3616 */ 3617 .max_period = (1ULL<<31) - 1, 3618 .get_event_constraints = intel_get_event_constraints, 3619 .put_event_constraints = intel_put_event_constraints, 3620 .event_constraints = intel_core_event_constraints, 3621 .guest_get_msrs = core_guest_get_msrs, 3622 .format_attrs = intel_arch_formats_attr, 3623 .events_sysfs_show = intel_event_sysfs_show, 3624 3625 /* 3626 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 3627 * together with PMU version 1 and thus be using core_pmu with 3628 * shared_regs. We need following callbacks here to allocate 3629 * it properly. 3630 */ 3631 .cpu_prepare = intel_pmu_cpu_prepare, 3632 .cpu_starting = intel_pmu_cpu_starting, 3633 .cpu_dying = intel_pmu_cpu_dying, 3634 }; 3635 3636 static struct attribute *intel_pmu_attrs[]; 3637 3638 static __initconst const struct x86_pmu intel_pmu = { 3639 .name = "Intel", 3640 .handle_irq = intel_pmu_handle_irq, 3641 .disable_all = intel_pmu_disable_all, 3642 .enable_all = intel_pmu_enable_all, 3643 .enable = intel_pmu_enable_event, 3644 .disable = intel_pmu_disable_event, 3645 .add = intel_pmu_add_event, 3646 .del = intel_pmu_del_event, 3647 .read = intel_pmu_read_event, 3648 .hw_config = intel_pmu_hw_config, 3649 .schedule_events = x86_schedule_events, 3650 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 3651 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 3652 .event_map = intel_pmu_event_map, 3653 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3654 .apic = 1, 3655 .large_pebs_flags = LARGE_PEBS_FLAGS, 3656 /* 3657 * Intel PMCs cannot be accessed sanely above 32 bit width, 3658 * so we install an artificial 1<<31 period regardless of 3659 * the generic event period: 3660 */ 3661 .max_period = (1ULL << 31) - 1, 3662 .get_event_constraints = intel_get_event_constraints, 3663 .put_event_constraints = intel_put_event_constraints, 3664 .pebs_aliases = intel_pebs_aliases_core2, 3665 3666 .format_attrs = intel_arch3_formats_attr, 3667 .events_sysfs_show = intel_event_sysfs_show, 3668 3669 .attrs = intel_pmu_attrs, 3670 3671 .cpu_prepare = intel_pmu_cpu_prepare, 3672 .cpu_starting = intel_pmu_cpu_starting, 3673 .cpu_dying = intel_pmu_cpu_dying, 3674 .guest_get_msrs = intel_guest_get_msrs, 3675 .sched_task = intel_pmu_sched_task, 3676 }; 3677 3678 static __init void intel_clovertown_quirk(void) 3679 { 3680 /* 3681 * PEBS is unreliable due to: 3682 * 3683 * AJ67 - PEBS may experience CPL leaks 3684 * AJ68 - PEBS PMI may be delayed by one event 3685 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 3686 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 3687 * 3688 * AJ67 could be worked around by restricting the OS/USR flags. 3689 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 3690 * 3691 * AJ106 could possibly be worked around by not allowing LBR 3692 * usage from PEBS, including the fixup. 3693 * AJ68 could possibly be worked around by always programming 3694 * a pebs_event_reset[0] value and coping with the lost events. 3695 * 3696 * But taken together it might just make sense to not enable PEBS on 3697 * these chips. 3698 */ 3699 pr_warn("PEBS disabled due to CPU errata\n"); 3700 x86_pmu.pebs = 0; 3701 x86_pmu.pebs_constraints = NULL; 3702 } 3703 3704 static int intel_snb_pebs_broken(int cpu) 3705 { 3706 u32 rev = UINT_MAX; /* default to broken for unknown models */ 3707 3708 switch (cpu_data(cpu).x86_model) { 3709 case INTEL_FAM6_SANDYBRIDGE: 3710 rev = 0x28; 3711 break; 3712 3713 case INTEL_FAM6_SANDYBRIDGE_X: 3714 switch (cpu_data(cpu).x86_stepping) { 3715 case 6: rev = 0x618; break; 3716 case 7: rev = 0x70c; break; 3717 } 3718 } 3719 3720 return (cpu_data(cpu).microcode < rev); 3721 } 3722 3723 static void intel_snb_check_microcode(void) 3724 { 3725 int pebs_broken = 0; 3726 int cpu; 3727 3728 for_each_online_cpu(cpu) { 3729 if ((pebs_broken = intel_snb_pebs_broken(cpu))) 3730 break; 3731 } 3732 3733 if (pebs_broken == x86_pmu.pebs_broken) 3734 return; 3735 3736 /* 3737 * Serialized by the microcode lock.. 3738 */ 3739 if (x86_pmu.pebs_broken) { 3740 pr_info("PEBS enabled due to microcode update\n"); 3741 x86_pmu.pebs_broken = 0; 3742 } else { 3743 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 3744 x86_pmu.pebs_broken = 1; 3745 } 3746 } 3747 3748 static bool is_lbr_from(unsigned long msr) 3749 { 3750 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 3751 3752 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 3753 } 3754 3755 /* 3756 * Under certain circumstances, access certain MSR may cause #GP. 3757 * The function tests if the input MSR can be safely accessed. 3758 */ 3759 static bool check_msr(unsigned long msr, u64 mask) 3760 { 3761 u64 val_old, val_new, val_tmp; 3762 3763 /* 3764 * Read the current value, change it and read it back to see if it 3765 * matches, this is needed to detect certain hardware emulators 3766 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 3767 */ 3768 if (rdmsrl_safe(msr, &val_old)) 3769 return false; 3770 3771 /* 3772 * Only change the bits which can be updated by wrmsrl. 3773 */ 3774 val_tmp = val_old ^ mask; 3775 3776 if (is_lbr_from(msr)) 3777 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 3778 3779 if (wrmsrl_safe(msr, val_tmp) || 3780 rdmsrl_safe(msr, &val_new)) 3781 return false; 3782 3783 /* 3784 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 3785 * should equal rdmsrl()'s even with the quirk. 3786 */ 3787 if (val_new != val_tmp) 3788 return false; 3789 3790 if (is_lbr_from(msr)) 3791 val_old = lbr_from_signext_quirk_wr(val_old); 3792 3793 /* Here it's sure that the MSR can be safely accessed. 3794 * Restore the old value and return. 3795 */ 3796 wrmsrl(msr, val_old); 3797 3798 return true; 3799 } 3800 3801 static __init void intel_sandybridge_quirk(void) 3802 { 3803 x86_pmu.check_microcode = intel_snb_check_microcode; 3804 cpus_read_lock(); 3805 intel_snb_check_microcode(); 3806 cpus_read_unlock(); 3807 } 3808 3809 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 3810 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 3811 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 3812 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 3813 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 3814 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 3815 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 3816 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 3817 }; 3818 3819 static __init void intel_arch_events_quirk(void) 3820 { 3821 int bit; 3822 3823 /* disable event that reported as not presend by cpuid */ 3824 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 3825 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 3826 pr_warn("CPUID marked event: \'%s\' unavailable\n", 3827 intel_arch_events_map[bit].name); 3828 } 3829 } 3830 3831 static __init void intel_nehalem_quirk(void) 3832 { 3833 union cpuid10_ebx ebx; 3834 3835 ebx.full = x86_pmu.events_maskl; 3836 if (ebx.split.no_branch_misses_retired) { 3837 /* 3838 * Erratum AAJ80 detected, we work it around by using 3839 * the BR_MISP_EXEC.ANY event. This will over-count 3840 * branch-misses, but it's still much better than the 3841 * architectural event which is often completely bogus: 3842 */ 3843 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 3844 ebx.split.no_branch_misses_retired = 0; 3845 x86_pmu.events_maskl = ebx.full; 3846 pr_info("CPU erratum AAJ80 worked around\n"); 3847 } 3848 } 3849 3850 static bool intel_glp_counter_freezing_broken(int cpu) 3851 { 3852 u32 rev = UINT_MAX; /* default to broken for unknown stepping */ 3853 3854 switch (cpu_data(cpu).x86_stepping) { 3855 case 1: 3856 rev = 0x28; 3857 break; 3858 case 8: 3859 rev = 0x6; 3860 break; 3861 } 3862 3863 return (cpu_data(cpu).microcode < rev); 3864 } 3865 3866 static __init void intel_glp_counter_freezing_quirk(void) 3867 { 3868 /* Check if it's already disabled */ 3869 if (disable_counter_freezing) 3870 return; 3871 3872 /* 3873 * If the system starts with the wrong ucode, leave the 3874 * counter-freezing feature permanently disabled. 3875 */ 3876 if (intel_glp_counter_freezing_broken(raw_smp_processor_id())) { 3877 pr_info("PMU counter freezing disabled due to CPU errata," 3878 "please upgrade microcode\n"); 3879 x86_pmu.counter_freezing = false; 3880 x86_pmu.handle_irq = intel_pmu_handle_irq; 3881 } 3882 } 3883 3884 /* 3885 * enable software workaround for errata: 3886 * SNB: BJ122 3887 * IVB: BV98 3888 * HSW: HSD29 3889 * 3890 * Only needed when HT is enabled. However detecting 3891 * if HT is enabled is difficult (model specific). So instead, 3892 * we enable the workaround in the early boot, and verify if 3893 * it is needed in a later initcall phase once we have valid 3894 * topology information to check if HT is actually enabled 3895 */ 3896 static __init void intel_ht_bug(void) 3897 { 3898 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 3899 3900 x86_pmu.start_scheduling = intel_start_scheduling; 3901 x86_pmu.commit_scheduling = intel_commit_scheduling; 3902 x86_pmu.stop_scheduling = intel_stop_scheduling; 3903 } 3904 3905 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 3906 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 3907 3908 /* Haswell special events */ 3909 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 3910 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 3911 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 3912 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 3913 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 3914 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 3915 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 3916 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 3917 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 3918 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 3919 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 3920 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 3921 3922 static struct attribute *hsw_events_attrs[] = { 3923 EVENT_PTR(td_slots_issued), 3924 EVENT_PTR(td_slots_retired), 3925 EVENT_PTR(td_fetch_bubbles), 3926 EVENT_PTR(td_total_slots), 3927 EVENT_PTR(td_total_slots_scale), 3928 EVENT_PTR(td_recovery_bubbles), 3929 EVENT_PTR(td_recovery_bubbles_scale), 3930 NULL 3931 }; 3932 3933 static struct attribute *hsw_mem_events_attrs[] = { 3934 EVENT_PTR(mem_ld_hsw), 3935 EVENT_PTR(mem_st_hsw), 3936 NULL, 3937 }; 3938 3939 static struct attribute *hsw_tsx_events_attrs[] = { 3940 EVENT_PTR(tx_start), 3941 EVENT_PTR(tx_commit), 3942 EVENT_PTR(tx_abort), 3943 EVENT_PTR(tx_capacity), 3944 EVENT_PTR(tx_conflict), 3945 EVENT_PTR(el_start), 3946 EVENT_PTR(el_commit), 3947 EVENT_PTR(el_abort), 3948 EVENT_PTR(el_capacity), 3949 EVENT_PTR(el_conflict), 3950 EVENT_PTR(cycles_t), 3951 EVENT_PTR(cycles_ct), 3952 NULL 3953 }; 3954 3955 static ssize_t freeze_on_smi_show(struct device *cdev, 3956 struct device_attribute *attr, 3957 char *buf) 3958 { 3959 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 3960 } 3961 3962 static DEFINE_MUTEX(freeze_on_smi_mutex); 3963 3964 static ssize_t freeze_on_smi_store(struct device *cdev, 3965 struct device_attribute *attr, 3966 const char *buf, size_t count) 3967 { 3968 unsigned long val; 3969 ssize_t ret; 3970 3971 ret = kstrtoul(buf, 0, &val); 3972 if (ret) 3973 return ret; 3974 3975 if (val > 1) 3976 return -EINVAL; 3977 3978 mutex_lock(&freeze_on_smi_mutex); 3979 3980 if (x86_pmu.attr_freeze_on_smi == val) 3981 goto done; 3982 3983 x86_pmu.attr_freeze_on_smi = val; 3984 3985 get_online_cpus(); 3986 on_each_cpu(flip_smm_bit, &val, 1); 3987 put_online_cpus(); 3988 done: 3989 mutex_unlock(&freeze_on_smi_mutex); 3990 3991 return count; 3992 } 3993 3994 static DEVICE_ATTR_RW(freeze_on_smi); 3995 3996 static ssize_t branches_show(struct device *cdev, 3997 struct device_attribute *attr, 3998 char *buf) 3999 { 4000 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 4001 } 4002 4003 static DEVICE_ATTR_RO(branches); 4004 4005 static struct attribute *lbr_attrs[] = { 4006 &dev_attr_branches.attr, 4007 NULL 4008 }; 4009 4010 static char pmu_name_str[30]; 4011 4012 static ssize_t pmu_name_show(struct device *cdev, 4013 struct device_attribute *attr, 4014 char *buf) 4015 { 4016 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 4017 } 4018 4019 static DEVICE_ATTR_RO(pmu_name); 4020 4021 static struct attribute *intel_pmu_caps_attrs[] = { 4022 &dev_attr_pmu_name.attr, 4023 NULL 4024 }; 4025 4026 static struct attribute *intel_pmu_attrs[] = { 4027 &dev_attr_freeze_on_smi.attr, 4028 NULL, 4029 }; 4030 4031 static __init struct attribute ** 4032 get_events_attrs(struct attribute **base, 4033 struct attribute **mem, 4034 struct attribute **tsx) 4035 { 4036 struct attribute **attrs = base; 4037 struct attribute **old; 4038 4039 if (mem && x86_pmu.pebs) 4040 attrs = merge_attr(attrs, mem); 4041 4042 if (tsx && boot_cpu_has(X86_FEATURE_RTM)) { 4043 old = attrs; 4044 attrs = merge_attr(attrs, tsx); 4045 if (old != base) 4046 kfree(old); 4047 } 4048 4049 return attrs; 4050 } 4051 4052 __init int intel_pmu_init(void) 4053 { 4054 struct attribute **extra_attr = NULL; 4055 struct attribute **mem_attr = NULL; 4056 struct attribute **tsx_attr = NULL; 4057 struct attribute **to_free = NULL; 4058 union cpuid10_edx edx; 4059 union cpuid10_eax eax; 4060 union cpuid10_ebx ebx; 4061 struct event_constraint *c; 4062 unsigned int unused; 4063 struct extra_reg *er; 4064 int version, i; 4065 char *name; 4066 4067 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 4068 switch (boot_cpu_data.x86) { 4069 case 0x6: 4070 return p6_pmu_init(); 4071 case 0xb: 4072 return knc_pmu_init(); 4073 case 0xf: 4074 return p4_pmu_init(); 4075 } 4076 return -ENODEV; 4077 } 4078 4079 /* 4080 * Check whether the Architectural PerfMon supports 4081 * Branch Misses Retired hw_event or not. 4082 */ 4083 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); 4084 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 4085 return -ENODEV; 4086 4087 version = eax.split.version_id; 4088 if (version < 2) 4089 x86_pmu = core_pmu; 4090 else 4091 x86_pmu = intel_pmu; 4092 4093 x86_pmu.version = version; 4094 x86_pmu.num_counters = eax.split.num_counters; 4095 x86_pmu.cntval_bits = eax.split.bit_width; 4096 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 4097 4098 x86_pmu.events_maskl = ebx.full; 4099 x86_pmu.events_mask_len = eax.split.mask_length; 4100 4101 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 4102 4103 /* 4104 * Quirk: v2 perfmon does not report fixed-purpose events, so 4105 * assume at least 3 events, when not running in a hypervisor: 4106 */ 4107 if (version > 1) { 4108 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 4109 4110 x86_pmu.num_counters_fixed = 4111 max((int)edx.split.num_counters_fixed, assume); 4112 } 4113 4114 if (version >= 4) 4115 x86_pmu.counter_freezing = !disable_counter_freezing; 4116 4117 if (boot_cpu_has(X86_FEATURE_PDCM)) { 4118 u64 capabilities; 4119 4120 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 4121 x86_pmu.intel_cap.capabilities = capabilities; 4122 } 4123 4124 intel_ds_init(); 4125 4126 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 4127 4128 /* 4129 * Install the hw-cache-events table: 4130 */ 4131 switch (boot_cpu_data.x86_model) { 4132 case INTEL_FAM6_CORE_YONAH: 4133 pr_cont("Core events, "); 4134 name = "core"; 4135 break; 4136 4137 case INTEL_FAM6_CORE2_MEROM: 4138 x86_add_quirk(intel_clovertown_quirk); 4139 case INTEL_FAM6_CORE2_MEROM_L: 4140 case INTEL_FAM6_CORE2_PENRYN: 4141 case INTEL_FAM6_CORE2_DUNNINGTON: 4142 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 4143 sizeof(hw_cache_event_ids)); 4144 4145 intel_pmu_lbr_init_core(); 4146 4147 x86_pmu.event_constraints = intel_core2_event_constraints; 4148 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 4149 pr_cont("Core2 events, "); 4150 name = "core2"; 4151 break; 4152 4153 case INTEL_FAM6_NEHALEM: 4154 case INTEL_FAM6_NEHALEM_EP: 4155 case INTEL_FAM6_NEHALEM_EX: 4156 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 4157 sizeof(hw_cache_event_ids)); 4158 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 4159 sizeof(hw_cache_extra_regs)); 4160 4161 intel_pmu_lbr_init_nhm(); 4162 4163 x86_pmu.event_constraints = intel_nehalem_event_constraints; 4164 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 4165 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 4166 x86_pmu.extra_regs = intel_nehalem_extra_regs; 4167 4168 mem_attr = nhm_mem_events_attrs; 4169 4170 /* UOPS_ISSUED.STALLED_CYCLES */ 4171 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4172 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4173 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 4174 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4175 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 4176 4177 intel_pmu_pebs_data_source_nhm(); 4178 x86_add_quirk(intel_nehalem_quirk); 4179 x86_pmu.pebs_no_tlb = 1; 4180 extra_attr = nhm_format_attr; 4181 4182 pr_cont("Nehalem events, "); 4183 name = "nehalem"; 4184 break; 4185 4186 case INTEL_FAM6_ATOM_BONNELL: 4187 case INTEL_FAM6_ATOM_BONNELL_MID: 4188 case INTEL_FAM6_ATOM_SALTWELL: 4189 case INTEL_FAM6_ATOM_SALTWELL_MID: 4190 case INTEL_FAM6_ATOM_SALTWELL_TABLET: 4191 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 4192 sizeof(hw_cache_event_ids)); 4193 4194 intel_pmu_lbr_init_atom(); 4195 4196 x86_pmu.event_constraints = intel_gen_event_constraints; 4197 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 4198 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 4199 pr_cont("Atom events, "); 4200 name = "bonnell"; 4201 break; 4202 4203 case INTEL_FAM6_ATOM_SILVERMONT: 4204 case INTEL_FAM6_ATOM_SILVERMONT_X: 4205 case INTEL_FAM6_ATOM_SILVERMONT_MID: 4206 case INTEL_FAM6_ATOM_AIRMONT: 4207 case INTEL_FAM6_ATOM_AIRMONT_MID: 4208 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 4209 sizeof(hw_cache_event_ids)); 4210 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 4211 sizeof(hw_cache_extra_regs)); 4212 4213 intel_pmu_lbr_init_slm(); 4214 4215 x86_pmu.event_constraints = intel_slm_event_constraints; 4216 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 4217 x86_pmu.extra_regs = intel_slm_extra_regs; 4218 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4219 x86_pmu.cpu_events = slm_events_attrs; 4220 extra_attr = slm_format_attr; 4221 pr_cont("Silvermont events, "); 4222 name = "silvermont"; 4223 break; 4224 4225 case INTEL_FAM6_ATOM_GOLDMONT: 4226 case INTEL_FAM6_ATOM_GOLDMONT_X: 4227 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 4228 sizeof(hw_cache_event_ids)); 4229 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 4230 sizeof(hw_cache_extra_regs)); 4231 4232 intel_pmu_lbr_init_skl(); 4233 4234 x86_pmu.event_constraints = intel_slm_event_constraints; 4235 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 4236 x86_pmu.extra_regs = intel_glm_extra_regs; 4237 /* 4238 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 4239 * for precise cycles. 4240 * :pp is identical to :ppp 4241 */ 4242 x86_pmu.pebs_aliases = NULL; 4243 x86_pmu.pebs_prec_dist = true; 4244 x86_pmu.lbr_pt_coexist = true; 4245 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4246 x86_pmu.cpu_events = glm_events_attrs; 4247 extra_attr = slm_format_attr; 4248 pr_cont("Goldmont events, "); 4249 name = "goldmont"; 4250 break; 4251 4252 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4253 x86_add_quirk(intel_glp_counter_freezing_quirk); 4254 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 4255 sizeof(hw_cache_event_ids)); 4256 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 4257 sizeof(hw_cache_extra_regs)); 4258 4259 intel_pmu_lbr_init_skl(); 4260 4261 x86_pmu.event_constraints = intel_slm_event_constraints; 4262 x86_pmu.extra_regs = intel_glm_extra_regs; 4263 /* 4264 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 4265 * for precise cycles. 4266 */ 4267 x86_pmu.pebs_aliases = NULL; 4268 x86_pmu.pebs_prec_dist = true; 4269 x86_pmu.lbr_pt_coexist = true; 4270 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4271 x86_pmu.flags |= PMU_FL_PEBS_ALL; 4272 x86_pmu.get_event_constraints = glp_get_event_constraints; 4273 x86_pmu.cpu_events = glm_events_attrs; 4274 /* Goldmont Plus has 4-wide pipeline */ 4275 event_attr_td_total_slots_scale_glm.event_str = "4"; 4276 extra_attr = slm_format_attr; 4277 pr_cont("Goldmont plus events, "); 4278 name = "goldmont_plus"; 4279 break; 4280 4281 case INTEL_FAM6_WESTMERE: 4282 case INTEL_FAM6_WESTMERE_EP: 4283 case INTEL_FAM6_WESTMERE_EX: 4284 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 4285 sizeof(hw_cache_event_ids)); 4286 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 4287 sizeof(hw_cache_extra_regs)); 4288 4289 intel_pmu_lbr_init_nhm(); 4290 4291 x86_pmu.event_constraints = intel_westmere_event_constraints; 4292 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 4293 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 4294 x86_pmu.extra_regs = intel_westmere_extra_regs; 4295 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4296 4297 mem_attr = nhm_mem_events_attrs; 4298 4299 /* UOPS_ISSUED.STALLED_CYCLES */ 4300 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4301 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4302 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 4303 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4304 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 4305 4306 intel_pmu_pebs_data_source_nhm(); 4307 extra_attr = nhm_format_attr; 4308 pr_cont("Westmere events, "); 4309 name = "westmere"; 4310 break; 4311 4312 case INTEL_FAM6_SANDYBRIDGE: 4313 case INTEL_FAM6_SANDYBRIDGE_X: 4314 x86_add_quirk(intel_sandybridge_quirk); 4315 x86_add_quirk(intel_ht_bug); 4316 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 4317 sizeof(hw_cache_event_ids)); 4318 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 4319 sizeof(hw_cache_extra_regs)); 4320 4321 intel_pmu_lbr_init_snb(); 4322 4323 x86_pmu.event_constraints = intel_snb_event_constraints; 4324 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 4325 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 4326 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 4327 x86_pmu.extra_regs = intel_snbep_extra_regs; 4328 else 4329 x86_pmu.extra_regs = intel_snb_extra_regs; 4330 4331 4332 /* all extra regs are per-cpu when HT is on */ 4333 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4334 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4335 4336 x86_pmu.cpu_events = snb_events_attrs; 4337 mem_attr = snb_mem_events_attrs; 4338 4339 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 4340 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4341 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4342 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 4343 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4344 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 4345 4346 extra_attr = nhm_format_attr; 4347 4348 pr_cont("SandyBridge events, "); 4349 name = "sandybridge"; 4350 break; 4351 4352 case INTEL_FAM6_IVYBRIDGE: 4353 case INTEL_FAM6_IVYBRIDGE_X: 4354 x86_add_quirk(intel_ht_bug); 4355 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 4356 sizeof(hw_cache_event_ids)); 4357 /* dTLB-load-misses on IVB is different than SNB */ 4358 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 4359 4360 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 4361 sizeof(hw_cache_extra_regs)); 4362 4363 intel_pmu_lbr_init_snb(); 4364 4365 x86_pmu.event_constraints = intel_ivb_event_constraints; 4366 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 4367 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4368 x86_pmu.pebs_prec_dist = true; 4369 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 4370 x86_pmu.extra_regs = intel_snbep_extra_regs; 4371 else 4372 x86_pmu.extra_regs = intel_snb_extra_regs; 4373 /* all extra regs are per-cpu when HT is on */ 4374 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4375 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4376 4377 x86_pmu.cpu_events = snb_events_attrs; 4378 mem_attr = snb_mem_events_attrs; 4379 4380 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 4381 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4382 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4383 4384 extra_attr = nhm_format_attr; 4385 4386 pr_cont("IvyBridge events, "); 4387 name = "ivybridge"; 4388 break; 4389 4390 4391 case INTEL_FAM6_HASWELL_CORE: 4392 case INTEL_FAM6_HASWELL_X: 4393 case INTEL_FAM6_HASWELL_ULT: 4394 case INTEL_FAM6_HASWELL_GT3E: 4395 x86_add_quirk(intel_ht_bug); 4396 x86_pmu.late_ack = true; 4397 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4398 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4399 4400 intel_pmu_lbr_init_hsw(); 4401 4402 x86_pmu.event_constraints = intel_hsw_event_constraints; 4403 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 4404 x86_pmu.extra_regs = intel_snbep_extra_regs; 4405 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4406 x86_pmu.pebs_prec_dist = true; 4407 /* all extra regs are per-cpu when HT is on */ 4408 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4409 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4410 4411 x86_pmu.hw_config = hsw_hw_config; 4412 x86_pmu.get_event_constraints = hsw_get_event_constraints; 4413 x86_pmu.cpu_events = hsw_events_attrs; 4414 x86_pmu.lbr_double_abort = true; 4415 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4416 hsw_format_attr : nhm_format_attr; 4417 mem_attr = hsw_mem_events_attrs; 4418 tsx_attr = hsw_tsx_events_attrs; 4419 pr_cont("Haswell events, "); 4420 name = "haswell"; 4421 break; 4422 4423 case INTEL_FAM6_BROADWELL_CORE: 4424 case INTEL_FAM6_BROADWELL_XEON_D: 4425 case INTEL_FAM6_BROADWELL_GT3E: 4426 case INTEL_FAM6_BROADWELL_X: 4427 x86_pmu.late_ack = true; 4428 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4429 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4430 4431 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 4432 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 4433 BDW_L3_MISS|HSW_SNOOP_DRAM; 4434 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 4435 HSW_SNOOP_DRAM; 4436 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 4437 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 4438 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 4439 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 4440 4441 intel_pmu_lbr_init_hsw(); 4442 4443 x86_pmu.event_constraints = intel_bdw_event_constraints; 4444 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 4445 x86_pmu.extra_regs = intel_snbep_extra_regs; 4446 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4447 x86_pmu.pebs_prec_dist = true; 4448 /* all extra regs are per-cpu when HT is on */ 4449 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4450 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4451 4452 x86_pmu.hw_config = hsw_hw_config; 4453 x86_pmu.get_event_constraints = hsw_get_event_constraints; 4454 x86_pmu.cpu_events = hsw_events_attrs; 4455 x86_pmu.limit_period = bdw_limit_period; 4456 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4457 hsw_format_attr : nhm_format_attr; 4458 mem_attr = hsw_mem_events_attrs; 4459 tsx_attr = hsw_tsx_events_attrs; 4460 pr_cont("Broadwell events, "); 4461 name = "broadwell"; 4462 break; 4463 4464 case INTEL_FAM6_XEON_PHI_KNL: 4465 case INTEL_FAM6_XEON_PHI_KNM: 4466 memcpy(hw_cache_event_ids, 4467 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4468 memcpy(hw_cache_extra_regs, 4469 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4470 intel_pmu_lbr_init_knl(); 4471 4472 x86_pmu.event_constraints = intel_slm_event_constraints; 4473 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 4474 x86_pmu.extra_regs = intel_knl_extra_regs; 4475 4476 /* all extra regs are per-cpu when HT is on */ 4477 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4478 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4479 extra_attr = slm_format_attr; 4480 pr_cont("Knights Landing/Mill events, "); 4481 name = "knights-landing"; 4482 break; 4483 4484 case INTEL_FAM6_SKYLAKE_MOBILE: 4485 case INTEL_FAM6_SKYLAKE_DESKTOP: 4486 case INTEL_FAM6_SKYLAKE_X: 4487 case INTEL_FAM6_KABYLAKE_MOBILE: 4488 case INTEL_FAM6_KABYLAKE_DESKTOP: 4489 x86_pmu.late_ack = true; 4490 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4491 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4492 intel_pmu_lbr_init_skl(); 4493 4494 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 4495 event_attr_td_recovery_bubbles.event_str_noht = 4496 "event=0xd,umask=0x1,cmask=1"; 4497 event_attr_td_recovery_bubbles.event_str_ht = 4498 "event=0xd,umask=0x1,cmask=1,any=1"; 4499 4500 x86_pmu.event_constraints = intel_skl_event_constraints; 4501 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 4502 x86_pmu.extra_regs = intel_skl_extra_regs; 4503 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 4504 x86_pmu.pebs_prec_dist = true; 4505 /* all extra regs are per-cpu when HT is on */ 4506 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4507 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4508 4509 x86_pmu.hw_config = hsw_hw_config; 4510 x86_pmu.get_event_constraints = hsw_get_event_constraints; 4511 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4512 hsw_format_attr : nhm_format_attr; 4513 extra_attr = merge_attr(extra_attr, skl_format_attr); 4514 to_free = extra_attr; 4515 x86_pmu.cpu_events = hsw_events_attrs; 4516 mem_attr = hsw_mem_events_attrs; 4517 tsx_attr = hsw_tsx_events_attrs; 4518 intel_pmu_pebs_data_source_skl( 4519 boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X); 4520 pr_cont("Skylake events, "); 4521 name = "skylake"; 4522 break; 4523 4524 default: 4525 switch (x86_pmu.version) { 4526 case 1: 4527 x86_pmu.event_constraints = intel_v1_event_constraints; 4528 pr_cont("generic architected perfmon v1, "); 4529 name = "generic_arch_v1"; 4530 break; 4531 default: 4532 /* 4533 * default constraints for v2 and up 4534 */ 4535 x86_pmu.event_constraints = intel_gen_event_constraints; 4536 pr_cont("generic architected perfmon, "); 4537 name = "generic_arch_v2+"; 4538 break; 4539 } 4540 } 4541 4542 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 4543 4544 if (version >= 2 && extra_attr) { 4545 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr, 4546 extra_attr); 4547 WARN_ON(!x86_pmu.format_attrs); 4548 } 4549 4550 x86_pmu.cpu_events = get_events_attrs(x86_pmu.cpu_events, 4551 mem_attr, tsx_attr); 4552 4553 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { 4554 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 4555 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); 4556 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; 4557 } 4558 x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1; 4559 4560 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { 4561 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 4562 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); 4563 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; 4564 } 4565 4566 x86_pmu.intel_ctrl |= 4567 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; 4568 4569 if (x86_pmu.event_constraints) { 4570 /* 4571 * event on fixed counter2 (REF_CYCLES) only works on this 4572 * counter, so do not extend mask to generic counters 4573 */ 4574 for_each_event_constraint(c, x86_pmu.event_constraints) { 4575 if (c->cmask == FIXED_EVENT_FLAGS 4576 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) { 4577 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; 4578 } 4579 c->idxmsk64 &= 4580 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed)); 4581 c->weight = hweight64(c->idxmsk64); 4582 } 4583 } 4584 4585 /* 4586 * Access LBR MSR may cause #GP under certain circumstances. 4587 * E.g. KVM doesn't support LBR MSR 4588 * Check all LBT MSR here. 4589 * Disable LBR access if any LBR MSRs can not be accessed. 4590 */ 4591 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 4592 x86_pmu.lbr_nr = 0; 4593 for (i = 0; i < x86_pmu.lbr_nr; i++) { 4594 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 4595 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 4596 x86_pmu.lbr_nr = 0; 4597 } 4598 4599 x86_pmu.caps_attrs = intel_pmu_caps_attrs; 4600 4601 if (x86_pmu.lbr_nr) { 4602 x86_pmu.caps_attrs = merge_attr(x86_pmu.caps_attrs, lbr_attrs); 4603 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 4604 } 4605 4606 /* 4607 * Access extra MSR may cause #GP under certain circumstances. 4608 * E.g. KVM doesn't support offcore event 4609 * Check all extra_regs here. 4610 */ 4611 if (x86_pmu.extra_regs) { 4612 for (er = x86_pmu.extra_regs; er->msr; er++) { 4613 er->extra_msr_access = check_msr(er->msr, 0x11UL); 4614 /* Disable LBR select mapping */ 4615 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 4616 x86_pmu.lbr_sel_map = NULL; 4617 } 4618 } 4619 4620 /* Support full width counters using alternative MSR range */ 4621 if (x86_pmu.intel_cap.full_width_write) { 4622 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 4623 x86_pmu.perfctr = MSR_IA32_PMC0; 4624 pr_cont("full-width counters, "); 4625 } 4626 4627 /* 4628 * For arch perfmon 4 use counter freezing to avoid 4629 * several MSR accesses in the PMI. 4630 */ 4631 if (x86_pmu.counter_freezing) 4632 x86_pmu.handle_irq = intel_pmu_handle_irq_v4; 4633 4634 kfree(to_free); 4635 return 0; 4636 } 4637 4638 /* 4639 * HT bug: phase 2 init 4640 * Called once we have valid topology information to check 4641 * whether or not HT is enabled 4642 * If HT is off, then we disable the workaround 4643 */ 4644 static __init int fixup_ht_bug(void) 4645 { 4646 int c; 4647 /* 4648 * problem not present on this CPU model, nothing to do 4649 */ 4650 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 4651 return 0; 4652 4653 if (topology_max_smt_threads() > 1) { 4654 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 4655 return 0; 4656 } 4657 4658 cpus_read_lock(); 4659 4660 hardlockup_detector_perf_stop(); 4661 4662 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 4663 4664 x86_pmu.start_scheduling = NULL; 4665 x86_pmu.commit_scheduling = NULL; 4666 x86_pmu.stop_scheduling = NULL; 4667 4668 hardlockup_detector_perf_restart(); 4669 4670 for_each_online_cpu(c) 4671 free_excl_cntrs(c); 4672 4673 cpus_read_unlock(); 4674 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 4675 return 0; 4676 } 4677 subsys_initcall(fixup_ht_bug) 4678