1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Per core/cpu state 4 * 5 * Used to coordinate shared registers between HT threads or 6 * among events on a single PMU. 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/stddef.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/export.h> 16 #include <linux/nmi.h> 17 18 #include <asm/cpufeature.h> 19 #include <asm/hardirq.h> 20 #include <asm/intel-family.h> 21 #include <asm/intel_pt.h> 22 #include <asm/apic.h> 23 #include <asm/cpu_device_id.h> 24 25 #include "../perf_event.h" 26 27 /* 28 * Intel PerfMon, used on Core and later. 29 */ 30 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 31 { 32 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 33 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 34 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 35 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 36 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 37 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 38 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 39 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 40 }; 41 42 static struct event_constraint intel_core_event_constraints[] __read_mostly = 43 { 44 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 45 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 46 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 47 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 48 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 49 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 50 EVENT_CONSTRAINT_END 51 }; 52 53 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 54 { 55 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 56 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 57 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 58 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 59 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 60 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 61 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 62 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 63 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 64 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 65 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 66 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 67 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 68 EVENT_CONSTRAINT_END 69 }; 70 71 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 72 { 73 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 74 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 75 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 76 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 77 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 78 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 79 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 80 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 81 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 82 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 83 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 84 EVENT_CONSTRAINT_END 85 }; 86 87 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 88 { 89 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 90 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 91 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 92 EVENT_EXTRA_END 93 }; 94 95 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 96 { 97 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 98 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 99 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 100 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 101 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 102 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 103 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 104 EVENT_CONSTRAINT_END 105 }; 106 107 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 108 { 109 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 110 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 111 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 112 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 113 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 114 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 115 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 116 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 117 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 118 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 119 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 120 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 121 122 /* 123 * When HT is off these events can only run on the bottom 4 counters 124 * When HT is on, they are impacted by the HT bug and require EXCL access 125 */ 126 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 127 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 128 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 129 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 130 131 EVENT_CONSTRAINT_END 132 }; 133 134 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 135 { 136 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 137 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 138 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 139 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 140 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ 141 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 142 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 143 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 144 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 145 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 146 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 147 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 148 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 149 150 /* 151 * When HT is off these events can only run on the bottom 4 counters 152 * When HT is on, they are impacted by the HT bug and require EXCL access 153 */ 154 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 155 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 156 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 157 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 158 159 EVENT_CONSTRAINT_END 160 }; 161 162 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 163 { 164 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 165 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 166 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 167 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 168 EVENT_EXTRA_END 169 }; 170 171 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 172 { 173 EVENT_CONSTRAINT_END 174 }; 175 176 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 177 { 178 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 179 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 180 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 181 EVENT_CONSTRAINT_END 182 }; 183 184 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 185 { 186 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 187 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 188 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 189 EVENT_CONSTRAINT_END 190 }; 191 192 static struct event_constraint intel_skl_event_constraints[] = { 193 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 194 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 195 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 196 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 197 198 /* 199 * when HT is off, these can only run on the bottom 4 counters 200 */ 201 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 202 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 203 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 204 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 205 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 206 207 EVENT_CONSTRAINT_END 208 }; 209 210 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 211 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 212 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 213 EVENT_EXTRA_END 214 }; 215 216 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 217 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 218 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 219 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 220 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 221 EVENT_EXTRA_END 222 }; 223 224 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 225 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 226 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 227 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 228 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 229 EVENT_EXTRA_END 230 }; 231 232 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 233 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 234 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 235 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 236 /* 237 * Note the low 8 bits eventsel code is not a continuous field, containing 238 * some #GPing bits. These are masked out. 239 */ 240 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 241 EVENT_EXTRA_END 242 }; 243 244 static struct event_constraint intel_icl_event_constraints[] = { 245 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 246 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */ 247 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 248 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 249 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 250 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 251 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 252 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 253 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 254 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 255 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 256 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 257 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf), 258 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 259 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 260 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 261 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 262 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 263 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 264 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 265 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 266 INTEL_EVENT_CONSTRAINT(0xef, 0xf), 267 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 268 EVENT_CONSTRAINT_END 269 }; 270 271 static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 272 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 273 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 274 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 275 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 276 EVENT_EXTRA_END 277 }; 278 279 static struct extra_reg intel_spr_extra_regs[] __read_mostly = { 280 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 281 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 282 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 283 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 284 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 285 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 286 EVENT_EXTRA_END 287 }; 288 289 static struct event_constraint intel_spr_event_constraints[] = { 290 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 291 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */ 292 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 293 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 294 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 295 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 296 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 297 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 298 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 299 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 300 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 301 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 302 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 303 304 INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 305 INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 306 /* 307 * Generally event codes < 0x90 are restricted to counters 0-3. 308 * The 0x2E and 0x3C are exception, which has no restriction. 309 */ 310 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 311 312 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 313 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 314 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 315 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 316 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 317 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 318 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 319 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 320 /* 321 * Generally event codes >= 0x90 are likely to have no restrictions. 322 * The exception are defined as above. 323 */ 324 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 325 326 EVENT_CONSTRAINT_END 327 }; 328 329 330 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 331 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 332 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 333 334 static struct attribute *nhm_mem_events_attrs[] = { 335 EVENT_PTR(mem_ld_nhm), 336 NULL, 337 }; 338 339 /* 340 * topdown events for Intel Core CPUs. 341 * 342 * The events are all in slots, which is a free slot in a 4 wide 343 * pipeline. Some events are already reported in slots, for cycle 344 * events we multiply by the pipeline width (4). 345 * 346 * With Hyper Threading on, topdown metrics are either summed or averaged 347 * between the threads of a core: (count_t0 + count_t1). 348 * 349 * For the average case the metric is always scaled to pipeline width, 350 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 351 */ 352 353 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 354 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 355 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 356 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 357 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 358 "event=0xe,umask=0x1"); /* uops_issued.any */ 359 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 360 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 361 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 362 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 363 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 364 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 365 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 366 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 367 "4", "2"); 368 369 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 370 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 371 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 372 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 373 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 374 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 375 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 376 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 377 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 378 379 static struct attribute *snb_events_attrs[] = { 380 EVENT_PTR(td_slots_issued), 381 EVENT_PTR(td_slots_retired), 382 EVENT_PTR(td_fetch_bubbles), 383 EVENT_PTR(td_total_slots), 384 EVENT_PTR(td_total_slots_scale), 385 EVENT_PTR(td_recovery_bubbles), 386 EVENT_PTR(td_recovery_bubbles_scale), 387 NULL, 388 }; 389 390 static struct attribute *snb_mem_events_attrs[] = { 391 EVENT_PTR(mem_ld_snb), 392 EVENT_PTR(mem_st_snb), 393 NULL, 394 }; 395 396 static struct event_constraint intel_hsw_event_constraints[] = { 397 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 398 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 399 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 400 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 401 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 402 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 403 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 404 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 405 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 406 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 407 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 408 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 409 410 /* 411 * When HT is off these events can only run on the bottom 4 counters 412 * When HT is on, they are impacted by the HT bug and require EXCL access 413 */ 414 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 415 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 416 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 417 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 418 419 EVENT_CONSTRAINT_END 420 }; 421 422 static struct event_constraint intel_bdw_event_constraints[] = { 423 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 424 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 425 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 426 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 427 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 428 /* 429 * when HT is off, these can only run on the bottom 4 counters 430 */ 431 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 432 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 433 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 434 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 435 EVENT_CONSTRAINT_END 436 }; 437 438 static u64 intel_pmu_event_map(int hw_event) 439 { 440 return intel_perfmon_event_map[hw_event]; 441 } 442 443 static __initconst const u64 spr_hw_cache_event_ids 444 [PERF_COUNT_HW_CACHE_MAX] 445 [PERF_COUNT_HW_CACHE_OP_MAX] 446 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 447 { 448 [ C(L1D ) ] = { 449 [ C(OP_READ) ] = { 450 [ C(RESULT_ACCESS) ] = 0x81d0, 451 [ C(RESULT_MISS) ] = 0xe124, 452 }, 453 [ C(OP_WRITE) ] = { 454 [ C(RESULT_ACCESS) ] = 0x82d0, 455 }, 456 }, 457 [ C(L1I ) ] = { 458 [ C(OP_READ) ] = { 459 [ C(RESULT_MISS) ] = 0xe424, 460 }, 461 [ C(OP_WRITE) ] = { 462 [ C(RESULT_ACCESS) ] = -1, 463 [ C(RESULT_MISS) ] = -1, 464 }, 465 }, 466 [ C(LL ) ] = { 467 [ C(OP_READ) ] = { 468 [ C(RESULT_ACCESS) ] = 0x12a, 469 [ C(RESULT_MISS) ] = 0x12a, 470 }, 471 [ C(OP_WRITE) ] = { 472 [ C(RESULT_ACCESS) ] = 0x12a, 473 [ C(RESULT_MISS) ] = 0x12a, 474 }, 475 }, 476 [ C(DTLB) ] = { 477 [ C(OP_READ) ] = { 478 [ C(RESULT_ACCESS) ] = 0x81d0, 479 [ C(RESULT_MISS) ] = 0xe12, 480 }, 481 [ C(OP_WRITE) ] = { 482 [ C(RESULT_ACCESS) ] = 0x82d0, 483 [ C(RESULT_MISS) ] = 0xe13, 484 }, 485 }, 486 [ C(ITLB) ] = { 487 [ C(OP_READ) ] = { 488 [ C(RESULT_ACCESS) ] = -1, 489 [ C(RESULT_MISS) ] = 0xe11, 490 }, 491 [ C(OP_WRITE) ] = { 492 [ C(RESULT_ACCESS) ] = -1, 493 [ C(RESULT_MISS) ] = -1, 494 }, 495 [ C(OP_PREFETCH) ] = { 496 [ C(RESULT_ACCESS) ] = -1, 497 [ C(RESULT_MISS) ] = -1, 498 }, 499 }, 500 [ C(BPU ) ] = { 501 [ C(OP_READ) ] = { 502 [ C(RESULT_ACCESS) ] = 0x4c4, 503 [ C(RESULT_MISS) ] = 0x4c5, 504 }, 505 [ C(OP_WRITE) ] = { 506 [ C(RESULT_ACCESS) ] = -1, 507 [ C(RESULT_MISS) ] = -1, 508 }, 509 [ C(OP_PREFETCH) ] = { 510 [ C(RESULT_ACCESS) ] = -1, 511 [ C(RESULT_MISS) ] = -1, 512 }, 513 }, 514 [ C(NODE) ] = { 515 [ C(OP_READ) ] = { 516 [ C(RESULT_ACCESS) ] = 0x12a, 517 [ C(RESULT_MISS) ] = 0x12a, 518 }, 519 }, 520 }; 521 522 static __initconst const u64 spr_hw_cache_extra_regs 523 [PERF_COUNT_HW_CACHE_MAX] 524 [PERF_COUNT_HW_CACHE_OP_MAX] 525 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 526 { 527 [ C(LL ) ] = { 528 [ C(OP_READ) ] = { 529 [ C(RESULT_ACCESS) ] = 0x10001, 530 [ C(RESULT_MISS) ] = 0x3fbfc00001, 531 }, 532 [ C(OP_WRITE) ] = { 533 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, 534 [ C(RESULT_MISS) ] = 0x3f3fc00002, 535 }, 536 }, 537 [ C(NODE) ] = { 538 [ C(OP_READ) ] = { 539 [ C(RESULT_ACCESS) ] = 0x10c000001, 540 [ C(RESULT_MISS) ] = 0x3fb3000001, 541 }, 542 }, 543 }; 544 545 /* 546 * Notes on the events: 547 * - data reads do not include code reads (comparable to earlier tables) 548 * - data counts include speculative execution (except L1 write, dtlb, bpu) 549 * - remote node access includes remote memory, remote cache, remote mmio. 550 * - prefetches are not included in the counts. 551 * - icache miss does not include decoded icache 552 */ 553 554 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 555 #define SKL_DEMAND_RFO BIT_ULL(1) 556 #define SKL_ANY_RESPONSE BIT_ULL(16) 557 #define SKL_SUPPLIER_NONE BIT_ULL(17) 558 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 559 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 560 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 561 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 562 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 563 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 564 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 565 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 566 #define SKL_SPL_HIT BIT_ULL(30) 567 #define SKL_SNOOP_NONE BIT_ULL(31) 568 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 569 #define SKL_SNOOP_MISS BIT_ULL(33) 570 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 571 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 572 #define SKL_SNOOP_HITM BIT_ULL(36) 573 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 574 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 575 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 576 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 577 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 578 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 579 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 580 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 581 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 582 SKL_SNOOP_HITM|SKL_SPL_HIT) 583 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 584 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 585 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 586 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 587 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 588 589 static __initconst const u64 skl_hw_cache_event_ids 590 [PERF_COUNT_HW_CACHE_MAX] 591 [PERF_COUNT_HW_CACHE_OP_MAX] 592 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 593 { 594 [ C(L1D ) ] = { 595 [ C(OP_READ) ] = { 596 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 597 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 598 }, 599 [ C(OP_WRITE) ] = { 600 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 601 [ C(RESULT_MISS) ] = 0x0, 602 }, 603 [ C(OP_PREFETCH) ] = { 604 [ C(RESULT_ACCESS) ] = 0x0, 605 [ C(RESULT_MISS) ] = 0x0, 606 }, 607 }, 608 [ C(L1I ) ] = { 609 [ C(OP_READ) ] = { 610 [ C(RESULT_ACCESS) ] = 0x0, 611 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 612 }, 613 [ C(OP_WRITE) ] = { 614 [ C(RESULT_ACCESS) ] = -1, 615 [ C(RESULT_MISS) ] = -1, 616 }, 617 [ C(OP_PREFETCH) ] = { 618 [ C(RESULT_ACCESS) ] = 0x0, 619 [ C(RESULT_MISS) ] = 0x0, 620 }, 621 }, 622 [ C(LL ) ] = { 623 [ C(OP_READ) ] = { 624 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 625 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 626 }, 627 [ C(OP_WRITE) ] = { 628 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 629 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 630 }, 631 [ C(OP_PREFETCH) ] = { 632 [ C(RESULT_ACCESS) ] = 0x0, 633 [ C(RESULT_MISS) ] = 0x0, 634 }, 635 }, 636 [ C(DTLB) ] = { 637 [ C(OP_READ) ] = { 638 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 639 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 640 }, 641 [ C(OP_WRITE) ] = { 642 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 643 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 644 }, 645 [ C(OP_PREFETCH) ] = { 646 [ C(RESULT_ACCESS) ] = 0x0, 647 [ C(RESULT_MISS) ] = 0x0, 648 }, 649 }, 650 [ C(ITLB) ] = { 651 [ C(OP_READ) ] = { 652 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 653 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 654 }, 655 [ C(OP_WRITE) ] = { 656 [ C(RESULT_ACCESS) ] = -1, 657 [ C(RESULT_MISS) ] = -1, 658 }, 659 [ C(OP_PREFETCH) ] = { 660 [ C(RESULT_ACCESS) ] = -1, 661 [ C(RESULT_MISS) ] = -1, 662 }, 663 }, 664 [ C(BPU ) ] = { 665 [ C(OP_READ) ] = { 666 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 667 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 668 }, 669 [ C(OP_WRITE) ] = { 670 [ C(RESULT_ACCESS) ] = -1, 671 [ C(RESULT_MISS) ] = -1, 672 }, 673 [ C(OP_PREFETCH) ] = { 674 [ C(RESULT_ACCESS) ] = -1, 675 [ C(RESULT_MISS) ] = -1, 676 }, 677 }, 678 [ C(NODE) ] = { 679 [ C(OP_READ) ] = { 680 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 681 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 682 }, 683 [ C(OP_WRITE) ] = { 684 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 685 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 686 }, 687 [ C(OP_PREFETCH) ] = { 688 [ C(RESULT_ACCESS) ] = 0x0, 689 [ C(RESULT_MISS) ] = 0x0, 690 }, 691 }, 692 }; 693 694 static __initconst const u64 skl_hw_cache_extra_regs 695 [PERF_COUNT_HW_CACHE_MAX] 696 [PERF_COUNT_HW_CACHE_OP_MAX] 697 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 698 { 699 [ C(LL ) ] = { 700 [ C(OP_READ) ] = { 701 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 702 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 703 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 704 SKL_L3_MISS|SKL_ANY_SNOOP| 705 SKL_SUPPLIER_NONE, 706 }, 707 [ C(OP_WRITE) ] = { 708 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 709 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 710 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 711 SKL_L3_MISS|SKL_ANY_SNOOP| 712 SKL_SUPPLIER_NONE, 713 }, 714 [ C(OP_PREFETCH) ] = { 715 [ C(RESULT_ACCESS) ] = 0x0, 716 [ C(RESULT_MISS) ] = 0x0, 717 }, 718 }, 719 [ C(NODE) ] = { 720 [ C(OP_READ) ] = { 721 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 722 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 723 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 724 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 725 }, 726 [ C(OP_WRITE) ] = { 727 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 728 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 729 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 730 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 731 }, 732 [ C(OP_PREFETCH) ] = { 733 [ C(RESULT_ACCESS) ] = 0x0, 734 [ C(RESULT_MISS) ] = 0x0, 735 }, 736 }, 737 }; 738 739 #define SNB_DMND_DATA_RD (1ULL << 0) 740 #define SNB_DMND_RFO (1ULL << 1) 741 #define SNB_DMND_IFETCH (1ULL << 2) 742 #define SNB_DMND_WB (1ULL << 3) 743 #define SNB_PF_DATA_RD (1ULL << 4) 744 #define SNB_PF_RFO (1ULL << 5) 745 #define SNB_PF_IFETCH (1ULL << 6) 746 #define SNB_LLC_DATA_RD (1ULL << 7) 747 #define SNB_LLC_RFO (1ULL << 8) 748 #define SNB_LLC_IFETCH (1ULL << 9) 749 #define SNB_BUS_LOCKS (1ULL << 10) 750 #define SNB_STRM_ST (1ULL << 11) 751 #define SNB_OTHER (1ULL << 15) 752 #define SNB_RESP_ANY (1ULL << 16) 753 #define SNB_NO_SUPP (1ULL << 17) 754 #define SNB_LLC_HITM (1ULL << 18) 755 #define SNB_LLC_HITE (1ULL << 19) 756 #define SNB_LLC_HITS (1ULL << 20) 757 #define SNB_LLC_HITF (1ULL << 21) 758 #define SNB_LOCAL (1ULL << 22) 759 #define SNB_REMOTE (0xffULL << 23) 760 #define SNB_SNP_NONE (1ULL << 31) 761 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 762 #define SNB_SNP_MISS (1ULL << 33) 763 #define SNB_NO_FWD (1ULL << 34) 764 #define SNB_SNP_FWD (1ULL << 35) 765 #define SNB_HITM (1ULL << 36) 766 #define SNB_NON_DRAM (1ULL << 37) 767 768 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 769 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 770 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 771 772 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 773 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 774 SNB_HITM) 775 776 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 777 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 778 779 #define SNB_L3_ACCESS SNB_RESP_ANY 780 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 781 782 static __initconst const u64 snb_hw_cache_extra_regs 783 [PERF_COUNT_HW_CACHE_MAX] 784 [PERF_COUNT_HW_CACHE_OP_MAX] 785 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 786 { 787 [ C(LL ) ] = { 788 [ C(OP_READ) ] = { 789 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 790 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 791 }, 792 [ C(OP_WRITE) ] = { 793 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 794 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 795 }, 796 [ C(OP_PREFETCH) ] = { 797 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 798 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 799 }, 800 }, 801 [ C(NODE) ] = { 802 [ C(OP_READ) ] = { 803 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 804 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 805 }, 806 [ C(OP_WRITE) ] = { 807 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 808 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 809 }, 810 [ C(OP_PREFETCH) ] = { 811 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 812 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 813 }, 814 }, 815 }; 816 817 static __initconst const u64 snb_hw_cache_event_ids 818 [PERF_COUNT_HW_CACHE_MAX] 819 [PERF_COUNT_HW_CACHE_OP_MAX] 820 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 821 { 822 [ C(L1D) ] = { 823 [ C(OP_READ) ] = { 824 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 825 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 826 }, 827 [ C(OP_WRITE) ] = { 828 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 829 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 830 }, 831 [ C(OP_PREFETCH) ] = { 832 [ C(RESULT_ACCESS) ] = 0x0, 833 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 834 }, 835 }, 836 [ C(L1I ) ] = { 837 [ C(OP_READ) ] = { 838 [ C(RESULT_ACCESS) ] = 0x0, 839 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 840 }, 841 [ C(OP_WRITE) ] = { 842 [ C(RESULT_ACCESS) ] = -1, 843 [ C(RESULT_MISS) ] = -1, 844 }, 845 [ C(OP_PREFETCH) ] = { 846 [ C(RESULT_ACCESS) ] = 0x0, 847 [ C(RESULT_MISS) ] = 0x0, 848 }, 849 }, 850 [ C(LL ) ] = { 851 [ C(OP_READ) ] = { 852 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 853 [ C(RESULT_ACCESS) ] = 0x01b7, 854 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 855 [ C(RESULT_MISS) ] = 0x01b7, 856 }, 857 [ C(OP_WRITE) ] = { 858 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 859 [ C(RESULT_ACCESS) ] = 0x01b7, 860 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 861 [ C(RESULT_MISS) ] = 0x01b7, 862 }, 863 [ C(OP_PREFETCH) ] = { 864 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 865 [ C(RESULT_ACCESS) ] = 0x01b7, 866 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 867 [ C(RESULT_MISS) ] = 0x01b7, 868 }, 869 }, 870 [ C(DTLB) ] = { 871 [ C(OP_READ) ] = { 872 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 873 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 874 }, 875 [ C(OP_WRITE) ] = { 876 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 877 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 878 }, 879 [ C(OP_PREFETCH) ] = { 880 [ C(RESULT_ACCESS) ] = 0x0, 881 [ C(RESULT_MISS) ] = 0x0, 882 }, 883 }, 884 [ C(ITLB) ] = { 885 [ C(OP_READ) ] = { 886 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 887 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 888 }, 889 [ C(OP_WRITE) ] = { 890 [ C(RESULT_ACCESS) ] = -1, 891 [ C(RESULT_MISS) ] = -1, 892 }, 893 [ C(OP_PREFETCH) ] = { 894 [ C(RESULT_ACCESS) ] = -1, 895 [ C(RESULT_MISS) ] = -1, 896 }, 897 }, 898 [ C(BPU ) ] = { 899 [ C(OP_READ) ] = { 900 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 901 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 902 }, 903 [ C(OP_WRITE) ] = { 904 [ C(RESULT_ACCESS) ] = -1, 905 [ C(RESULT_MISS) ] = -1, 906 }, 907 [ C(OP_PREFETCH) ] = { 908 [ C(RESULT_ACCESS) ] = -1, 909 [ C(RESULT_MISS) ] = -1, 910 }, 911 }, 912 [ C(NODE) ] = { 913 [ C(OP_READ) ] = { 914 [ C(RESULT_ACCESS) ] = 0x01b7, 915 [ C(RESULT_MISS) ] = 0x01b7, 916 }, 917 [ C(OP_WRITE) ] = { 918 [ C(RESULT_ACCESS) ] = 0x01b7, 919 [ C(RESULT_MISS) ] = 0x01b7, 920 }, 921 [ C(OP_PREFETCH) ] = { 922 [ C(RESULT_ACCESS) ] = 0x01b7, 923 [ C(RESULT_MISS) ] = 0x01b7, 924 }, 925 }, 926 927 }; 928 929 /* 930 * Notes on the events: 931 * - data reads do not include code reads (comparable to earlier tables) 932 * - data counts include speculative execution (except L1 write, dtlb, bpu) 933 * - remote node access includes remote memory, remote cache, remote mmio. 934 * - prefetches are not included in the counts because they are not 935 * reliably counted. 936 */ 937 938 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 939 #define HSW_DEMAND_RFO BIT_ULL(1) 940 #define HSW_ANY_RESPONSE BIT_ULL(16) 941 #define HSW_SUPPLIER_NONE BIT_ULL(17) 942 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 943 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 944 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 945 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 946 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 947 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 948 HSW_L3_MISS_REMOTE_HOP2P) 949 #define HSW_SNOOP_NONE BIT_ULL(31) 950 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 951 #define HSW_SNOOP_MISS BIT_ULL(33) 952 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 953 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 954 #define HSW_SNOOP_HITM BIT_ULL(36) 955 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 956 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 957 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 958 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 959 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 960 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 961 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 962 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 963 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 964 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 965 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 966 967 #define BDW_L3_MISS_LOCAL BIT(26) 968 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 969 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 970 HSW_L3_MISS_REMOTE_HOP2P) 971 972 973 static __initconst const u64 hsw_hw_cache_event_ids 974 [PERF_COUNT_HW_CACHE_MAX] 975 [PERF_COUNT_HW_CACHE_OP_MAX] 976 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 977 { 978 [ C(L1D ) ] = { 979 [ C(OP_READ) ] = { 980 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 981 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 982 }, 983 [ C(OP_WRITE) ] = { 984 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 985 [ C(RESULT_MISS) ] = 0x0, 986 }, 987 [ C(OP_PREFETCH) ] = { 988 [ C(RESULT_ACCESS) ] = 0x0, 989 [ C(RESULT_MISS) ] = 0x0, 990 }, 991 }, 992 [ C(L1I ) ] = { 993 [ C(OP_READ) ] = { 994 [ C(RESULT_ACCESS) ] = 0x0, 995 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 996 }, 997 [ C(OP_WRITE) ] = { 998 [ C(RESULT_ACCESS) ] = -1, 999 [ C(RESULT_MISS) ] = -1, 1000 }, 1001 [ C(OP_PREFETCH) ] = { 1002 [ C(RESULT_ACCESS) ] = 0x0, 1003 [ C(RESULT_MISS) ] = 0x0, 1004 }, 1005 }, 1006 [ C(LL ) ] = { 1007 [ C(OP_READ) ] = { 1008 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1009 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1010 }, 1011 [ C(OP_WRITE) ] = { 1012 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1013 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1014 }, 1015 [ C(OP_PREFETCH) ] = { 1016 [ C(RESULT_ACCESS) ] = 0x0, 1017 [ C(RESULT_MISS) ] = 0x0, 1018 }, 1019 }, 1020 [ C(DTLB) ] = { 1021 [ C(OP_READ) ] = { 1022 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1023 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1024 }, 1025 [ C(OP_WRITE) ] = { 1026 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1027 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1028 }, 1029 [ C(OP_PREFETCH) ] = { 1030 [ C(RESULT_ACCESS) ] = 0x0, 1031 [ C(RESULT_MISS) ] = 0x0, 1032 }, 1033 }, 1034 [ C(ITLB) ] = { 1035 [ C(OP_READ) ] = { 1036 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1037 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1038 }, 1039 [ C(OP_WRITE) ] = { 1040 [ C(RESULT_ACCESS) ] = -1, 1041 [ C(RESULT_MISS) ] = -1, 1042 }, 1043 [ C(OP_PREFETCH) ] = { 1044 [ C(RESULT_ACCESS) ] = -1, 1045 [ C(RESULT_MISS) ] = -1, 1046 }, 1047 }, 1048 [ C(BPU ) ] = { 1049 [ C(OP_READ) ] = { 1050 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1051 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1052 }, 1053 [ C(OP_WRITE) ] = { 1054 [ C(RESULT_ACCESS) ] = -1, 1055 [ C(RESULT_MISS) ] = -1, 1056 }, 1057 [ C(OP_PREFETCH) ] = { 1058 [ C(RESULT_ACCESS) ] = -1, 1059 [ C(RESULT_MISS) ] = -1, 1060 }, 1061 }, 1062 [ C(NODE) ] = { 1063 [ C(OP_READ) ] = { 1064 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1065 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1066 }, 1067 [ C(OP_WRITE) ] = { 1068 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1069 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1070 }, 1071 [ C(OP_PREFETCH) ] = { 1072 [ C(RESULT_ACCESS) ] = 0x0, 1073 [ C(RESULT_MISS) ] = 0x0, 1074 }, 1075 }, 1076 }; 1077 1078 static __initconst const u64 hsw_hw_cache_extra_regs 1079 [PERF_COUNT_HW_CACHE_MAX] 1080 [PERF_COUNT_HW_CACHE_OP_MAX] 1081 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1082 { 1083 [ C(LL ) ] = { 1084 [ C(OP_READ) ] = { 1085 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1086 HSW_LLC_ACCESS, 1087 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1088 HSW_L3_MISS|HSW_ANY_SNOOP, 1089 }, 1090 [ C(OP_WRITE) ] = { 1091 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1092 HSW_LLC_ACCESS, 1093 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1094 HSW_L3_MISS|HSW_ANY_SNOOP, 1095 }, 1096 [ C(OP_PREFETCH) ] = { 1097 [ C(RESULT_ACCESS) ] = 0x0, 1098 [ C(RESULT_MISS) ] = 0x0, 1099 }, 1100 }, 1101 [ C(NODE) ] = { 1102 [ C(OP_READ) ] = { 1103 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1104 HSW_L3_MISS_LOCAL_DRAM| 1105 HSW_SNOOP_DRAM, 1106 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1107 HSW_L3_MISS_REMOTE| 1108 HSW_SNOOP_DRAM, 1109 }, 1110 [ C(OP_WRITE) ] = { 1111 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1112 HSW_L3_MISS_LOCAL_DRAM| 1113 HSW_SNOOP_DRAM, 1114 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1115 HSW_L3_MISS_REMOTE| 1116 HSW_SNOOP_DRAM, 1117 }, 1118 [ C(OP_PREFETCH) ] = { 1119 [ C(RESULT_ACCESS) ] = 0x0, 1120 [ C(RESULT_MISS) ] = 0x0, 1121 }, 1122 }, 1123 }; 1124 1125 static __initconst const u64 westmere_hw_cache_event_ids 1126 [PERF_COUNT_HW_CACHE_MAX] 1127 [PERF_COUNT_HW_CACHE_OP_MAX] 1128 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1129 { 1130 [ C(L1D) ] = { 1131 [ C(OP_READ) ] = { 1132 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1133 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1134 }, 1135 [ C(OP_WRITE) ] = { 1136 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1137 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1138 }, 1139 [ C(OP_PREFETCH) ] = { 1140 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1141 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1142 }, 1143 }, 1144 [ C(L1I ) ] = { 1145 [ C(OP_READ) ] = { 1146 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1147 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1148 }, 1149 [ C(OP_WRITE) ] = { 1150 [ C(RESULT_ACCESS) ] = -1, 1151 [ C(RESULT_MISS) ] = -1, 1152 }, 1153 [ C(OP_PREFETCH) ] = { 1154 [ C(RESULT_ACCESS) ] = 0x0, 1155 [ C(RESULT_MISS) ] = 0x0, 1156 }, 1157 }, 1158 [ C(LL ) ] = { 1159 [ C(OP_READ) ] = { 1160 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1161 [ C(RESULT_ACCESS) ] = 0x01b7, 1162 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1163 [ C(RESULT_MISS) ] = 0x01b7, 1164 }, 1165 /* 1166 * Use RFO, not WRITEBACK, because a write miss would typically occur 1167 * on RFO. 1168 */ 1169 [ C(OP_WRITE) ] = { 1170 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1171 [ C(RESULT_ACCESS) ] = 0x01b7, 1172 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1173 [ C(RESULT_MISS) ] = 0x01b7, 1174 }, 1175 [ C(OP_PREFETCH) ] = { 1176 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1177 [ C(RESULT_ACCESS) ] = 0x01b7, 1178 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1179 [ C(RESULT_MISS) ] = 0x01b7, 1180 }, 1181 }, 1182 [ C(DTLB) ] = { 1183 [ C(OP_READ) ] = { 1184 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1185 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1186 }, 1187 [ C(OP_WRITE) ] = { 1188 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1189 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1190 }, 1191 [ C(OP_PREFETCH) ] = { 1192 [ C(RESULT_ACCESS) ] = 0x0, 1193 [ C(RESULT_MISS) ] = 0x0, 1194 }, 1195 }, 1196 [ C(ITLB) ] = { 1197 [ C(OP_READ) ] = { 1198 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1199 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1200 }, 1201 [ C(OP_WRITE) ] = { 1202 [ C(RESULT_ACCESS) ] = -1, 1203 [ C(RESULT_MISS) ] = -1, 1204 }, 1205 [ C(OP_PREFETCH) ] = { 1206 [ C(RESULT_ACCESS) ] = -1, 1207 [ C(RESULT_MISS) ] = -1, 1208 }, 1209 }, 1210 [ C(BPU ) ] = { 1211 [ C(OP_READ) ] = { 1212 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1213 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1214 }, 1215 [ C(OP_WRITE) ] = { 1216 [ C(RESULT_ACCESS) ] = -1, 1217 [ C(RESULT_MISS) ] = -1, 1218 }, 1219 [ C(OP_PREFETCH) ] = { 1220 [ C(RESULT_ACCESS) ] = -1, 1221 [ C(RESULT_MISS) ] = -1, 1222 }, 1223 }, 1224 [ C(NODE) ] = { 1225 [ C(OP_READ) ] = { 1226 [ C(RESULT_ACCESS) ] = 0x01b7, 1227 [ C(RESULT_MISS) ] = 0x01b7, 1228 }, 1229 [ C(OP_WRITE) ] = { 1230 [ C(RESULT_ACCESS) ] = 0x01b7, 1231 [ C(RESULT_MISS) ] = 0x01b7, 1232 }, 1233 [ C(OP_PREFETCH) ] = { 1234 [ C(RESULT_ACCESS) ] = 0x01b7, 1235 [ C(RESULT_MISS) ] = 0x01b7, 1236 }, 1237 }, 1238 }; 1239 1240 /* 1241 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1242 * See IA32 SDM Vol 3B 30.6.1.3 1243 */ 1244 1245 #define NHM_DMND_DATA_RD (1 << 0) 1246 #define NHM_DMND_RFO (1 << 1) 1247 #define NHM_DMND_IFETCH (1 << 2) 1248 #define NHM_DMND_WB (1 << 3) 1249 #define NHM_PF_DATA_RD (1 << 4) 1250 #define NHM_PF_DATA_RFO (1 << 5) 1251 #define NHM_PF_IFETCH (1 << 6) 1252 #define NHM_OFFCORE_OTHER (1 << 7) 1253 #define NHM_UNCORE_HIT (1 << 8) 1254 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1255 #define NHM_OTHER_CORE_HITM (1 << 10) 1256 /* reserved */ 1257 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1258 #define NHM_REMOTE_DRAM (1 << 13) 1259 #define NHM_LOCAL_DRAM (1 << 14) 1260 #define NHM_NON_DRAM (1 << 15) 1261 1262 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1263 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1264 1265 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1266 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1267 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1268 1269 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1270 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1271 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1272 1273 static __initconst const u64 nehalem_hw_cache_extra_regs 1274 [PERF_COUNT_HW_CACHE_MAX] 1275 [PERF_COUNT_HW_CACHE_OP_MAX] 1276 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1277 { 1278 [ C(LL ) ] = { 1279 [ C(OP_READ) ] = { 1280 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1281 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1282 }, 1283 [ C(OP_WRITE) ] = { 1284 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1285 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1286 }, 1287 [ C(OP_PREFETCH) ] = { 1288 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1289 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1290 }, 1291 }, 1292 [ C(NODE) ] = { 1293 [ C(OP_READ) ] = { 1294 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1295 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1296 }, 1297 [ C(OP_WRITE) ] = { 1298 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1299 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1300 }, 1301 [ C(OP_PREFETCH) ] = { 1302 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1303 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1304 }, 1305 }, 1306 }; 1307 1308 static __initconst const u64 nehalem_hw_cache_event_ids 1309 [PERF_COUNT_HW_CACHE_MAX] 1310 [PERF_COUNT_HW_CACHE_OP_MAX] 1311 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1312 { 1313 [ C(L1D) ] = { 1314 [ C(OP_READ) ] = { 1315 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1316 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1317 }, 1318 [ C(OP_WRITE) ] = { 1319 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1320 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1321 }, 1322 [ C(OP_PREFETCH) ] = { 1323 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1324 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1325 }, 1326 }, 1327 [ C(L1I ) ] = { 1328 [ C(OP_READ) ] = { 1329 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1330 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1331 }, 1332 [ C(OP_WRITE) ] = { 1333 [ C(RESULT_ACCESS) ] = -1, 1334 [ C(RESULT_MISS) ] = -1, 1335 }, 1336 [ C(OP_PREFETCH) ] = { 1337 [ C(RESULT_ACCESS) ] = 0x0, 1338 [ C(RESULT_MISS) ] = 0x0, 1339 }, 1340 }, 1341 [ C(LL ) ] = { 1342 [ C(OP_READ) ] = { 1343 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1344 [ C(RESULT_ACCESS) ] = 0x01b7, 1345 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1346 [ C(RESULT_MISS) ] = 0x01b7, 1347 }, 1348 /* 1349 * Use RFO, not WRITEBACK, because a write miss would typically occur 1350 * on RFO. 1351 */ 1352 [ C(OP_WRITE) ] = { 1353 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1354 [ C(RESULT_ACCESS) ] = 0x01b7, 1355 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1356 [ C(RESULT_MISS) ] = 0x01b7, 1357 }, 1358 [ C(OP_PREFETCH) ] = { 1359 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1360 [ C(RESULT_ACCESS) ] = 0x01b7, 1361 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1362 [ C(RESULT_MISS) ] = 0x01b7, 1363 }, 1364 }, 1365 [ C(DTLB) ] = { 1366 [ C(OP_READ) ] = { 1367 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1368 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1369 }, 1370 [ C(OP_WRITE) ] = { 1371 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1372 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1373 }, 1374 [ C(OP_PREFETCH) ] = { 1375 [ C(RESULT_ACCESS) ] = 0x0, 1376 [ C(RESULT_MISS) ] = 0x0, 1377 }, 1378 }, 1379 [ C(ITLB) ] = { 1380 [ C(OP_READ) ] = { 1381 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1382 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1383 }, 1384 [ C(OP_WRITE) ] = { 1385 [ C(RESULT_ACCESS) ] = -1, 1386 [ C(RESULT_MISS) ] = -1, 1387 }, 1388 [ C(OP_PREFETCH) ] = { 1389 [ C(RESULT_ACCESS) ] = -1, 1390 [ C(RESULT_MISS) ] = -1, 1391 }, 1392 }, 1393 [ C(BPU ) ] = { 1394 [ C(OP_READ) ] = { 1395 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1396 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1397 }, 1398 [ C(OP_WRITE) ] = { 1399 [ C(RESULT_ACCESS) ] = -1, 1400 [ C(RESULT_MISS) ] = -1, 1401 }, 1402 [ C(OP_PREFETCH) ] = { 1403 [ C(RESULT_ACCESS) ] = -1, 1404 [ C(RESULT_MISS) ] = -1, 1405 }, 1406 }, 1407 [ C(NODE) ] = { 1408 [ C(OP_READ) ] = { 1409 [ C(RESULT_ACCESS) ] = 0x01b7, 1410 [ C(RESULT_MISS) ] = 0x01b7, 1411 }, 1412 [ C(OP_WRITE) ] = { 1413 [ C(RESULT_ACCESS) ] = 0x01b7, 1414 [ C(RESULT_MISS) ] = 0x01b7, 1415 }, 1416 [ C(OP_PREFETCH) ] = { 1417 [ C(RESULT_ACCESS) ] = 0x01b7, 1418 [ C(RESULT_MISS) ] = 0x01b7, 1419 }, 1420 }, 1421 }; 1422 1423 static __initconst const u64 core2_hw_cache_event_ids 1424 [PERF_COUNT_HW_CACHE_MAX] 1425 [PERF_COUNT_HW_CACHE_OP_MAX] 1426 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1427 { 1428 [ C(L1D) ] = { 1429 [ C(OP_READ) ] = { 1430 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1431 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1432 }, 1433 [ C(OP_WRITE) ] = { 1434 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1435 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1436 }, 1437 [ C(OP_PREFETCH) ] = { 1438 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1439 [ C(RESULT_MISS) ] = 0, 1440 }, 1441 }, 1442 [ C(L1I ) ] = { 1443 [ C(OP_READ) ] = { 1444 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1445 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1446 }, 1447 [ C(OP_WRITE) ] = { 1448 [ C(RESULT_ACCESS) ] = -1, 1449 [ C(RESULT_MISS) ] = -1, 1450 }, 1451 [ C(OP_PREFETCH) ] = { 1452 [ C(RESULT_ACCESS) ] = 0, 1453 [ C(RESULT_MISS) ] = 0, 1454 }, 1455 }, 1456 [ C(LL ) ] = { 1457 [ C(OP_READ) ] = { 1458 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1459 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1460 }, 1461 [ C(OP_WRITE) ] = { 1462 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1463 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1464 }, 1465 [ C(OP_PREFETCH) ] = { 1466 [ C(RESULT_ACCESS) ] = 0, 1467 [ C(RESULT_MISS) ] = 0, 1468 }, 1469 }, 1470 [ C(DTLB) ] = { 1471 [ C(OP_READ) ] = { 1472 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1473 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1474 }, 1475 [ C(OP_WRITE) ] = { 1476 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1477 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1478 }, 1479 [ C(OP_PREFETCH) ] = { 1480 [ C(RESULT_ACCESS) ] = 0, 1481 [ C(RESULT_MISS) ] = 0, 1482 }, 1483 }, 1484 [ C(ITLB) ] = { 1485 [ C(OP_READ) ] = { 1486 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1487 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1488 }, 1489 [ C(OP_WRITE) ] = { 1490 [ C(RESULT_ACCESS) ] = -1, 1491 [ C(RESULT_MISS) ] = -1, 1492 }, 1493 [ C(OP_PREFETCH) ] = { 1494 [ C(RESULT_ACCESS) ] = -1, 1495 [ C(RESULT_MISS) ] = -1, 1496 }, 1497 }, 1498 [ C(BPU ) ] = { 1499 [ C(OP_READ) ] = { 1500 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1501 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1502 }, 1503 [ C(OP_WRITE) ] = { 1504 [ C(RESULT_ACCESS) ] = -1, 1505 [ C(RESULT_MISS) ] = -1, 1506 }, 1507 [ C(OP_PREFETCH) ] = { 1508 [ C(RESULT_ACCESS) ] = -1, 1509 [ C(RESULT_MISS) ] = -1, 1510 }, 1511 }, 1512 }; 1513 1514 static __initconst const u64 atom_hw_cache_event_ids 1515 [PERF_COUNT_HW_CACHE_MAX] 1516 [PERF_COUNT_HW_CACHE_OP_MAX] 1517 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1518 { 1519 [ C(L1D) ] = { 1520 [ C(OP_READ) ] = { 1521 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1522 [ C(RESULT_MISS) ] = 0, 1523 }, 1524 [ C(OP_WRITE) ] = { 1525 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1526 [ C(RESULT_MISS) ] = 0, 1527 }, 1528 [ C(OP_PREFETCH) ] = { 1529 [ C(RESULT_ACCESS) ] = 0x0, 1530 [ C(RESULT_MISS) ] = 0, 1531 }, 1532 }, 1533 [ C(L1I ) ] = { 1534 [ C(OP_READ) ] = { 1535 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1536 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1537 }, 1538 [ C(OP_WRITE) ] = { 1539 [ C(RESULT_ACCESS) ] = -1, 1540 [ C(RESULT_MISS) ] = -1, 1541 }, 1542 [ C(OP_PREFETCH) ] = { 1543 [ C(RESULT_ACCESS) ] = 0, 1544 [ C(RESULT_MISS) ] = 0, 1545 }, 1546 }, 1547 [ C(LL ) ] = { 1548 [ C(OP_READ) ] = { 1549 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1550 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1551 }, 1552 [ C(OP_WRITE) ] = { 1553 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1554 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1555 }, 1556 [ C(OP_PREFETCH) ] = { 1557 [ C(RESULT_ACCESS) ] = 0, 1558 [ C(RESULT_MISS) ] = 0, 1559 }, 1560 }, 1561 [ C(DTLB) ] = { 1562 [ C(OP_READ) ] = { 1563 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1564 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1565 }, 1566 [ C(OP_WRITE) ] = { 1567 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1568 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1569 }, 1570 [ C(OP_PREFETCH) ] = { 1571 [ C(RESULT_ACCESS) ] = 0, 1572 [ C(RESULT_MISS) ] = 0, 1573 }, 1574 }, 1575 [ C(ITLB) ] = { 1576 [ C(OP_READ) ] = { 1577 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1578 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1579 }, 1580 [ C(OP_WRITE) ] = { 1581 [ C(RESULT_ACCESS) ] = -1, 1582 [ C(RESULT_MISS) ] = -1, 1583 }, 1584 [ C(OP_PREFETCH) ] = { 1585 [ C(RESULT_ACCESS) ] = -1, 1586 [ C(RESULT_MISS) ] = -1, 1587 }, 1588 }, 1589 [ C(BPU ) ] = { 1590 [ C(OP_READ) ] = { 1591 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1592 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1593 }, 1594 [ C(OP_WRITE) ] = { 1595 [ C(RESULT_ACCESS) ] = -1, 1596 [ C(RESULT_MISS) ] = -1, 1597 }, 1598 [ C(OP_PREFETCH) ] = { 1599 [ C(RESULT_ACCESS) ] = -1, 1600 [ C(RESULT_MISS) ] = -1, 1601 }, 1602 }, 1603 }; 1604 1605 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1606 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1607 /* no_alloc_cycles.not_delivered */ 1608 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1609 "event=0xca,umask=0x50"); 1610 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1611 /* uops_retired.all */ 1612 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1613 "event=0xc2,umask=0x10"); 1614 /* uops_retired.all */ 1615 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1616 "event=0xc2,umask=0x10"); 1617 1618 static struct attribute *slm_events_attrs[] = { 1619 EVENT_PTR(td_total_slots_slm), 1620 EVENT_PTR(td_total_slots_scale_slm), 1621 EVENT_PTR(td_fetch_bubbles_slm), 1622 EVENT_PTR(td_fetch_bubbles_scale_slm), 1623 EVENT_PTR(td_slots_issued_slm), 1624 EVENT_PTR(td_slots_retired_slm), 1625 NULL 1626 }; 1627 1628 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1629 { 1630 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1631 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1632 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1633 EVENT_EXTRA_END 1634 }; 1635 1636 #define SLM_DMND_READ SNB_DMND_DATA_RD 1637 #define SLM_DMND_WRITE SNB_DMND_RFO 1638 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1639 1640 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1641 #define SLM_LLC_ACCESS SNB_RESP_ANY 1642 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1643 1644 static __initconst const u64 slm_hw_cache_extra_regs 1645 [PERF_COUNT_HW_CACHE_MAX] 1646 [PERF_COUNT_HW_CACHE_OP_MAX] 1647 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1648 { 1649 [ C(LL ) ] = { 1650 [ C(OP_READ) ] = { 1651 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1652 [ C(RESULT_MISS) ] = 0, 1653 }, 1654 [ C(OP_WRITE) ] = { 1655 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1656 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1657 }, 1658 [ C(OP_PREFETCH) ] = { 1659 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1660 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1661 }, 1662 }, 1663 }; 1664 1665 static __initconst const u64 slm_hw_cache_event_ids 1666 [PERF_COUNT_HW_CACHE_MAX] 1667 [PERF_COUNT_HW_CACHE_OP_MAX] 1668 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1669 { 1670 [ C(L1D) ] = { 1671 [ C(OP_READ) ] = { 1672 [ C(RESULT_ACCESS) ] = 0, 1673 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1674 }, 1675 [ C(OP_WRITE) ] = { 1676 [ C(RESULT_ACCESS) ] = 0, 1677 [ C(RESULT_MISS) ] = 0, 1678 }, 1679 [ C(OP_PREFETCH) ] = { 1680 [ C(RESULT_ACCESS) ] = 0, 1681 [ C(RESULT_MISS) ] = 0, 1682 }, 1683 }, 1684 [ C(L1I ) ] = { 1685 [ C(OP_READ) ] = { 1686 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1687 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1688 }, 1689 [ C(OP_WRITE) ] = { 1690 [ C(RESULT_ACCESS) ] = -1, 1691 [ C(RESULT_MISS) ] = -1, 1692 }, 1693 [ C(OP_PREFETCH) ] = { 1694 [ C(RESULT_ACCESS) ] = 0, 1695 [ C(RESULT_MISS) ] = 0, 1696 }, 1697 }, 1698 [ C(LL ) ] = { 1699 [ C(OP_READ) ] = { 1700 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1701 [ C(RESULT_ACCESS) ] = 0x01b7, 1702 [ C(RESULT_MISS) ] = 0, 1703 }, 1704 [ C(OP_WRITE) ] = { 1705 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1706 [ C(RESULT_ACCESS) ] = 0x01b7, 1707 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1708 [ C(RESULT_MISS) ] = 0x01b7, 1709 }, 1710 [ C(OP_PREFETCH) ] = { 1711 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1712 [ C(RESULT_ACCESS) ] = 0x01b7, 1713 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1714 [ C(RESULT_MISS) ] = 0x01b7, 1715 }, 1716 }, 1717 [ C(DTLB) ] = { 1718 [ C(OP_READ) ] = { 1719 [ C(RESULT_ACCESS) ] = 0, 1720 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1721 }, 1722 [ C(OP_WRITE) ] = { 1723 [ C(RESULT_ACCESS) ] = 0, 1724 [ C(RESULT_MISS) ] = 0, 1725 }, 1726 [ C(OP_PREFETCH) ] = { 1727 [ C(RESULT_ACCESS) ] = 0, 1728 [ C(RESULT_MISS) ] = 0, 1729 }, 1730 }, 1731 [ C(ITLB) ] = { 1732 [ C(OP_READ) ] = { 1733 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1734 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1735 }, 1736 [ C(OP_WRITE) ] = { 1737 [ C(RESULT_ACCESS) ] = -1, 1738 [ C(RESULT_MISS) ] = -1, 1739 }, 1740 [ C(OP_PREFETCH) ] = { 1741 [ C(RESULT_ACCESS) ] = -1, 1742 [ C(RESULT_MISS) ] = -1, 1743 }, 1744 }, 1745 [ C(BPU ) ] = { 1746 [ C(OP_READ) ] = { 1747 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1748 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1749 }, 1750 [ C(OP_WRITE) ] = { 1751 [ C(RESULT_ACCESS) ] = -1, 1752 [ C(RESULT_MISS) ] = -1, 1753 }, 1754 [ C(OP_PREFETCH) ] = { 1755 [ C(RESULT_ACCESS) ] = -1, 1756 [ C(RESULT_MISS) ] = -1, 1757 }, 1758 }, 1759 }; 1760 1761 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1762 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1763 /* UOPS_NOT_DELIVERED.ANY */ 1764 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1765 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1766 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1767 /* UOPS_RETIRED.ANY */ 1768 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1769 /* UOPS_ISSUED.ANY */ 1770 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1771 1772 static struct attribute *glm_events_attrs[] = { 1773 EVENT_PTR(td_total_slots_glm), 1774 EVENT_PTR(td_total_slots_scale_glm), 1775 EVENT_PTR(td_fetch_bubbles_glm), 1776 EVENT_PTR(td_recovery_bubbles_glm), 1777 EVENT_PTR(td_slots_issued_glm), 1778 EVENT_PTR(td_slots_retired_glm), 1779 NULL 1780 }; 1781 1782 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1783 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1784 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1785 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1786 EVENT_EXTRA_END 1787 }; 1788 1789 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 1790 #define GLM_DEMAND_RFO BIT_ULL(1) 1791 #define GLM_ANY_RESPONSE BIT_ULL(16) 1792 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1793 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1794 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1795 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1796 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1797 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1798 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1799 1800 static __initconst const u64 glm_hw_cache_event_ids 1801 [PERF_COUNT_HW_CACHE_MAX] 1802 [PERF_COUNT_HW_CACHE_OP_MAX] 1803 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1804 [C(L1D)] = { 1805 [C(OP_READ)] = { 1806 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1807 [C(RESULT_MISS)] = 0x0, 1808 }, 1809 [C(OP_WRITE)] = { 1810 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1811 [C(RESULT_MISS)] = 0x0, 1812 }, 1813 [C(OP_PREFETCH)] = { 1814 [C(RESULT_ACCESS)] = 0x0, 1815 [C(RESULT_MISS)] = 0x0, 1816 }, 1817 }, 1818 [C(L1I)] = { 1819 [C(OP_READ)] = { 1820 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1821 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1822 }, 1823 [C(OP_WRITE)] = { 1824 [C(RESULT_ACCESS)] = -1, 1825 [C(RESULT_MISS)] = -1, 1826 }, 1827 [C(OP_PREFETCH)] = { 1828 [C(RESULT_ACCESS)] = 0x0, 1829 [C(RESULT_MISS)] = 0x0, 1830 }, 1831 }, 1832 [C(LL)] = { 1833 [C(OP_READ)] = { 1834 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1835 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1836 }, 1837 [C(OP_WRITE)] = { 1838 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1839 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1840 }, 1841 [C(OP_PREFETCH)] = { 1842 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1843 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1844 }, 1845 }, 1846 [C(DTLB)] = { 1847 [C(OP_READ)] = { 1848 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1849 [C(RESULT_MISS)] = 0x0, 1850 }, 1851 [C(OP_WRITE)] = { 1852 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1853 [C(RESULT_MISS)] = 0x0, 1854 }, 1855 [C(OP_PREFETCH)] = { 1856 [C(RESULT_ACCESS)] = 0x0, 1857 [C(RESULT_MISS)] = 0x0, 1858 }, 1859 }, 1860 [C(ITLB)] = { 1861 [C(OP_READ)] = { 1862 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1863 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1864 }, 1865 [C(OP_WRITE)] = { 1866 [C(RESULT_ACCESS)] = -1, 1867 [C(RESULT_MISS)] = -1, 1868 }, 1869 [C(OP_PREFETCH)] = { 1870 [C(RESULT_ACCESS)] = -1, 1871 [C(RESULT_MISS)] = -1, 1872 }, 1873 }, 1874 [C(BPU)] = { 1875 [C(OP_READ)] = { 1876 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1877 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1878 }, 1879 [C(OP_WRITE)] = { 1880 [C(RESULT_ACCESS)] = -1, 1881 [C(RESULT_MISS)] = -1, 1882 }, 1883 [C(OP_PREFETCH)] = { 1884 [C(RESULT_ACCESS)] = -1, 1885 [C(RESULT_MISS)] = -1, 1886 }, 1887 }, 1888 }; 1889 1890 static __initconst const u64 glm_hw_cache_extra_regs 1891 [PERF_COUNT_HW_CACHE_MAX] 1892 [PERF_COUNT_HW_CACHE_OP_MAX] 1893 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1894 [C(LL)] = { 1895 [C(OP_READ)] = { 1896 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1897 GLM_LLC_ACCESS, 1898 [C(RESULT_MISS)] = GLM_DEMAND_READ| 1899 GLM_LLC_MISS, 1900 }, 1901 [C(OP_WRITE)] = { 1902 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1903 GLM_LLC_ACCESS, 1904 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1905 GLM_LLC_MISS, 1906 }, 1907 [C(OP_PREFETCH)] = { 1908 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 1909 GLM_LLC_ACCESS, 1910 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 1911 GLM_LLC_MISS, 1912 }, 1913 }, 1914 }; 1915 1916 static __initconst const u64 glp_hw_cache_event_ids 1917 [PERF_COUNT_HW_CACHE_MAX] 1918 [PERF_COUNT_HW_CACHE_OP_MAX] 1919 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1920 [C(L1D)] = { 1921 [C(OP_READ)] = { 1922 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1923 [C(RESULT_MISS)] = 0x0, 1924 }, 1925 [C(OP_WRITE)] = { 1926 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1927 [C(RESULT_MISS)] = 0x0, 1928 }, 1929 [C(OP_PREFETCH)] = { 1930 [C(RESULT_ACCESS)] = 0x0, 1931 [C(RESULT_MISS)] = 0x0, 1932 }, 1933 }, 1934 [C(L1I)] = { 1935 [C(OP_READ)] = { 1936 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1937 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1938 }, 1939 [C(OP_WRITE)] = { 1940 [C(RESULT_ACCESS)] = -1, 1941 [C(RESULT_MISS)] = -1, 1942 }, 1943 [C(OP_PREFETCH)] = { 1944 [C(RESULT_ACCESS)] = 0x0, 1945 [C(RESULT_MISS)] = 0x0, 1946 }, 1947 }, 1948 [C(LL)] = { 1949 [C(OP_READ)] = { 1950 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1951 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1952 }, 1953 [C(OP_WRITE)] = { 1954 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1955 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1956 }, 1957 [C(OP_PREFETCH)] = { 1958 [C(RESULT_ACCESS)] = 0x0, 1959 [C(RESULT_MISS)] = 0x0, 1960 }, 1961 }, 1962 [C(DTLB)] = { 1963 [C(OP_READ)] = { 1964 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1965 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1966 }, 1967 [C(OP_WRITE)] = { 1968 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1969 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1970 }, 1971 [C(OP_PREFETCH)] = { 1972 [C(RESULT_ACCESS)] = 0x0, 1973 [C(RESULT_MISS)] = 0x0, 1974 }, 1975 }, 1976 [C(ITLB)] = { 1977 [C(OP_READ)] = { 1978 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1979 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1980 }, 1981 [C(OP_WRITE)] = { 1982 [C(RESULT_ACCESS)] = -1, 1983 [C(RESULT_MISS)] = -1, 1984 }, 1985 [C(OP_PREFETCH)] = { 1986 [C(RESULT_ACCESS)] = -1, 1987 [C(RESULT_MISS)] = -1, 1988 }, 1989 }, 1990 [C(BPU)] = { 1991 [C(OP_READ)] = { 1992 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1993 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1994 }, 1995 [C(OP_WRITE)] = { 1996 [C(RESULT_ACCESS)] = -1, 1997 [C(RESULT_MISS)] = -1, 1998 }, 1999 [C(OP_PREFETCH)] = { 2000 [C(RESULT_ACCESS)] = -1, 2001 [C(RESULT_MISS)] = -1, 2002 }, 2003 }, 2004 }; 2005 2006 static __initconst const u64 glp_hw_cache_extra_regs 2007 [PERF_COUNT_HW_CACHE_MAX] 2008 [PERF_COUNT_HW_CACHE_OP_MAX] 2009 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2010 [C(LL)] = { 2011 [C(OP_READ)] = { 2012 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2013 GLM_LLC_ACCESS, 2014 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2015 GLM_LLC_MISS, 2016 }, 2017 [C(OP_WRITE)] = { 2018 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2019 GLM_LLC_ACCESS, 2020 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2021 GLM_LLC_MISS, 2022 }, 2023 [C(OP_PREFETCH)] = { 2024 [C(RESULT_ACCESS)] = 0x0, 2025 [C(RESULT_MISS)] = 0x0, 2026 }, 2027 }, 2028 }; 2029 2030 #define TNT_LOCAL_DRAM BIT_ULL(26) 2031 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 2032 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 2033 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 2034 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 2035 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 2036 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 2037 2038 static __initconst const u64 tnt_hw_cache_extra_regs 2039 [PERF_COUNT_HW_CACHE_MAX] 2040 [PERF_COUNT_HW_CACHE_OP_MAX] 2041 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2042 [C(LL)] = { 2043 [C(OP_READ)] = { 2044 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 2045 TNT_LLC_ACCESS, 2046 [C(RESULT_MISS)] = TNT_DEMAND_READ| 2047 TNT_LLC_MISS, 2048 }, 2049 [C(OP_WRITE)] = { 2050 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 2051 TNT_LLC_ACCESS, 2052 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 2053 TNT_LLC_MISS, 2054 }, 2055 [C(OP_PREFETCH)] = { 2056 [C(RESULT_ACCESS)] = 0x0, 2057 [C(RESULT_MISS)] = 0x0, 2058 }, 2059 }, 2060 }; 2061 2062 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2063 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2064 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2065 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2066 2067 static struct attribute *tnt_events_attrs[] = { 2068 EVENT_PTR(td_fe_bound_tnt), 2069 EVENT_PTR(td_retiring_tnt), 2070 EVENT_PTR(td_bad_spec_tnt), 2071 EVENT_PTR(td_be_bound_tnt), 2072 NULL, 2073 }; 2074 2075 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 2076 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2077 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 2078 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 2079 EVENT_EXTRA_END 2080 }; 2081 2082 static struct extra_reg intel_grt_extra_regs[] __read_mostly = { 2083 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2084 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 2085 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 2086 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2087 EVENT_EXTRA_END 2088 }; 2089 2090 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2091 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2092 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 2093 #define KNL_MCDRAM_FAR BIT_ULL(22) 2094 #define KNL_DDR_LOCAL BIT_ULL(23) 2095 #define KNL_DDR_FAR BIT_ULL(24) 2096 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2097 KNL_DDR_LOCAL | KNL_DDR_FAR) 2098 #define KNL_L2_READ SLM_DMND_READ 2099 #define KNL_L2_WRITE SLM_DMND_WRITE 2100 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2101 #define KNL_L2_ACCESS SLM_LLC_ACCESS 2102 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2103 KNL_DRAM_ANY | SNB_SNP_ANY | \ 2104 SNB_NON_DRAM) 2105 2106 static __initconst const u64 knl_hw_cache_extra_regs 2107 [PERF_COUNT_HW_CACHE_MAX] 2108 [PERF_COUNT_HW_CACHE_OP_MAX] 2109 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2110 [C(LL)] = { 2111 [C(OP_READ)] = { 2112 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2113 [C(RESULT_MISS)] = 0, 2114 }, 2115 [C(OP_WRITE)] = { 2116 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2117 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2118 }, 2119 [C(OP_PREFETCH)] = { 2120 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2121 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2122 }, 2123 }, 2124 }; 2125 2126 /* 2127 * Used from PMIs where the LBRs are already disabled. 2128 * 2129 * This function could be called consecutively. It is required to remain in 2130 * disabled state if called consecutively. 2131 * 2132 * During consecutive calls, the same disable value will be written to related 2133 * registers, so the PMU state remains unchanged. 2134 * 2135 * intel_bts events don't coexist with intel PMU's BTS events because of 2136 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2137 * disabled around intel PMU's event batching etc, only inside the PMI handler. 2138 * 2139 * Avoid PEBS_ENABLE MSR access in PMIs. 2140 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 2141 * It doesn't matter if the PEBS is enabled or not. 2142 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 2143 * access PEBS_ENABLE MSR in disable_all()/enable_all(). 2144 * However, there are some cases which may change PEBS status, e.g. PMI 2145 * throttle. The PEBS_ENABLE should be updated where the status changes. 2146 */ 2147 static __always_inline void __intel_pmu_disable_all(bool bts) 2148 { 2149 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2150 2151 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2152 2153 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2154 intel_pmu_disable_bts(); 2155 } 2156 2157 static __always_inline void intel_pmu_disable_all(void) 2158 { 2159 __intel_pmu_disable_all(true); 2160 intel_pmu_pebs_disable_all(); 2161 intel_pmu_lbr_disable_all(); 2162 } 2163 2164 static void __intel_pmu_enable_all(int added, bool pmi) 2165 { 2166 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2167 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2168 2169 intel_pmu_lbr_enable_all(pmi); 2170 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 2171 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2172 2173 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2174 struct perf_event *event = 2175 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2176 2177 if (WARN_ON_ONCE(!event)) 2178 return; 2179 2180 intel_pmu_enable_bts(event->hw.config); 2181 } 2182 } 2183 2184 static void intel_pmu_enable_all(int added) 2185 { 2186 intel_pmu_pebs_enable_all(); 2187 __intel_pmu_enable_all(added, false); 2188 } 2189 2190 static noinline int 2191 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, 2192 unsigned int cnt, unsigned long flags) 2193 { 2194 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2195 2196 intel_pmu_lbr_read(); 2197 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); 2198 2199 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); 2200 intel_pmu_enable_all(0); 2201 local_irq_restore(flags); 2202 return cnt; 2203 } 2204 2205 static int 2206 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2207 { 2208 unsigned long flags; 2209 2210 /* must not have branches... */ 2211 local_irq_save(flags); 2212 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2213 __intel_pmu_pebs_disable_all(); 2214 __intel_pmu_lbr_disable(); 2215 /* ... until here */ 2216 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2217 } 2218 2219 static int 2220 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2221 { 2222 unsigned long flags; 2223 2224 /* must not have branches... */ 2225 local_irq_save(flags); 2226 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2227 __intel_pmu_pebs_disable_all(); 2228 __intel_pmu_arch_lbr_disable(); 2229 /* ... until here */ 2230 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2231 } 2232 2233 /* 2234 * Workaround for: 2235 * Intel Errata AAK100 (model 26) 2236 * Intel Errata AAP53 (model 30) 2237 * Intel Errata BD53 (model 44) 2238 * 2239 * The official story: 2240 * These chips need to be 'reset' when adding counters by programming the 2241 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2242 * in sequence on the same PMC or on different PMCs. 2243 * 2244 * In practice it appears some of these events do in fact count, and 2245 * we need to program all 4 events. 2246 */ 2247 static void intel_pmu_nhm_workaround(void) 2248 { 2249 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2250 static const unsigned long nhm_magic[4] = { 2251 0x4300B5, 2252 0x4300D2, 2253 0x4300B1, 2254 0x4300B1 2255 }; 2256 struct perf_event *event; 2257 int i; 2258 2259 /* 2260 * The Errata requires below steps: 2261 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2262 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2263 * the corresponding PMCx; 2264 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2265 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2266 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2267 */ 2268 2269 /* 2270 * The real steps we choose are a little different from above. 2271 * A) To reduce MSR operations, we don't run step 1) as they 2272 * are already cleared before this function is called; 2273 * B) Call x86_perf_event_update to save PMCx before configuring 2274 * PERFEVTSELx with magic number; 2275 * C) With step 5), we do clear only when the PERFEVTSELx is 2276 * not used currently. 2277 * D) Call x86_perf_event_set_period to restore PMCx; 2278 */ 2279 2280 /* We always operate 4 pairs of PERF Counters */ 2281 for (i = 0; i < 4; i++) { 2282 event = cpuc->events[i]; 2283 if (event) 2284 x86_perf_event_update(event); 2285 } 2286 2287 for (i = 0; i < 4; i++) { 2288 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2289 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2290 } 2291 2292 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2293 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2294 2295 for (i = 0; i < 4; i++) { 2296 event = cpuc->events[i]; 2297 2298 if (event) { 2299 x86_perf_event_set_period(event); 2300 __x86_pmu_enable_event(&event->hw, 2301 ARCH_PERFMON_EVENTSEL_ENABLE); 2302 } else 2303 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2304 } 2305 } 2306 2307 static void intel_pmu_nhm_enable_all(int added) 2308 { 2309 if (added) 2310 intel_pmu_nhm_workaround(); 2311 intel_pmu_enable_all(added); 2312 } 2313 2314 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2315 { 2316 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2317 2318 if (cpuc->tfa_shadow != val) { 2319 cpuc->tfa_shadow = val; 2320 wrmsrl(MSR_TSX_FORCE_ABORT, val); 2321 } 2322 } 2323 2324 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2325 { 2326 /* 2327 * We're going to use PMC3, make sure TFA is set before we touch it. 2328 */ 2329 if (cntr == 3) 2330 intel_set_tfa(cpuc, true); 2331 } 2332 2333 static void intel_tfa_pmu_enable_all(int added) 2334 { 2335 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2336 2337 /* 2338 * If we find PMC3 is no longer used when we enable the PMU, we can 2339 * clear TFA. 2340 */ 2341 if (!test_bit(3, cpuc->active_mask)) 2342 intel_set_tfa(cpuc, false); 2343 2344 intel_pmu_enable_all(added); 2345 } 2346 2347 static inline u64 intel_pmu_get_status(void) 2348 { 2349 u64 status; 2350 2351 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2352 2353 return status; 2354 } 2355 2356 static inline void intel_pmu_ack_status(u64 ack) 2357 { 2358 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2359 } 2360 2361 static inline bool event_is_checkpointed(struct perf_event *event) 2362 { 2363 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2364 } 2365 2366 static inline void intel_set_masks(struct perf_event *event, int idx) 2367 { 2368 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2369 2370 if (event->attr.exclude_host) 2371 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2372 if (event->attr.exclude_guest) 2373 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2374 if (event_is_checkpointed(event)) 2375 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2376 } 2377 2378 static inline void intel_clear_masks(struct perf_event *event, int idx) 2379 { 2380 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2381 2382 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2383 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2384 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2385 } 2386 2387 static void intel_pmu_disable_fixed(struct perf_event *event) 2388 { 2389 struct hw_perf_event *hwc = &event->hw; 2390 u64 ctrl_val, mask; 2391 int idx = hwc->idx; 2392 2393 if (is_topdown_idx(idx)) { 2394 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2395 2396 /* 2397 * When there are other active TopDown events, 2398 * don't disable the fixed counter 3. 2399 */ 2400 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2401 return; 2402 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2403 } 2404 2405 intel_clear_masks(event, idx); 2406 2407 mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4); 2408 rdmsrl(hwc->config_base, ctrl_val); 2409 ctrl_val &= ~mask; 2410 wrmsrl(hwc->config_base, ctrl_val); 2411 } 2412 2413 static void intel_pmu_disable_event(struct perf_event *event) 2414 { 2415 struct hw_perf_event *hwc = &event->hw; 2416 int idx = hwc->idx; 2417 2418 switch (idx) { 2419 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2420 intel_clear_masks(event, idx); 2421 x86_pmu_disable_event(event); 2422 break; 2423 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2424 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2425 intel_pmu_disable_fixed(event); 2426 break; 2427 case INTEL_PMC_IDX_FIXED_BTS: 2428 intel_pmu_disable_bts(); 2429 intel_pmu_drain_bts_buffer(); 2430 return; 2431 case INTEL_PMC_IDX_FIXED_VLBR: 2432 intel_clear_masks(event, idx); 2433 break; 2434 default: 2435 intel_clear_masks(event, idx); 2436 pr_warn("Failed to disable the event with invalid index %d\n", 2437 idx); 2438 return; 2439 } 2440 2441 /* 2442 * Needs to be called after x86_pmu_disable_event, 2443 * so we don't trigger the event without PEBS bit set. 2444 */ 2445 if (unlikely(event->attr.precise_ip)) 2446 intel_pmu_pebs_disable(event); 2447 } 2448 2449 static void intel_pmu_del_event(struct perf_event *event) 2450 { 2451 if (needs_branch_stack(event)) 2452 intel_pmu_lbr_del(event); 2453 if (event->attr.precise_ip) 2454 intel_pmu_pebs_del(event); 2455 } 2456 2457 static int icl_set_topdown_event_period(struct perf_event *event) 2458 { 2459 struct hw_perf_event *hwc = &event->hw; 2460 s64 left = local64_read(&hwc->period_left); 2461 2462 /* 2463 * The values in PERF_METRICS MSR are derived from fixed counter 3. 2464 * Software should start both registers, PERF_METRICS and fixed 2465 * counter 3, from zero. 2466 * Clear PERF_METRICS and Fixed counter 3 in initialization. 2467 * After that, both MSRs will be cleared for each read. 2468 * Don't need to clear them again. 2469 */ 2470 if (left == x86_pmu.max_period) { 2471 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2472 wrmsrl(MSR_PERF_METRICS, 0); 2473 hwc->saved_slots = 0; 2474 hwc->saved_metric = 0; 2475 } 2476 2477 if ((hwc->saved_slots) && is_slots_event(event)) { 2478 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2479 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric); 2480 } 2481 2482 perf_event_update_userpage(event); 2483 2484 return 0; 2485 } 2486 2487 static int adl_set_topdown_event_period(struct perf_event *event) 2488 { 2489 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2490 2491 if (pmu->cpu_type != hybrid_big) 2492 return 0; 2493 2494 return icl_set_topdown_event_period(event); 2495 } 2496 2497 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 2498 { 2499 u32 val; 2500 2501 /* 2502 * The metric is reported as an 8bit integer fraction 2503 * summing up to 0xff. 2504 * slots-in-metric = (Metric / 0xff) * slots 2505 */ 2506 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 2507 return mul_u64_u32_div(slots, val, 0xff); 2508 } 2509 2510 static u64 icl_get_topdown_value(struct perf_event *event, 2511 u64 slots, u64 metrics) 2512 { 2513 int idx = event->hw.idx; 2514 u64 delta; 2515 2516 if (is_metric_idx(idx)) 2517 delta = icl_get_metrics_event_value(metrics, slots, idx); 2518 else 2519 delta = slots; 2520 2521 return delta; 2522 } 2523 2524 static void __icl_update_topdown_event(struct perf_event *event, 2525 u64 slots, u64 metrics, 2526 u64 last_slots, u64 last_metrics) 2527 { 2528 u64 delta, last = 0; 2529 2530 delta = icl_get_topdown_value(event, slots, metrics); 2531 if (last_slots) 2532 last = icl_get_topdown_value(event, last_slots, last_metrics); 2533 2534 /* 2535 * The 8bit integer fraction of metric may be not accurate, 2536 * especially when the changes is very small. 2537 * For example, if only a few bad_spec happens, the fraction 2538 * may be reduced from 1 to 0. If so, the bad_spec event value 2539 * will be 0 which is definitely less than the last value. 2540 * Avoid update event->count for this case. 2541 */ 2542 if (delta > last) { 2543 delta -= last; 2544 local64_add(delta, &event->count); 2545 } 2546 } 2547 2548 static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 2549 u64 metrics, int metric_end) 2550 { 2551 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2552 struct perf_event *other; 2553 int idx; 2554 2555 event->hw.saved_slots = slots; 2556 event->hw.saved_metric = metrics; 2557 2558 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2559 if (!is_topdown_idx(idx)) 2560 continue; 2561 other = cpuc->events[idx]; 2562 other->hw.saved_slots = slots; 2563 other->hw.saved_metric = metrics; 2564 } 2565 } 2566 2567 /* 2568 * Update all active Topdown events. 2569 * 2570 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 2571 * modify by a NMI. PMU has to be disabled before calling this function. 2572 */ 2573 2574 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end) 2575 { 2576 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2577 struct perf_event *other; 2578 u64 slots, metrics; 2579 bool reset = true; 2580 int idx; 2581 2582 /* read Fixed counter 3 */ 2583 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); 2584 if (!slots) 2585 return 0; 2586 2587 /* read PERF_METRICS */ 2588 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); 2589 2590 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2591 if (!is_topdown_idx(idx)) 2592 continue; 2593 other = cpuc->events[idx]; 2594 __icl_update_topdown_event(other, slots, metrics, 2595 event ? event->hw.saved_slots : 0, 2596 event ? event->hw.saved_metric : 0); 2597 } 2598 2599 /* 2600 * Check and update this event, which may have been cleared 2601 * in active_mask e.g. x86_pmu_stop() 2602 */ 2603 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 2604 __icl_update_topdown_event(event, slots, metrics, 2605 event->hw.saved_slots, 2606 event->hw.saved_metric); 2607 2608 /* 2609 * In x86_pmu_stop(), the event is cleared in active_mask first, 2610 * then drain the delta, which indicates context switch for 2611 * counting. 2612 * Save metric and slots for context switch. 2613 * Don't need to reset the PERF_METRICS and Fixed counter 3. 2614 * Because the values will be restored in next schedule in. 2615 */ 2616 update_saved_topdown_regs(event, slots, metrics, metric_end); 2617 reset = false; 2618 } 2619 2620 if (reset) { 2621 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 2622 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2623 wrmsrl(MSR_PERF_METRICS, 0); 2624 if (event) 2625 update_saved_topdown_regs(event, 0, 0, metric_end); 2626 } 2627 2628 return slots; 2629 } 2630 2631 static u64 icl_update_topdown_event(struct perf_event *event) 2632 { 2633 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 2634 x86_pmu.num_topdown_events - 1); 2635 } 2636 2637 static u64 adl_update_topdown_event(struct perf_event *event) 2638 { 2639 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2640 2641 if (pmu->cpu_type != hybrid_big) 2642 return 0; 2643 2644 return icl_update_topdown_event(event); 2645 } 2646 2647 2648 static void intel_pmu_read_topdown_event(struct perf_event *event) 2649 { 2650 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2651 2652 /* Only need to call update_topdown_event() once for group read. */ 2653 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) && 2654 !is_slots_event(event)) 2655 return; 2656 2657 perf_pmu_disable(event->pmu); 2658 x86_pmu.update_topdown_event(event); 2659 perf_pmu_enable(event->pmu); 2660 } 2661 2662 static void intel_pmu_read_event(struct perf_event *event) 2663 { 2664 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2665 intel_pmu_auto_reload_read(event); 2666 else if (is_topdown_count(event) && x86_pmu.update_topdown_event) 2667 intel_pmu_read_topdown_event(event); 2668 else 2669 x86_perf_event_update(event); 2670 } 2671 2672 static void intel_pmu_enable_fixed(struct perf_event *event) 2673 { 2674 struct hw_perf_event *hwc = &event->hw; 2675 u64 ctrl_val, mask, bits = 0; 2676 int idx = hwc->idx; 2677 2678 if (is_topdown_idx(idx)) { 2679 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2680 /* 2681 * When there are other active TopDown events, 2682 * don't enable the fixed counter 3 again. 2683 */ 2684 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2685 return; 2686 2687 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2688 } 2689 2690 intel_set_masks(event, idx); 2691 2692 /* 2693 * Enable IRQ generation (0x8), if not PEBS, 2694 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2695 * if requested: 2696 */ 2697 if (!event->attr.precise_ip) 2698 bits |= 0x8; 2699 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2700 bits |= 0x2; 2701 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2702 bits |= 0x1; 2703 2704 /* 2705 * ANY bit is supported in v3 and up 2706 */ 2707 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2708 bits |= 0x4; 2709 2710 idx -= INTEL_PMC_IDX_FIXED; 2711 bits <<= (idx * 4); 2712 mask = 0xfULL << (idx * 4); 2713 2714 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2715 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2716 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2717 } 2718 2719 rdmsrl(hwc->config_base, ctrl_val); 2720 ctrl_val &= ~mask; 2721 ctrl_val |= bits; 2722 wrmsrl(hwc->config_base, ctrl_val); 2723 } 2724 2725 static void intel_pmu_enable_event(struct perf_event *event) 2726 { 2727 struct hw_perf_event *hwc = &event->hw; 2728 int idx = hwc->idx; 2729 2730 if (unlikely(event->attr.precise_ip)) 2731 intel_pmu_pebs_enable(event); 2732 2733 switch (idx) { 2734 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2735 intel_set_masks(event, idx); 2736 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 2737 break; 2738 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2739 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2740 intel_pmu_enable_fixed(event); 2741 break; 2742 case INTEL_PMC_IDX_FIXED_BTS: 2743 if (!__this_cpu_read(cpu_hw_events.enabled)) 2744 return; 2745 intel_pmu_enable_bts(hwc->config); 2746 break; 2747 case INTEL_PMC_IDX_FIXED_VLBR: 2748 intel_set_masks(event, idx); 2749 break; 2750 default: 2751 pr_warn("Failed to enable the event with invalid index %d\n", 2752 idx); 2753 } 2754 } 2755 2756 static void intel_pmu_add_event(struct perf_event *event) 2757 { 2758 if (event->attr.precise_ip) 2759 intel_pmu_pebs_add(event); 2760 if (needs_branch_stack(event)) 2761 intel_pmu_lbr_add(event); 2762 } 2763 2764 /* 2765 * Save and restart an expired event. Called by NMI contexts, 2766 * so it has to be careful about preempting normal event ops: 2767 */ 2768 int intel_pmu_save_and_restart(struct perf_event *event) 2769 { 2770 x86_perf_event_update(event); 2771 /* 2772 * For a checkpointed counter always reset back to 0. This 2773 * avoids a situation where the counter overflows, aborts the 2774 * transaction and is then set back to shortly before the 2775 * overflow, and overflows and aborts again. 2776 */ 2777 if (unlikely(event_is_checkpointed(event))) { 2778 /* No race with NMIs because the counter should not be armed */ 2779 wrmsrl(event->hw.event_base, 0); 2780 local64_set(&event->hw.prev_count, 0); 2781 } 2782 return x86_perf_event_set_period(event); 2783 } 2784 2785 static void intel_pmu_reset(void) 2786 { 2787 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2788 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2789 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed); 2790 int num_counters = hybrid(cpuc->pmu, num_counters); 2791 unsigned long flags; 2792 int idx; 2793 2794 if (!num_counters) 2795 return; 2796 2797 local_irq_save(flags); 2798 2799 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2800 2801 for (idx = 0; idx < num_counters; idx++) { 2802 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2803 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2804 } 2805 for (idx = 0; idx < num_counters_fixed; idx++) { 2806 if (fixed_counter_disabled(idx, cpuc->pmu)) 2807 continue; 2808 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2809 } 2810 2811 if (ds) 2812 ds->bts_index = ds->bts_buffer_base; 2813 2814 /* Ack all overflows and disable fixed counters */ 2815 if (x86_pmu.version >= 2) { 2816 intel_pmu_ack_status(intel_pmu_get_status()); 2817 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2818 } 2819 2820 /* Reset LBRs and LBR freezing */ 2821 if (x86_pmu.lbr_nr) { 2822 update_debugctlmsr(get_debugctlmsr() & 2823 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2824 } 2825 2826 local_irq_restore(flags); 2827 } 2828 2829 static int handle_pmi_common(struct pt_regs *regs, u64 status) 2830 { 2831 struct perf_sample_data data; 2832 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2833 int bit; 2834 int handled = 0; 2835 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2836 2837 inc_irq_stat(apic_perf_irqs); 2838 2839 /* 2840 * Ignore a range of extra bits in status that do not indicate 2841 * overflow by themselves. 2842 */ 2843 status &= ~(GLOBAL_STATUS_COND_CHG | 2844 GLOBAL_STATUS_ASIF | 2845 GLOBAL_STATUS_LBRS_FROZEN); 2846 if (!status) 2847 return 0; 2848 /* 2849 * In case multiple PEBS events are sampled at the same time, 2850 * it is possible to have GLOBAL_STATUS bit 62 set indicating 2851 * PEBS buffer overflow and also seeing at most 3 PEBS counters 2852 * having their bits set in the status register. This is a sign 2853 * that there was at least one PEBS record pending at the time 2854 * of the PMU interrupt. PEBS counters must only be processed 2855 * via the drain_pebs() calls and not via the regular sample 2856 * processing loop coming after that the function, otherwise 2857 * phony regular samples may be generated in the sampling buffer 2858 * not marked with the EXACT tag. Another possibility is to have 2859 * one PEBS event and at least one non-PEBS event which overflows 2860 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2861 * not be set, yet the overflow status bit for the PEBS counter will 2862 * be on Skylake. 2863 * 2864 * To avoid this problem, we systematically ignore the PEBS-enabled 2865 * counters from the GLOBAL_STATUS mask and we always process PEBS 2866 * events via drain_pebs(). 2867 */ 2868 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 2869 status &= ~cpuc->pebs_enabled; 2870 else 2871 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 2872 2873 /* 2874 * PEBS overflow sets bit 62 in the global status register 2875 */ 2876 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 2877 u64 pebs_enabled = cpuc->pebs_enabled; 2878 2879 handled++; 2880 x86_pmu.drain_pebs(regs, &data); 2881 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 2882 2883 /* 2884 * PMI throttle may be triggered, which stops the PEBS event. 2885 * Although cpuc->pebs_enabled is updated accordingly, the 2886 * MSR_IA32_PEBS_ENABLE is not updated. Because the 2887 * cpuc->enabled has been forced to 0 in PMI. 2888 * Update the MSR if pebs_enabled is changed. 2889 */ 2890 if (pebs_enabled != cpuc->pebs_enabled) 2891 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 2892 } 2893 2894 /* 2895 * Intel PT 2896 */ 2897 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 2898 handled++; 2899 if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() && 2900 perf_guest_cbs->handle_intel_pt_intr)) 2901 perf_guest_cbs->handle_intel_pt_intr(); 2902 else 2903 intel_pt_interrupt(); 2904 } 2905 2906 /* 2907 * Intel Perf metrics 2908 */ 2909 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 2910 handled++; 2911 if (x86_pmu.update_topdown_event) 2912 x86_pmu.update_topdown_event(NULL); 2913 } 2914 2915 /* 2916 * Checkpointed counters can lead to 'spurious' PMIs because the 2917 * rollback caused by the PMI will have cleared the overflow status 2918 * bit. Therefore always force probe these counters. 2919 */ 2920 status |= cpuc->intel_cp_status; 2921 2922 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 2923 struct perf_event *event = cpuc->events[bit]; 2924 2925 handled++; 2926 2927 if (!test_bit(bit, cpuc->active_mask)) 2928 continue; 2929 2930 if (!intel_pmu_save_and_restart(event)) 2931 continue; 2932 2933 perf_sample_data_init(&data, 0, event->hw.last_period); 2934 2935 if (has_branch_stack(event)) 2936 data.br_stack = &cpuc->lbr_stack; 2937 2938 if (perf_event_overflow(event, &data, regs)) 2939 x86_pmu_stop(event, 0); 2940 } 2941 2942 return handled; 2943 } 2944 2945 /* 2946 * This handler is triggered by the local APIC, so the APIC IRQ handling 2947 * rules apply: 2948 */ 2949 static int intel_pmu_handle_irq(struct pt_regs *regs) 2950 { 2951 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2952 bool late_ack = hybrid_bit(cpuc->pmu, late_ack); 2953 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); 2954 int loops; 2955 u64 status; 2956 int handled; 2957 int pmu_enabled; 2958 2959 /* 2960 * Save the PMU state. 2961 * It needs to be restored when leaving the handler. 2962 */ 2963 pmu_enabled = cpuc->enabled; 2964 /* 2965 * In general, the early ACK is only applied for old platforms. 2966 * For the big core starts from Haswell, the late ACK should be 2967 * applied. 2968 * For the small core after Tremont, we have to do the ACK right 2969 * before re-enabling counters, which is in the middle of the 2970 * NMI handler. 2971 */ 2972 if (!late_ack && !mid_ack) 2973 apic_write(APIC_LVTPC, APIC_DM_NMI); 2974 intel_bts_disable_local(); 2975 cpuc->enabled = 0; 2976 __intel_pmu_disable_all(true); 2977 handled = intel_pmu_drain_bts_buffer(); 2978 handled += intel_bts_interrupt(); 2979 status = intel_pmu_get_status(); 2980 if (!status) 2981 goto done; 2982 2983 loops = 0; 2984 again: 2985 intel_pmu_lbr_read(); 2986 intel_pmu_ack_status(status); 2987 if (++loops > 100) { 2988 static bool warned; 2989 2990 if (!warned) { 2991 WARN(1, "perfevents: irq loop stuck!\n"); 2992 perf_event_print_debug(); 2993 warned = true; 2994 } 2995 intel_pmu_reset(); 2996 goto done; 2997 } 2998 2999 handled += handle_pmi_common(regs, status); 3000 3001 /* 3002 * Repeat if there is more work to be done: 3003 */ 3004 status = intel_pmu_get_status(); 3005 if (status) 3006 goto again; 3007 3008 done: 3009 if (mid_ack) 3010 apic_write(APIC_LVTPC, APIC_DM_NMI); 3011 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 3012 cpuc->enabled = pmu_enabled; 3013 if (pmu_enabled) 3014 __intel_pmu_enable_all(0, true); 3015 intel_bts_enable_local(); 3016 3017 /* 3018 * Only unmask the NMI after the overflow counters 3019 * have been reset. This avoids spurious NMIs on 3020 * Haswell CPUs. 3021 */ 3022 if (late_ack) 3023 apic_write(APIC_LVTPC, APIC_DM_NMI); 3024 return handled; 3025 } 3026 3027 static struct event_constraint * 3028 intel_bts_constraints(struct perf_event *event) 3029 { 3030 if (unlikely(intel_pmu_has_bts(event))) 3031 return &bts_constraint; 3032 3033 return NULL; 3034 } 3035 3036 /* 3037 * Note: matches a fake event, like Fixed2. 3038 */ 3039 static struct event_constraint * 3040 intel_vlbr_constraints(struct perf_event *event) 3041 { 3042 struct event_constraint *c = &vlbr_constraint; 3043 3044 if (unlikely(constraint_match(c, event->hw.config))) 3045 return c; 3046 3047 return NULL; 3048 } 3049 3050 static int intel_alt_er(struct cpu_hw_events *cpuc, 3051 int idx, u64 config) 3052 { 3053 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); 3054 int alt_idx = idx; 3055 3056 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 3057 return idx; 3058 3059 if (idx == EXTRA_REG_RSP_0) 3060 alt_idx = EXTRA_REG_RSP_1; 3061 3062 if (idx == EXTRA_REG_RSP_1) 3063 alt_idx = EXTRA_REG_RSP_0; 3064 3065 if (config & ~extra_regs[alt_idx].valid_mask) 3066 return idx; 3067 3068 return alt_idx; 3069 } 3070 3071 static void intel_fixup_er(struct perf_event *event, int idx) 3072 { 3073 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); 3074 event->hw.extra_reg.idx = idx; 3075 3076 if (idx == EXTRA_REG_RSP_0) { 3077 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3078 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event; 3079 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 3080 } else if (idx == EXTRA_REG_RSP_1) { 3081 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3082 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event; 3083 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 3084 } 3085 } 3086 3087 /* 3088 * manage allocation of shared extra msr for certain events 3089 * 3090 * sharing can be: 3091 * per-cpu: to be shared between the various events on a single PMU 3092 * per-core: per-cpu + shared by HT threads 3093 */ 3094 static struct event_constraint * 3095 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 3096 struct perf_event *event, 3097 struct hw_perf_event_extra *reg) 3098 { 3099 struct event_constraint *c = &emptyconstraint; 3100 struct er_account *era; 3101 unsigned long flags; 3102 int idx = reg->idx; 3103 3104 /* 3105 * reg->alloc can be set due to existing state, so for fake cpuc we 3106 * need to ignore this, otherwise we might fail to allocate proper fake 3107 * state for this extra reg constraint. Also see the comment below. 3108 */ 3109 if (reg->alloc && !cpuc->is_fake) 3110 return NULL; /* call x86_get_event_constraint() */ 3111 3112 again: 3113 era = &cpuc->shared_regs->regs[idx]; 3114 /* 3115 * we use spin_lock_irqsave() to avoid lockdep issues when 3116 * passing a fake cpuc 3117 */ 3118 raw_spin_lock_irqsave(&era->lock, flags); 3119 3120 if (!atomic_read(&era->ref) || era->config == reg->config) { 3121 3122 /* 3123 * If its a fake cpuc -- as per validate_{group,event}() we 3124 * shouldn't touch event state and we can avoid doing so 3125 * since both will only call get_event_constraints() once 3126 * on each event, this avoids the need for reg->alloc. 3127 * 3128 * Not doing the ER fixup will only result in era->reg being 3129 * wrong, but since we won't actually try and program hardware 3130 * this isn't a problem either. 3131 */ 3132 if (!cpuc->is_fake) { 3133 if (idx != reg->idx) 3134 intel_fixup_er(event, idx); 3135 3136 /* 3137 * x86_schedule_events() can call get_event_constraints() 3138 * multiple times on events in the case of incremental 3139 * scheduling(). reg->alloc ensures we only do the ER 3140 * allocation once. 3141 */ 3142 reg->alloc = 1; 3143 } 3144 3145 /* lock in msr value */ 3146 era->config = reg->config; 3147 era->reg = reg->reg; 3148 3149 /* one more user */ 3150 atomic_inc(&era->ref); 3151 3152 /* 3153 * need to call x86_get_event_constraint() 3154 * to check if associated event has constraints 3155 */ 3156 c = NULL; 3157 } else { 3158 idx = intel_alt_er(cpuc, idx, reg->config); 3159 if (idx != reg->idx) { 3160 raw_spin_unlock_irqrestore(&era->lock, flags); 3161 goto again; 3162 } 3163 } 3164 raw_spin_unlock_irqrestore(&era->lock, flags); 3165 3166 return c; 3167 } 3168 3169 static void 3170 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3171 struct hw_perf_event_extra *reg) 3172 { 3173 struct er_account *era; 3174 3175 /* 3176 * Only put constraint if extra reg was actually allocated. Also takes 3177 * care of event which do not use an extra shared reg. 3178 * 3179 * Also, if this is a fake cpuc we shouldn't touch any event state 3180 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3181 * either since it'll be thrown out. 3182 */ 3183 if (!reg->alloc || cpuc->is_fake) 3184 return; 3185 3186 era = &cpuc->shared_regs->regs[reg->idx]; 3187 3188 /* one fewer user */ 3189 atomic_dec(&era->ref); 3190 3191 /* allocate again next time */ 3192 reg->alloc = 0; 3193 } 3194 3195 static struct event_constraint * 3196 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3197 struct perf_event *event) 3198 { 3199 struct event_constraint *c = NULL, *d; 3200 struct hw_perf_event_extra *xreg, *breg; 3201 3202 xreg = &event->hw.extra_reg; 3203 if (xreg->idx != EXTRA_REG_NONE) { 3204 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3205 if (c == &emptyconstraint) 3206 return c; 3207 } 3208 breg = &event->hw.branch_reg; 3209 if (breg->idx != EXTRA_REG_NONE) { 3210 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3211 if (d == &emptyconstraint) { 3212 __intel_shared_reg_put_constraints(cpuc, xreg); 3213 c = d; 3214 } 3215 } 3216 return c; 3217 } 3218 3219 struct event_constraint * 3220 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3221 struct perf_event *event) 3222 { 3223 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); 3224 struct event_constraint *c; 3225 3226 if (event_constraints) { 3227 for_each_event_constraint(c, event_constraints) { 3228 if (constraint_match(c, event->hw.config)) { 3229 event->hw.flags |= c->flags; 3230 return c; 3231 } 3232 } 3233 } 3234 3235 return &hybrid_var(cpuc->pmu, unconstrained); 3236 } 3237 3238 static struct event_constraint * 3239 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3240 struct perf_event *event) 3241 { 3242 struct event_constraint *c; 3243 3244 c = intel_vlbr_constraints(event); 3245 if (c) 3246 return c; 3247 3248 c = intel_bts_constraints(event); 3249 if (c) 3250 return c; 3251 3252 c = intel_shared_regs_constraints(cpuc, event); 3253 if (c) 3254 return c; 3255 3256 c = intel_pebs_constraints(event); 3257 if (c) 3258 return c; 3259 3260 return x86_get_event_constraints(cpuc, idx, event); 3261 } 3262 3263 static void 3264 intel_start_scheduling(struct cpu_hw_events *cpuc) 3265 { 3266 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3267 struct intel_excl_states *xl; 3268 int tid = cpuc->excl_thread_id; 3269 3270 /* 3271 * nothing needed if in group validation mode 3272 */ 3273 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3274 return; 3275 3276 /* 3277 * no exclusion needed 3278 */ 3279 if (WARN_ON_ONCE(!excl_cntrs)) 3280 return; 3281 3282 xl = &excl_cntrs->states[tid]; 3283 3284 xl->sched_started = true; 3285 /* 3286 * lock shared state until we are done scheduling 3287 * in stop_event_scheduling() 3288 * makes scheduling appear as a transaction 3289 */ 3290 raw_spin_lock(&excl_cntrs->lock); 3291 } 3292 3293 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3294 { 3295 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3296 struct event_constraint *c = cpuc->event_constraint[idx]; 3297 struct intel_excl_states *xl; 3298 int tid = cpuc->excl_thread_id; 3299 3300 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3301 return; 3302 3303 if (WARN_ON_ONCE(!excl_cntrs)) 3304 return; 3305 3306 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3307 return; 3308 3309 xl = &excl_cntrs->states[tid]; 3310 3311 lockdep_assert_held(&excl_cntrs->lock); 3312 3313 if (c->flags & PERF_X86_EVENT_EXCL) 3314 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3315 else 3316 xl->state[cntr] = INTEL_EXCL_SHARED; 3317 } 3318 3319 static void 3320 intel_stop_scheduling(struct cpu_hw_events *cpuc) 3321 { 3322 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3323 struct intel_excl_states *xl; 3324 int tid = cpuc->excl_thread_id; 3325 3326 /* 3327 * nothing needed if in group validation mode 3328 */ 3329 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3330 return; 3331 /* 3332 * no exclusion needed 3333 */ 3334 if (WARN_ON_ONCE(!excl_cntrs)) 3335 return; 3336 3337 xl = &excl_cntrs->states[tid]; 3338 3339 xl->sched_started = false; 3340 /* 3341 * release shared state lock (acquired in intel_start_scheduling()) 3342 */ 3343 raw_spin_unlock(&excl_cntrs->lock); 3344 } 3345 3346 static struct event_constraint * 3347 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 3348 { 3349 WARN_ON_ONCE(!cpuc->constraint_list); 3350 3351 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 3352 struct event_constraint *cx; 3353 3354 /* 3355 * grab pre-allocated constraint entry 3356 */ 3357 cx = &cpuc->constraint_list[idx]; 3358 3359 /* 3360 * initialize dynamic constraint 3361 * with static constraint 3362 */ 3363 *cx = *c; 3364 3365 /* 3366 * mark constraint as dynamic 3367 */ 3368 cx->flags |= PERF_X86_EVENT_DYNAMIC; 3369 c = cx; 3370 } 3371 3372 return c; 3373 } 3374 3375 static struct event_constraint * 3376 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3377 int idx, struct event_constraint *c) 3378 { 3379 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3380 struct intel_excl_states *xlo; 3381 int tid = cpuc->excl_thread_id; 3382 int is_excl, i, w; 3383 3384 /* 3385 * validating a group does not require 3386 * enforcing cross-thread exclusion 3387 */ 3388 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3389 return c; 3390 3391 /* 3392 * no exclusion needed 3393 */ 3394 if (WARN_ON_ONCE(!excl_cntrs)) 3395 return c; 3396 3397 /* 3398 * because we modify the constraint, we need 3399 * to make a copy. Static constraints come 3400 * from static const tables. 3401 * 3402 * only needed when constraint has not yet 3403 * been cloned (marked dynamic) 3404 */ 3405 c = dyn_constraint(cpuc, c, idx); 3406 3407 /* 3408 * From here on, the constraint is dynamic. 3409 * Either it was just allocated above, or it 3410 * was allocated during a earlier invocation 3411 * of this function 3412 */ 3413 3414 /* 3415 * state of sibling HT 3416 */ 3417 xlo = &excl_cntrs->states[tid ^ 1]; 3418 3419 /* 3420 * event requires exclusive counter access 3421 * across HT threads 3422 */ 3423 is_excl = c->flags & PERF_X86_EVENT_EXCL; 3424 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3425 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3426 if (!cpuc->n_excl++) 3427 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3428 } 3429 3430 /* 3431 * Modify static constraint with current dynamic 3432 * state of thread 3433 * 3434 * EXCLUSIVE: sibling counter measuring exclusive event 3435 * SHARED : sibling counter measuring non-exclusive event 3436 * UNUSED : sibling counter unused 3437 */ 3438 w = c->weight; 3439 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3440 /* 3441 * exclusive event in sibling counter 3442 * our corresponding counter cannot be used 3443 * regardless of our event 3444 */ 3445 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3446 __clear_bit(i, c->idxmsk); 3447 w--; 3448 continue; 3449 } 3450 /* 3451 * if measuring an exclusive event, sibling 3452 * measuring non-exclusive, then counter cannot 3453 * be used 3454 */ 3455 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3456 __clear_bit(i, c->idxmsk); 3457 w--; 3458 continue; 3459 } 3460 } 3461 3462 /* 3463 * if we return an empty mask, then switch 3464 * back to static empty constraint to avoid 3465 * the cost of freeing later on 3466 */ 3467 if (!w) 3468 c = &emptyconstraint; 3469 3470 c->weight = w; 3471 3472 return c; 3473 } 3474 3475 static struct event_constraint * 3476 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3477 struct perf_event *event) 3478 { 3479 struct event_constraint *c1, *c2; 3480 3481 c1 = cpuc->event_constraint[idx]; 3482 3483 /* 3484 * first time only 3485 * - static constraint: no change across incremental scheduling calls 3486 * - dynamic constraint: handled by intel_get_excl_constraints() 3487 */ 3488 c2 = __intel_get_event_constraints(cpuc, idx, event); 3489 if (c1) { 3490 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3491 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3492 c1->weight = c2->weight; 3493 c2 = c1; 3494 } 3495 3496 if (cpuc->excl_cntrs) 3497 return intel_get_excl_constraints(cpuc, event, idx, c2); 3498 3499 return c2; 3500 } 3501 3502 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3503 struct perf_event *event) 3504 { 3505 struct hw_perf_event *hwc = &event->hw; 3506 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3507 int tid = cpuc->excl_thread_id; 3508 struct intel_excl_states *xl; 3509 3510 /* 3511 * nothing needed if in group validation mode 3512 */ 3513 if (cpuc->is_fake) 3514 return; 3515 3516 if (WARN_ON_ONCE(!excl_cntrs)) 3517 return; 3518 3519 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3520 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3521 if (!--cpuc->n_excl) 3522 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3523 } 3524 3525 /* 3526 * If event was actually assigned, then mark the counter state as 3527 * unused now. 3528 */ 3529 if (hwc->idx >= 0) { 3530 xl = &excl_cntrs->states[tid]; 3531 3532 /* 3533 * put_constraint may be called from x86_schedule_events() 3534 * which already has the lock held so here make locking 3535 * conditional. 3536 */ 3537 if (!xl->sched_started) 3538 raw_spin_lock(&excl_cntrs->lock); 3539 3540 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3541 3542 if (!xl->sched_started) 3543 raw_spin_unlock(&excl_cntrs->lock); 3544 } 3545 } 3546 3547 static void 3548 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3549 struct perf_event *event) 3550 { 3551 struct hw_perf_event_extra *reg; 3552 3553 reg = &event->hw.extra_reg; 3554 if (reg->idx != EXTRA_REG_NONE) 3555 __intel_shared_reg_put_constraints(cpuc, reg); 3556 3557 reg = &event->hw.branch_reg; 3558 if (reg->idx != EXTRA_REG_NONE) 3559 __intel_shared_reg_put_constraints(cpuc, reg); 3560 } 3561 3562 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3563 struct perf_event *event) 3564 { 3565 intel_put_shared_regs_event_constraints(cpuc, event); 3566 3567 /* 3568 * is PMU has exclusive counter restrictions, then 3569 * all events are subject to and must call the 3570 * put_excl_constraints() routine 3571 */ 3572 if (cpuc->excl_cntrs) 3573 intel_put_excl_constraints(cpuc, event); 3574 } 3575 3576 static void intel_pebs_aliases_core2(struct perf_event *event) 3577 { 3578 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3579 /* 3580 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3581 * (0x003c) so that we can use it with PEBS. 3582 * 3583 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3584 * PEBS capable. However we can use INST_RETIRED.ANY_P 3585 * (0x00c0), which is a PEBS capable event, to get the same 3586 * count. 3587 * 3588 * INST_RETIRED.ANY_P counts the number of cycles that retires 3589 * CNTMASK instructions. By setting CNTMASK to a value (16) 3590 * larger than the maximum number of instructions that can be 3591 * retired per cycle (4) and then inverting the condition, we 3592 * count all cycles that retire 16 or less instructions, which 3593 * is every cycle. 3594 * 3595 * Thereby we gain a PEBS capable cycle counter. 3596 */ 3597 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3598 3599 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3600 event->hw.config = alt_config; 3601 } 3602 } 3603 3604 static void intel_pebs_aliases_snb(struct perf_event *event) 3605 { 3606 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3607 /* 3608 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3609 * (0x003c) so that we can use it with PEBS. 3610 * 3611 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3612 * PEBS capable. However we can use UOPS_RETIRED.ALL 3613 * (0x01c2), which is a PEBS capable event, to get the same 3614 * count. 3615 * 3616 * UOPS_RETIRED.ALL counts the number of cycles that retires 3617 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3618 * larger than the maximum number of micro-ops that can be 3619 * retired per cycle (4) and then inverting the condition, we 3620 * count all cycles that retire 16 or less micro-ops, which 3621 * is every cycle. 3622 * 3623 * Thereby we gain a PEBS capable cycle counter. 3624 */ 3625 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3626 3627 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3628 event->hw.config = alt_config; 3629 } 3630 } 3631 3632 static void intel_pebs_aliases_precdist(struct perf_event *event) 3633 { 3634 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3635 /* 3636 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3637 * (0x003c) so that we can use it with PEBS. 3638 * 3639 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3640 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3641 * (0x01c0), which is a PEBS capable event, to get the same 3642 * count. 3643 * 3644 * The PREC_DIST event has special support to minimize sample 3645 * shadowing effects. One drawback is that it can be 3646 * only programmed on counter 1, but that seems like an 3647 * acceptable trade off. 3648 */ 3649 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3650 3651 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3652 event->hw.config = alt_config; 3653 } 3654 } 3655 3656 static void intel_pebs_aliases_ivb(struct perf_event *event) 3657 { 3658 if (event->attr.precise_ip < 3) 3659 return intel_pebs_aliases_snb(event); 3660 return intel_pebs_aliases_precdist(event); 3661 } 3662 3663 static void intel_pebs_aliases_skl(struct perf_event *event) 3664 { 3665 if (event->attr.precise_ip < 3) 3666 return intel_pebs_aliases_core2(event); 3667 return intel_pebs_aliases_precdist(event); 3668 } 3669 3670 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3671 { 3672 unsigned long flags = x86_pmu.large_pebs_flags; 3673 3674 if (event->attr.use_clockid) 3675 flags &= ~PERF_SAMPLE_TIME; 3676 if (!event->attr.exclude_kernel) 3677 flags &= ~PERF_SAMPLE_REGS_USER; 3678 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3679 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3680 return flags; 3681 } 3682 3683 static int intel_pmu_bts_config(struct perf_event *event) 3684 { 3685 struct perf_event_attr *attr = &event->attr; 3686 3687 if (unlikely(intel_pmu_has_bts(event))) { 3688 /* BTS is not supported by this architecture. */ 3689 if (!x86_pmu.bts_active) 3690 return -EOPNOTSUPP; 3691 3692 /* BTS is currently only allowed for user-mode. */ 3693 if (!attr->exclude_kernel) 3694 return -EOPNOTSUPP; 3695 3696 /* BTS is not allowed for precise events. */ 3697 if (attr->precise_ip) 3698 return -EOPNOTSUPP; 3699 3700 /* disallow bts if conflicting events are present */ 3701 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3702 return -EBUSY; 3703 3704 event->destroy = hw_perf_lbr_event_destroy; 3705 } 3706 3707 return 0; 3708 } 3709 3710 static int core_pmu_hw_config(struct perf_event *event) 3711 { 3712 int ret = x86_pmu_hw_config(event); 3713 3714 if (ret) 3715 return ret; 3716 3717 return intel_pmu_bts_config(event); 3718 } 3719 3720 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 3721 ((x86_pmu.num_topdown_events - 1) << 8)) 3722 3723 static bool is_available_metric_event(struct perf_event *event) 3724 { 3725 return is_metric_event(event) && 3726 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 3727 } 3728 3729 static inline bool is_mem_loads_event(struct perf_event *event) 3730 { 3731 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 3732 } 3733 3734 static inline bool is_mem_loads_aux_event(struct perf_event *event) 3735 { 3736 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 3737 } 3738 3739 static inline bool require_mem_loads_aux_event(struct perf_event *event) 3740 { 3741 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) 3742 return false; 3743 3744 if (is_hybrid()) 3745 return hybrid_pmu(event->pmu)->cpu_type == hybrid_big; 3746 3747 return true; 3748 } 3749 3750 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) 3751 { 3752 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); 3753 3754 return test_bit(idx, (unsigned long *)&intel_cap->capabilities); 3755 } 3756 3757 static int intel_pmu_hw_config(struct perf_event *event) 3758 { 3759 int ret = x86_pmu_hw_config(event); 3760 3761 if (ret) 3762 return ret; 3763 3764 ret = intel_pmu_bts_config(event); 3765 if (ret) 3766 return ret; 3767 3768 if (event->attr.precise_ip) { 3769 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) 3770 return -EINVAL; 3771 3772 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 3773 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3774 if (!(event->attr.sample_type & 3775 ~intel_pmu_large_pebs_flags(event))) { 3776 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3777 event->attach_state |= PERF_ATTACH_SCHED_CB; 3778 } 3779 } 3780 if (x86_pmu.pebs_aliases) 3781 x86_pmu.pebs_aliases(event); 3782 3783 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) 3784 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY; 3785 } 3786 3787 if (needs_branch_stack(event)) { 3788 ret = intel_pmu_setup_lbr_filter(event); 3789 if (ret) 3790 return ret; 3791 event->attach_state |= PERF_ATTACH_SCHED_CB; 3792 3793 /* 3794 * BTS is set up earlier in this path, so don't account twice 3795 */ 3796 if (!unlikely(intel_pmu_has_bts(event))) { 3797 /* disallow lbr if conflicting events are present */ 3798 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3799 return -EBUSY; 3800 3801 event->destroy = hw_perf_lbr_event_destroy; 3802 } 3803 } 3804 3805 if (event->attr.aux_output) { 3806 if (!event->attr.precise_ip) 3807 return -EINVAL; 3808 3809 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 3810 } 3811 3812 if ((event->attr.type == PERF_TYPE_HARDWARE) || 3813 (event->attr.type == PERF_TYPE_HW_CACHE)) 3814 return 0; 3815 3816 /* 3817 * Config Topdown slots and metric events 3818 * 3819 * The slots event on Fixed Counter 3 can support sampling, 3820 * which will be handled normally in x86_perf_event_update(). 3821 * 3822 * Metric events don't support sampling and require being paired 3823 * with a slots event as group leader. When the slots event 3824 * is used in a metrics group, it too cannot support sampling. 3825 */ 3826 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { 3827 if (event->attr.config1 || event->attr.config2) 3828 return -EINVAL; 3829 3830 /* 3831 * The TopDown metrics events and slots event don't 3832 * support any filters. 3833 */ 3834 if (event->attr.config & X86_ALL_EVENT_FLAGS) 3835 return -EINVAL; 3836 3837 if (is_available_metric_event(event)) { 3838 struct perf_event *leader = event->group_leader; 3839 3840 /* The metric events don't support sampling. */ 3841 if (is_sampling_event(event)) 3842 return -EINVAL; 3843 3844 /* The metric events require a slots group leader. */ 3845 if (!is_slots_event(leader)) 3846 return -EINVAL; 3847 3848 /* 3849 * The leader/SLOTS must not be a sampling event for 3850 * metric use; hardware requires it starts at 0 when used 3851 * in conjunction with MSR_PERF_METRICS. 3852 */ 3853 if (is_sampling_event(leader)) 3854 return -EINVAL; 3855 3856 event->event_caps |= PERF_EV_CAP_SIBLING; 3857 /* 3858 * Only once we have a METRICs sibling do we 3859 * need TopDown magic. 3860 */ 3861 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3862 event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3863 } 3864 } 3865 3866 /* 3867 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 3868 * doesn't function quite right. As a work-around it needs to always be 3869 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 3870 * The actual count of this second event is irrelevant it just needs 3871 * to be active to make the first event function correctly. 3872 * 3873 * In a group, the auxiliary event must be in front of the load latency 3874 * event. The rule is to simplify the implementation of the check. 3875 * That's because perf cannot have a complete group at the moment. 3876 */ 3877 if (require_mem_loads_aux_event(event) && 3878 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 3879 is_mem_loads_event(event)) { 3880 struct perf_event *leader = event->group_leader; 3881 struct perf_event *sibling = NULL; 3882 3883 if (!is_mem_loads_aux_event(leader)) { 3884 for_each_sibling_event(sibling, leader) { 3885 if (is_mem_loads_aux_event(sibling)) 3886 break; 3887 } 3888 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 3889 return -ENODATA; 3890 } 3891 } 3892 3893 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 3894 return 0; 3895 3896 if (x86_pmu.version < 3) 3897 return -EINVAL; 3898 3899 ret = perf_allow_cpu(&event->attr); 3900 if (ret) 3901 return ret; 3902 3903 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 3904 3905 return 0; 3906 } 3907 3908 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) 3909 { 3910 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3911 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3912 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 3913 3914 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; 3915 arr[0].host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask; 3916 arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask; 3917 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 3918 arr[0].guest &= ~cpuc->pebs_enabled; 3919 else 3920 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 3921 *nr = 1; 3922 3923 if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) { 3924 /* 3925 * If PMU counter has PEBS enabled it is not enough to 3926 * disable counter on a guest entry since PEBS memory 3927 * write can overshoot guest entry and corrupt guest 3928 * memory. Disabling PEBS solves the problem. 3929 * 3930 * Don't do this if the CPU already enforces it. 3931 */ 3932 arr[1].msr = MSR_IA32_PEBS_ENABLE; 3933 arr[1].host = cpuc->pebs_enabled; 3934 arr[1].guest = 0; 3935 *nr = 2; 3936 } 3937 3938 return arr; 3939 } 3940 3941 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) 3942 { 3943 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3944 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3945 int idx; 3946 3947 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3948 struct perf_event *event = cpuc->events[idx]; 3949 3950 arr[idx].msr = x86_pmu_config_addr(idx); 3951 arr[idx].host = arr[idx].guest = 0; 3952 3953 if (!test_bit(idx, cpuc->active_mask)) 3954 continue; 3955 3956 arr[idx].host = arr[idx].guest = 3957 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 3958 3959 if (event->attr.exclude_host) 3960 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3961 else if (event->attr.exclude_guest) 3962 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3963 } 3964 3965 *nr = x86_pmu.num_counters; 3966 return arr; 3967 } 3968 3969 static void core_pmu_enable_event(struct perf_event *event) 3970 { 3971 if (!event->attr.exclude_host) 3972 x86_pmu_enable_event(event); 3973 } 3974 3975 static void core_pmu_enable_all(int added) 3976 { 3977 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3978 int idx; 3979 3980 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3981 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 3982 3983 if (!test_bit(idx, cpuc->active_mask) || 3984 cpuc->events[idx]->attr.exclude_host) 3985 continue; 3986 3987 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 3988 } 3989 } 3990 3991 static int hsw_hw_config(struct perf_event *event) 3992 { 3993 int ret = intel_pmu_hw_config(event); 3994 3995 if (ret) 3996 return ret; 3997 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 3998 return 0; 3999 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 4000 4001 /* 4002 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 4003 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 4004 * this combination. 4005 */ 4006 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 4007 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 4008 event->attr.precise_ip > 0)) 4009 return -EOPNOTSUPP; 4010 4011 if (event_is_checkpointed(event)) { 4012 /* 4013 * Sampling of checkpointed events can cause situations where 4014 * the CPU constantly aborts because of a overflow, which is 4015 * then checkpointed back and ignored. Forbid checkpointing 4016 * for sampling. 4017 * 4018 * But still allow a long sampling period, so that perf stat 4019 * from KVM works. 4020 */ 4021 if (event->attr.sample_period > 0 && 4022 event->attr.sample_period < 0x7fffffff) 4023 return -EOPNOTSUPP; 4024 } 4025 return 0; 4026 } 4027 4028 static struct event_constraint counter0_constraint = 4029 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 4030 4031 static struct event_constraint counter2_constraint = 4032 EVENT_CONSTRAINT(0, 0x4, 0); 4033 4034 static struct event_constraint fixed0_constraint = 4035 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 4036 4037 static struct event_constraint fixed0_counter0_constraint = 4038 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 4039 4040 static struct event_constraint * 4041 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4042 struct perf_event *event) 4043 { 4044 struct event_constraint *c; 4045 4046 c = intel_get_event_constraints(cpuc, idx, event); 4047 4048 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 4049 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 4050 if (c->idxmsk64 & (1U << 2)) 4051 return &counter2_constraint; 4052 return &emptyconstraint; 4053 } 4054 4055 return c; 4056 } 4057 4058 static struct event_constraint * 4059 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4060 struct perf_event *event) 4061 { 4062 /* 4063 * Fixed counter 0 has less skid. 4064 * Force instruction:ppp in Fixed counter 0 4065 */ 4066 if ((event->attr.precise_ip == 3) && 4067 constraint_match(&fixed0_constraint, event->hw.config)) 4068 return &fixed0_constraint; 4069 4070 return hsw_get_event_constraints(cpuc, idx, event); 4071 } 4072 4073 static struct event_constraint * 4074 spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4075 struct perf_event *event) 4076 { 4077 struct event_constraint *c; 4078 4079 c = icl_get_event_constraints(cpuc, idx, event); 4080 4081 /* 4082 * The :ppp indicates the Precise Distribution (PDist) facility, which 4083 * is only supported on the GP counter 0. If a :ppp event which is not 4084 * available on the GP counter 0, error out. 4085 * Exception: Instruction PDIR is only available on the fixed counter 0. 4086 */ 4087 if ((event->attr.precise_ip == 3) && 4088 !constraint_match(&fixed0_constraint, event->hw.config)) { 4089 if (c->idxmsk64 & BIT_ULL(0)) 4090 return &counter0_constraint; 4091 4092 return &emptyconstraint; 4093 } 4094 4095 return c; 4096 } 4097 4098 static struct event_constraint * 4099 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4100 struct perf_event *event) 4101 { 4102 struct event_constraint *c; 4103 4104 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 4105 if (event->attr.precise_ip == 3) 4106 return &counter0_constraint; 4107 4108 c = intel_get_event_constraints(cpuc, idx, event); 4109 4110 return c; 4111 } 4112 4113 static struct event_constraint * 4114 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4115 struct perf_event *event) 4116 { 4117 struct event_constraint *c; 4118 4119 /* 4120 * :ppp means to do reduced skid PEBS, 4121 * which is available on PMC0 and fixed counter 0. 4122 */ 4123 if (event->attr.precise_ip == 3) { 4124 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 4125 if (constraint_match(&fixed0_constraint, event->hw.config)) 4126 return &fixed0_counter0_constraint; 4127 4128 return &counter0_constraint; 4129 } 4130 4131 c = intel_get_event_constraints(cpuc, idx, event); 4132 4133 return c; 4134 } 4135 4136 static bool allow_tsx_force_abort = true; 4137 4138 static struct event_constraint * 4139 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4140 struct perf_event *event) 4141 { 4142 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 4143 4144 /* 4145 * Without TFA we must not use PMC3. 4146 */ 4147 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 4148 c = dyn_constraint(cpuc, c, idx); 4149 c->idxmsk64 &= ~(1ULL << 3); 4150 c->weight--; 4151 } 4152 4153 return c; 4154 } 4155 4156 static struct event_constraint * 4157 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4158 struct perf_event *event) 4159 { 4160 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4161 4162 if (pmu->cpu_type == hybrid_big) 4163 return spr_get_event_constraints(cpuc, idx, event); 4164 else if (pmu->cpu_type == hybrid_small) 4165 return tnt_get_event_constraints(cpuc, idx, event); 4166 4167 WARN_ON(1); 4168 return &emptyconstraint; 4169 } 4170 4171 static int adl_hw_config(struct perf_event *event) 4172 { 4173 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4174 4175 if (pmu->cpu_type == hybrid_big) 4176 return hsw_hw_config(event); 4177 else if (pmu->cpu_type == hybrid_small) 4178 return intel_pmu_hw_config(event); 4179 4180 WARN_ON(1); 4181 return -EOPNOTSUPP; 4182 } 4183 4184 static u8 adl_get_hybrid_cpu_type(void) 4185 { 4186 return hybrid_big; 4187 } 4188 4189 /* 4190 * Broadwell: 4191 * 4192 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 4193 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 4194 * the two to enforce a minimum period of 128 (the smallest value that has bits 4195 * 0-5 cleared and >= 100). 4196 * 4197 * Because of how the code in x86_perf_event_set_period() works, the truncation 4198 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 4199 * to make up for the 'lost' events due to carrying the 'error' in period_left. 4200 * 4201 * Therefore the effective (average) period matches the requested period, 4202 * despite coarser hardware granularity. 4203 */ 4204 static u64 bdw_limit_period(struct perf_event *event, u64 left) 4205 { 4206 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 4207 X86_CONFIG(.event=0xc0, .umask=0x01)) { 4208 if (left < 128) 4209 left = 128; 4210 left &= ~0x3fULL; 4211 } 4212 return left; 4213 } 4214 4215 static u64 nhm_limit_period(struct perf_event *event, u64 left) 4216 { 4217 return max(left, 32ULL); 4218 } 4219 4220 static u64 spr_limit_period(struct perf_event *event, u64 left) 4221 { 4222 if (event->attr.precise_ip == 3) 4223 return max(left, 128ULL); 4224 4225 return left; 4226 } 4227 4228 PMU_FORMAT_ATTR(event, "config:0-7" ); 4229 PMU_FORMAT_ATTR(umask, "config:8-15" ); 4230 PMU_FORMAT_ATTR(edge, "config:18" ); 4231 PMU_FORMAT_ATTR(pc, "config:19" ); 4232 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 4233 PMU_FORMAT_ATTR(inv, "config:23" ); 4234 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 4235 PMU_FORMAT_ATTR(in_tx, "config:32"); 4236 PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 4237 4238 static struct attribute *intel_arch_formats_attr[] = { 4239 &format_attr_event.attr, 4240 &format_attr_umask.attr, 4241 &format_attr_edge.attr, 4242 &format_attr_pc.attr, 4243 &format_attr_inv.attr, 4244 &format_attr_cmask.attr, 4245 NULL, 4246 }; 4247 4248 ssize_t intel_event_sysfs_show(char *page, u64 config) 4249 { 4250 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 4251 4252 return x86_event_sysfs_show(page, config, event); 4253 } 4254 4255 static struct intel_shared_regs *allocate_shared_regs(int cpu) 4256 { 4257 struct intel_shared_regs *regs; 4258 int i; 4259 4260 regs = kzalloc_node(sizeof(struct intel_shared_regs), 4261 GFP_KERNEL, cpu_to_node(cpu)); 4262 if (regs) { 4263 /* 4264 * initialize the locks to keep lockdep happy 4265 */ 4266 for (i = 0; i < EXTRA_REG_MAX; i++) 4267 raw_spin_lock_init(®s->regs[i].lock); 4268 4269 regs->core_id = -1; 4270 } 4271 return regs; 4272 } 4273 4274 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 4275 { 4276 struct intel_excl_cntrs *c; 4277 4278 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 4279 GFP_KERNEL, cpu_to_node(cpu)); 4280 if (c) { 4281 raw_spin_lock_init(&c->lock); 4282 c->core_id = -1; 4283 } 4284 return c; 4285 } 4286 4287 4288 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 4289 { 4290 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 4291 4292 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 4293 cpuc->shared_regs = allocate_shared_regs(cpu); 4294 if (!cpuc->shared_regs) 4295 goto err; 4296 } 4297 4298 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { 4299 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 4300 4301 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 4302 if (!cpuc->constraint_list) 4303 goto err_shared_regs; 4304 } 4305 4306 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4307 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 4308 if (!cpuc->excl_cntrs) 4309 goto err_constraint_list; 4310 4311 cpuc->excl_thread_id = 0; 4312 } 4313 4314 return 0; 4315 4316 err_constraint_list: 4317 kfree(cpuc->constraint_list); 4318 cpuc->constraint_list = NULL; 4319 4320 err_shared_regs: 4321 kfree(cpuc->shared_regs); 4322 cpuc->shared_regs = NULL; 4323 4324 err: 4325 return -ENOMEM; 4326 } 4327 4328 static int intel_pmu_cpu_prepare(int cpu) 4329 { 4330 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 4331 } 4332 4333 static void flip_smm_bit(void *data) 4334 { 4335 unsigned long set = *(unsigned long *)data; 4336 4337 if (set > 0) { 4338 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 4339 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4340 } else { 4341 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 4342 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4343 } 4344 } 4345 4346 static bool init_hybrid_pmu(int cpu) 4347 { 4348 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4349 u8 cpu_type = get_this_hybrid_cpu_type(); 4350 struct x86_hybrid_pmu *pmu = NULL; 4351 int i; 4352 4353 if (!cpu_type && x86_pmu.get_hybrid_cpu_type) 4354 cpu_type = x86_pmu.get_hybrid_cpu_type(); 4355 4356 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 4357 if (x86_pmu.hybrid_pmu[i].cpu_type == cpu_type) { 4358 pmu = &x86_pmu.hybrid_pmu[i]; 4359 break; 4360 } 4361 } 4362 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { 4363 cpuc->pmu = NULL; 4364 return false; 4365 } 4366 4367 /* Only check and dump the PMU information for the first CPU */ 4368 if (!cpumask_empty(&pmu->supported_cpus)) 4369 goto end; 4370 4371 if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed)) 4372 return false; 4373 4374 pr_info("%s PMU driver: ", pmu->name); 4375 4376 if (pmu->intel_cap.pebs_output_pt_available) 4377 pr_cont("PEBS-via-PT "); 4378 4379 pr_cont("\n"); 4380 4381 x86_pmu_show_pmu_cap(pmu->num_counters, pmu->num_counters_fixed, 4382 pmu->intel_ctrl); 4383 4384 end: 4385 cpumask_set_cpu(cpu, &pmu->supported_cpus); 4386 cpuc->pmu = &pmu->pmu; 4387 4388 x86_pmu_update_cpu_context(&pmu->pmu, cpu); 4389 4390 return true; 4391 } 4392 4393 static void intel_pmu_cpu_starting(int cpu) 4394 { 4395 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4396 int core_id = topology_core_id(cpu); 4397 int i; 4398 4399 if (is_hybrid() && !init_hybrid_pmu(cpu)) 4400 return; 4401 4402 init_debug_store_on_cpu(cpu); 4403 /* 4404 * Deal with CPUs that don't clear their LBRs on power-up. 4405 */ 4406 intel_pmu_lbr_reset(); 4407 4408 cpuc->lbr_sel = NULL; 4409 4410 if (x86_pmu.flags & PMU_FL_TFA) { 4411 WARN_ON_ONCE(cpuc->tfa_shadow); 4412 cpuc->tfa_shadow = ~0ULL; 4413 intel_set_tfa(cpuc, false); 4414 } 4415 4416 if (x86_pmu.version > 1) 4417 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 4418 4419 /* 4420 * Disable perf metrics if any added CPU doesn't support it. 4421 * 4422 * Turn off the check for a hybrid architecture, because the 4423 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate 4424 * the architecture features. The perf metrics is a model-specific 4425 * feature for now. The corresponding bit should always be 0 on 4426 * a hybrid platform, e.g., Alder Lake. 4427 */ 4428 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 4429 union perf_capabilities perf_cap; 4430 4431 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 4432 if (!perf_cap.perf_metrics) { 4433 x86_pmu.intel_cap.perf_metrics = 0; 4434 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 4435 } 4436 } 4437 4438 if (!cpuc->shared_regs) 4439 return; 4440 4441 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 4442 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4443 struct intel_shared_regs *pc; 4444 4445 pc = per_cpu(cpu_hw_events, i).shared_regs; 4446 if (pc && pc->core_id == core_id) { 4447 cpuc->kfree_on_online[0] = cpuc->shared_regs; 4448 cpuc->shared_regs = pc; 4449 break; 4450 } 4451 } 4452 cpuc->shared_regs->core_id = core_id; 4453 cpuc->shared_regs->refcnt++; 4454 } 4455 4456 if (x86_pmu.lbr_sel_map) 4457 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 4458 4459 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4460 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4461 struct cpu_hw_events *sibling; 4462 struct intel_excl_cntrs *c; 4463 4464 sibling = &per_cpu(cpu_hw_events, i); 4465 c = sibling->excl_cntrs; 4466 if (c && c->core_id == core_id) { 4467 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 4468 cpuc->excl_cntrs = c; 4469 if (!sibling->excl_thread_id) 4470 cpuc->excl_thread_id = 1; 4471 break; 4472 } 4473 } 4474 cpuc->excl_cntrs->core_id = core_id; 4475 cpuc->excl_cntrs->refcnt++; 4476 } 4477 } 4478 4479 static void free_excl_cntrs(struct cpu_hw_events *cpuc) 4480 { 4481 struct intel_excl_cntrs *c; 4482 4483 c = cpuc->excl_cntrs; 4484 if (c) { 4485 if (c->core_id == -1 || --c->refcnt == 0) 4486 kfree(c); 4487 cpuc->excl_cntrs = NULL; 4488 } 4489 4490 kfree(cpuc->constraint_list); 4491 cpuc->constraint_list = NULL; 4492 } 4493 4494 static void intel_pmu_cpu_dying(int cpu) 4495 { 4496 fini_debug_store_on_cpu(cpu); 4497 } 4498 4499 void intel_cpuc_finish(struct cpu_hw_events *cpuc) 4500 { 4501 struct intel_shared_regs *pc; 4502 4503 pc = cpuc->shared_regs; 4504 if (pc) { 4505 if (pc->core_id == -1 || --pc->refcnt == 0) 4506 kfree(pc); 4507 cpuc->shared_regs = NULL; 4508 } 4509 4510 free_excl_cntrs(cpuc); 4511 } 4512 4513 static void intel_pmu_cpu_dead(int cpu) 4514 { 4515 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4516 4517 intel_cpuc_finish(cpuc); 4518 4519 if (is_hybrid() && cpuc->pmu) 4520 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); 4521 } 4522 4523 static void intel_pmu_sched_task(struct perf_event_context *ctx, 4524 bool sched_in) 4525 { 4526 intel_pmu_pebs_sched_task(ctx, sched_in); 4527 intel_pmu_lbr_sched_task(ctx, sched_in); 4528 } 4529 4530 static void intel_pmu_swap_task_ctx(struct perf_event_context *prev, 4531 struct perf_event_context *next) 4532 { 4533 intel_pmu_lbr_swap_task_ctx(prev, next); 4534 } 4535 4536 static int intel_pmu_check_period(struct perf_event *event, u64 value) 4537 { 4538 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 4539 } 4540 4541 static int intel_pmu_aux_output_match(struct perf_event *event) 4542 { 4543 if (!x86_pmu.intel_cap.pebs_output_pt_available) 4544 return 0; 4545 4546 return is_intel_pt_event(event); 4547 } 4548 4549 static int intel_pmu_filter_match(struct perf_event *event) 4550 { 4551 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4552 unsigned int cpu = smp_processor_id(); 4553 4554 return cpumask_test_cpu(cpu, &pmu->supported_cpus); 4555 } 4556 4557 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 4558 4559 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 4560 4561 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 4562 4563 static struct attribute *intel_arch3_formats_attr[] = { 4564 &format_attr_event.attr, 4565 &format_attr_umask.attr, 4566 &format_attr_edge.attr, 4567 &format_attr_pc.attr, 4568 &format_attr_any.attr, 4569 &format_attr_inv.attr, 4570 &format_attr_cmask.attr, 4571 NULL, 4572 }; 4573 4574 static struct attribute *hsw_format_attr[] = { 4575 &format_attr_in_tx.attr, 4576 &format_attr_in_tx_cp.attr, 4577 &format_attr_offcore_rsp.attr, 4578 &format_attr_ldlat.attr, 4579 NULL 4580 }; 4581 4582 static struct attribute *nhm_format_attr[] = { 4583 &format_attr_offcore_rsp.attr, 4584 &format_attr_ldlat.attr, 4585 NULL 4586 }; 4587 4588 static struct attribute *slm_format_attr[] = { 4589 &format_attr_offcore_rsp.attr, 4590 NULL 4591 }; 4592 4593 static struct attribute *skl_format_attr[] = { 4594 &format_attr_frontend.attr, 4595 NULL, 4596 }; 4597 4598 static __initconst const struct x86_pmu core_pmu = { 4599 .name = "core", 4600 .handle_irq = x86_pmu_handle_irq, 4601 .disable_all = x86_pmu_disable_all, 4602 .enable_all = core_pmu_enable_all, 4603 .enable = core_pmu_enable_event, 4604 .disable = x86_pmu_disable_event, 4605 .hw_config = core_pmu_hw_config, 4606 .schedule_events = x86_schedule_events, 4607 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4608 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4609 .event_map = intel_pmu_event_map, 4610 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4611 .apic = 1, 4612 .large_pebs_flags = LARGE_PEBS_FLAGS, 4613 4614 /* 4615 * Intel PMCs cannot be accessed sanely above 32-bit width, 4616 * so we install an artificial 1<<31 period regardless of 4617 * the generic event period: 4618 */ 4619 .max_period = (1ULL<<31) - 1, 4620 .get_event_constraints = intel_get_event_constraints, 4621 .put_event_constraints = intel_put_event_constraints, 4622 .event_constraints = intel_core_event_constraints, 4623 .guest_get_msrs = core_guest_get_msrs, 4624 .format_attrs = intel_arch_formats_attr, 4625 .events_sysfs_show = intel_event_sysfs_show, 4626 4627 /* 4628 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 4629 * together with PMU version 1 and thus be using core_pmu with 4630 * shared_regs. We need following callbacks here to allocate 4631 * it properly. 4632 */ 4633 .cpu_prepare = intel_pmu_cpu_prepare, 4634 .cpu_starting = intel_pmu_cpu_starting, 4635 .cpu_dying = intel_pmu_cpu_dying, 4636 .cpu_dead = intel_pmu_cpu_dead, 4637 4638 .check_period = intel_pmu_check_period, 4639 4640 .lbr_reset = intel_pmu_lbr_reset_64, 4641 .lbr_read = intel_pmu_lbr_read_64, 4642 .lbr_save = intel_pmu_lbr_save, 4643 .lbr_restore = intel_pmu_lbr_restore, 4644 }; 4645 4646 static __initconst const struct x86_pmu intel_pmu = { 4647 .name = "Intel", 4648 .handle_irq = intel_pmu_handle_irq, 4649 .disable_all = intel_pmu_disable_all, 4650 .enable_all = intel_pmu_enable_all, 4651 .enable = intel_pmu_enable_event, 4652 .disable = intel_pmu_disable_event, 4653 .add = intel_pmu_add_event, 4654 .del = intel_pmu_del_event, 4655 .read = intel_pmu_read_event, 4656 .hw_config = intel_pmu_hw_config, 4657 .schedule_events = x86_schedule_events, 4658 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4659 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4660 .event_map = intel_pmu_event_map, 4661 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4662 .apic = 1, 4663 .large_pebs_flags = LARGE_PEBS_FLAGS, 4664 /* 4665 * Intel PMCs cannot be accessed sanely above 32 bit width, 4666 * so we install an artificial 1<<31 period regardless of 4667 * the generic event period: 4668 */ 4669 .max_period = (1ULL << 31) - 1, 4670 .get_event_constraints = intel_get_event_constraints, 4671 .put_event_constraints = intel_put_event_constraints, 4672 .pebs_aliases = intel_pebs_aliases_core2, 4673 4674 .format_attrs = intel_arch3_formats_attr, 4675 .events_sysfs_show = intel_event_sysfs_show, 4676 4677 .cpu_prepare = intel_pmu_cpu_prepare, 4678 .cpu_starting = intel_pmu_cpu_starting, 4679 .cpu_dying = intel_pmu_cpu_dying, 4680 .cpu_dead = intel_pmu_cpu_dead, 4681 4682 .guest_get_msrs = intel_guest_get_msrs, 4683 .sched_task = intel_pmu_sched_task, 4684 .swap_task_ctx = intel_pmu_swap_task_ctx, 4685 4686 .check_period = intel_pmu_check_period, 4687 4688 .aux_output_match = intel_pmu_aux_output_match, 4689 4690 .lbr_reset = intel_pmu_lbr_reset_64, 4691 .lbr_read = intel_pmu_lbr_read_64, 4692 .lbr_save = intel_pmu_lbr_save, 4693 .lbr_restore = intel_pmu_lbr_restore, 4694 }; 4695 4696 static __init void intel_clovertown_quirk(void) 4697 { 4698 /* 4699 * PEBS is unreliable due to: 4700 * 4701 * AJ67 - PEBS may experience CPL leaks 4702 * AJ68 - PEBS PMI may be delayed by one event 4703 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 4704 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 4705 * 4706 * AJ67 could be worked around by restricting the OS/USR flags. 4707 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 4708 * 4709 * AJ106 could possibly be worked around by not allowing LBR 4710 * usage from PEBS, including the fixup. 4711 * AJ68 could possibly be worked around by always programming 4712 * a pebs_event_reset[0] value and coping with the lost events. 4713 * 4714 * But taken together it might just make sense to not enable PEBS on 4715 * these chips. 4716 */ 4717 pr_warn("PEBS disabled due to CPU errata\n"); 4718 x86_pmu.pebs = 0; 4719 x86_pmu.pebs_constraints = NULL; 4720 } 4721 4722 static const struct x86_cpu_desc isolation_ucodes[] = { 4723 INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f), 4724 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e), 4725 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015), 4726 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), 4727 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), 4728 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023), 4729 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014), 4730 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010), 4731 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009), 4732 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009), 4733 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002), 4734 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 1, 0x0b000014), 4735 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), 4736 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), 4737 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 5, 0x00000000), 4738 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 6, 0x00000000), 4739 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 7, 0x00000000), 4740 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c), 4741 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c), 4742 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e), 4743 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e), 4744 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e), 4745 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e), 4746 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e), 4747 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e), 4748 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e), 4749 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e), 4750 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e), 4751 {} 4752 }; 4753 4754 static void intel_check_pebs_isolation(void) 4755 { 4756 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 4757 } 4758 4759 static __init void intel_pebs_isolation_quirk(void) 4760 { 4761 WARN_ON_ONCE(x86_pmu.check_microcode); 4762 x86_pmu.check_microcode = intel_check_pebs_isolation; 4763 intel_check_pebs_isolation(); 4764 } 4765 4766 static const struct x86_cpu_desc pebs_ucodes[] = { 4767 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), 4768 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), 4769 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), 4770 {} 4771 }; 4772 4773 static bool intel_snb_pebs_broken(void) 4774 { 4775 return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 4776 } 4777 4778 static void intel_snb_check_microcode(void) 4779 { 4780 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 4781 return; 4782 4783 /* 4784 * Serialized by the microcode lock.. 4785 */ 4786 if (x86_pmu.pebs_broken) { 4787 pr_info("PEBS enabled due to microcode update\n"); 4788 x86_pmu.pebs_broken = 0; 4789 } else { 4790 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 4791 x86_pmu.pebs_broken = 1; 4792 } 4793 } 4794 4795 static bool is_lbr_from(unsigned long msr) 4796 { 4797 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 4798 4799 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 4800 } 4801 4802 /* 4803 * Under certain circumstances, access certain MSR may cause #GP. 4804 * The function tests if the input MSR can be safely accessed. 4805 */ 4806 static bool check_msr(unsigned long msr, u64 mask) 4807 { 4808 u64 val_old, val_new, val_tmp; 4809 4810 /* 4811 * Disable the check for real HW, so we don't 4812 * mess with potentially enabled registers: 4813 */ 4814 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 4815 return true; 4816 4817 /* 4818 * Read the current value, change it and read it back to see if it 4819 * matches, this is needed to detect certain hardware emulators 4820 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 4821 */ 4822 if (rdmsrl_safe(msr, &val_old)) 4823 return false; 4824 4825 /* 4826 * Only change the bits which can be updated by wrmsrl. 4827 */ 4828 val_tmp = val_old ^ mask; 4829 4830 if (is_lbr_from(msr)) 4831 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 4832 4833 if (wrmsrl_safe(msr, val_tmp) || 4834 rdmsrl_safe(msr, &val_new)) 4835 return false; 4836 4837 /* 4838 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 4839 * should equal rdmsrl()'s even with the quirk. 4840 */ 4841 if (val_new != val_tmp) 4842 return false; 4843 4844 if (is_lbr_from(msr)) 4845 val_old = lbr_from_signext_quirk_wr(val_old); 4846 4847 /* Here it's sure that the MSR can be safely accessed. 4848 * Restore the old value and return. 4849 */ 4850 wrmsrl(msr, val_old); 4851 4852 return true; 4853 } 4854 4855 static __init void intel_sandybridge_quirk(void) 4856 { 4857 x86_pmu.check_microcode = intel_snb_check_microcode; 4858 cpus_read_lock(); 4859 intel_snb_check_microcode(); 4860 cpus_read_unlock(); 4861 } 4862 4863 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 4864 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 4865 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 4866 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 4867 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 4868 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 4869 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 4870 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 4871 }; 4872 4873 static __init void intel_arch_events_quirk(void) 4874 { 4875 int bit; 4876 4877 /* disable event that reported as not present by cpuid */ 4878 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 4879 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 4880 pr_warn("CPUID marked event: \'%s\' unavailable\n", 4881 intel_arch_events_map[bit].name); 4882 } 4883 } 4884 4885 static __init void intel_nehalem_quirk(void) 4886 { 4887 union cpuid10_ebx ebx; 4888 4889 ebx.full = x86_pmu.events_maskl; 4890 if (ebx.split.no_branch_misses_retired) { 4891 /* 4892 * Erratum AAJ80 detected, we work it around by using 4893 * the BR_MISP_EXEC.ANY event. This will over-count 4894 * branch-misses, but it's still much better than the 4895 * architectural event which is often completely bogus: 4896 */ 4897 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 4898 ebx.split.no_branch_misses_retired = 0; 4899 x86_pmu.events_maskl = ebx.full; 4900 pr_info("CPU erratum AAJ80 worked around\n"); 4901 } 4902 } 4903 4904 /* 4905 * enable software workaround for errata: 4906 * SNB: BJ122 4907 * IVB: BV98 4908 * HSW: HSD29 4909 * 4910 * Only needed when HT is enabled. However detecting 4911 * if HT is enabled is difficult (model specific). So instead, 4912 * we enable the workaround in the early boot, and verify if 4913 * it is needed in a later initcall phase once we have valid 4914 * topology information to check if HT is actually enabled 4915 */ 4916 static __init void intel_ht_bug(void) 4917 { 4918 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 4919 4920 x86_pmu.start_scheduling = intel_start_scheduling; 4921 x86_pmu.commit_scheduling = intel_commit_scheduling; 4922 x86_pmu.stop_scheduling = intel_stop_scheduling; 4923 } 4924 4925 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 4926 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 4927 4928 /* Haswell special events */ 4929 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 4930 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 4931 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 4932 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 4933 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 4934 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 4935 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 4936 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 4937 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 4938 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 4939 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 4940 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 4941 4942 static struct attribute *hsw_events_attrs[] = { 4943 EVENT_PTR(td_slots_issued), 4944 EVENT_PTR(td_slots_retired), 4945 EVENT_PTR(td_fetch_bubbles), 4946 EVENT_PTR(td_total_slots), 4947 EVENT_PTR(td_total_slots_scale), 4948 EVENT_PTR(td_recovery_bubbles), 4949 EVENT_PTR(td_recovery_bubbles_scale), 4950 NULL 4951 }; 4952 4953 static struct attribute *hsw_mem_events_attrs[] = { 4954 EVENT_PTR(mem_ld_hsw), 4955 EVENT_PTR(mem_st_hsw), 4956 NULL, 4957 }; 4958 4959 static struct attribute *hsw_tsx_events_attrs[] = { 4960 EVENT_PTR(tx_start), 4961 EVENT_PTR(tx_commit), 4962 EVENT_PTR(tx_abort), 4963 EVENT_PTR(tx_capacity), 4964 EVENT_PTR(tx_conflict), 4965 EVENT_PTR(el_start), 4966 EVENT_PTR(el_commit), 4967 EVENT_PTR(el_abort), 4968 EVENT_PTR(el_capacity), 4969 EVENT_PTR(el_conflict), 4970 EVENT_PTR(cycles_t), 4971 EVENT_PTR(cycles_ct), 4972 NULL 4973 }; 4974 4975 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 4976 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 4977 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 4978 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 4979 4980 static struct attribute *icl_events_attrs[] = { 4981 EVENT_PTR(mem_ld_hsw), 4982 EVENT_PTR(mem_st_hsw), 4983 NULL, 4984 }; 4985 4986 static struct attribute *icl_td_events_attrs[] = { 4987 EVENT_PTR(slots), 4988 EVENT_PTR(td_retiring), 4989 EVENT_PTR(td_bad_spec), 4990 EVENT_PTR(td_fe_bound), 4991 EVENT_PTR(td_be_bound), 4992 NULL, 4993 }; 4994 4995 static struct attribute *icl_tsx_events_attrs[] = { 4996 EVENT_PTR(tx_start), 4997 EVENT_PTR(tx_abort), 4998 EVENT_PTR(tx_commit), 4999 EVENT_PTR(tx_capacity_read), 5000 EVENT_PTR(tx_capacity_write), 5001 EVENT_PTR(tx_conflict), 5002 EVENT_PTR(el_start), 5003 EVENT_PTR(el_abort), 5004 EVENT_PTR(el_commit), 5005 EVENT_PTR(el_capacity_read), 5006 EVENT_PTR(el_capacity_write), 5007 EVENT_PTR(el_conflict), 5008 EVENT_PTR(cycles_t), 5009 EVENT_PTR(cycles_ct), 5010 NULL, 5011 }; 5012 5013 5014 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 5015 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 5016 5017 static struct attribute *spr_events_attrs[] = { 5018 EVENT_PTR(mem_ld_hsw), 5019 EVENT_PTR(mem_st_spr), 5020 EVENT_PTR(mem_ld_aux), 5021 NULL, 5022 }; 5023 5024 static struct attribute *spr_td_events_attrs[] = { 5025 EVENT_PTR(slots), 5026 EVENT_PTR(td_retiring), 5027 EVENT_PTR(td_bad_spec), 5028 EVENT_PTR(td_fe_bound), 5029 EVENT_PTR(td_be_bound), 5030 EVENT_PTR(td_heavy_ops), 5031 EVENT_PTR(td_br_mispredict), 5032 EVENT_PTR(td_fetch_lat), 5033 EVENT_PTR(td_mem_bound), 5034 NULL, 5035 }; 5036 5037 static struct attribute *spr_tsx_events_attrs[] = { 5038 EVENT_PTR(tx_start), 5039 EVENT_PTR(tx_abort), 5040 EVENT_PTR(tx_commit), 5041 EVENT_PTR(tx_capacity_read), 5042 EVENT_PTR(tx_capacity_write), 5043 EVENT_PTR(tx_conflict), 5044 EVENT_PTR(cycles_t), 5045 EVENT_PTR(cycles_ct), 5046 NULL, 5047 }; 5048 5049 static ssize_t freeze_on_smi_show(struct device *cdev, 5050 struct device_attribute *attr, 5051 char *buf) 5052 { 5053 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 5054 } 5055 5056 static DEFINE_MUTEX(freeze_on_smi_mutex); 5057 5058 static ssize_t freeze_on_smi_store(struct device *cdev, 5059 struct device_attribute *attr, 5060 const char *buf, size_t count) 5061 { 5062 unsigned long val; 5063 ssize_t ret; 5064 5065 ret = kstrtoul(buf, 0, &val); 5066 if (ret) 5067 return ret; 5068 5069 if (val > 1) 5070 return -EINVAL; 5071 5072 mutex_lock(&freeze_on_smi_mutex); 5073 5074 if (x86_pmu.attr_freeze_on_smi == val) 5075 goto done; 5076 5077 x86_pmu.attr_freeze_on_smi = val; 5078 5079 cpus_read_lock(); 5080 on_each_cpu(flip_smm_bit, &val, 1); 5081 cpus_read_unlock(); 5082 done: 5083 mutex_unlock(&freeze_on_smi_mutex); 5084 5085 return count; 5086 } 5087 5088 static void update_tfa_sched(void *ignored) 5089 { 5090 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5091 5092 /* 5093 * check if PMC3 is used 5094 * and if so force schedule out for all event types all contexts 5095 */ 5096 if (test_bit(3, cpuc->active_mask)) 5097 perf_pmu_resched(x86_get_pmu(smp_processor_id())); 5098 } 5099 5100 static ssize_t show_sysctl_tfa(struct device *cdev, 5101 struct device_attribute *attr, 5102 char *buf) 5103 { 5104 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 5105 } 5106 5107 static ssize_t set_sysctl_tfa(struct device *cdev, 5108 struct device_attribute *attr, 5109 const char *buf, size_t count) 5110 { 5111 bool val; 5112 ssize_t ret; 5113 5114 ret = kstrtobool(buf, &val); 5115 if (ret) 5116 return ret; 5117 5118 /* no change */ 5119 if (val == allow_tsx_force_abort) 5120 return count; 5121 5122 allow_tsx_force_abort = val; 5123 5124 cpus_read_lock(); 5125 on_each_cpu(update_tfa_sched, NULL, 1); 5126 cpus_read_unlock(); 5127 5128 return count; 5129 } 5130 5131 5132 static DEVICE_ATTR_RW(freeze_on_smi); 5133 5134 static ssize_t branches_show(struct device *cdev, 5135 struct device_attribute *attr, 5136 char *buf) 5137 { 5138 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 5139 } 5140 5141 static DEVICE_ATTR_RO(branches); 5142 5143 static struct attribute *lbr_attrs[] = { 5144 &dev_attr_branches.attr, 5145 NULL 5146 }; 5147 5148 static char pmu_name_str[30]; 5149 5150 static ssize_t pmu_name_show(struct device *cdev, 5151 struct device_attribute *attr, 5152 char *buf) 5153 { 5154 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 5155 } 5156 5157 static DEVICE_ATTR_RO(pmu_name); 5158 5159 static struct attribute *intel_pmu_caps_attrs[] = { 5160 &dev_attr_pmu_name.attr, 5161 NULL 5162 }; 5163 5164 static DEVICE_ATTR(allow_tsx_force_abort, 0644, 5165 show_sysctl_tfa, 5166 set_sysctl_tfa); 5167 5168 static struct attribute *intel_pmu_attrs[] = { 5169 &dev_attr_freeze_on_smi.attr, 5170 &dev_attr_allow_tsx_force_abort.attr, 5171 NULL, 5172 }; 5173 5174 static umode_t 5175 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5176 { 5177 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 5178 } 5179 5180 static umode_t 5181 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5182 { 5183 return x86_pmu.pebs ? attr->mode : 0; 5184 } 5185 5186 static umode_t 5187 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5188 { 5189 return x86_pmu.lbr_nr ? attr->mode : 0; 5190 } 5191 5192 static umode_t 5193 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5194 { 5195 return x86_pmu.version >= 2 ? attr->mode : 0; 5196 } 5197 5198 static umode_t 5199 default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5200 { 5201 if (attr == &dev_attr_allow_tsx_force_abort.attr) 5202 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 5203 5204 return attr->mode; 5205 } 5206 5207 static struct attribute_group group_events_td = { 5208 .name = "events", 5209 }; 5210 5211 static struct attribute_group group_events_mem = { 5212 .name = "events", 5213 .is_visible = pebs_is_visible, 5214 }; 5215 5216 static struct attribute_group group_events_tsx = { 5217 .name = "events", 5218 .is_visible = tsx_is_visible, 5219 }; 5220 5221 static struct attribute_group group_caps_gen = { 5222 .name = "caps", 5223 .attrs = intel_pmu_caps_attrs, 5224 }; 5225 5226 static struct attribute_group group_caps_lbr = { 5227 .name = "caps", 5228 .attrs = lbr_attrs, 5229 .is_visible = lbr_is_visible, 5230 }; 5231 5232 static struct attribute_group group_format_extra = { 5233 .name = "format", 5234 .is_visible = exra_is_visible, 5235 }; 5236 5237 static struct attribute_group group_format_extra_skl = { 5238 .name = "format", 5239 .is_visible = exra_is_visible, 5240 }; 5241 5242 static struct attribute_group group_default = { 5243 .attrs = intel_pmu_attrs, 5244 .is_visible = default_is_visible, 5245 }; 5246 5247 static const struct attribute_group *attr_update[] = { 5248 &group_events_td, 5249 &group_events_mem, 5250 &group_events_tsx, 5251 &group_caps_gen, 5252 &group_caps_lbr, 5253 &group_format_extra, 5254 &group_format_extra_skl, 5255 &group_default, 5256 NULL, 5257 }; 5258 5259 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); 5260 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); 5261 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); 5262 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); 5263 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); 5264 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); 5265 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); 5266 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); 5267 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); 5268 5269 static struct attribute *adl_hybrid_events_attrs[] = { 5270 EVENT_PTR(slots_adl), 5271 EVENT_PTR(td_retiring_adl), 5272 EVENT_PTR(td_bad_spec_adl), 5273 EVENT_PTR(td_fe_bound_adl), 5274 EVENT_PTR(td_be_bound_adl), 5275 EVENT_PTR(td_heavy_ops_adl), 5276 EVENT_PTR(td_br_mis_adl), 5277 EVENT_PTR(td_fetch_lat_adl), 5278 EVENT_PTR(td_mem_bound_adl), 5279 NULL, 5280 }; 5281 5282 /* Must be in IDX order */ 5283 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); 5284 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); 5285 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); 5286 5287 static struct attribute *adl_hybrid_mem_attrs[] = { 5288 EVENT_PTR(mem_ld_adl), 5289 EVENT_PTR(mem_st_adl), 5290 EVENT_PTR(mem_ld_aux_adl), 5291 NULL, 5292 }; 5293 5294 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); 5295 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); 5296 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); 5297 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); 5298 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); 5299 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); 5300 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); 5301 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); 5302 5303 static struct attribute *adl_hybrid_tsx_attrs[] = { 5304 EVENT_PTR(tx_start_adl), 5305 EVENT_PTR(tx_abort_adl), 5306 EVENT_PTR(tx_commit_adl), 5307 EVENT_PTR(tx_capacity_read_adl), 5308 EVENT_PTR(tx_capacity_write_adl), 5309 EVENT_PTR(tx_conflict_adl), 5310 EVENT_PTR(cycles_t_adl), 5311 EVENT_PTR(cycles_ct_adl), 5312 NULL, 5313 }; 5314 5315 FORMAT_ATTR_HYBRID(in_tx, hybrid_big); 5316 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); 5317 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small); 5318 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small); 5319 FORMAT_ATTR_HYBRID(frontend, hybrid_big); 5320 5321 static struct attribute *adl_hybrid_extra_attr_rtm[] = { 5322 FORMAT_HYBRID_PTR(in_tx), 5323 FORMAT_HYBRID_PTR(in_tx_cp), 5324 FORMAT_HYBRID_PTR(offcore_rsp), 5325 FORMAT_HYBRID_PTR(ldlat), 5326 FORMAT_HYBRID_PTR(frontend), 5327 NULL, 5328 }; 5329 5330 static struct attribute *adl_hybrid_extra_attr[] = { 5331 FORMAT_HYBRID_PTR(offcore_rsp), 5332 FORMAT_HYBRID_PTR(ldlat), 5333 FORMAT_HYBRID_PTR(frontend), 5334 NULL, 5335 }; 5336 5337 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) 5338 { 5339 struct device *dev = kobj_to_dev(kobj); 5340 struct x86_hybrid_pmu *pmu = 5341 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5342 struct perf_pmu_events_hybrid_attr *pmu_attr = 5343 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); 5344 5345 return pmu->cpu_type & pmu_attr->pmu_type; 5346 } 5347 5348 static umode_t hybrid_events_is_visible(struct kobject *kobj, 5349 struct attribute *attr, int i) 5350 { 5351 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; 5352 } 5353 5354 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) 5355 { 5356 int cpu = cpumask_first(&pmu->supported_cpus); 5357 5358 return (cpu >= nr_cpu_ids) ? -1 : cpu; 5359 } 5360 5361 static umode_t hybrid_tsx_is_visible(struct kobject *kobj, 5362 struct attribute *attr, int i) 5363 { 5364 struct device *dev = kobj_to_dev(kobj); 5365 struct x86_hybrid_pmu *pmu = 5366 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5367 int cpu = hybrid_find_supported_cpu(pmu); 5368 5369 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; 5370 } 5371 5372 static umode_t hybrid_format_is_visible(struct kobject *kobj, 5373 struct attribute *attr, int i) 5374 { 5375 struct device *dev = kobj_to_dev(kobj); 5376 struct x86_hybrid_pmu *pmu = 5377 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5378 struct perf_pmu_format_hybrid_attr *pmu_attr = 5379 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); 5380 int cpu = hybrid_find_supported_cpu(pmu); 5381 5382 return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0; 5383 } 5384 5385 static struct attribute_group hybrid_group_events_td = { 5386 .name = "events", 5387 .is_visible = hybrid_events_is_visible, 5388 }; 5389 5390 static struct attribute_group hybrid_group_events_mem = { 5391 .name = "events", 5392 .is_visible = hybrid_events_is_visible, 5393 }; 5394 5395 static struct attribute_group hybrid_group_events_tsx = { 5396 .name = "events", 5397 .is_visible = hybrid_tsx_is_visible, 5398 }; 5399 5400 static struct attribute_group hybrid_group_format_extra = { 5401 .name = "format", 5402 .is_visible = hybrid_format_is_visible, 5403 }; 5404 5405 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, 5406 struct device_attribute *attr, 5407 char *buf) 5408 { 5409 struct x86_hybrid_pmu *pmu = 5410 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5411 5412 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus); 5413 } 5414 5415 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); 5416 static struct attribute *intel_hybrid_cpus_attrs[] = { 5417 &dev_attr_cpus.attr, 5418 NULL, 5419 }; 5420 5421 static struct attribute_group hybrid_group_cpus = { 5422 .attrs = intel_hybrid_cpus_attrs, 5423 }; 5424 5425 static const struct attribute_group *hybrid_attr_update[] = { 5426 &hybrid_group_events_td, 5427 &hybrid_group_events_mem, 5428 &hybrid_group_events_tsx, 5429 &group_caps_gen, 5430 &group_caps_lbr, 5431 &hybrid_group_format_extra, 5432 &group_default, 5433 &hybrid_group_cpus, 5434 NULL, 5435 }; 5436 5437 static struct attribute *empty_attrs; 5438 5439 static void intel_pmu_check_num_counters(int *num_counters, 5440 int *num_counters_fixed, 5441 u64 *intel_ctrl, u64 fixed_mask) 5442 { 5443 if (*num_counters > INTEL_PMC_MAX_GENERIC) { 5444 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5445 *num_counters, INTEL_PMC_MAX_GENERIC); 5446 *num_counters = INTEL_PMC_MAX_GENERIC; 5447 } 5448 *intel_ctrl = (1ULL << *num_counters) - 1; 5449 5450 if (*num_counters_fixed > INTEL_PMC_MAX_FIXED) { 5451 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5452 *num_counters_fixed, INTEL_PMC_MAX_FIXED); 5453 *num_counters_fixed = INTEL_PMC_MAX_FIXED; 5454 } 5455 5456 *intel_ctrl |= fixed_mask << INTEL_PMC_IDX_FIXED; 5457 } 5458 5459 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 5460 int num_counters, 5461 int num_counters_fixed, 5462 u64 intel_ctrl) 5463 { 5464 struct event_constraint *c; 5465 5466 if (!event_constraints) 5467 return; 5468 5469 /* 5470 * event on fixed counter2 (REF_CYCLES) only works on this 5471 * counter, so do not extend mask to generic counters 5472 */ 5473 for_each_event_constraint(c, event_constraints) { 5474 /* 5475 * Don't extend the topdown slots and metrics 5476 * events to the generic counters. 5477 */ 5478 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 5479 /* 5480 * Disable topdown slots and metrics events, 5481 * if slots event is not in CPUID. 5482 */ 5483 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) 5484 c->idxmsk64 = 0; 5485 c->weight = hweight64(c->idxmsk64); 5486 continue; 5487 } 5488 5489 if (c->cmask == FIXED_EVENT_FLAGS) { 5490 /* Disabled fixed counters which are not in CPUID */ 5491 c->idxmsk64 &= intel_ctrl; 5492 5493 if (c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) 5494 c->idxmsk64 |= (1ULL << num_counters) - 1; 5495 } 5496 c->idxmsk64 &= 5497 ~(~0ULL << (INTEL_PMC_IDX_FIXED + num_counters_fixed)); 5498 c->weight = hweight64(c->idxmsk64); 5499 } 5500 } 5501 5502 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) 5503 { 5504 struct extra_reg *er; 5505 5506 /* 5507 * Access extra MSR may cause #GP under certain circumstances. 5508 * E.g. KVM doesn't support offcore event 5509 * Check all extra_regs here. 5510 */ 5511 if (!extra_regs) 5512 return; 5513 5514 for (er = extra_regs; er->msr; er++) { 5515 er->extra_msr_access = check_msr(er->msr, 0x11UL); 5516 /* Disable LBR select mapping */ 5517 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 5518 x86_pmu.lbr_sel_map = NULL; 5519 } 5520 } 5521 5522 static void intel_pmu_check_hybrid_pmus(u64 fixed_mask) 5523 { 5524 struct x86_hybrid_pmu *pmu; 5525 int i; 5526 5527 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 5528 pmu = &x86_pmu.hybrid_pmu[i]; 5529 5530 intel_pmu_check_num_counters(&pmu->num_counters, 5531 &pmu->num_counters_fixed, 5532 &pmu->intel_ctrl, 5533 fixed_mask); 5534 5535 if (pmu->intel_cap.perf_metrics) { 5536 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 5537 pmu->intel_ctrl |= INTEL_PMC_MSK_FIXED_SLOTS; 5538 } 5539 5540 if (pmu->intel_cap.pebs_output_pt_available) 5541 pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT; 5542 5543 intel_pmu_check_event_constraints(pmu->event_constraints, 5544 pmu->num_counters, 5545 pmu->num_counters_fixed, 5546 pmu->intel_ctrl); 5547 5548 intel_pmu_check_extra_regs(pmu->extra_regs); 5549 } 5550 } 5551 5552 __init int intel_pmu_init(void) 5553 { 5554 struct attribute **extra_skl_attr = &empty_attrs; 5555 struct attribute **extra_attr = &empty_attrs; 5556 struct attribute **td_attr = &empty_attrs; 5557 struct attribute **mem_attr = &empty_attrs; 5558 struct attribute **tsx_attr = &empty_attrs; 5559 union cpuid10_edx edx; 5560 union cpuid10_eax eax; 5561 union cpuid10_ebx ebx; 5562 unsigned int fixed_mask; 5563 bool pmem = false; 5564 int version, i; 5565 char *name; 5566 struct x86_hybrid_pmu *pmu; 5567 5568 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 5569 switch (boot_cpu_data.x86) { 5570 case 0x6: 5571 return p6_pmu_init(); 5572 case 0xb: 5573 return knc_pmu_init(); 5574 case 0xf: 5575 return p4_pmu_init(); 5576 } 5577 return -ENODEV; 5578 } 5579 5580 /* 5581 * Check whether the Architectural PerfMon supports 5582 * Branch Misses Retired hw_event or not. 5583 */ 5584 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); 5585 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 5586 return -ENODEV; 5587 5588 version = eax.split.version_id; 5589 if (version < 2) 5590 x86_pmu = core_pmu; 5591 else 5592 x86_pmu = intel_pmu; 5593 5594 x86_pmu.version = version; 5595 x86_pmu.num_counters = eax.split.num_counters; 5596 x86_pmu.cntval_bits = eax.split.bit_width; 5597 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 5598 5599 x86_pmu.events_maskl = ebx.full; 5600 x86_pmu.events_mask_len = eax.split.mask_length; 5601 5602 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 5603 5604 /* 5605 * Quirk: v2 perfmon does not report fixed-purpose events, so 5606 * assume at least 3 events, when not running in a hypervisor: 5607 */ 5608 if (version > 1 && version < 5) { 5609 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 5610 5611 x86_pmu.num_counters_fixed = 5612 max((int)edx.split.num_counters_fixed, assume); 5613 5614 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1; 5615 } else if (version >= 5) 5616 x86_pmu.num_counters_fixed = fls(fixed_mask); 5617 5618 if (boot_cpu_has(X86_FEATURE_PDCM)) { 5619 u64 capabilities; 5620 5621 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 5622 x86_pmu.intel_cap.capabilities = capabilities; 5623 } 5624 5625 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 5626 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 5627 x86_pmu.lbr_read = intel_pmu_lbr_read_32; 5628 } 5629 5630 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 5631 intel_pmu_arch_lbr_init(); 5632 5633 intel_ds_init(); 5634 5635 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 5636 5637 if (version >= 5) { 5638 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 5639 if (x86_pmu.intel_cap.anythread_deprecated) 5640 pr_cont(" AnyThread deprecated, "); 5641 } 5642 5643 /* 5644 * Install the hw-cache-events table: 5645 */ 5646 switch (boot_cpu_data.x86_model) { 5647 case INTEL_FAM6_CORE_YONAH: 5648 pr_cont("Core events, "); 5649 name = "core"; 5650 break; 5651 5652 case INTEL_FAM6_CORE2_MEROM: 5653 x86_add_quirk(intel_clovertown_quirk); 5654 fallthrough; 5655 5656 case INTEL_FAM6_CORE2_MEROM_L: 5657 case INTEL_FAM6_CORE2_PENRYN: 5658 case INTEL_FAM6_CORE2_DUNNINGTON: 5659 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 5660 sizeof(hw_cache_event_ids)); 5661 5662 intel_pmu_lbr_init_core(); 5663 5664 x86_pmu.event_constraints = intel_core2_event_constraints; 5665 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 5666 pr_cont("Core2 events, "); 5667 name = "core2"; 5668 break; 5669 5670 case INTEL_FAM6_NEHALEM: 5671 case INTEL_FAM6_NEHALEM_EP: 5672 case INTEL_FAM6_NEHALEM_EX: 5673 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 5674 sizeof(hw_cache_event_ids)); 5675 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5676 sizeof(hw_cache_extra_regs)); 5677 5678 intel_pmu_lbr_init_nhm(); 5679 5680 x86_pmu.event_constraints = intel_nehalem_event_constraints; 5681 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 5682 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5683 x86_pmu.extra_regs = intel_nehalem_extra_regs; 5684 x86_pmu.limit_period = nhm_limit_period; 5685 5686 mem_attr = nhm_mem_events_attrs; 5687 5688 /* UOPS_ISSUED.STALLED_CYCLES */ 5689 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5690 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5691 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5692 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5693 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5694 5695 intel_pmu_pebs_data_source_nhm(); 5696 x86_add_quirk(intel_nehalem_quirk); 5697 x86_pmu.pebs_no_tlb = 1; 5698 extra_attr = nhm_format_attr; 5699 5700 pr_cont("Nehalem events, "); 5701 name = "nehalem"; 5702 break; 5703 5704 case INTEL_FAM6_ATOM_BONNELL: 5705 case INTEL_FAM6_ATOM_BONNELL_MID: 5706 case INTEL_FAM6_ATOM_SALTWELL: 5707 case INTEL_FAM6_ATOM_SALTWELL_MID: 5708 case INTEL_FAM6_ATOM_SALTWELL_TABLET: 5709 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 5710 sizeof(hw_cache_event_ids)); 5711 5712 intel_pmu_lbr_init_atom(); 5713 5714 x86_pmu.event_constraints = intel_gen_event_constraints; 5715 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 5716 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 5717 pr_cont("Atom events, "); 5718 name = "bonnell"; 5719 break; 5720 5721 case INTEL_FAM6_ATOM_SILVERMONT: 5722 case INTEL_FAM6_ATOM_SILVERMONT_D: 5723 case INTEL_FAM6_ATOM_SILVERMONT_MID: 5724 case INTEL_FAM6_ATOM_AIRMONT: 5725 case INTEL_FAM6_ATOM_AIRMONT_MID: 5726 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 5727 sizeof(hw_cache_event_ids)); 5728 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 5729 sizeof(hw_cache_extra_regs)); 5730 5731 intel_pmu_lbr_init_slm(); 5732 5733 x86_pmu.event_constraints = intel_slm_event_constraints; 5734 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 5735 x86_pmu.extra_regs = intel_slm_extra_regs; 5736 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5737 td_attr = slm_events_attrs; 5738 extra_attr = slm_format_attr; 5739 pr_cont("Silvermont events, "); 5740 name = "silvermont"; 5741 break; 5742 5743 case INTEL_FAM6_ATOM_GOLDMONT: 5744 case INTEL_FAM6_ATOM_GOLDMONT_D: 5745 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 5746 sizeof(hw_cache_event_ids)); 5747 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 5748 sizeof(hw_cache_extra_regs)); 5749 5750 intel_pmu_lbr_init_skl(); 5751 5752 x86_pmu.event_constraints = intel_slm_event_constraints; 5753 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 5754 x86_pmu.extra_regs = intel_glm_extra_regs; 5755 /* 5756 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5757 * for precise cycles. 5758 * :pp is identical to :ppp 5759 */ 5760 x86_pmu.pebs_aliases = NULL; 5761 x86_pmu.pebs_prec_dist = true; 5762 x86_pmu.lbr_pt_coexist = true; 5763 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5764 td_attr = glm_events_attrs; 5765 extra_attr = slm_format_attr; 5766 pr_cont("Goldmont events, "); 5767 name = "goldmont"; 5768 break; 5769 5770 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5771 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5772 sizeof(hw_cache_event_ids)); 5773 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 5774 sizeof(hw_cache_extra_regs)); 5775 5776 intel_pmu_lbr_init_skl(); 5777 5778 x86_pmu.event_constraints = intel_slm_event_constraints; 5779 x86_pmu.extra_regs = intel_glm_extra_regs; 5780 /* 5781 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5782 * for precise cycles. 5783 */ 5784 x86_pmu.pebs_aliases = NULL; 5785 x86_pmu.pebs_prec_dist = true; 5786 x86_pmu.lbr_pt_coexist = true; 5787 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5788 x86_pmu.flags |= PMU_FL_PEBS_ALL; 5789 x86_pmu.get_event_constraints = glp_get_event_constraints; 5790 td_attr = glm_events_attrs; 5791 /* Goldmont Plus has 4-wide pipeline */ 5792 event_attr_td_total_slots_scale_glm.event_str = "4"; 5793 extra_attr = slm_format_attr; 5794 pr_cont("Goldmont plus events, "); 5795 name = "goldmont_plus"; 5796 break; 5797 5798 case INTEL_FAM6_ATOM_TREMONT_D: 5799 case INTEL_FAM6_ATOM_TREMONT: 5800 case INTEL_FAM6_ATOM_TREMONT_L: 5801 x86_pmu.late_ack = true; 5802 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5803 sizeof(hw_cache_event_ids)); 5804 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 5805 sizeof(hw_cache_extra_regs)); 5806 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 5807 5808 intel_pmu_lbr_init_skl(); 5809 5810 x86_pmu.event_constraints = intel_slm_event_constraints; 5811 x86_pmu.extra_regs = intel_tnt_extra_regs; 5812 /* 5813 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5814 * for precise cycles. 5815 */ 5816 x86_pmu.pebs_aliases = NULL; 5817 x86_pmu.pebs_prec_dist = true; 5818 x86_pmu.lbr_pt_coexist = true; 5819 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5820 x86_pmu.get_event_constraints = tnt_get_event_constraints; 5821 td_attr = tnt_events_attrs; 5822 extra_attr = slm_format_attr; 5823 pr_cont("Tremont events, "); 5824 name = "Tremont"; 5825 break; 5826 5827 case INTEL_FAM6_WESTMERE: 5828 case INTEL_FAM6_WESTMERE_EP: 5829 case INTEL_FAM6_WESTMERE_EX: 5830 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 5831 sizeof(hw_cache_event_ids)); 5832 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5833 sizeof(hw_cache_extra_regs)); 5834 5835 intel_pmu_lbr_init_nhm(); 5836 5837 x86_pmu.event_constraints = intel_westmere_event_constraints; 5838 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5839 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 5840 x86_pmu.extra_regs = intel_westmere_extra_regs; 5841 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5842 5843 mem_attr = nhm_mem_events_attrs; 5844 5845 /* UOPS_ISSUED.STALLED_CYCLES */ 5846 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5847 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5848 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5849 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5850 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5851 5852 intel_pmu_pebs_data_source_nhm(); 5853 extra_attr = nhm_format_attr; 5854 pr_cont("Westmere events, "); 5855 name = "westmere"; 5856 break; 5857 5858 case INTEL_FAM6_SANDYBRIDGE: 5859 case INTEL_FAM6_SANDYBRIDGE_X: 5860 x86_add_quirk(intel_sandybridge_quirk); 5861 x86_add_quirk(intel_ht_bug); 5862 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5863 sizeof(hw_cache_event_ids)); 5864 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5865 sizeof(hw_cache_extra_regs)); 5866 5867 intel_pmu_lbr_init_snb(); 5868 5869 x86_pmu.event_constraints = intel_snb_event_constraints; 5870 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 5871 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 5872 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 5873 x86_pmu.extra_regs = intel_snbep_extra_regs; 5874 else 5875 x86_pmu.extra_regs = intel_snb_extra_regs; 5876 5877 5878 /* all extra regs are per-cpu when HT is on */ 5879 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5880 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5881 5882 td_attr = snb_events_attrs; 5883 mem_attr = snb_mem_events_attrs; 5884 5885 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5886 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5887 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5888 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 5889 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5890 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 5891 5892 extra_attr = nhm_format_attr; 5893 5894 pr_cont("SandyBridge events, "); 5895 name = "sandybridge"; 5896 break; 5897 5898 case INTEL_FAM6_IVYBRIDGE: 5899 case INTEL_FAM6_IVYBRIDGE_X: 5900 x86_add_quirk(intel_ht_bug); 5901 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5902 sizeof(hw_cache_event_ids)); 5903 /* dTLB-load-misses on IVB is different than SNB */ 5904 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 5905 5906 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5907 sizeof(hw_cache_extra_regs)); 5908 5909 intel_pmu_lbr_init_snb(); 5910 5911 x86_pmu.event_constraints = intel_ivb_event_constraints; 5912 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 5913 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5914 x86_pmu.pebs_prec_dist = true; 5915 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 5916 x86_pmu.extra_regs = intel_snbep_extra_regs; 5917 else 5918 x86_pmu.extra_regs = intel_snb_extra_regs; 5919 /* all extra regs are per-cpu when HT is on */ 5920 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5921 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5922 5923 td_attr = snb_events_attrs; 5924 mem_attr = snb_mem_events_attrs; 5925 5926 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5927 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5928 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5929 5930 extra_attr = nhm_format_attr; 5931 5932 pr_cont("IvyBridge events, "); 5933 name = "ivybridge"; 5934 break; 5935 5936 5937 case INTEL_FAM6_HASWELL: 5938 case INTEL_FAM6_HASWELL_X: 5939 case INTEL_FAM6_HASWELL_L: 5940 case INTEL_FAM6_HASWELL_G: 5941 x86_add_quirk(intel_ht_bug); 5942 x86_add_quirk(intel_pebs_isolation_quirk); 5943 x86_pmu.late_ack = true; 5944 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5945 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5946 5947 intel_pmu_lbr_init_hsw(); 5948 5949 x86_pmu.event_constraints = intel_hsw_event_constraints; 5950 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 5951 x86_pmu.extra_regs = intel_snbep_extra_regs; 5952 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5953 x86_pmu.pebs_prec_dist = true; 5954 /* all extra regs are per-cpu when HT is on */ 5955 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5956 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5957 5958 x86_pmu.hw_config = hsw_hw_config; 5959 x86_pmu.get_event_constraints = hsw_get_event_constraints; 5960 x86_pmu.lbr_double_abort = true; 5961 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5962 hsw_format_attr : nhm_format_attr; 5963 td_attr = hsw_events_attrs; 5964 mem_attr = hsw_mem_events_attrs; 5965 tsx_attr = hsw_tsx_events_attrs; 5966 pr_cont("Haswell events, "); 5967 name = "haswell"; 5968 break; 5969 5970 case INTEL_FAM6_BROADWELL: 5971 case INTEL_FAM6_BROADWELL_D: 5972 case INTEL_FAM6_BROADWELL_G: 5973 case INTEL_FAM6_BROADWELL_X: 5974 x86_add_quirk(intel_pebs_isolation_quirk); 5975 x86_pmu.late_ack = true; 5976 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5977 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5978 5979 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 5980 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 5981 BDW_L3_MISS|HSW_SNOOP_DRAM; 5982 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 5983 HSW_SNOOP_DRAM; 5984 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 5985 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 5986 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 5987 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 5988 5989 intel_pmu_lbr_init_hsw(); 5990 5991 x86_pmu.event_constraints = intel_bdw_event_constraints; 5992 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 5993 x86_pmu.extra_regs = intel_snbep_extra_regs; 5994 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5995 x86_pmu.pebs_prec_dist = true; 5996 /* all extra regs are per-cpu when HT is on */ 5997 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5998 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5999 6000 x86_pmu.hw_config = hsw_hw_config; 6001 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6002 x86_pmu.limit_period = bdw_limit_period; 6003 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6004 hsw_format_attr : nhm_format_attr; 6005 td_attr = hsw_events_attrs; 6006 mem_attr = hsw_mem_events_attrs; 6007 tsx_attr = hsw_tsx_events_attrs; 6008 pr_cont("Broadwell events, "); 6009 name = "broadwell"; 6010 break; 6011 6012 case INTEL_FAM6_XEON_PHI_KNL: 6013 case INTEL_FAM6_XEON_PHI_KNM: 6014 memcpy(hw_cache_event_ids, 6015 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6016 memcpy(hw_cache_extra_regs, 6017 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6018 intel_pmu_lbr_init_knl(); 6019 6020 x86_pmu.event_constraints = intel_slm_event_constraints; 6021 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 6022 x86_pmu.extra_regs = intel_knl_extra_regs; 6023 6024 /* all extra regs are per-cpu when HT is on */ 6025 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6026 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6027 extra_attr = slm_format_attr; 6028 pr_cont("Knights Landing/Mill events, "); 6029 name = "knights-landing"; 6030 break; 6031 6032 case INTEL_FAM6_SKYLAKE_X: 6033 pmem = true; 6034 fallthrough; 6035 case INTEL_FAM6_SKYLAKE_L: 6036 case INTEL_FAM6_SKYLAKE: 6037 case INTEL_FAM6_KABYLAKE_L: 6038 case INTEL_FAM6_KABYLAKE: 6039 case INTEL_FAM6_COMETLAKE_L: 6040 case INTEL_FAM6_COMETLAKE: 6041 x86_add_quirk(intel_pebs_isolation_quirk); 6042 x86_pmu.late_ack = true; 6043 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6044 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6045 intel_pmu_lbr_init_skl(); 6046 6047 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 6048 event_attr_td_recovery_bubbles.event_str_noht = 6049 "event=0xd,umask=0x1,cmask=1"; 6050 event_attr_td_recovery_bubbles.event_str_ht = 6051 "event=0xd,umask=0x1,cmask=1,any=1"; 6052 6053 x86_pmu.event_constraints = intel_skl_event_constraints; 6054 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 6055 x86_pmu.extra_regs = intel_skl_extra_regs; 6056 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 6057 x86_pmu.pebs_prec_dist = true; 6058 /* all extra regs are per-cpu when HT is on */ 6059 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6060 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6061 6062 x86_pmu.hw_config = hsw_hw_config; 6063 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6064 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6065 hsw_format_attr : nhm_format_attr; 6066 extra_skl_attr = skl_format_attr; 6067 td_attr = hsw_events_attrs; 6068 mem_attr = hsw_mem_events_attrs; 6069 tsx_attr = hsw_tsx_events_attrs; 6070 intel_pmu_pebs_data_source_skl(pmem); 6071 6072 /* 6073 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. 6074 * TSX force abort hooks are not required on these systems. Only deploy 6075 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. 6076 */ 6077 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && 6078 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { 6079 x86_pmu.flags |= PMU_FL_TFA; 6080 x86_pmu.get_event_constraints = tfa_get_event_constraints; 6081 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 6082 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 6083 } 6084 6085 pr_cont("Skylake events, "); 6086 name = "skylake"; 6087 break; 6088 6089 case INTEL_FAM6_ICELAKE_X: 6090 case INTEL_FAM6_ICELAKE_D: 6091 pmem = true; 6092 fallthrough; 6093 case INTEL_FAM6_ICELAKE_L: 6094 case INTEL_FAM6_ICELAKE: 6095 case INTEL_FAM6_TIGERLAKE_L: 6096 case INTEL_FAM6_TIGERLAKE: 6097 case INTEL_FAM6_ROCKETLAKE: 6098 x86_pmu.late_ack = true; 6099 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6100 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6101 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6102 intel_pmu_lbr_init_skl(); 6103 6104 x86_pmu.event_constraints = intel_icl_event_constraints; 6105 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 6106 x86_pmu.extra_regs = intel_icl_extra_regs; 6107 x86_pmu.pebs_aliases = NULL; 6108 x86_pmu.pebs_prec_dist = true; 6109 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6110 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6111 6112 x86_pmu.hw_config = hsw_hw_config; 6113 x86_pmu.get_event_constraints = icl_get_event_constraints; 6114 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6115 hsw_format_attr : nhm_format_attr; 6116 extra_skl_attr = skl_format_attr; 6117 mem_attr = icl_events_attrs; 6118 td_attr = icl_td_events_attrs; 6119 tsx_attr = icl_tsx_events_attrs; 6120 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6121 x86_pmu.lbr_pt_coexist = true; 6122 intel_pmu_pebs_data_source_skl(pmem); 6123 x86_pmu.num_topdown_events = 4; 6124 x86_pmu.update_topdown_event = icl_update_topdown_event; 6125 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 6126 pr_cont("Icelake events, "); 6127 name = "icelake"; 6128 break; 6129 6130 case INTEL_FAM6_SAPPHIRERAPIDS_X: 6131 pmem = true; 6132 x86_pmu.late_ack = true; 6133 memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6134 memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6135 6136 x86_pmu.event_constraints = intel_spr_event_constraints; 6137 x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints; 6138 x86_pmu.extra_regs = intel_spr_extra_regs; 6139 x86_pmu.limit_period = spr_limit_period; 6140 x86_pmu.pebs_aliases = NULL; 6141 x86_pmu.pebs_prec_dist = true; 6142 x86_pmu.pebs_block = true; 6143 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6144 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6145 x86_pmu.flags |= PMU_FL_PEBS_ALL; 6146 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6147 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 6148 6149 x86_pmu.hw_config = hsw_hw_config; 6150 x86_pmu.get_event_constraints = spr_get_event_constraints; 6151 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6152 hsw_format_attr : nhm_format_attr; 6153 extra_skl_attr = skl_format_attr; 6154 mem_attr = spr_events_attrs; 6155 td_attr = spr_td_events_attrs; 6156 tsx_attr = spr_tsx_events_attrs; 6157 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6158 x86_pmu.lbr_pt_coexist = true; 6159 intel_pmu_pebs_data_source_skl(pmem); 6160 x86_pmu.num_topdown_events = 8; 6161 x86_pmu.update_topdown_event = icl_update_topdown_event; 6162 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 6163 pr_cont("Sapphire Rapids events, "); 6164 name = "sapphire_rapids"; 6165 break; 6166 6167 case INTEL_FAM6_ALDERLAKE: 6168 case INTEL_FAM6_ALDERLAKE_L: 6169 /* 6170 * Alder Lake has 2 types of CPU, core and atom. 6171 * 6172 * Initialize the common PerfMon capabilities here. 6173 */ 6174 x86_pmu.hybrid_pmu = kcalloc(X86_HYBRID_NUM_PMUS, 6175 sizeof(struct x86_hybrid_pmu), 6176 GFP_KERNEL); 6177 if (!x86_pmu.hybrid_pmu) 6178 return -ENOMEM; 6179 static_branch_enable(&perf_is_hybrid); 6180 x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS; 6181 6182 x86_pmu.pebs_aliases = NULL; 6183 x86_pmu.pebs_prec_dist = true; 6184 x86_pmu.pebs_block = true; 6185 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6186 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6187 x86_pmu.flags |= PMU_FL_PEBS_ALL; 6188 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6189 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 6190 x86_pmu.lbr_pt_coexist = true; 6191 intel_pmu_pebs_data_source_skl(false); 6192 x86_pmu.num_topdown_events = 8; 6193 x86_pmu.update_topdown_event = adl_update_topdown_event; 6194 x86_pmu.set_topdown_event_period = adl_set_topdown_event_period; 6195 6196 x86_pmu.filter_match = intel_pmu_filter_match; 6197 x86_pmu.get_event_constraints = adl_get_event_constraints; 6198 x86_pmu.hw_config = adl_hw_config; 6199 x86_pmu.limit_period = spr_limit_period; 6200 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; 6201 /* 6202 * The rtm_abort_event is used to check whether to enable GPRs 6203 * for the RTM abort event. Atom doesn't have the RTM abort 6204 * event. There is no harmful to set it in the common 6205 * x86_pmu.rtm_abort_event. 6206 */ 6207 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6208 6209 td_attr = adl_hybrid_events_attrs; 6210 mem_attr = adl_hybrid_mem_attrs; 6211 tsx_attr = adl_hybrid_tsx_attrs; 6212 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6213 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; 6214 6215 /* Initialize big core specific PerfMon capabilities.*/ 6216 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 6217 pmu->name = "cpu_core"; 6218 pmu->cpu_type = hybrid_big; 6219 pmu->late_ack = true; 6220 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 6221 pmu->num_counters = x86_pmu.num_counters + 2; 6222 pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1; 6223 } else { 6224 pmu->num_counters = x86_pmu.num_counters; 6225 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6226 } 6227 pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters); 6228 pmu->unconstrained = (struct event_constraint) 6229 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6230 0, pmu->num_counters, 0, 0); 6231 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6232 pmu->intel_cap.perf_metrics = 1; 6233 pmu->intel_cap.pebs_output_pt_available = 0; 6234 6235 memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6236 memcpy(pmu->hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6237 pmu->event_constraints = intel_spr_event_constraints; 6238 pmu->pebs_constraints = intel_spr_pebs_event_constraints; 6239 pmu->extra_regs = intel_spr_extra_regs; 6240 6241 /* Initialize Atom core specific PerfMon capabilities.*/ 6242 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 6243 pmu->name = "cpu_atom"; 6244 pmu->cpu_type = hybrid_small; 6245 pmu->mid_ack = true; 6246 pmu->num_counters = x86_pmu.num_counters; 6247 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6248 pmu->max_pebs_events = x86_pmu.max_pebs_events; 6249 pmu->unconstrained = (struct event_constraint) 6250 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6251 0, pmu->num_counters, 0, 0); 6252 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6253 pmu->intel_cap.perf_metrics = 0; 6254 pmu->intel_cap.pebs_output_pt_available = 1; 6255 6256 memcpy(pmu->hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6257 memcpy(pmu->hw_cache_extra_regs, tnt_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6258 pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6259 pmu->event_constraints = intel_slm_event_constraints; 6260 pmu->pebs_constraints = intel_grt_pebs_event_constraints; 6261 pmu->extra_regs = intel_grt_extra_regs; 6262 pr_cont("Alderlake Hybrid events, "); 6263 name = "alderlake_hybrid"; 6264 break; 6265 6266 default: 6267 switch (x86_pmu.version) { 6268 case 1: 6269 x86_pmu.event_constraints = intel_v1_event_constraints; 6270 pr_cont("generic architected perfmon v1, "); 6271 name = "generic_arch_v1"; 6272 break; 6273 default: 6274 /* 6275 * default constraints for v2 and up 6276 */ 6277 x86_pmu.event_constraints = intel_gen_event_constraints; 6278 pr_cont("generic architected perfmon, "); 6279 name = "generic_arch_v2+"; 6280 break; 6281 } 6282 } 6283 6284 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 6285 6286 if (!is_hybrid()) { 6287 group_events_td.attrs = td_attr; 6288 group_events_mem.attrs = mem_attr; 6289 group_events_tsx.attrs = tsx_attr; 6290 group_format_extra.attrs = extra_attr; 6291 group_format_extra_skl.attrs = extra_skl_attr; 6292 6293 x86_pmu.attr_update = attr_update; 6294 } else { 6295 hybrid_group_events_td.attrs = td_attr; 6296 hybrid_group_events_mem.attrs = mem_attr; 6297 hybrid_group_events_tsx.attrs = tsx_attr; 6298 hybrid_group_format_extra.attrs = extra_attr; 6299 6300 x86_pmu.attr_update = hybrid_attr_update; 6301 } 6302 6303 intel_pmu_check_num_counters(&x86_pmu.num_counters, 6304 &x86_pmu.num_counters_fixed, 6305 &x86_pmu.intel_ctrl, 6306 (u64)fixed_mask); 6307 6308 /* AnyThread may be deprecated on arch perfmon v5 or later */ 6309 if (x86_pmu.intel_cap.anythread_deprecated) 6310 x86_pmu.format_attrs = intel_arch_formats_attr; 6311 6312 intel_pmu_check_event_constraints(x86_pmu.event_constraints, 6313 x86_pmu.num_counters, 6314 x86_pmu.num_counters_fixed, 6315 x86_pmu.intel_ctrl); 6316 /* 6317 * Access LBR MSR may cause #GP under certain circumstances. 6318 * E.g. KVM doesn't support LBR MSR 6319 * Check all LBT MSR here. 6320 * Disable LBR access if any LBR MSRs can not be accessed. 6321 */ 6322 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 6323 x86_pmu.lbr_nr = 0; 6324 for (i = 0; i < x86_pmu.lbr_nr; i++) { 6325 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 6326 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 6327 x86_pmu.lbr_nr = 0; 6328 } 6329 6330 if (x86_pmu.lbr_nr) { 6331 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 6332 6333 /* only support branch_stack snapshot for perfmon >= v2 */ 6334 if (x86_pmu.disable_all == intel_pmu_disable_all) { 6335 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) { 6336 static_call_update(perf_snapshot_branch_stack, 6337 intel_pmu_snapshot_arch_branch_stack); 6338 } else { 6339 static_call_update(perf_snapshot_branch_stack, 6340 intel_pmu_snapshot_branch_stack); 6341 } 6342 } 6343 } 6344 6345 intel_pmu_check_extra_regs(x86_pmu.extra_regs); 6346 6347 /* Support full width counters using alternative MSR range */ 6348 if (x86_pmu.intel_cap.full_width_write) { 6349 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 6350 x86_pmu.perfctr = MSR_IA32_PMC0; 6351 pr_cont("full-width counters, "); 6352 } 6353 6354 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 6355 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 6356 6357 if (is_hybrid()) 6358 intel_pmu_check_hybrid_pmus((u64)fixed_mask); 6359 6360 return 0; 6361 } 6362 6363 /* 6364 * HT bug: phase 2 init 6365 * Called once we have valid topology information to check 6366 * whether or not HT is enabled 6367 * If HT is off, then we disable the workaround 6368 */ 6369 static __init int fixup_ht_bug(void) 6370 { 6371 int c; 6372 /* 6373 * problem not present on this CPU model, nothing to do 6374 */ 6375 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 6376 return 0; 6377 6378 if (topology_max_smt_threads() > 1) { 6379 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 6380 return 0; 6381 } 6382 6383 cpus_read_lock(); 6384 6385 hardlockup_detector_perf_stop(); 6386 6387 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 6388 6389 x86_pmu.start_scheduling = NULL; 6390 x86_pmu.commit_scheduling = NULL; 6391 x86_pmu.stop_scheduling = NULL; 6392 6393 hardlockup_detector_perf_restart(); 6394 6395 for_each_online_cpu(c) 6396 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 6397 6398 cpus_read_unlock(); 6399 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 6400 return 0; 6401 } 6402 subsys_initcall(fixup_ht_bug) 6403