1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Per core/cpu state 4 * 5 * Used to coordinate shared registers between HT threads or 6 * among events on a single PMU. 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/stddef.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/export.h> 16 #include <linux/nmi.h> 17 #include <linux/kvm_host.h> 18 19 #include <asm/cpufeature.h> 20 #include <asm/debugreg.h> 21 #include <asm/hardirq.h> 22 #include <asm/intel-family.h> 23 #include <asm/intel_pt.h> 24 #include <asm/apic.h> 25 #include <asm/cpu_device_id.h> 26 #include <asm/msr.h> 27 28 #include "../perf_event.h" 29 30 /* 31 * Intel PerfMon, used on Core and later. 32 */ 33 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 34 { 35 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 36 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 37 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 38 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 39 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 40 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 41 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 42 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 43 }; 44 45 static struct event_constraint intel_core_event_constraints[] __read_mostly = 46 { 47 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 48 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 49 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 50 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 51 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 52 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 53 EVENT_CONSTRAINT_END 54 }; 55 56 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 57 { 58 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 59 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 60 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 61 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 62 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 63 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 64 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 65 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 66 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 67 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 68 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 69 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 70 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 71 EVENT_CONSTRAINT_END 72 }; 73 74 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 75 { 76 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 77 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 78 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 79 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 80 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 81 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 82 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 83 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 84 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 85 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 86 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 87 EVENT_CONSTRAINT_END 88 }; 89 90 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 91 { 92 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 93 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 94 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 95 EVENT_EXTRA_END 96 }; 97 98 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 99 { 100 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 101 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 102 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 103 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 104 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 105 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 106 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 107 EVENT_CONSTRAINT_END 108 }; 109 110 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 111 { 112 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 113 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 114 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 115 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 116 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 117 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 118 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 119 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 120 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 121 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 122 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 123 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 124 125 /* 126 * When HT is off these events can only run on the bottom 4 counters 127 * When HT is on, they are impacted by the HT bug and require EXCL access 128 */ 129 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 130 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 131 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 132 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 133 134 EVENT_CONSTRAINT_END 135 }; 136 137 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 138 { 139 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 140 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 141 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 142 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 143 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ 144 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 145 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 146 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 147 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 148 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 149 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 150 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 151 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 152 153 /* 154 * When HT is off these events can only run on the bottom 4 counters 155 * When HT is on, they are impacted by the HT bug and require EXCL access 156 */ 157 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 158 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 159 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 160 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 161 162 EVENT_CONSTRAINT_END 163 }; 164 165 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 166 { 167 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 168 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 169 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 170 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 171 EVENT_EXTRA_END 172 }; 173 174 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 175 { 176 EVENT_CONSTRAINT_END 177 }; 178 179 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 180 { 181 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 182 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 183 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 184 EVENT_CONSTRAINT_END 185 }; 186 187 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly = 188 { 189 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 190 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 191 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 192 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 193 FIXED_EVENT_CONSTRAINT(0x0500, 4), 194 FIXED_EVENT_CONSTRAINT(0x0600, 5), 195 FIXED_EVENT_CONSTRAINT(0x0700, 6), 196 FIXED_EVENT_CONSTRAINT(0x0800, 7), 197 FIXED_EVENT_CONSTRAINT(0x0900, 8), 198 FIXED_EVENT_CONSTRAINT(0x0a00, 9), 199 FIXED_EVENT_CONSTRAINT(0x0b00, 10), 200 FIXED_EVENT_CONSTRAINT(0x0c00, 11), 201 FIXED_EVENT_CONSTRAINT(0x0d00, 12), 202 FIXED_EVENT_CONSTRAINT(0x0e00, 13), 203 FIXED_EVENT_CONSTRAINT(0x0f00, 14), 204 FIXED_EVENT_CONSTRAINT(0x1000, 15), 205 EVENT_CONSTRAINT_END 206 }; 207 208 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 209 { 210 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 211 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 212 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 213 EVENT_CONSTRAINT_END 214 }; 215 216 static struct event_constraint intel_grt_event_constraints[] __read_mostly = { 217 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 218 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 219 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 220 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 221 EVENT_CONSTRAINT_END 222 }; 223 224 static struct event_constraint intel_skt_event_constraints[] __read_mostly = { 225 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 226 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 227 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 228 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 229 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */ 230 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */ 231 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */ 232 EVENT_CONSTRAINT_END 233 }; 234 235 static struct event_constraint intel_skl_event_constraints[] = { 236 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 237 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 238 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 239 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 240 241 /* 242 * when HT is off, these can only run on the bottom 4 counters 243 */ 244 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 245 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 246 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 247 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 248 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 249 250 EVENT_CONSTRAINT_END 251 }; 252 253 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 254 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 255 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 256 EVENT_EXTRA_END 257 }; 258 259 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 260 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 261 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 262 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 263 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 264 EVENT_EXTRA_END 265 }; 266 267 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 268 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 269 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 270 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 271 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 272 EVENT_EXTRA_END 273 }; 274 275 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 276 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 277 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 278 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 279 /* 280 * Note the low 8 bits eventsel code is not a continuous field, containing 281 * some #GPing bits. These are masked out. 282 */ 283 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 284 EVENT_EXTRA_END 285 }; 286 287 static struct event_constraint intel_icl_event_constraints[] = { 288 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 289 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ 290 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 291 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 292 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 293 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 294 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 295 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 296 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 297 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 298 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 299 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 300 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 301 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf), 302 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 303 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 304 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 305 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 306 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 307 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 308 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 309 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 310 INTEL_EVENT_CONSTRAINT(0xef, 0xf), 311 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 312 EVENT_CONSTRAINT_END 313 }; 314 315 static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 316 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 317 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 318 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 319 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 320 EVENT_EXTRA_END 321 }; 322 323 static struct extra_reg intel_glc_extra_regs[] __read_mostly = { 324 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 325 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 326 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 327 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 328 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 329 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 330 EVENT_EXTRA_END 331 }; 332 333 static struct event_constraint intel_glc_event_constraints[] = { 334 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 335 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 336 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 337 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 338 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 339 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 340 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 341 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 342 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 343 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 344 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 345 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 346 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 347 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 348 349 INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 350 INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 351 /* 352 * Generally event codes < 0x90 are restricted to counters 0-3. 353 * The 0x2E and 0x3C are exception, which has no restriction. 354 */ 355 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 356 357 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 358 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 359 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 360 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 361 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 362 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 363 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 364 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 365 /* 366 * Generally event codes >= 0x90 are likely to have no restrictions. 367 * The exception are defined as above. 368 */ 369 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 370 371 EVENT_CONSTRAINT_END 372 }; 373 374 static struct extra_reg intel_rwc_extra_regs[] __read_mostly = { 375 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 376 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 377 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 378 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 379 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 380 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 381 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 382 EVENT_EXTRA_END 383 }; 384 385 static struct event_constraint intel_lnc_event_constraints[] = { 386 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 387 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 388 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 389 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 390 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 391 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 392 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 393 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 394 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 395 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 396 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 397 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 398 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 399 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 400 401 INTEL_EVENT_CONSTRAINT(0x20, 0xf), 402 403 INTEL_UEVENT_CONSTRAINT(0x012a, 0xf), 404 INTEL_UEVENT_CONSTRAINT(0x012b, 0xf), 405 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), 406 INTEL_UEVENT_CONSTRAINT(0x0175, 0x4), 407 408 INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff), 409 INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff), 410 411 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 412 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 413 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 414 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 415 INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1), 416 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8), 417 INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc), 418 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3), 419 420 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 421 422 INTEL_UEVENT_CONSTRAINT(0x00e0, 0xf), 423 424 EVENT_CONSTRAINT_END 425 }; 426 427 static struct extra_reg intel_lnc_extra_regs[] __read_mostly = { 428 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0), 429 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1), 430 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 431 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 432 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 433 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE), 434 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 435 EVENT_EXTRA_END 436 }; 437 438 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 439 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 440 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 441 442 static struct attribute *nhm_mem_events_attrs[] = { 443 EVENT_PTR(mem_ld_nhm), 444 NULL, 445 }; 446 447 /* 448 * topdown events for Intel Core CPUs. 449 * 450 * The events are all in slots, which is a free slot in a 4 wide 451 * pipeline. Some events are already reported in slots, for cycle 452 * events we multiply by the pipeline width (4). 453 * 454 * With Hyper Threading on, topdown metrics are either summed or averaged 455 * between the threads of a core: (count_t0 + count_t1). 456 * 457 * For the average case the metric is always scaled to pipeline width, 458 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 459 */ 460 461 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 462 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 463 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 464 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 465 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 466 "event=0xe,umask=0x1"); /* uops_issued.any */ 467 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 468 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 469 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 470 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 471 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 472 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 473 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 474 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 475 "4", "2"); 476 477 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 478 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 479 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 480 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 481 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 482 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 483 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 484 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 485 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 486 487 static struct attribute *snb_events_attrs[] = { 488 EVENT_PTR(td_slots_issued), 489 EVENT_PTR(td_slots_retired), 490 EVENT_PTR(td_fetch_bubbles), 491 EVENT_PTR(td_total_slots), 492 EVENT_PTR(td_total_slots_scale), 493 EVENT_PTR(td_recovery_bubbles), 494 EVENT_PTR(td_recovery_bubbles_scale), 495 NULL, 496 }; 497 498 static struct attribute *snb_mem_events_attrs[] = { 499 EVENT_PTR(mem_ld_snb), 500 EVENT_PTR(mem_st_snb), 501 NULL, 502 }; 503 504 static struct event_constraint intel_hsw_event_constraints[] = { 505 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 506 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 507 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 508 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 509 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 510 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 511 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 512 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 513 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 514 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 515 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 516 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 517 518 /* 519 * When HT is off these events can only run on the bottom 4 counters 520 * When HT is on, they are impacted by the HT bug and require EXCL access 521 */ 522 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 523 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 524 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 525 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 526 527 EVENT_CONSTRAINT_END 528 }; 529 530 static struct event_constraint intel_bdw_event_constraints[] = { 531 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 532 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 533 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 534 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 535 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 536 /* 537 * when HT is off, these can only run on the bottom 4 counters 538 */ 539 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 540 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 541 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 542 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 543 EVENT_CONSTRAINT_END 544 }; 545 546 static u64 intel_pmu_event_map(int hw_event) 547 { 548 return intel_perfmon_event_map[hw_event]; 549 } 550 551 static __initconst const u64 glc_hw_cache_event_ids 552 [PERF_COUNT_HW_CACHE_MAX] 553 [PERF_COUNT_HW_CACHE_OP_MAX] 554 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 555 { 556 [ C(L1D ) ] = { 557 [ C(OP_READ) ] = { 558 [ C(RESULT_ACCESS) ] = 0x81d0, 559 [ C(RESULT_MISS) ] = 0xe124, 560 }, 561 [ C(OP_WRITE) ] = { 562 [ C(RESULT_ACCESS) ] = 0x82d0, 563 }, 564 }, 565 [ C(L1I ) ] = { 566 [ C(OP_READ) ] = { 567 [ C(RESULT_MISS) ] = 0xe424, 568 }, 569 [ C(OP_WRITE) ] = { 570 [ C(RESULT_ACCESS) ] = -1, 571 [ C(RESULT_MISS) ] = -1, 572 }, 573 }, 574 [ C(LL ) ] = { 575 [ C(OP_READ) ] = { 576 [ C(RESULT_ACCESS) ] = 0x12a, 577 [ C(RESULT_MISS) ] = 0x12a, 578 }, 579 [ C(OP_WRITE) ] = { 580 [ C(RESULT_ACCESS) ] = 0x12a, 581 [ C(RESULT_MISS) ] = 0x12a, 582 }, 583 }, 584 [ C(DTLB) ] = { 585 [ C(OP_READ) ] = { 586 [ C(RESULT_ACCESS) ] = 0x81d0, 587 [ C(RESULT_MISS) ] = 0xe12, 588 }, 589 [ C(OP_WRITE) ] = { 590 [ C(RESULT_ACCESS) ] = 0x82d0, 591 [ C(RESULT_MISS) ] = 0xe13, 592 }, 593 }, 594 [ C(ITLB) ] = { 595 [ C(OP_READ) ] = { 596 [ C(RESULT_ACCESS) ] = -1, 597 [ C(RESULT_MISS) ] = 0xe11, 598 }, 599 [ C(OP_WRITE) ] = { 600 [ C(RESULT_ACCESS) ] = -1, 601 [ C(RESULT_MISS) ] = -1, 602 }, 603 [ C(OP_PREFETCH) ] = { 604 [ C(RESULT_ACCESS) ] = -1, 605 [ C(RESULT_MISS) ] = -1, 606 }, 607 }, 608 [ C(BPU ) ] = { 609 [ C(OP_READ) ] = { 610 [ C(RESULT_ACCESS) ] = 0x4c4, 611 [ C(RESULT_MISS) ] = 0x4c5, 612 }, 613 [ C(OP_WRITE) ] = { 614 [ C(RESULT_ACCESS) ] = -1, 615 [ C(RESULT_MISS) ] = -1, 616 }, 617 [ C(OP_PREFETCH) ] = { 618 [ C(RESULT_ACCESS) ] = -1, 619 [ C(RESULT_MISS) ] = -1, 620 }, 621 }, 622 [ C(NODE) ] = { 623 [ C(OP_READ) ] = { 624 [ C(RESULT_ACCESS) ] = 0x12a, 625 [ C(RESULT_MISS) ] = 0x12a, 626 }, 627 }, 628 }; 629 630 static __initconst const u64 glc_hw_cache_extra_regs 631 [PERF_COUNT_HW_CACHE_MAX] 632 [PERF_COUNT_HW_CACHE_OP_MAX] 633 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 634 { 635 [ C(LL ) ] = { 636 [ C(OP_READ) ] = { 637 [ C(RESULT_ACCESS) ] = 0x10001, 638 [ C(RESULT_MISS) ] = 0x3fbfc00001, 639 }, 640 [ C(OP_WRITE) ] = { 641 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, 642 [ C(RESULT_MISS) ] = 0x3f3fc00002, 643 }, 644 }, 645 [ C(NODE) ] = { 646 [ C(OP_READ) ] = { 647 [ C(RESULT_ACCESS) ] = 0x10c000001, 648 [ C(RESULT_MISS) ] = 0x3fb3000001, 649 }, 650 }, 651 }; 652 653 /* 654 * Notes on the events: 655 * - data reads do not include code reads (comparable to earlier tables) 656 * - data counts include speculative execution (except L1 write, dtlb, bpu) 657 * - remote node access includes remote memory, remote cache, remote mmio. 658 * - prefetches are not included in the counts. 659 * - icache miss does not include decoded icache 660 */ 661 662 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 663 #define SKL_DEMAND_RFO BIT_ULL(1) 664 #define SKL_ANY_RESPONSE BIT_ULL(16) 665 #define SKL_SUPPLIER_NONE BIT_ULL(17) 666 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 667 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 668 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 669 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 670 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 671 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 672 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 673 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 674 #define SKL_SPL_HIT BIT_ULL(30) 675 #define SKL_SNOOP_NONE BIT_ULL(31) 676 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 677 #define SKL_SNOOP_MISS BIT_ULL(33) 678 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 679 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 680 #define SKL_SNOOP_HITM BIT_ULL(36) 681 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 682 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 683 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 684 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 685 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 686 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 687 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 688 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 689 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 690 SKL_SNOOP_HITM|SKL_SPL_HIT) 691 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 692 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 693 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 694 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 695 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 696 697 static __initconst const u64 skl_hw_cache_event_ids 698 [PERF_COUNT_HW_CACHE_MAX] 699 [PERF_COUNT_HW_CACHE_OP_MAX] 700 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 701 { 702 [ C(L1D ) ] = { 703 [ C(OP_READ) ] = { 704 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 705 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 706 }, 707 [ C(OP_WRITE) ] = { 708 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 709 [ C(RESULT_MISS) ] = 0x0, 710 }, 711 [ C(OP_PREFETCH) ] = { 712 [ C(RESULT_ACCESS) ] = 0x0, 713 [ C(RESULT_MISS) ] = 0x0, 714 }, 715 }, 716 [ C(L1I ) ] = { 717 [ C(OP_READ) ] = { 718 [ C(RESULT_ACCESS) ] = 0x0, 719 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 720 }, 721 [ C(OP_WRITE) ] = { 722 [ C(RESULT_ACCESS) ] = -1, 723 [ C(RESULT_MISS) ] = -1, 724 }, 725 [ C(OP_PREFETCH) ] = { 726 [ C(RESULT_ACCESS) ] = 0x0, 727 [ C(RESULT_MISS) ] = 0x0, 728 }, 729 }, 730 [ C(LL ) ] = { 731 [ C(OP_READ) ] = { 732 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 733 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 734 }, 735 [ C(OP_WRITE) ] = { 736 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 737 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 738 }, 739 [ C(OP_PREFETCH) ] = { 740 [ C(RESULT_ACCESS) ] = 0x0, 741 [ C(RESULT_MISS) ] = 0x0, 742 }, 743 }, 744 [ C(DTLB) ] = { 745 [ C(OP_READ) ] = { 746 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 747 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 748 }, 749 [ C(OP_WRITE) ] = { 750 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 751 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 752 }, 753 [ C(OP_PREFETCH) ] = { 754 [ C(RESULT_ACCESS) ] = 0x0, 755 [ C(RESULT_MISS) ] = 0x0, 756 }, 757 }, 758 [ C(ITLB) ] = { 759 [ C(OP_READ) ] = { 760 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 761 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 762 }, 763 [ C(OP_WRITE) ] = { 764 [ C(RESULT_ACCESS) ] = -1, 765 [ C(RESULT_MISS) ] = -1, 766 }, 767 [ C(OP_PREFETCH) ] = { 768 [ C(RESULT_ACCESS) ] = -1, 769 [ C(RESULT_MISS) ] = -1, 770 }, 771 }, 772 [ C(BPU ) ] = { 773 [ C(OP_READ) ] = { 774 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 775 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 776 }, 777 [ C(OP_WRITE) ] = { 778 [ C(RESULT_ACCESS) ] = -1, 779 [ C(RESULT_MISS) ] = -1, 780 }, 781 [ C(OP_PREFETCH) ] = { 782 [ C(RESULT_ACCESS) ] = -1, 783 [ C(RESULT_MISS) ] = -1, 784 }, 785 }, 786 [ C(NODE) ] = { 787 [ C(OP_READ) ] = { 788 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 789 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 790 }, 791 [ C(OP_WRITE) ] = { 792 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 793 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 794 }, 795 [ C(OP_PREFETCH) ] = { 796 [ C(RESULT_ACCESS) ] = 0x0, 797 [ C(RESULT_MISS) ] = 0x0, 798 }, 799 }, 800 }; 801 802 static __initconst const u64 skl_hw_cache_extra_regs 803 [PERF_COUNT_HW_CACHE_MAX] 804 [PERF_COUNT_HW_CACHE_OP_MAX] 805 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 806 { 807 [ C(LL ) ] = { 808 [ C(OP_READ) ] = { 809 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 810 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 811 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 812 SKL_L3_MISS|SKL_ANY_SNOOP| 813 SKL_SUPPLIER_NONE, 814 }, 815 [ C(OP_WRITE) ] = { 816 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 817 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 818 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 819 SKL_L3_MISS|SKL_ANY_SNOOP| 820 SKL_SUPPLIER_NONE, 821 }, 822 [ C(OP_PREFETCH) ] = { 823 [ C(RESULT_ACCESS) ] = 0x0, 824 [ C(RESULT_MISS) ] = 0x0, 825 }, 826 }, 827 [ C(NODE) ] = { 828 [ C(OP_READ) ] = { 829 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 830 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 831 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 832 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 833 }, 834 [ C(OP_WRITE) ] = { 835 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 836 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 837 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 838 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 839 }, 840 [ C(OP_PREFETCH) ] = { 841 [ C(RESULT_ACCESS) ] = 0x0, 842 [ C(RESULT_MISS) ] = 0x0, 843 }, 844 }, 845 }; 846 847 #define SNB_DMND_DATA_RD (1ULL << 0) 848 #define SNB_DMND_RFO (1ULL << 1) 849 #define SNB_DMND_IFETCH (1ULL << 2) 850 #define SNB_DMND_WB (1ULL << 3) 851 #define SNB_PF_DATA_RD (1ULL << 4) 852 #define SNB_PF_RFO (1ULL << 5) 853 #define SNB_PF_IFETCH (1ULL << 6) 854 #define SNB_LLC_DATA_RD (1ULL << 7) 855 #define SNB_LLC_RFO (1ULL << 8) 856 #define SNB_LLC_IFETCH (1ULL << 9) 857 #define SNB_BUS_LOCKS (1ULL << 10) 858 #define SNB_STRM_ST (1ULL << 11) 859 #define SNB_OTHER (1ULL << 15) 860 #define SNB_RESP_ANY (1ULL << 16) 861 #define SNB_NO_SUPP (1ULL << 17) 862 #define SNB_LLC_HITM (1ULL << 18) 863 #define SNB_LLC_HITE (1ULL << 19) 864 #define SNB_LLC_HITS (1ULL << 20) 865 #define SNB_LLC_HITF (1ULL << 21) 866 #define SNB_LOCAL (1ULL << 22) 867 #define SNB_REMOTE (0xffULL << 23) 868 #define SNB_SNP_NONE (1ULL << 31) 869 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 870 #define SNB_SNP_MISS (1ULL << 33) 871 #define SNB_NO_FWD (1ULL << 34) 872 #define SNB_SNP_FWD (1ULL << 35) 873 #define SNB_HITM (1ULL << 36) 874 #define SNB_NON_DRAM (1ULL << 37) 875 876 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 877 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 878 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 879 880 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 881 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 882 SNB_HITM) 883 884 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 885 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 886 887 #define SNB_L3_ACCESS SNB_RESP_ANY 888 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 889 890 static __initconst const u64 snb_hw_cache_extra_regs 891 [PERF_COUNT_HW_CACHE_MAX] 892 [PERF_COUNT_HW_CACHE_OP_MAX] 893 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 894 { 895 [ C(LL ) ] = { 896 [ C(OP_READ) ] = { 897 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 898 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 899 }, 900 [ C(OP_WRITE) ] = { 901 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 902 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 903 }, 904 [ C(OP_PREFETCH) ] = { 905 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 906 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 907 }, 908 }, 909 [ C(NODE) ] = { 910 [ C(OP_READ) ] = { 911 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 912 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 913 }, 914 [ C(OP_WRITE) ] = { 915 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 916 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 917 }, 918 [ C(OP_PREFETCH) ] = { 919 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 920 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 921 }, 922 }, 923 }; 924 925 static __initconst const u64 snb_hw_cache_event_ids 926 [PERF_COUNT_HW_CACHE_MAX] 927 [PERF_COUNT_HW_CACHE_OP_MAX] 928 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 929 { 930 [ C(L1D) ] = { 931 [ C(OP_READ) ] = { 932 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 933 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 934 }, 935 [ C(OP_WRITE) ] = { 936 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 937 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 938 }, 939 [ C(OP_PREFETCH) ] = { 940 [ C(RESULT_ACCESS) ] = 0x0, 941 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 942 }, 943 }, 944 [ C(L1I ) ] = { 945 [ C(OP_READ) ] = { 946 [ C(RESULT_ACCESS) ] = 0x0, 947 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 948 }, 949 [ C(OP_WRITE) ] = { 950 [ C(RESULT_ACCESS) ] = -1, 951 [ C(RESULT_MISS) ] = -1, 952 }, 953 [ C(OP_PREFETCH) ] = { 954 [ C(RESULT_ACCESS) ] = 0x0, 955 [ C(RESULT_MISS) ] = 0x0, 956 }, 957 }, 958 [ C(LL ) ] = { 959 [ C(OP_READ) ] = { 960 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 961 [ C(RESULT_ACCESS) ] = 0x01b7, 962 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 963 [ C(RESULT_MISS) ] = 0x01b7, 964 }, 965 [ C(OP_WRITE) ] = { 966 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 967 [ C(RESULT_ACCESS) ] = 0x01b7, 968 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 969 [ C(RESULT_MISS) ] = 0x01b7, 970 }, 971 [ C(OP_PREFETCH) ] = { 972 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 973 [ C(RESULT_ACCESS) ] = 0x01b7, 974 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 975 [ C(RESULT_MISS) ] = 0x01b7, 976 }, 977 }, 978 [ C(DTLB) ] = { 979 [ C(OP_READ) ] = { 980 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 981 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 982 }, 983 [ C(OP_WRITE) ] = { 984 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 985 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 986 }, 987 [ C(OP_PREFETCH) ] = { 988 [ C(RESULT_ACCESS) ] = 0x0, 989 [ C(RESULT_MISS) ] = 0x0, 990 }, 991 }, 992 [ C(ITLB) ] = { 993 [ C(OP_READ) ] = { 994 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 995 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 996 }, 997 [ C(OP_WRITE) ] = { 998 [ C(RESULT_ACCESS) ] = -1, 999 [ C(RESULT_MISS) ] = -1, 1000 }, 1001 [ C(OP_PREFETCH) ] = { 1002 [ C(RESULT_ACCESS) ] = -1, 1003 [ C(RESULT_MISS) ] = -1, 1004 }, 1005 }, 1006 [ C(BPU ) ] = { 1007 [ C(OP_READ) ] = { 1008 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1009 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1010 }, 1011 [ C(OP_WRITE) ] = { 1012 [ C(RESULT_ACCESS) ] = -1, 1013 [ C(RESULT_MISS) ] = -1, 1014 }, 1015 [ C(OP_PREFETCH) ] = { 1016 [ C(RESULT_ACCESS) ] = -1, 1017 [ C(RESULT_MISS) ] = -1, 1018 }, 1019 }, 1020 [ C(NODE) ] = { 1021 [ C(OP_READ) ] = { 1022 [ C(RESULT_ACCESS) ] = 0x01b7, 1023 [ C(RESULT_MISS) ] = 0x01b7, 1024 }, 1025 [ C(OP_WRITE) ] = { 1026 [ C(RESULT_ACCESS) ] = 0x01b7, 1027 [ C(RESULT_MISS) ] = 0x01b7, 1028 }, 1029 [ C(OP_PREFETCH) ] = { 1030 [ C(RESULT_ACCESS) ] = 0x01b7, 1031 [ C(RESULT_MISS) ] = 0x01b7, 1032 }, 1033 }, 1034 1035 }; 1036 1037 /* 1038 * Notes on the events: 1039 * - data reads do not include code reads (comparable to earlier tables) 1040 * - data counts include speculative execution (except L1 write, dtlb, bpu) 1041 * - remote node access includes remote memory, remote cache, remote mmio. 1042 * - prefetches are not included in the counts because they are not 1043 * reliably counted. 1044 */ 1045 1046 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 1047 #define HSW_DEMAND_RFO BIT_ULL(1) 1048 #define HSW_ANY_RESPONSE BIT_ULL(16) 1049 #define HSW_SUPPLIER_NONE BIT_ULL(17) 1050 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 1051 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 1052 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 1053 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 1054 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 1055 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 1056 HSW_L3_MISS_REMOTE_HOP2P) 1057 #define HSW_SNOOP_NONE BIT_ULL(31) 1058 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 1059 #define HSW_SNOOP_MISS BIT_ULL(33) 1060 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 1061 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 1062 #define HSW_SNOOP_HITM BIT_ULL(36) 1063 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 1064 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 1065 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 1066 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 1067 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 1068 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 1069 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 1070 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 1071 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 1072 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 1073 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 1074 1075 #define BDW_L3_MISS_LOCAL BIT(26) 1076 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 1077 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 1078 HSW_L3_MISS_REMOTE_HOP2P) 1079 1080 1081 static __initconst const u64 hsw_hw_cache_event_ids 1082 [PERF_COUNT_HW_CACHE_MAX] 1083 [PERF_COUNT_HW_CACHE_OP_MAX] 1084 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1085 { 1086 [ C(L1D ) ] = { 1087 [ C(OP_READ) ] = { 1088 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1089 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 1090 }, 1091 [ C(OP_WRITE) ] = { 1092 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1093 [ C(RESULT_MISS) ] = 0x0, 1094 }, 1095 [ C(OP_PREFETCH) ] = { 1096 [ C(RESULT_ACCESS) ] = 0x0, 1097 [ C(RESULT_MISS) ] = 0x0, 1098 }, 1099 }, 1100 [ C(L1I ) ] = { 1101 [ C(OP_READ) ] = { 1102 [ C(RESULT_ACCESS) ] = 0x0, 1103 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 1104 }, 1105 [ C(OP_WRITE) ] = { 1106 [ C(RESULT_ACCESS) ] = -1, 1107 [ C(RESULT_MISS) ] = -1, 1108 }, 1109 [ C(OP_PREFETCH) ] = { 1110 [ C(RESULT_ACCESS) ] = 0x0, 1111 [ C(RESULT_MISS) ] = 0x0, 1112 }, 1113 }, 1114 [ C(LL ) ] = { 1115 [ C(OP_READ) ] = { 1116 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1117 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1118 }, 1119 [ C(OP_WRITE) ] = { 1120 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1121 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1122 }, 1123 [ C(OP_PREFETCH) ] = { 1124 [ C(RESULT_ACCESS) ] = 0x0, 1125 [ C(RESULT_MISS) ] = 0x0, 1126 }, 1127 }, 1128 [ C(DTLB) ] = { 1129 [ C(OP_READ) ] = { 1130 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1131 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1132 }, 1133 [ C(OP_WRITE) ] = { 1134 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1135 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1136 }, 1137 [ C(OP_PREFETCH) ] = { 1138 [ C(RESULT_ACCESS) ] = 0x0, 1139 [ C(RESULT_MISS) ] = 0x0, 1140 }, 1141 }, 1142 [ C(ITLB) ] = { 1143 [ C(OP_READ) ] = { 1144 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1145 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1146 }, 1147 [ C(OP_WRITE) ] = { 1148 [ C(RESULT_ACCESS) ] = -1, 1149 [ C(RESULT_MISS) ] = -1, 1150 }, 1151 [ C(OP_PREFETCH) ] = { 1152 [ C(RESULT_ACCESS) ] = -1, 1153 [ C(RESULT_MISS) ] = -1, 1154 }, 1155 }, 1156 [ C(BPU ) ] = { 1157 [ C(OP_READ) ] = { 1158 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1159 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1160 }, 1161 [ C(OP_WRITE) ] = { 1162 [ C(RESULT_ACCESS) ] = -1, 1163 [ C(RESULT_MISS) ] = -1, 1164 }, 1165 [ C(OP_PREFETCH) ] = { 1166 [ C(RESULT_ACCESS) ] = -1, 1167 [ C(RESULT_MISS) ] = -1, 1168 }, 1169 }, 1170 [ C(NODE) ] = { 1171 [ C(OP_READ) ] = { 1172 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1173 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1174 }, 1175 [ C(OP_WRITE) ] = { 1176 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1177 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1178 }, 1179 [ C(OP_PREFETCH) ] = { 1180 [ C(RESULT_ACCESS) ] = 0x0, 1181 [ C(RESULT_MISS) ] = 0x0, 1182 }, 1183 }, 1184 }; 1185 1186 static __initconst const u64 hsw_hw_cache_extra_regs 1187 [PERF_COUNT_HW_CACHE_MAX] 1188 [PERF_COUNT_HW_CACHE_OP_MAX] 1189 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1190 { 1191 [ C(LL ) ] = { 1192 [ C(OP_READ) ] = { 1193 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1194 HSW_LLC_ACCESS, 1195 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1196 HSW_L3_MISS|HSW_ANY_SNOOP, 1197 }, 1198 [ C(OP_WRITE) ] = { 1199 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1200 HSW_LLC_ACCESS, 1201 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1202 HSW_L3_MISS|HSW_ANY_SNOOP, 1203 }, 1204 [ C(OP_PREFETCH) ] = { 1205 [ C(RESULT_ACCESS) ] = 0x0, 1206 [ C(RESULT_MISS) ] = 0x0, 1207 }, 1208 }, 1209 [ C(NODE) ] = { 1210 [ C(OP_READ) ] = { 1211 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1212 HSW_L3_MISS_LOCAL_DRAM| 1213 HSW_SNOOP_DRAM, 1214 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1215 HSW_L3_MISS_REMOTE| 1216 HSW_SNOOP_DRAM, 1217 }, 1218 [ C(OP_WRITE) ] = { 1219 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1220 HSW_L3_MISS_LOCAL_DRAM| 1221 HSW_SNOOP_DRAM, 1222 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1223 HSW_L3_MISS_REMOTE| 1224 HSW_SNOOP_DRAM, 1225 }, 1226 [ C(OP_PREFETCH) ] = { 1227 [ C(RESULT_ACCESS) ] = 0x0, 1228 [ C(RESULT_MISS) ] = 0x0, 1229 }, 1230 }, 1231 }; 1232 1233 static __initconst const u64 westmere_hw_cache_event_ids 1234 [PERF_COUNT_HW_CACHE_MAX] 1235 [PERF_COUNT_HW_CACHE_OP_MAX] 1236 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1237 { 1238 [ C(L1D) ] = { 1239 [ C(OP_READ) ] = { 1240 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1241 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1242 }, 1243 [ C(OP_WRITE) ] = { 1244 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1245 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1246 }, 1247 [ C(OP_PREFETCH) ] = { 1248 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1249 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1250 }, 1251 }, 1252 [ C(L1I ) ] = { 1253 [ C(OP_READ) ] = { 1254 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1255 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1256 }, 1257 [ C(OP_WRITE) ] = { 1258 [ C(RESULT_ACCESS) ] = -1, 1259 [ C(RESULT_MISS) ] = -1, 1260 }, 1261 [ C(OP_PREFETCH) ] = { 1262 [ C(RESULT_ACCESS) ] = 0x0, 1263 [ C(RESULT_MISS) ] = 0x0, 1264 }, 1265 }, 1266 [ C(LL ) ] = { 1267 [ C(OP_READ) ] = { 1268 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1269 [ C(RESULT_ACCESS) ] = 0x01b7, 1270 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1271 [ C(RESULT_MISS) ] = 0x01b7, 1272 }, 1273 /* 1274 * Use RFO, not WRITEBACK, because a write miss would typically occur 1275 * on RFO. 1276 */ 1277 [ C(OP_WRITE) ] = { 1278 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1279 [ C(RESULT_ACCESS) ] = 0x01b7, 1280 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1281 [ C(RESULT_MISS) ] = 0x01b7, 1282 }, 1283 [ C(OP_PREFETCH) ] = { 1284 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1285 [ C(RESULT_ACCESS) ] = 0x01b7, 1286 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1287 [ C(RESULT_MISS) ] = 0x01b7, 1288 }, 1289 }, 1290 [ C(DTLB) ] = { 1291 [ C(OP_READ) ] = { 1292 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1293 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1294 }, 1295 [ C(OP_WRITE) ] = { 1296 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1297 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1298 }, 1299 [ C(OP_PREFETCH) ] = { 1300 [ C(RESULT_ACCESS) ] = 0x0, 1301 [ C(RESULT_MISS) ] = 0x0, 1302 }, 1303 }, 1304 [ C(ITLB) ] = { 1305 [ C(OP_READ) ] = { 1306 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1307 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1308 }, 1309 [ C(OP_WRITE) ] = { 1310 [ C(RESULT_ACCESS) ] = -1, 1311 [ C(RESULT_MISS) ] = -1, 1312 }, 1313 [ C(OP_PREFETCH) ] = { 1314 [ C(RESULT_ACCESS) ] = -1, 1315 [ C(RESULT_MISS) ] = -1, 1316 }, 1317 }, 1318 [ C(BPU ) ] = { 1319 [ C(OP_READ) ] = { 1320 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1321 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1322 }, 1323 [ C(OP_WRITE) ] = { 1324 [ C(RESULT_ACCESS) ] = -1, 1325 [ C(RESULT_MISS) ] = -1, 1326 }, 1327 [ C(OP_PREFETCH) ] = { 1328 [ C(RESULT_ACCESS) ] = -1, 1329 [ C(RESULT_MISS) ] = -1, 1330 }, 1331 }, 1332 [ C(NODE) ] = { 1333 [ C(OP_READ) ] = { 1334 [ C(RESULT_ACCESS) ] = 0x01b7, 1335 [ C(RESULT_MISS) ] = 0x01b7, 1336 }, 1337 [ C(OP_WRITE) ] = { 1338 [ C(RESULT_ACCESS) ] = 0x01b7, 1339 [ C(RESULT_MISS) ] = 0x01b7, 1340 }, 1341 [ C(OP_PREFETCH) ] = { 1342 [ C(RESULT_ACCESS) ] = 0x01b7, 1343 [ C(RESULT_MISS) ] = 0x01b7, 1344 }, 1345 }, 1346 }; 1347 1348 /* 1349 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1350 * See IA32 SDM Vol 3B 30.6.1.3 1351 */ 1352 1353 #define NHM_DMND_DATA_RD (1 << 0) 1354 #define NHM_DMND_RFO (1 << 1) 1355 #define NHM_DMND_IFETCH (1 << 2) 1356 #define NHM_DMND_WB (1 << 3) 1357 #define NHM_PF_DATA_RD (1 << 4) 1358 #define NHM_PF_DATA_RFO (1 << 5) 1359 #define NHM_PF_IFETCH (1 << 6) 1360 #define NHM_OFFCORE_OTHER (1 << 7) 1361 #define NHM_UNCORE_HIT (1 << 8) 1362 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1363 #define NHM_OTHER_CORE_HITM (1 << 10) 1364 /* reserved */ 1365 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1366 #define NHM_REMOTE_DRAM (1 << 13) 1367 #define NHM_LOCAL_DRAM (1 << 14) 1368 #define NHM_NON_DRAM (1 << 15) 1369 1370 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1371 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1372 1373 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1374 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1375 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1376 1377 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1378 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1379 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1380 1381 static __initconst const u64 nehalem_hw_cache_extra_regs 1382 [PERF_COUNT_HW_CACHE_MAX] 1383 [PERF_COUNT_HW_CACHE_OP_MAX] 1384 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1385 { 1386 [ C(LL ) ] = { 1387 [ C(OP_READ) ] = { 1388 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1389 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1390 }, 1391 [ C(OP_WRITE) ] = { 1392 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1393 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1394 }, 1395 [ C(OP_PREFETCH) ] = { 1396 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1397 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1398 }, 1399 }, 1400 [ C(NODE) ] = { 1401 [ C(OP_READ) ] = { 1402 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1403 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1404 }, 1405 [ C(OP_WRITE) ] = { 1406 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1407 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1408 }, 1409 [ C(OP_PREFETCH) ] = { 1410 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1411 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1412 }, 1413 }, 1414 }; 1415 1416 static __initconst const u64 nehalem_hw_cache_event_ids 1417 [PERF_COUNT_HW_CACHE_MAX] 1418 [PERF_COUNT_HW_CACHE_OP_MAX] 1419 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1420 { 1421 [ C(L1D) ] = { 1422 [ C(OP_READ) ] = { 1423 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1424 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1425 }, 1426 [ C(OP_WRITE) ] = { 1427 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1428 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1429 }, 1430 [ C(OP_PREFETCH) ] = { 1431 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1432 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1433 }, 1434 }, 1435 [ C(L1I ) ] = { 1436 [ C(OP_READ) ] = { 1437 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1438 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1439 }, 1440 [ C(OP_WRITE) ] = { 1441 [ C(RESULT_ACCESS) ] = -1, 1442 [ C(RESULT_MISS) ] = -1, 1443 }, 1444 [ C(OP_PREFETCH) ] = { 1445 [ C(RESULT_ACCESS) ] = 0x0, 1446 [ C(RESULT_MISS) ] = 0x0, 1447 }, 1448 }, 1449 [ C(LL ) ] = { 1450 [ C(OP_READ) ] = { 1451 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1452 [ C(RESULT_ACCESS) ] = 0x01b7, 1453 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1454 [ C(RESULT_MISS) ] = 0x01b7, 1455 }, 1456 /* 1457 * Use RFO, not WRITEBACK, because a write miss would typically occur 1458 * on RFO. 1459 */ 1460 [ C(OP_WRITE) ] = { 1461 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1462 [ C(RESULT_ACCESS) ] = 0x01b7, 1463 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1464 [ C(RESULT_MISS) ] = 0x01b7, 1465 }, 1466 [ C(OP_PREFETCH) ] = { 1467 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1468 [ C(RESULT_ACCESS) ] = 0x01b7, 1469 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1470 [ C(RESULT_MISS) ] = 0x01b7, 1471 }, 1472 }, 1473 [ C(DTLB) ] = { 1474 [ C(OP_READ) ] = { 1475 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1476 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1477 }, 1478 [ C(OP_WRITE) ] = { 1479 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1480 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1481 }, 1482 [ C(OP_PREFETCH) ] = { 1483 [ C(RESULT_ACCESS) ] = 0x0, 1484 [ C(RESULT_MISS) ] = 0x0, 1485 }, 1486 }, 1487 [ C(ITLB) ] = { 1488 [ C(OP_READ) ] = { 1489 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1490 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1491 }, 1492 [ C(OP_WRITE) ] = { 1493 [ C(RESULT_ACCESS) ] = -1, 1494 [ C(RESULT_MISS) ] = -1, 1495 }, 1496 [ C(OP_PREFETCH) ] = { 1497 [ C(RESULT_ACCESS) ] = -1, 1498 [ C(RESULT_MISS) ] = -1, 1499 }, 1500 }, 1501 [ C(BPU ) ] = { 1502 [ C(OP_READ) ] = { 1503 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1504 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1505 }, 1506 [ C(OP_WRITE) ] = { 1507 [ C(RESULT_ACCESS) ] = -1, 1508 [ C(RESULT_MISS) ] = -1, 1509 }, 1510 [ C(OP_PREFETCH) ] = { 1511 [ C(RESULT_ACCESS) ] = -1, 1512 [ C(RESULT_MISS) ] = -1, 1513 }, 1514 }, 1515 [ C(NODE) ] = { 1516 [ C(OP_READ) ] = { 1517 [ C(RESULT_ACCESS) ] = 0x01b7, 1518 [ C(RESULT_MISS) ] = 0x01b7, 1519 }, 1520 [ C(OP_WRITE) ] = { 1521 [ C(RESULT_ACCESS) ] = 0x01b7, 1522 [ C(RESULT_MISS) ] = 0x01b7, 1523 }, 1524 [ C(OP_PREFETCH) ] = { 1525 [ C(RESULT_ACCESS) ] = 0x01b7, 1526 [ C(RESULT_MISS) ] = 0x01b7, 1527 }, 1528 }, 1529 }; 1530 1531 static __initconst const u64 core2_hw_cache_event_ids 1532 [PERF_COUNT_HW_CACHE_MAX] 1533 [PERF_COUNT_HW_CACHE_OP_MAX] 1534 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1535 { 1536 [ C(L1D) ] = { 1537 [ C(OP_READ) ] = { 1538 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1539 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1540 }, 1541 [ C(OP_WRITE) ] = { 1542 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1543 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1544 }, 1545 [ C(OP_PREFETCH) ] = { 1546 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1547 [ C(RESULT_MISS) ] = 0, 1548 }, 1549 }, 1550 [ C(L1I ) ] = { 1551 [ C(OP_READ) ] = { 1552 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1553 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1554 }, 1555 [ C(OP_WRITE) ] = { 1556 [ C(RESULT_ACCESS) ] = -1, 1557 [ C(RESULT_MISS) ] = -1, 1558 }, 1559 [ C(OP_PREFETCH) ] = { 1560 [ C(RESULT_ACCESS) ] = 0, 1561 [ C(RESULT_MISS) ] = 0, 1562 }, 1563 }, 1564 [ C(LL ) ] = { 1565 [ C(OP_READ) ] = { 1566 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1567 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1568 }, 1569 [ C(OP_WRITE) ] = { 1570 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1571 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1572 }, 1573 [ C(OP_PREFETCH) ] = { 1574 [ C(RESULT_ACCESS) ] = 0, 1575 [ C(RESULT_MISS) ] = 0, 1576 }, 1577 }, 1578 [ C(DTLB) ] = { 1579 [ C(OP_READ) ] = { 1580 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1581 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1582 }, 1583 [ C(OP_WRITE) ] = { 1584 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1585 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1586 }, 1587 [ C(OP_PREFETCH) ] = { 1588 [ C(RESULT_ACCESS) ] = 0, 1589 [ C(RESULT_MISS) ] = 0, 1590 }, 1591 }, 1592 [ C(ITLB) ] = { 1593 [ C(OP_READ) ] = { 1594 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1595 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1596 }, 1597 [ C(OP_WRITE) ] = { 1598 [ C(RESULT_ACCESS) ] = -1, 1599 [ C(RESULT_MISS) ] = -1, 1600 }, 1601 [ C(OP_PREFETCH) ] = { 1602 [ C(RESULT_ACCESS) ] = -1, 1603 [ C(RESULT_MISS) ] = -1, 1604 }, 1605 }, 1606 [ C(BPU ) ] = { 1607 [ C(OP_READ) ] = { 1608 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1609 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1610 }, 1611 [ C(OP_WRITE) ] = { 1612 [ C(RESULT_ACCESS) ] = -1, 1613 [ C(RESULT_MISS) ] = -1, 1614 }, 1615 [ C(OP_PREFETCH) ] = { 1616 [ C(RESULT_ACCESS) ] = -1, 1617 [ C(RESULT_MISS) ] = -1, 1618 }, 1619 }, 1620 }; 1621 1622 static __initconst const u64 atom_hw_cache_event_ids 1623 [PERF_COUNT_HW_CACHE_MAX] 1624 [PERF_COUNT_HW_CACHE_OP_MAX] 1625 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1626 { 1627 [ C(L1D) ] = { 1628 [ C(OP_READ) ] = { 1629 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1630 [ C(RESULT_MISS) ] = 0, 1631 }, 1632 [ C(OP_WRITE) ] = { 1633 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1634 [ C(RESULT_MISS) ] = 0, 1635 }, 1636 [ C(OP_PREFETCH) ] = { 1637 [ C(RESULT_ACCESS) ] = 0x0, 1638 [ C(RESULT_MISS) ] = 0, 1639 }, 1640 }, 1641 [ C(L1I ) ] = { 1642 [ C(OP_READ) ] = { 1643 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1644 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1645 }, 1646 [ C(OP_WRITE) ] = { 1647 [ C(RESULT_ACCESS) ] = -1, 1648 [ C(RESULT_MISS) ] = -1, 1649 }, 1650 [ C(OP_PREFETCH) ] = { 1651 [ C(RESULT_ACCESS) ] = 0, 1652 [ C(RESULT_MISS) ] = 0, 1653 }, 1654 }, 1655 [ C(LL ) ] = { 1656 [ C(OP_READ) ] = { 1657 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1658 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1659 }, 1660 [ C(OP_WRITE) ] = { 1661 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1662 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1663 }, 1664 [ C(OP_PREFETCH) ] = { 1665 [ C(RESULT_ACCESS) ] = 0, 1666 [ C(RESULT_MISS) ] = 0, 1667 }, 1668 }, 1669 [ C(DTLB) ] = { 1670 [ C(OP_READ) ] = { 1671 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1672 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1673 }, 1674 [ C(OP_WRITE) ] = { 1675 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1676 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1677 }, 1678 [ C(OP_PREFETCH) ] = { 1679 [ C(RESULT_ACCESS) ] = 0, 1680 [ C(RESULT_MISS) ] = 0, 1681 }, 1682 }, 1683 [ C(ITLB) ] = { 1684 [ C(OP_READ) ] = { 1685 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1686 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1687 }, 1688 [ C(OP_WRITE) ] = { 1689 [ C(RESULT_ACCESS) ] = -1, 1690 [ C(RESULT_MISS) ] = -1, 1691 }, 1692 [ C(OP_PREFETCH) ] = { 1693 [ C(RESULT_ACCESS) ] = -1, 1694 [ C(RESULT_MISS) ] = -1, 1695 }, 1696 }, 1697 [ C(BPU ) ] = { 1698 [ C(OP_READ) ] = { 1699 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1700 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1701 }, 1702 [ C(OP_WRITE) ] = { 1703 [ C(RESULT_ACCESS) ] = -1, 1704 [ C(RESULT_MISS) ] = -1, 1705 }, 1706 [ C(OP_PREFETCH) ] = { 1707 [ C(RESULT_ACCESS) ] = -1, 1708 [ C(RESULT_MISS) ] = -1, 1709 }, 1710 }, 1711 }; 1712 1713 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1714 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1715 /* no_alloc_cycles.not_delivered */ 1716 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1717 "event=0xca,umask=0x50"); 1718 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1719 /* uops_retired.all */ 1720 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1721 "event=0xc2,umask=0x10"); 1722 /* uops_retired.all */ 1723 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1724 "event=0xc2,umask=0x10"); 1725 1726 static struct attribute *slm_events_attrs[] = { 1727 EVENT_PTR(td_total_slots_slm), 1728 EVENT_PTR(td_total_slots_scale_slm), 1729 EVENT_PTR(td_fetch_bubbles_slm), 1730 EVENT_PTR(td_fetch_bubbles_scale_slm), 1731 EVENT_PTR(td_slots_issued_slm), 1732 EVENT_PTR(td_slots_retired_slm), 1733 NULL 1734 }; 1735 1736 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1737 { 1738 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1739 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1740 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1741 EVENT_EXTRA_END 1742 }; 1743 1744 #define SLM_DMND_READ SNB_DMND_DATA_RD 1745 #define SLM_DMND_WRITE SNB_DMND_RFO 1746 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1747 1748 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1749 #define SLM_LLC_ACCESS SNB_RESP_ANY 1750 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1751 1752 static __initconst const u64 slm_hw_cache_extra_regs 1753 [PERF_COUNT_HW_CACHE_MAX] 1754 [PERF_COUNT_HW_CACHE_OP_MAX] 1755 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1756 { 1757 [ C(LL ) ] = { 1758 [ C(OP_READ) ] = { 1759 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1760 [ C(RESULT_MISS) ] = 0, 1761 }, 1762 [ C(OP_WRITE) ] = { 1763 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1764 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1765 }, 1766 [ C(OP_PREFETCH) ] = { 1767 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1768 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1769 }, 1770 }, 1771 }; 1772 1773 static __initconst const u64 slm_hw_cache_event_ids 1774 [PERF_COUNT_HW_CACHE_MAX] 1775 [PERF_COUNT_HW_CACHE_OP_MAX] 1776 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1777 { 1778 [ C(L1D) ] = { 1779 [ C(OP_READ) ] = { 1780 [ C(RESULT_ACCESS) ] = 0, 1781 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1782 }, 1783 [ C(OP_WRITE) ] = { 1784 [ C(RESULT_ACCESS) ] = 0, 1785 [ C(RESULT_MISS) ] = 0, 1786 }, 1787 [ C(OP_PREFETCH) ] = { 1788 [ C(RESULT_ACCESS) ] = 0, 1789 [ C(RESULT_MISS) ] = 0, 1790 }, 1791 }, 1792 [ C(L1I ) ] = { 1793 [ C(OP_READ) ] = { 1794 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1795 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1796 }, 1797 [ C(OP_WRITE) ] = { 1798 [ C(RESULT_ACCESS) ] = -1, 1799 [ C(RESULT_MISS) ] = -1, 1800 }, 1801 [ C(OP_PREFETCH) ] = { 1802 [ C(RESULT_ACCESS) ] = 0, 1803 [ C(RESULT_MISS) ] = 0, 1804 }, 1805 }, 1806 [ C(LL ) ] = { 1807 [ C(OP_READ) ] = { 1808 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1809 [ C(RESULT_ACCESS) ] = 0x01b7, 1810 [ C(RESULT_MISS) ] = 0, 1811 }, 1812 [ C(OP_WRITE) ] = { 1813 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1814 [ C(RESULT_ACCESS) ] = 0x01b7, 1815 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1816 [ C(RESULT_MISS) ] = 0x01b7, 1817 }, 1818 [ C(OP_PREFETCH) ] = { 1819 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1820 [ C(RESULT_ACCESS) ] = 0x01b7, 1821 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1822 [ C(RESULT_MISS) ] = 0x01b7, 1823 }, 1824 }, 1825 [ C(DTLB) ] = { 1826 [ C(OP_READ) ] = { 1827 [ C(RESULT_ACCESS) ] = 0, 1828 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1829 }, 1830 [ C(OP_WRITE) ] = { 1831 [ C(RESULT_ACCESS) ] = 0, 1832 [ C(RESULT_MISS) ] = 0, 1833 }, 1834 [ C(OP_PREFETCH) ] = { 1835 [ C(RESULT_ACCESS) ] = 0, 1836 [ C(RESULT_MISS) ] = 0, 1837 }, 1838 }, 1839 [ C(ITLB) ] = { 1840 [ C(OP_READ) ] = { 1841 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1842 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1843 }, 1844 [ C(OP_WRITE) ] = { 1845 [ C(RESULT_ACCESS) ] = -1, 1846 [ C(RESULT_MISS) ] = -1, 1847 }, 1848 [ C(OP_PREFETCH) ] = { 1849 [ C(RESULT_ACCESS) ] = -1, 1850 [ C(RESULT_MISS) ] = -1, 1851 }, 1852 }, 1853 [ C(BPU ) ] = { 1854 [ C(OP_READ) ] = { 1855 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1856 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1857 }, 1858 [ C(OP_WRITE) ] = { 1859 [ C(RESULT_ACCESS) ] = -1, 1860 [ C(RESULT_MISS) ] = -1, 1861 }, 1862 [ C(OP_PREFETCH) ] = { 1863 [ C(RESULT_ACCESS) ] = -1, 1864 [ C(RESULT_MISS) ] = -1, 1865 }, 1866 }, 1867 }; 1868 1869 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1870 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1871 /* UOPS_NOT_DELIVERED.ANY */ 1872 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1873 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1874 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1875 /* UOPS_RETIRED.ANY */ 1876 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1877 /* UOPS_ISSUED.ANY */ 1878 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1879 1880 static struct attribute *glm_events_attrs[] = { 1881 EVENT_PTR(td_total_slots_glm), 1882 EVENT_PTR(td_total_slots_scale_glm), 1883 EVENT_PTR(td_fetch_bubbles_glm), 1884 EVENT_PTR(td_recovery_bubbles_glm), 1885 EVENT_PTR(td_slots_issued_glm), 1886 EVENT_PTR(td_slots_retired_glm), 1887 NULL 1888 }; 1889 1890 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1891 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1892 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1893 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1894 EVENT_EXTRA_END 1895 }; 1896 1897 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 1898 #define GLM_DEMAND_RFO BIT_ULL(1) 1899 #define GLM_ANY_RESPONSE BIT_ULL(16) 1900 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1901 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1902 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1903 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1904 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1905 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1906 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1907 1908 static __initconst const u64 glm_hw_cache_event_ids 1909 [PERF_COUNT_HW_CACHE_MAX] 1910 [PERF_COUNT_HW_CACHE_OP_MAX] 1911 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1912 [C(L1D)] = { 1913 [C(OP_READ)] = { 1914 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1915 [C(RESULT_MISS)] = 0x0, 1916 }, 1917 [C(OP_WRITE)] = { 1918 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1919 [C(RESULT_MISS)] = 0x0, 1920 }, 1921 [C(OP_PREFETCH)] = { 1922 [C(RESULT_ACCESS)] = 0x0, 1923 [C(RESULT_MISS)] = 0x0, 1924 }, 1925 }, 1926 [C(L1I)] = { 1927 [C(OP_READ)] = { 1928 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1929 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1930 }, 1931 [C(OP_WRITE)] = { 1932 [C(RESULT_ACCESS)] = -1, 1933 [C(RESULT_MISS)] = -1, 1934 }, 1935 [C(OP_PREFETCH)] = { 1936 [C(RESULT_ACCESS)] = 0x0, 1937 [C(RESULT_MISS)] = 0x0, 1938 }, 1939 }, 1940 [C(LL)] = { 1941 [C(OP_READ)] = { 1942 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1943 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1944 }, 1945 [C(OP_WRITE)] = { 1946 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1947 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1948 }, 1949 [C(OP_PREFETCH)] = { 1950 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1951 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1952 }, 1953 }, 1954 [C(DTLB)] = { 1955 [C(OP_READ)] = { 1956 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1957 [C(RESULT_MISS)] = 0x0, 1958 }, 1959 [C(OP_WRITE)] = { 1960 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1961 [C(RESULT_MISS)] = 0x0, 1962 }, 1963 [C(OP_PREFETCH)] = { 1964 [C(RESULT_ACCESS)] = 0x0, 1965 [C(RESULT_MISS)] = 0x0, 1966 }, 1967 }, 1968 [C(ITLB)] = { 1969 [C(OP_READ)] = { 1970 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1971 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1972 }, 1973 [C(OP_WRITE)] = { 1974 [C(RESULT_ACCESS)] = -1, 1975 [C(RESULT_MISS)] = -1, 1976 }, 1977 [C(OP_PREFETCH)] = { 1978 [C(RESULT_ACCESS)] = -1, 1979 [C(RESULT_MISS)] = -1, 1980 }, 1981 }, 1982 [C(BPU)] = { 1983 [C(OP_READ)] = { 1984 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1985 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1986 }, 1987 [C(OP_WRITE)] = { 1988 [C(RESULT_ACCESS)] = -1, 1989 [C(RESULT_MISS)] = -1, 1990 }, 1991 [C(OP_PREFETCH)] = { 1992 [C(RESULT_ACCESS)] = -1, 1993 [C(RESULT_MISS)] = -1, 1994 }, 1995 }, 1996 }; 1997 1998 static __initconst const u64 glm_hw_cache_extra_regs 1999 [PERF_COUNT_HW_CACHE_MAX] 2000 [PERF_COUNT_HW_CACHE_OP_MAX] 2001 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2002 [C(LL)] = { 2003 [C(OP_READ)] = { 2004 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2005 GLM_LLC_ACCESS, 2006 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2007 GLM_LLC_MISS, 2008 }, 2009 [C(OP_WRITE)] = { 2010 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2011 GLM_LLC_ACCESS, 2012 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2013 GLM_LLC_MISS, 2014 }, 2015 [C(OP_PREFETCH)] = { 2016 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 2017 GLM_LLC_ACCESS, 2018 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 2019 GLM_LLC_MISS, 2020 }, 2021 }, 2022 }; 2023 2024 static __initconst const u64 glp_hw_cache_event_ids 2025 [PERF_COUNT_HW_CACHE_MAX] 2026 [PERF_COUNT_HW_CACHE_OP_MAX] 2027 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2028 [C(L1D)] = { 2029 [C(OP_READ)] = { 2030 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2031 [C(RESULT_MISS)] = 0x0, 2032 }, 2033 [C(OP_WRITE)] = { 2034 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2035 [C(RESULT_MISS)] = 0x0, 2036 }, 2037 [C(OP_PREFETCH)] = { 2038 [C(RESULT_ACCESS)] = 0x0, 2039 [C(RESULT_MISS)] = 0x0, 2040 }, 2041 }, 2042 [C(L1I)] = { 2043 [C(OP_READ)] = { 2044 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 2045 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 2046 }, 2047 [C(OP_WRITE)] = { 2048 [C(RESULT_ACCESS)] = -1, 2049 [C(RESULT_MISS)] = -1, 2050 }, 2051 [C(OP_PREFETCH)] = { 2052 [C(RESULT_ACCESS)] = 0x0, 2053 [C(RESULT_MISS)] = 0x0, 2054 }, 2055 }, 2056 [C(LL)] = { 2057 [C(OP_READ)] = { 2058 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2059 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2060 }, 2061 [C(OP_WRITE)] = { 2062 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2063 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2064 }, 2065 [C(OP_PREFETCH)] = { 2066 [C(RESULT_ACCESS)] = 0x0, 2067 [C(RESULT_MISS)] = 0x0, 2068 }, 2069 }, 2070 [C(DTLB)] = { 2071 [C(OP_READ)] = { 2072 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2073 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 2074 }, 2075 [C(OP_WRITE)] = { 2076 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2077 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 2078 }, 2079 [C(OP_PREFETCH)] = { 2080 [C(RESULT_ACCESS)] = 0x0, 2081 [C(RESULT_MISS)] = 0x0, 2082 }, 2083 }, 2084 [C(ITLB)] = { 2085 [C(OP_READ)] = { 2086 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 2087 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 2088 }, 2089 [C(OP_WRITE)] = { 2090 [C(RESULT_ACCESS)] = -1, 2091 [C(RESULT_MISS)] = -1, 2092 }, 2093 [C(OP_PREFETCH)] = { 2094 [C(RESULT_ACCESS)] = -1, 2095 [C(RESULT_MISS)] = -1, 2096 }, 2097 }, 2098 [C(BPU)] = { 2099 [C(OP_READ)] = { 2100 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 2101 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 2102 }, 2103 [C(OP_WRITE)] = { 2104 [C(RESULT_ACCESS)] = -1, 2105 [C(RESULT_MISS)] = -1, 2106 }, 2107 [C(OP_PREFETCH)] = { 2108 [C(RESULT_ACCESS)] = -1, 2109 [C(RESULT_MISS)] = -1, 2110 }, 2111 }, 2112 }; 2113 2114 static __initconst const u64 glp_hw_cache_extra_regs 2115 [PERF_COUNT_HW_CACHE_MAX] 2116 [PERF_COUNT_HW_CACHE_OP_MAX] 2117 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2118 [C(LL)] = { 2119 [C(OP_READ)] = { 2120 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2121 GLM_LLC_ACCESS, 2122 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2123 GLM_LLC_MISS, 2124 }, 2125 [C(OP_WRITE)] = { 2126 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2127 GLM_LLC_ACCESS, 2128 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2129 GLM_LLC_MISS, 2130 }, 2131 [C(OP_PREFETCH)] = { 2132 [C(RESULT_ACCESS)] = 0x0, 2133 [C(RESULT_MISS)] = 0x0, 2134 }, 2135 }, 2136 }; 2137 2138 #define TNT_LOCAL_DRAM BIT_ULL(26) 2139 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 2140 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 2141 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 2142 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 2143 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 2144 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 2145 2146 static __initconst const u64 tnt_hw_cache_extra_regs 2147 [PERF_COUNT_HW_CACHE_MAX] 2148 [PERF_COUNT_HW_CACHE_OP_MAX] 2149 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2150 [C(LL)] = { 2151 [C(OP_READ)] = { 2152 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 2153 TNT_LLC_ACCESS, 2154 [C(RESULT_MISS)] = TNT_DEMAND_READ| 2155 TNT_LLC_MISS, 2156 }, 2157 [C(OP_WRITE)] = { 2158 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 2159 TNT_LLC_ACCESS, 2160 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 2161 TNT_LLC_MISS, 2162 }, 2163 [C(OP_PREFETCH)] = { 2164 [C(RESULT_ACCESS)] = 0x0, 2165 [C(RESULT_MISS)] = 0x0, 2166 }, 2167 }, 2168 }; 2169 2170 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2171 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2172 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2173 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2174 2175 static struct attribute *tnt_events_attrs[] = { 2176 EVENT_PTR(td_fe_bound_tnt), 2177 EVENT_PTR(td_retiring_tnt), 2178 EVENT_PTR(td_bad_spec_tnt), 2179 EVENT_PTR(td_be_bound_tnt), 2180 NULL, 2181 }; 2182 2183 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 2184 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2185 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 2186 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 2187 EVENT_EXTRA_END 2188 }; 2189 2190 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3"); 2191 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6"); 2192 2193 static struct attribute *grt_mem_attrs[] = { 2194 EVENT_PTR(mem_ld_grt), 2195 EVENT_PTR(mem_st_grt), 2196 NULL 2197 }; 2198 2199 static struct extra_reg intel_grt_extra_regs[] __read_mostly = { 2200 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2201 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 2202 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 2203 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2204 EVENT_EXTRA_END 2205 }; 2206 2207 EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0"); 2208 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0"); 2209 2210 static struct attribute *cmt_events_attrs[] = { 2211 EVENT_PTR(td_fe_bound_tnt), 2212 EVENT_PTR(td_retiring_cmt), 2213 EVENT_PTR(td_bad_spec_cmt), 2214 EVENT_PTR(td_be_bound_tnt), 2215 NULL 2216 }; 2217 2218 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = { 2219 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2220 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0), 2221 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1), 2222 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2223 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0), 2224 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1), 2225 EVENT_EXTRA_END 2226 }; 2227 2228 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2229 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2230 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 2231 #define KNL_MCDRAM_FAR BIT_ULL(22) 2232 #define KNL_DDR_LOCAL BIT_ULL(23) 2233 #define KNL_DDR_FAR BIT_ULL(24) 2234 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2235 KNL_DDR_LOCAL | KNL_DDR_FAR) 2236 #define KNL_L2_READ SLM_DMND_READ 2237 #define KNL_L2_WRITE SLM_DMND_WRITE 2238 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2239 #define KNL_L2_ACCESS SLM_LLC_ACCESS 2240 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2241 KNL_DRAM_ANY | SNB_SNP_ANY | \ 2242 SNB_NON_DRAM) 2243 2244 static __initconst const u64 knl_hw_cache_extra_regs 2245 [PERF_COUNT_HW_CACHE_MAX] 2246 [PERF_COUNT_HW_CACHE_OP_MAX] 2247 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2248 [C(LL)] = { 2249 [C(OP_READ)] = { 2250 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2251 [C(RESULT_MISS)] = 0, 2252 }, 2253 [C(OP_WRITE)] = { 2254 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2255 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2256 }, 2257 [C(OP_PREFETCH)] = { 2258 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2259 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2260 }, 2261 }, 2262 }; 2263 2264 /* 2265 * Used from PMIs where the LBRs are already disabled. 2266 * 2267 * This function could be called consecutively. It is required to remain in 2268 * disabled state if called consecutively. 2269 * 2270 * During consecutive calls, the same disable value will be written to related 2271 * registers, so the PMU state remains unchanged. 2272 * 2273 * intel_bts events don't coexist with intel PMU's BTS events because of 2274 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2275 * disabled around intel PMU's event batching etc, only inside the PMI handler. 2276 * 2277 * Avoid PEBS_ENABLE MSR access in PMIs. 2278 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 2279 * It doesn't matter if the PEBS is enabled or not. 2280 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 2281 * access PEBS_ENABLE MSR in disable_all()/enable_all(). 2282 * However, there are some cases which may change PEBS status, e.g. PMI 2283 * throttle. The PEBS_ENABLE should be updated where the status changes. 2284 */ 2285 static __always_inline void __intel_pmu_disable_all(bool bts) 2286 { 2287 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2288 2289 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2290 2291 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2292 intel_pmu_disable_bts(); 2293 } 2294 2295 static __always_inline void intel_pmu_disable_all(void) 2296 { 2297 __intel_pmu_disable_all(true); 2298 intel_pmu_pebs_disable_all(); 2299 intel_pmu_lbr_disable_all(); 2300 } 2301 2302 static void __intel_pmu_enable_all(int added, bool pmi) 2303 { 2304 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2305 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2306 2307 intel_pmu_lbr_enable_all(pmi); 2308 2309 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) { 2310 wrmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val); 2311 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val; 2312 } 2313 2314 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 2315 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2316 2317 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2318 struct perf_event *event = 2319 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2320 2321 if (WARN_ON_ONCE(!event)) 2322 return; 2323 2324 intel_pmu_enable_bts(event->hw.config); 2325 } 2326 } 2327 2328 static void intel_pmu_enable_all(int added) 2329 { 2330 intel_pmu_pebs_enable_all(); 2331 __intel_pmu_enable_all(added, false); 2332 } 2333 2334 static noinline int 2335 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, 2336 unsigned int cnt, unsigned long flags) 2337 { 2338 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2339 2340 intel_pmu_lbr_read(); 2341 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); 2342 2343 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); 2344 intel_pmu_enable_all(0); 2345 local_irq_restore(flags); 2346 return cnt; 2347 } 2348 2349 static int 2350 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2351 { 2352 unsigned long flags; 2353 2354 /* must not have branches... */ 2355 local_irq_save(flags); 2356 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2357 __intel_pmu_lbr_disable(); 2358 /* ... until here */ 2359 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2360 } 2361 2362 static int 2363 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2364 { 2365 unsigned long flags; 2366 2367 /* must not have branches... */ 2368 local_irq_save(flags); 2369 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2370 __intel_pmu_arch_lbr_disable(); 2371 /* ... until here */ 2372 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2373 } 2374 2375 /* 2376 * Workaround for: 2377 * Intel Errata AAK100 (model 26) 2378 * Intel Errata AAP53 (model 30) 2379 * Intel Errata BD53 (model 44) 2380 * 2381 * The official story: 2382 * These chips need to be 'reset' when adding counters by programming the 2383 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2384 * in sequence on the same PMC or on different PMCs. 2385 * 2386 * In practice it appears some of these events do in fact count, and 2387 * we need to program all 4 events. 2388 */ 2389 static void intel_pmu_nhm_workaround(void) 2390 { 2391 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2392 static const unsigned long nhm_magic[4] = { 2393 0x4300B5, 2394 0x4300D2, 2395 0x4300B1, 2396 0x4300B1 2397 }; 2398 struct perf_event *event; 2399 int i; 2400 2401 /* 2402 * The Errata requires below steps: 2403 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2404 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2405 * the corresponding PMCx; 2406 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2407 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2408 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2409 */ 2410 2411 /* 2412 * The real steps we choose are a little different from above. 2413 * A) To reduce MSR operations, we don't run step 1) as they 2414 * are already cleared before this function is called; 2415 * B) Call x86_perf_event_update to save PMCx before configuring 2416 * PERFEVTSELx with magic number; 2417 * C) With step 5), we do clear only when the PERFEVTSELx is 2418 * not used currently. 2419 * D) Call x86_perf_event_set_period to restore PMCx; 2420 */ 2421 2422 /* We always operate 4 pairs of PERF Counters */ 2423 for (i = 0; i < 4; i++) { 2424 event = cpuc->events[i]; 2425 if (event) 2426 static_call(x86_pmu_update)(event); 2427 } 2428 2429 for (i = 0; i < 4; i++) { 2430 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2431 wrmsrq(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2432 } 2433 2434 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2435 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2436 2437 for (i = 0; i < 4; i++) { 2438 event = cpuc->events[i]; 2439 2440 if (event) { 2441 static_call(x86_pmu_set_period)(event); 2442 __x86_pmu_enable_event(&event->hw, 2443 ARCH_PERFMON_EVENTSEL_ENABLE); 2444 } else 2445 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2446 } 2447 } 2448 2449 static void intel_pmu_nhm_enable_all(int added) 2450 { 2451 if (added) 2452 intel_pmu_nhm_workaround(); 2453 intel_pmu_enable_all(added); 2454 } 2455 2456 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2457 { 2458 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2459 2460 if (cpuc->tfa_shadow != val) { 2461 cpuc->tfa_shadow = val; 2462 wrmsrq(MSR_TSX_FORCE_ABORT, val); 2463 } 2464 } 2465 2466 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2467 { 2468 /* 2469 * We're going to use PMC3, make sure TFA is set before we touch it. 2470 */ 2471 if (cntr == 3) 2472 intel_set_tfa(cpuc, true); 2473 } 2474 2475 static void intel_tfa_pmu_enable_all(int added) 2476 { 2477 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2478 2479 /* 2480 * If we find PMC3 is no longer used when we enable the PMU, we can 2481 * clear TFA. 2482 */ 2483 if (!test_bit(3, cpuc->active_mask)) 2484 intel_set_tfa(cpuc, false); 2485 2486 intel_pmu_enable_all(added); 2487 } 2488 2489 static inline u64 intel_pmu_get_status(void) 2490 { 2491 u64 status; 2492 2493 rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status); 2494 2495 return status; 2496 } 2497 2498 static inline void intel_pmu_ack_status(u64 ack) 2499 { 2500 wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2501 } 2502 2503 static inline bool event_is_checkpointed(struct perf_event *event) 2504 { 2505 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2506 } 2507 2508 static inline void intel_set_masks(struct perf_event *event, int idx) 2509 { 2510 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2511 2512 if (event->attr.exclude_host) 2513 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2514 if (event->attr.exclude_guest) 2515 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2516 if (event_is_checkpointed(event)) 2517 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2518 } 2519 2520 static inline void intel_clear_masks(struct perf_event *event, int idx) 2521 { 2522 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2523 2524 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2525 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2526 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2527 } 2528 2529 static void intel_pmu_disable_fixed(struct perf_event *event) 2530 { 2531 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2532 struct hw_perf_event *hwc = &event->hw; 2533 int idx = hwc->idx; 2534 u64 mask; 2535 2536 if (is_topdown_idx(idx)) { 2537 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2538 2539 /* 2540 * When there are other active TopDown events, 2541 * don't disable the fixed counter 3. 2542 */ 2543 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2544 return; 2545 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2546 } 2547 2548 intel_clear_masks(event, idx); 2549 2550 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK); 2551 cpuc->fixed_ctrl_val &= ~mask; 2552 } 2553 2554 static void intel_pmu_disable_event(struct perf_event *event) 2555 { 2556 struct hw_perf_event *hwc = &event->hw; 2557 int idx = hwc->idx; 2558 2559 switch (idx) { 2560 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2561 intel_clear_masks(event, idx); 2562 x86_pmu_disable_event(event); 2563 break; 2564 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2565 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2566 intel_pmu_disable_fixed(event); 2567 break; 2568 case INTEL_PMC_IDX_FIXED_BTS: 2569 intel_pmu_disable_bts(); 2570 intel_pmu_drain_bts_buffer(); 2571 return; 2572 case INTEL_PMC_IDX_FIXED_VLBR: 2573 intel_clear_masks(event, idx); 2574 break; 2575 default: 2576 intel_clear_masks(event, idx); 2577 pr_warn("Failed to disable the event with invalid index %d\n", 2578 idx); 2579 return; 2580 } 2581 2582 /* 2583 * Needs to be called after x86_pmu_disable_event, 2584 * so we don't trigger the event without PEBS bit set. 2585 */ 2586 if (unlikely(event->attr.precise_ip)) 2587 intel_pmu_pebs_disable(event); 2588 } 2589 2590 static void intel_pmu_assign_event(struct perf_event *event, int idx) 2591 { 2592 if (is_pebs_pt(event)) 2593 perf_report_aux_output_id(event, idx); 2594 } 2595 2596 static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event) 2597 { 2598 return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK; 2599 } 2600 2601 static void intel_pmu_del_event(struct perf_event *event) 2602 { 2603 if (intel_pmu_needs_branch_stack(event)) 2604 intel_pmu_lbr_del(event); 2605 if (event->attr.precise_ip) 2606 intel_pmu_pebs_del(event); 2607 } 2608 2609 static int icl_set_topdown_event_period(struct perf_event *event) 2610 { 2611 struct hw_perf_event *hwc = &event->hw; 2612 s64 left = local64_read(&hwc->period_left); 2613 2614 /* 2615 * The values in PERF_METRICS MSR are derived from fixed counter 3. 2616 * Software should start both registers, PERF_METRICS and fixed 2617 * counter 3, from zero. 2618 * Clear PERF_METRICS and Fixed counter 3 in initialization. 2619 * After that, both MSRs will be cleared for each read. 2620 * Don't need to clear them again. 2621 */ 2622 if (left == x86_pmu.max_period) { 2623 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0); 2624 wrmsrq(MSR_PERF_METRICS, 0); 2625 hwc->saved_slots = 0; 2626 hwc->saved_metric = 0; 2627 } 2628 2629 if ((hwc->saved_slots) && is_slots_event(event)) { 2630 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2631 wrmsrq(MSR_PERF_METRICS, hwc->saved_metric); 2632 } 2633 2634 perf_event_update_userpage(event); 2635 2636 return 0; 2637 } 2638 2639 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period); 2640 2641 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 2642 { 2643 u32 val; 2644 2645 /* 2646 * The metric is reported as an 8bit integer fraction 2647 * summing up to 0xff. 2648 * slots-in-metric = (Metric / 0xff) * slots 2649 */ 2650 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 2651 return mul_u64_u32_div(slots, val, 0xff); 2652 } 2653 2654 static u64 icl_get_topdown_value(struct perf_event *event, 2655 u64 slots, u64 metrics) 2656 { 2657 int idx = event->hw.idx; 2658 u64 delta; 2659 2660 if (is_metric_idx(idx)) 2661 delta = icl_get_metrics_event_value(metrics, slots, idx); 2662 else 2663 delta = slots; 2664 2665 return delta; 2666 } 2667 2668 static void __icl_update_topdown_event(struct perf_event *event, 2669 u64 slots, u64 metrics, 2670 u64 last_slots, u64 last_metrics) 2671 { 2672 u64 delta, last = 0; 2673 2674 delta = icl_get_topdown_value(event, slots, metrics); 2675 if (last_slots) 2676 last = icl_get_topdown_value(event, last_slots, last_metrics); 2677 2678 /* 2679 * The 8bit integer fraction of metric may be not accurate, 2680 * especially when the changes is very small. 2681 * For example, if only a few bad_spec happens, the fraction 2682 * may be reduced from 1 to 0. If so, the bad_spec event value 2683 * will be 0 which is definitely less than the last value. 2684 * Avoid update event->count for this case. 2685 */ 2686 if (delta > last) { 2687 delta -= last; 2688 local64_add(delta, &event->count); 2689 } 2690 } 2691 2692 static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 2693 u64 metrics, int metric_end) 2694 { 2695 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2696 struct perf_event *other; 2697 int idx; 2698 2699 event->hw.saved_slots = slots; 2700 event->hw.saved_metric = metrics; 2701 2702 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2703 if (!is_topdown_idx(idx)) 2704 continue; 2705 other = cpuc->events[idx]; 2706 other->hw.saved_slots = slots; 2707 other->hw.saved_metric = metrics; 2708 } 2709 } 2710 2711 /* 2712 * Update all active Topdown events. 2713 * 2714 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 2715 * modify by a NMI. PMU has to be disabled before calling this function. 2716 */ 2717 2718 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end, u64 *val) 2719 { 2720 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2721 struct perf_event *other; 2722 u64 slots, metrics; 2723 bool reset = true; 2724 int idx; 2725 2726 if (!val) { 2727 /* read Fixed counter 3 */ 2728 slots = rdpmc(3 | INTEL_PMC_FIXED_RDPMC_BASE); 2729 if (!slots) 2730 return 0; 2731 2732 /* read PERF_METRICS */ 2733 metrics = rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS); 2734 } else { 2735 slots = val[0]; 2736 metrics = val[1]; 2737 /* 2738 * Don't reset the PERF_METRICS and Fixed counter 3 2739 * for each PEBS record read. Utilize the RDPMC metrics 2740 * clear mode. 2741 */ 2742 reset = false; 2743 } 2744 2745 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2746 if (!is_topdown_idx(idx)) 2747 continue; 2748 other = cpuc->events[idx]; 2749 __icl_update_topdown_event(other, slots, metrics, 2750 event ? event->hw.saved_slots : 0, 2751 event ? event->hw.saved_metric : 0); 2752 } 2753 2754 /* 2755 * Check and update this event, which may have been cleared 2756 * in active_mask e.g. x86_pmu_stop() 2757 */ 2758 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 2759 __icl_update_topdown_event(event, slots, metrics, 2760 event->hw.saved_slots, 2761 event->hw.saved_metric); 2762 2763 /* 2764 * In x86_pmu_stop(), the event is cleared in active_mask first, 2765 * then drain the delta, which indicates context switch for 2766 * counting. 2767 * Save metric and slots for context switch. 2768 * Don't need to reset the PERF_METRICS and Fixed counter 3. 2769 * Because the values will be restored in next schedule in. 2770 */ 2771 update_saved_topdown_regs(event, slots, metrics, metric_end); 2772 reset = false; 2773 } 2774 2775 if (reset) { 2776 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 2777 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0); 2778 wrmsrq(MSR_PERF_METRICS, 0); 2779 if (event) 2780 update_saved_topdown_regs(event, 0, 0, metric_end); 2781 } 2782 2783 return slots; 2784 } 2785 2786 static u64 icl_update_topdown_event(struct perf_event *event, u64 *val) 2787 { 2788 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 2789 x86_pmu.num_topdown_events - 1, 2790 val); 2791 } 2792 2793 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, intel_pmu_topdown_event_update); 2794 2795 static void intel_pmu_read_event(struct perf_event *event) 2796 { 2797 if (event->hw.flags & (PERF_X86_EVENT_AUTO_RELOAD | PERF_X86_EVENT_TOPDOWN) || 2798 is_pebs_counter_event_group(event)) { 2799 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2800 bool pmu_enabled = cpuc->enabled; 2801 2802 /* Only need to call update_topdown_event() once for group read. */ 2803 if (is_metric_event(event) && (cpuc->txn_flags & PERF_PMU_TXN_READ)) 2804 return; 2805 2806 cpuc->enabled = 0; 2807 if (pmu_enabled) 2808 intel_pmu_disable_all(); 2809 2810 /* 2811 * If the PEBS counters snapshotting is enabled, 2812 * the topdown event is available in PEBS records. 2813 */ 2814 if (is_topdown_event(event) && !is_pebs_counter_event_group(event)) 2815 static_call(intel_pmu_update_topdown_event)(event, NULL); 2816 else 2817 intel_pmu_drain_pebs_buffer(); 2818 2819 cpuc->enabled = pmu_enabled; 2820 if (pmu_enabled) 2821 intel_pmu_enable_all(0); 2822 2823 return; 2824 } 2825 2826 x86_perf_event_update(event); 2827 } 2828 2829 static void intel_pmu_enable_fixed(struct perf_event *event) 2830 { 2831 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2832 struct hw_perf_event *hwc = &event->hw; 2833 u64 mask, bits = 0; 2834 int idx = hwc->idx; 2835 2836 if (is_topdown_idx(idx)) { 2837 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2838 /* 2839 * When there are other active TopDown events, 2840 * don't enable the fixed counter 3 again. 2841 */ 2842 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2843 return; 2844 2845 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2846 2847 if (event->attr.config1 & INTEL_TD_CFG_METRIC_CLEAR) 2848 bits |= INTEL_FIXED_3_METRICS_CLEAR; 2849 } 2850 2851 intel_set_masks(event, idx); 2852 2853 /* 2854 * Enable IRQ generation (0x8), if not PEBS, 2855 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2856 * if requested: 2857 */ 2858 if (!event->attr.precise_ip) 2859 bits |= INTEL_FIXED_0_ENABLE_PMI; 2860 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2861 bits |= INTEL_FIXED_0_USER; 2862 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2863 bits |= INTEL_FIXED_0_KERNEL; 2864 2865 /* 2866 * ANY bit is supported in v3 and up 2867 */ 2868 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2869 bits |= INTEL_FIXED_0_ANYTHREAD; 2870 2871 idx -= INTEL_PMC_IDX_FIXED; 2872 bits = intel_fixed_bits_by_idx(idx, bits); 2873 mask = intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK); 2874 2875 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2876 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); 2877 mask |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); 2878 } 2879 2880 cpuc->fixed_ctrl_val &= ~mask; 2881 cpuc->fixed_ctrl_val |= bits; 2882 } 2883 2884 static void intel_pmu_enable_event(struct perf_event *event) 2885 { 2886 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE; 2887 struct hw_perf_event *hwc = &event->hw; 2888 int idx = hwc->idx; 2889 2890 if (unlikely(event->attr.precise_ip)) 2891 intel_pmu_pebs_enable(event); 2892 2893 switch (idx) { 2894 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2895 if (branch_sample_counters(event)) 2896 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR; 2897 intel_set_masks(event, idx); 2898 __x86_pmu_enable_event(hwc, enable_mask); 2899 break; 2900 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2901 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2902 intel_pmu_enable_fixed(event); 2903 break; 2904 case INTEL_PMC_IDX_FIXED_BTS: 2905 if (!__this_cpu_read(cpu_hw_events.enabled)) 2906 return; 2907 intel_pmu_enable_bts(hwc->config); 2908 break; 2909 case INTEL_PMC_IDX_FIXED_VLBR: 2910 intel_set_masks(event, idx); 2911 break; 2912 default: 2913 pr_warn("Failed to enable the event with invalid index %d\n", 2914 idx); 2915 } 2916 } 2917 2918 static void intel_pmu_add_event(struct perf_event *event) 2919 { 2920 if (event->attr.precise_ip) 2921 intel_pmu_pebs_add(event); 2922 if (intel_pmu_needs_branch_stack(event)) 2923 intel_pmu_lbr_add(event); 2924 } 2925 2926 /* 2927 * Save and restart an expired event. Called by NMI contexts, 2928 * so it has to be careful about preempting normal event ops: 2929 */ 2930 int intel_pmu_save_and_restart(struct perf_event *event) 2931 { 2932 static_call(x86_pmu_update)(event); 2933 /* 2934 * For a checkpointed counter always reset back to 0. This 2935 * avoids a situation where the counter overflows, aborts the 2936 * transaction and is then set back to shortly before the 2937 * overflow, and overflows and aborts again. 2938 */ 2939 if (unlikely(event_is_checkpointed(event))) { 2940 /* No race with NMIs because the counter should not be armed */ 2941 wrmsrq(event->hw.event_base, 0); 2942 local64_set(&event->hw.prev_count, 0); 2943 } 2944 return static_call(x86_pmu_set_period)(event); 2945 } 2946 2947 static int intel_pmu_set_period(struct perf_event *event) 2948 { 2949 if (unlikely(is_topdown_count(event))) 2950 return static_call(intel_pmu_set_topdown_event_period)(event); 2951 2952 return x86_perf_event_set_period(event); 2953 } 2954 2955 static u64 intel_pmu_update(struct perf_event *event) 2956 { 2957 if (unlikely(is_topdown_count(event))) 2958 return static_call(intel_pmu_update_topdown_event)(event, NULL); 2959 2960 return x86_perf_event_update(event); 2961 } 2962 2963 static void intel_pmu_reset(void) 2964 { 2965 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2966 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2967 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask); 2968 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask); 2969 unsigned long flags; 2970 int idx; 2971 2972 if (!*(u64 *)cntr_mask) 2973 return; 2974 2975 local_irq_save(flags); 2976 2977 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2978 2979 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) { 2980 wrmsrq_safe(x86_pmu_config_addr(idx), 0ull); 2981 wrmsrq_safe(x86_pmu_event_addr(idx), 0ull); 2982 } 2983 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) { 2984 if (fixed_counter_disabled(idx, cpuc->pmu)) 2985 continue; 2986 wrmsrq_safe(x86_pmu_fixed_ctr_addr(idx), 0ull); 2987 } 2988 2989 if (ds) 2990 ds->bts_index = ds->bts_buffer_base; 2991 2992 /* Ack all overflows and disable fixed counters */ 2993 if (x86_pmu.version >= 2) { 2994 intel_pmu_ack_status(intel_pmu_get_status()); 2995 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2996 } 2997 2998 /* Reset LBRs and LBR freezing */ 2999 if (x86_pmu.lbr_nr) { 3000 update_debugctlmsr(get_debugctlmsr() & 3001 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 3002 } 3003 3004 local_irq_restore(flags); 3005 } 3006 3007 /* 3008 * We may be running with guest PEBS events created by KVM, and the 3009 * PEBS records are logged into the guest's DS and invisible to host. 3010 * 3011 * In the case of guest PEBS overflow, we only trigger a fake event 3012 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM. 3013 * The guest will then vm-entry and check the guest DS area to read 3014 * the guest PEBS records. 3015 * 3016 * The contents and other behavior of the guest event do not matter. 3017 */ 3018 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs, 3019 struct perf_sample_data *data) 3020 { 3021 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3022 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask; 3023 struct perf_event *event = NULL; 3024 int bit; 3025 3026 if (!unlikely(perf_guest_state())) 3027 return; 3028 3029 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active || 3030 !guest_pebs_idxs) 3031 return; 3032 3033 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) { 3034 event = cpuc->events[bit]; 3035 if (!event->attr.precise_ip) 3036 continue; 3037 3038 perf_sample_data_init(data, 0, event->hw.last_period); 3039 if (perf_event_overflow(event, data, regs)) 3040 x86_pmu_stop(event, 0); 3041 3042 /* Inject one fake event is enough. */ 3043 break; 3044 } 3045 } 3046 3047 static int handle_pmi_common(struct pt_regs *regs, u64 status) 3048 { 3049 struct perf_sample_data data; 3050 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3051 int bit; 3052 int handled = 0; 3053 3054 inc_irq_stat(apic_perf_irqs); 3055 3056 /* 3057 * Ignore a range of extra bits in status that do not indicate 3058 * overflow by themselves. 3059 */ 3060 status &= ~(GLOBAL_STATUS_COND_CHG | 3061 GLOBAL_STATUS_ASIF | 3062 GLOBAL_STATUS_LBRS_FROZEN); 3063 if (!status) 3064 return 0; 3065 /* 3066 * In case multiple PEBS events are sampled at the same time, 3067 * it is possible to have GLOBAL_STATUS bit 62 set indicating 3068 * PEBS buffer overflow and also seeing at most 3 PEBS counters 3069 * having their bits set in the status register. This is a sign 3070 * that there was at least one PEBS record pending at the time 3071 * of the PMU interrupt. PEBS counters must only be processed 3072 * via the drain_pebs() calls and not via the regular sample 3073 * processing loop coming after that the function, otherwise 3074 * phony regular samples may be generated in the sampling buffer 3075 * not marked with the EXACT tag. Another possibility is to have 3076 * one PEBS event and at least one non-PEBS event which overflows 3077 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 3078 * not be set, yet the overflow status bit for the PEBS counter will 3079 * be on Skylake. 3080 * 3081 * To avoid this problem, we systematically ignore the PEBS-enabled 3082 * counters from the GLOBAL_STATUS mask and we always process PEBS 3083 * events via drain_pebs(). 3084 */ 3085 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable); 3086 3087 /* 3088 * PEBS overflow sets bit 62 in the global status register 3089 */ 3090 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 3091 u64 pebs_enabled = cpuc->pebs_enabled; 3092 3093 handled++; 3094 x86_pmu_handle_guest_pebs(regs, &data); 3095 static_call(x86_pmu_drain_pebs)(regs, &data); 3096 3097 /* 3098 * PMI throttle may be triggered, which stops the PEBS event. 3099 * Although cpuc->pebs_enabled is updated accordingly, the 3100 * MSR_IA32_PEBS_ENABLE is not updated. Because the 3101 * cpuc->enabled has been forced to 0 in PMI. 3102 * Update the MSR if pebs_enabled is changed. 3103 */ 3104 if (pebs_enabled != cpuc->pebs_enabled) 3105 wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 3106 3107 /* 3108 * Above PEBS handler (PEBS counters snapshotting) has updated fixed 3109 * counter 3 and perf metrics counts if they are in counter group, 3110 * unnecessary to update again. 3111 */ 3112 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] && 3113 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS])) 3114 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT; 3115 } 3116 3117 /* 3118 * Intel PT 3119 */ 3120 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 3121 handled++; 3122 if (!perf_guest_handle_intel_pt_intr()) 3123 intel_pt_interrupt(); 3124 } 3125 3126 /* 3127 * Intel Perf metrics 3128 */ 3129 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 3130 handled++; 3131 static_call(intel_pmu_update_topdown_event)(NULL, NULL); 3132 } 3133 3134 status &= hybrid(cpuc->pmu, intel_ctrl); 3135 3136 /* 3137 * Checkpointed counters can lead to 'spurious' PMIs because the 3138 * rollback caused by the PMI will have cleared the overflow status 3139 * bit. Therefore always force probe these counters. 3140 */ 3141 status |= cpuc->intel_cp_status; 3142 3143 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 3144 struct perf_event *event = cpuc->events[bit]; 3145 3146 handled++; 3147 3148 if (!test_bit(bit, cpuc->active_mask)) 3149 continue; 3150 3151 /* 3152 * There may be unprocessed PEBS records in the PEBS buffer, 3153 * which still stores the previous values. 3154 * Process those records first before handling the latest value. 3155 * For example, 3156 * A is a regular counter 3157 * B is a PEBS event which reads A 3158 * C is a PEBS event 3159 * 3160 * The following can happen: 3161 * B-assist A=1 3162 * C A=2 3163 * B-assist A=3 3164 * A-overflow-PMI A=4 3165 * C-assist-PMI (PEBS buffer) A=5 3166 * 3167 * The PEBS buffer has to be drained before handling the A-PMI 3168 */ 3169 if (is_pebs_counter_event_group(event)) 3170 x86_pmu.drain_pebs(regs, &data); 3171 3172 if (!intel_pmu_save_and_restart(event)) 3173 continue; 3174 3175 perf_sample_data_init(&data, 0, event->hw.last_period); 3176 3177 if (has_branch_stack(event)) 3178 intel_pmu_lbr_save_brstack(&data, cpuc, event); 3179 3180 if (perf_event_overflow(event, &data, regs)) 3181 x86_pmu_stop(event, 0); 3182 } 3183 3184 return handled; 3185 } 3186 3187 /* 3188 * This handler is triggered by the local APIC, so the APIC IRQ handling 3189 * rules apply: 3190 */ 3191 static int intel_pmu_handle_irq(struct pt_regs *regs) 3192 { 3193 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3194 bool late_ack = hybrid_bit(cpuc->pmu, late_ack); 3195 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); 3196 int loops; 3197 u64 status; 3198 int handled; 3199 int pmu_enabled; 3200 3201 /* 3202 * Save the PMU state. 3203 * It needs to be restored when leaving the handler. 3204 */ 3205 pmu_enabled = cpuc->enabled; 3206 /* 3207 * In general, the early ACK is only applied for old platforms. 3208 * For the big core starts from Haswell, the late ACK should be 3209 * applied. 3210 * For the small core after Tremont, we have to do the ACK right 3211 * before re-enabling counters, which is in the middle of the 3212 * NMI handler. 3213 */ 3214 if (!late_ack && !mid_ack) 3215 apic_write(APIC_LVTPC, APIC_DM_NMI); 3216 intel_bts_disable_local(); 3217 cpuc->enabled = 0; 3218 __intel_pmu_disable_all(true); 3219 handled = intel_pmu_drain_bts_buffer(); 3220 handled += intel_bts_interrupt(); 3221 status = intel_pmu_get_status(); 3222 if (!status) 3223 goto done; 3224 3225 loops = 0; 3226 again: 3227 intel_pmu_lbr_read(); 3228 intel_pmu_ack_status(status); 3229 if (++loops > 100) { 3230 static bool warned; 3231 3232 if (!warned) { 3233 WARN(1, "perfevents: irq loop stuck!\n"); 3234 perf_event_print_debug(); 3235 warned = true; 3236 } 3237 intel_pmu_reset(); 3238 goto done; 3239 } 3240 3241 handled += handle_pmi_common(regs, status); 3242 3243 /* 3244 * Repeat if there is more work to be done: 3245 */ 3246 status = intel_pmu_get_status(); 3247 if (status) 3248 goto again; 3249 3250 done: 3251 if (mid_ack) 3252 apic_write(APIC_LVTPC, APIC_DM_NMI); 3253 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 3254 cpuc->enabled = pmu_enabled; 3255 if (pmu_enabled) 3256 __intel_pmu_enable_all(0, true); 3257 intel_bts_enable_local(); 3258 3259 /* 3260 * Only unmask the NMI after the overflow counters 3261 * have been reset. This avoids spurious NMIs on 3262 * Haswell CPUs. 3263 */ 3264 if (late_ack) 3265 apic_write(APIC_LVTPC, APIC_DM_NMI); 3266 return handled; 3267 } 3268 3269 static struct event_constraint * 3270 intel_bts_constraints(struct perf_event *event) 3271 { 3272 if (unlikely(intel_pmu_has_bts(event))) 3273 return &bts_constraint; 3274 3275 return NULL; 3276 } 3277 3278 /* 3279 * Note: matches a fake event, like Fixed2. 3280 */ 3281 static struct event_constraint * 3282 intel_vlbr_constraints(struct perf_event *event) 3283 { 3284 struct event_constraint *c = &vlbr_constraint; 3285 3286 if (unlikely(constraint_match(c, event->hw.config))) { 3287 event->hw.flags |= c->flags; 3288 return c; 3289 } 3290 3291 return NULL; 3292 } 3293 3294 static int intel_alt_er(struct cpu_hw_events *cpuc, 3295 int idx, u64 config) 3296 { 3297 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); 3298 int alt_idx = idx; 3299 3300 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 3301 return idx; 3302 3303 if (idx == EXTRA_REG_RSP_0) 3304 alt_idx = EXTRA_REG_RSP_1; 3305 3306 if (idx == EXTRA_REG_RSP_1) 3307 alt_idx = EXTRA_REG_RSP_0; 3308 3309 if (config & ~extra_regs[alt_idx].valid_mask) 3310 return idx; 3311 3312 return alt_idx; 3313 } 3314 3315 static void intel_fixup_er(struct perf_event *event, int idx) 3316 { 3317 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); 3318 event->hw.extra_reg.idx = idx; 3319 3320 if (idx == EXTRA_REG_RSP_0) { 3321 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3322 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event; 3323 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 3324 } else if (idx == EXTRA_REG_RSP_1) { 3325 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3326 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event; 3327 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 3328 } 3329 } 3330 3331 /* 3332 * manage allocation of shared extra msr for certain events 3333 * 3334 * sharing can be: 3335 * per-cpu: to be shared between the various events on a single PMU 3336 * per-core: per-cpu + shared by HT threads 3337 */ 3338 static struct event_constraint * 3339 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 3340 struct perf_event *event, 3341 struct hw_perf_event_extra *reg) 3342 { 3343 struct event_constraint *c = &emptyconstraint; 3344 struct er_account *era; 3345 unsigned long flags; 3346 int idx = reg->idx; 3347 3348 /* 3349 * reg->alloc can be set due to existing state, so for fake cpuc we 3350 * need to ignore this, otherwise we might fail to allocate proper fake 3351 * state for this extra reg constraint. Also see the comment below. 3352 */ 3353 if (reg->alloc && !cpuc->is_fake) 3354 return NULL; /* call x86_get_event_constraint() */ 3355 3356 again: 3357 era = &cpuc->shared_regs->regs[idx]; 3358 /* 3359 * we use spin_lock_irqsave() to avoid lockdep issues when 3360 * passing a fake cpuc 3361 */ 3362 raw_spin_lock_irqsave(&era->lock, flags); 3363 3364 if (!atomic_read(&era->ref) || era->config == reg->config) { 3365 3366 /* 3367 * If its a fake cpuc -- as per validate_{group,event}() we 3368 * shouldn't touch event state and we can avoid doing so 3369 * since both will only call get_event_constraints() once 3370 * on each event, this avoids the need for reg->alloc. 3371 * 3372 * Not doing the ER fixup will only result in era->reg being 3373 * wrong, but since we won't actually try and program hardware 3374 * this isn't a problem either. 3375 */ 3376 if (!cpuc->is_fake) { 3377 if (idx != reg->idx) 3378 intel_fixup_er(event, idx); 3379 3380 /* 3381 * x86_schedule_events() can call get_event_constraints() 3382 * multiple times on events in the case of incremental 3383 * scheduling(). reg->alloc ensures we only do the ER 3384 * allocation once. 3385 */ 3386 reg->alloc = 1; 3387 } 3388 3389 /* lock in msr value */ 3390 era->config = reg->config; 3391 era->reg = reg->reg; 3392 3393 /* one more user */ 3394 atomic_inc(&era->ref); 3395 3396 /* 3397 * need to call x86_get_event_constraint() 3398 * to check if associated event has constraints 3399 */ 3400 c = NULL; 3401 } else { 3402 idx = intel_alt_er(cpuc, idx, reg->config); 3403 if (idx != reg->idx) { 3404 raw_spin_unlock_irqrestore(&era->lock, flags); 3405 goto again; 3406 } 3407 } 3408 raw_spin_unlock_irqrestore(&era->lock, flags); 3409 3410 return c; 3411 } 3412 3413 static void 3414 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3415 struct hw_perf_event_extra *reg) 3416 { 3417 struct er_account *era; 3418 3419 /* 3420 * Only put constraint if extra reg was actually allocated. Also takes 3421 * care of event which do not use an extra shared reg. 3422 * 3423 * Also, if this is a fake cpuc we shouldn't touch any event state 3424 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3425 * either since it'll be thrown out. 3426 */ 3427 if (!reg->alloc || cpuc->is_fake) 3428 return; 3429 3430 era = &cpuc->shared_regs->regs[reg->idx]; 3431 3432 /* one fewer user */ 3433 atomic_dec(&era->ref); 3434 3435 /* allocate again next time */ 3436 reg->alloc = 0; 3437 } 3438 3439 static struct event_constraint * 3440 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3441 struct perf_event *event) 3442 { 3443 struct event_constraint *c = NULL, *d; 3444 struct hw_perf_event_extra *xreg, *breg; 3445 3446 xreg = &event->hw.extra_reg; 3447 if (xreg->idx != EXTRA_REG_NONE) { 3448 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3449 if (c == &emptyconstraint) 3450 return c; 3451 } 3452 breg = &event->hw.branch_reg; 3453 if (breg->idx != EXTRA_REG_NONE) { 3454 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3455 if (d == &emptyconstraint) { 3456 __intel_shared_reg_put_constraints(cpuc, xreg); 3457 c = d; 3458 } 3459 } 3460 return c; 3461 } 3462 3463 struct event_constraint * 3464 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3465 struct perf_event *event) 3466 { 3467 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); 3468 struct event_constraint *c; 3469 3470 if (event_constraints) { 3471 for_each_event_constraint(c, event_constraints) { 3472 if (constraint_match(c, event->hw.config)) { 3473 event->hw.flags |= c->flags; 3474 return c; 3475 } 3476 } 3477 } 3478 3479 return &hybrid_var(cpuc->pmu, unconstrained); 3480 } 3481 3482 static struct event_constraint * 3483 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3484 struct perf_event *event) 3485 { 3486 struct event_constraint *c; 3487 3488 c = intel_vlbr_constraints(event); 3489 if (c) 3490 return c; 3491 3492 c = intel_bts_constraints(event); 3493 if (c) 3494 return c; 3495 3496 c = intel_shared_regs_constraints(cpuc, event); 3497 if (c) 3498 return c; 3499 3500 c = intel_pebs_constraints(event); 3501 if (c) 3502 return c; 3503 3504 return x86_get_event_constraints(cpuc, idx, event); 3505 } 3506 3507 static void 3508 intel_start_scheduling(struct cpu_hw_events *cpuc) 3509 { 3510 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3511 struct intel_excl_states *xl; 3512 int tid = cpuc->excl_thread_id; 3513 3514 /* 3515 * nothing needed if in group validation mode 3516 */ 3517 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3518 return; 3519 3520 /* 3521 * no exclusion needed 3522 */ 3523 if (WARN_ON_ONCE(!excl_cntrs)) 3524 return; 3525 3526 xl = &excl_cntrs->states[tid]; 3527 3528 xl->sched_started = true; 3529 /* 3530 * lock shared state until we are done scheduling 3531 * in stop_event_scheduling() 3532 * makes scheduling appear as a transaction 3533 */ 3534 raw_spin_lock(&excl_cntrs->lock); 3535 } 3536 3537 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3538 { 3539 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3540 struct event_constraint *c = cpuc->event_constraint[idx]; 3541 struct intel_excl_states *xl; 3542 int tid = cpuc->excl_thread_id; 3543 3544 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3545 return; 3546 3547 if (WARN_ON_ONCE(!excl_cntrs)) 3548 return; 3549 3550 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3551 return; 3552 3553 xl = &excl_cntrs->states[tid]; 3554 3555 lockdep_assert_held(&excl_cntrs->lock); 3556 3557 if (c->flags & PERF_X86_EVENT_EXCL) 3558 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3559 else 3560 xl->state[cntr] = INTEL_EXCL_SHARED; 3561 } 3562 3563 static void 3564 intel_stop_scheduling(struct cpu_hw_events *cpuc) 3565 { 3566 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3567 struct intel_excl_states *xl; 3568 int tid = cpuc->excl_thread_id; 3569 3570 /* 3571 * nothing needed if in group validation mode 3572 */ 3573 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3574 return; 3575 /* 3576 * no exclusion needed 3577 */ 3578 if (WARN_ON_ONCE(!excl_cntrs)) 3579 return; 3580 3581 xl = &excl_cntrs->states[tid]; 3582 3583 xl->sched_started = false; 3584 /* 3585 * release shared state lock (acquired in intel_start_scheduling()) 3586 */ 3587 raw_spin_unlock(&excl_cntrs->lock); 3588 } 3589 3590 static struct event_constraint * 3591 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 3592 { 3593 WARN_ON_ONCE(!cpuc->constraint_list); 3594 3595 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 3596 struct event_constraint *cx; 3597 3598 /* 3599 * grab pre-allocated constraint entry 3600 */ 3601 cx = &cpuc->constraint_list[idx]; 3602 3603 /* 3604 * initialize dynamic constraint 3605 * with static constraint 3606 */ 3607 *cx = *c; 3608 3609 /* 3610 * mark constraint as dynamic 3611 */ 3612 cx->flags |= PERF_X86_EVENT_DYNAMIC; 3613 c = cx; 3614 } 3615 3616 return c; 3617 } 3618 3619 static struct event_constraint * 3620 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3621 int idx, struct event_constraint *c) 3622 { 3623 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3624 struct intel_excl_states *xlo; 3625 int tid = cpuc->excl_thread_id; 3626 int is_excl, i, w; 3627 3628 /* 3629 * validating a group does not require 3630 * enforcing cross-thread exclusion 3631 */ 3632 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3633 return c; 3634 3635 /* 3636 * no exclusion needed 3637 */ 3638 if (WARN_ON_ONCE(!excl_cntrs)) 3639 return c; 3640 3641 /* 3642 * because we modify the constraint, we need 3643 * to make a copy. Static constraints come 3644 * from static const tables. 3645 * 3646 * only needed when constraint has not yet 3647 * been cloned (marked dynamic) 3648 */ 3649 c = dyn_constraint(cpuc, c, idx); 3650 3651 /* 3652 * From here on, the constraint is dynamic. 3653 * Either it was just allocated above, or it 3654 * was allocated during a earlier invocation 3655 * of this function 3656 */ 3657 3658 /* 3659 * state of sibling HT 3660 */ 3661 xlo = &excl_cntrs->states[tid ^ 1]; 3662 3663 /* 3664 * event requires exclusive counter access 3665 * across HT threads 3666 */ 3667 is_excl = c->flags & PERF_X86_EVENT_EXCL; 3668 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3669 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3670 if (!cpuc->n_excl++) 3671 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3672 } 3673 3674 /* 3675 * Modify static constraint with current dynamic 3676 * state of thread 3677 * 3678 * EXCLUSIVE: sibling counter measuring exclusive event 3679 * SHARED : sibling counter measuring non-exclusive event 3680 * UNUSED : sibling counter unused 3681 */ 3682 w = c->weight; 3683 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3684 /* 3685 * exclusive event in sibling counter 3686 * our corresponding counter cannot be used 3687 * regardless of our event 3688 */ 3689 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3690 __clear_bit(i, c->idxmsk); 3691 w--; 3692 continue; 3693 } 3694 /* 3695 * if measuring an exclusive event, sibling 3696 * measuring non-exclusive, then counter cannot 3697 * be used 3698 */ 3699 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3700 __clear_bit(i, c->idxmsk); 3701 w--; 3702 continue; 3703 } 3704 } 3705 3706 /* 3707 * if we return an empty mask, then switch 3708 * back to static empty constraint to avoid 3709 * the cost of freeing later on 3710 */ 3711 if (!w) 3712 c = &emptyconstraint; 3713 3714 c->weight = w; 3715 3716 return c; 3717 } 3718 3719 static struct event_constraint * 3720 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3721 struct perf_event *event) 3722 { 3723 struct event_constraint *c1, *c2; 3724 3725 c1 = cpuc->event_constraint[idx]; 3726 3727 /* 3728 * first time only 3729 * - static constraint: no change across incremental scheduling calls 3730 * - dynamic constraint: handled by intel_get_excl_constraints() 3731 */ 3732 c2 = __intel_get_event_constraints(cpuc, idx, event); 3733 if (c1) { 3734 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3735 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3736 c1->weight = c2->weight; 3737 c2 = c1; 3738 } 3739 3740 if (cpuc->excl_cntrs) 3741 return intel_get_excl_constraints(cpuc, event, idx, c2); 3742 3743 /* Not all counters support the branch counter feature. */ 3744 if (branch_sample_counters(event)) { 3745 c2 = dyn_constraint(cpuc, c2, idx); 3746 c2->idxmsk64 &= x86_pmu.lbr_counters; 3747 c2->weight = hweight64(c2->idxmsk64); 3748 } 3749 3750 return c2; 3751 } 3752 3753 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3754 struct perf_event *event) 3755 { 3756 struct hw_perf_event *hwc = &event->hw; 3757 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3758 int tid = cpuc->excl_thread_id; 3759 struct intel_excl_states *xl; 3760 3761 /* 3762 * nothing needed if in group validation mode 3763 */ 3764 if (cpuc->is_fake) 3765 return; 3766 3767 if (WARN_ON_ONCE(!excl_cntrs)) 3768 return; 3769 3770 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3771 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3772 if (!--cpuc->n_excl) 3773 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3774 } 3775 3776 /* 3777 * If event was actually assigned, then mark the counter state as 3778 * unused now. 3779 */ 3780 if (hwc->idx >= 0) { 3781 xl = &excl_cntrs->states[tid]; 3782 3783 /* 3784 * put_constraint may be called from x86_schedule_events() 3785 * which already has the lock held so here make locking 3786 * conditional. 3787 */ 3788 if (!xl->sched_started) 3789 raw_spin_lock(&excl_cntrs->lock); 3790 3791 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3792 3793 if (!xl->sched_started) 3794 raw_spin_unlock(&excl_cntrs->lock); 3795 } 3796 } 3797 3798 static void 3799 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3800 struct perf_event *event) 3801 { 3802 struct hw_perf_event_extra *reg; 3803 3804 reg = &event->hw.extra_reg; 3805 if (reg->idx != EXTRA_REG_NONE) 3806 __intel_shared_reg_put_constraints(cpuc, reg); 3807 3808 reg = &event->hw.branch_reg; 3809 if (reg->idx != EXTRA_REG_NONE) 3810 __intel_shared_reg_put_constraints(cpuc, reg); 3811 } 3812 3813 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3814 struct perf_event *event) 3815 { 3816 intel_put_shared_regs_event_constraints(cpuc, event); 3817 3818 /* 3819 * is PMU has exclusive counter restrictions, then 3820 * all events are subject to and must call the 3821 * put_excl_constraints() routine 3822 */ 3823 if (cpuc->excl_cntrs) 3824 intel_put_excl_constraints(cpuc, event); 3825 } 3826 3827 static void intel_pebs_aliases_core2(struct perf_event *event) 3828 { 3829 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3830 /* 3831 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3832 * (0x003c) so that we can use it with PEBS. 3833 * 3834 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3835 * PEBS capable. However we can use INST_RETIRED.ANY_P 3836 * (0x00c0), which is a PEBS capable event, to get the same 3837 * count. 3838 * 3839 * INST_RETIRED.ANY_P counts the number of cycles that retires 3840 * CNTMASK instructions. By setting CNTMASK to a value (16) 3841 * larger than the maximum number of instructions that can be 3842 * retired per cycle (4) and then inverting the condition, we 3843 * count all cycles that retire 16 or less instructions, which 3844 * is every cycle. 3845 * 3846 * Thereby we gain a PEBS capable cycle counter. 3847 */ 3848 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3849 3850 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3851 event->hw.config = alt_config; 3852 } 3853 } 3854 3855 static void intel_pebs_aliases_snb(struct perf_event *event) 3856 { 3857 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3858 /* 3859 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3860 * (0x003c) so that we can use it with PEBS. 3861 * 3862 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3863 * PEBS capable. However we can use UOPS_RETIRED.ALL 3864 * (0x01c2), which is a PEBS capable event, to get the same 3865 * count. 3866 * 3867 * UOPS_RETIRED.ALL counts the number of cycles that retires 3868 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3869 * larger than the maximum number of micro-ops that can be 3870 * retired per cycle (4) and then inverting the condition, we 3871 * count all cycles that retire 16 or less micro-ops, which 3872 * is every cycle. 3873 * 3874 * Thereby we gain a PEBS capable cycle counter. 3875 */ 3876 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3877 3878 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3879 event->hw.config = alt_config; 3880 } 3881 } 3882 3883 static void intel_pebs_aliases_precdist(struct perf_event *event) 3884 { 3885 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3886 /* 3887 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3888 * (0x003c) so that we can use it with PEBS. 3889 * 3890 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3891 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3892 * (0x01c0), which is a PEBS capable event, to get the same 3893 * count. 3894 * 3895 * The PREC_DIST event has special support to minimize sample 3896 * shadowing effects. One drawback is that it can be 3897 * only programmed on counter 1, but that seems like an 3898 * acceptable trade off. 3899 */ 3900 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3901 3902 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3903 event->hw.config = alt_config; 3904 } 3905 } 3906 3907 static void intel_pebs_aliases_ivb(struct perf_event *event) 3908 { 3909 if (event->attr.precise_ip < 3) 3910 return intel_pebs_aliases_snb(event); 3911 return intel_pebs_aliases_precdist(event); 3912 } 3913 3914 static void intel_pebs_aliases_skl(struct perf_event *event) 3915 { 3916 if (event->attr.precise_ip < 3) 3917 return intel_pebs_aliases_core2(event); 3918 return intel_pebs_aliases_precdist(event); 3919 } 3920 3921 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3922 { 3923 unsigned long flags = x86_pmu.large_pebs_flags; 3924 3925 if (event->attr.use_clockid) 3926 flags &= ~PERF_SAMPLE_TIME; 3927 if (!event->attr.exclude_kernel) 3928 flags &= ~PERF_SAMPLE_REGS_USER; 3929 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3930 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3931 return flags; 3932 } 3933 3934 static int intel_pmu_bts_config(struct perf_event *event) 3935 { 3936 struct perf_event_attr *attr = &event->attr; 3937 3938 if (unlikely(intel_pmu_has_bts(event))) { 3939 /* BTS is not supported by this architecture. */ 3940 if (!x86_pmu.bts_active) 3941 return -EOPNOTSUPP; 3942 3943 /* BTS is currently only allowed for user-mode. */ 3944 if (!attr->exclude_kernel) 3945 return -EOPNOTSUPP; 3946 3947 /* BTS is not allowed for precise events. */ 3948 if (attr->precise_ip) 3949 return -EOPNOTSUPP; 3950 3951 /* disallow bts if conflicting events are present */ 3952 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3953 return -EBUSY; 3954 3955 event->destroy = hw_perf_lbr_event_destroy; 3956 } 3957 3958 return 0; 3959 } 3960 3961 static int core_pmu_hw_config(struct perf_event *event) 3962 { 3963 int ret = x86_pmu_hw_config(event); 3964 3965 if (ret) 3966 return ret; 3967 3968 return intel_pmu_bts_config(event); 3969 } 3970 3971 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 3972 ((x86_pmu.num_topdown_events - 1) << 8)) 3973 3974 static bool is_available_metric_event(struct perf_event *event) 3975 { 3976 return is_metric_event(event) && 3977 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 3978 } 3979 3980 static inline bool is_mem_loads_event(struct perf_event *event) 3981 { 3982 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 3983 } 3984 3985 static inline bool is_mem_loads_aux_event(struct perf_event *event) 3986 { 3987 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 3988 } 3989 3990 static inline bool require_mem_loads_aux_event(struct perf_event *event) 3991 { 3992 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) 3993 return false; 3994 3995 if (is_hybrid()) 3996 return hybrid_pmu(event->pmu)->pmu_type == hybrid_big; 3997 3998 return true; 3999 } 4000 4001 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) 4002 { 4003 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); 4004 4005 return test_bit(idx, (unsigned long *)&intel_cap->capabilities); 4006 } 4007 4008 static u64 intel_pmu_freq_start_period(struct perf_event *event) 4009 { 4010 int type = event->attr.type; 4011 u64 config, factor; 4012 s64 start; 4013 4014 /* 4015 * The 127 is the lowest possible recommended SAV (sample after value) 4016 * for a 4000 freq (default freq), according to the event list JSON file. 4017 * Also, assume the workload is idle 50% time. 4018 */ 4019 factor = 64 * 4000; 4020 if (type != PERF_TYPE_HARDWARE && type != PERF_TYPE_HW_CACHE) 4021 goto end; 4022 4023 /* 4024 * The estimation of the start period in the freq mode is 4025 * based on the below assumption. 4026 * 4027 * For a cycles or an instructions event, 1GHZ of the 4028 * underlying platform, 1 IPC. The workload is idle 50% time. 4029 * The start period = 1,000,000,000 * 1 / freq / 2. 4030 * = 500,000,000 / freq 4031 * 4032 * Usually, the branch-related events occur less than the 4033 * instructions event. According to the Intel event list JSON 4034 * file, the SAV (sample after value) of a branch-related event 4035 * is usually 1/4 of an instruction event. 4036 * The start period of branch-related events = 125,000,000 / freq. 4037 * 4038 * The cache-related events occurs even less. The SAV is usually 4039 * 1/20 of an instruction event. 4040 * The start period of cache-related events = 25,000,000 / freq. 4041 */ 4042 config = event->attr.config & PERF_HW_EVENT_MASK; 4043 if (type == PERF_TYPE_HARDWARE) { 4044 switch (config) { 4045 case PERF_COUNT_HW_CPU_CYCLES: 4046 case PERF_COUNT_HW_INSTRUCTIONS: 4047 case PERF_COUNT_HW_BUS_CYCLES: 4048 case PERF_COUNT_HW_STALLED_CYCLES_FRONTEND: 4049 case PERF_COUNT_HW_STALLED_CYCLES_BACKEND: 4050 case PERF_COUNT_HW_REF_CPU_CYCLES: 4051 factor = 500000000; 4052 break; 4053 case PERF_COUNT_HW_BRANCH_INSTRUCTIONS: 4054 case PERF_COUNT_HW_BRANCH_MISSES: 4055 factor = 125000000; 4056 break; 4057 case PERF_COUNT_HW_CACHE_REFERENCES: 4058 case PERF_COUNT_HW_CACHE_MISSES: 4059 factor = 25000000; 4060 break; 4061 default: 4062 goto end; 4063 } 4064 } 4065 4066 if (type == PERF_TYPE_HW_CACHE) 4067 factor = 25000000; 4068 end: 4069 /* 4070 * Usually, a prime or a number with less factors (close to prime) 4071 * is chosen as an SAV, which makes it less likely that the sampling 4072 * period synchronizes with some periodic event in the workload. 4073 * Minus 1 to make it at least avoiding values near power of twos 4074 * for the default freq. 4075 */ 4076 start = DIV_ROUND_UP_ULL(factor, event->attr.sample_freq) - 1; 4077 4078 if (start > x86_pmu.max_period) 4079 start = x86_pmu.max_period; 4080 4081 if (x86_pmu.limit_period) 4082 x86_pmu.limit_period(event, &start); 4083 4084 return start; 4085 } 4086 4087 static int intel_pmu_hw_config(struct perf_event *event) 4088 { 4089 int ret = x86_pmu_hw_config(event); 4090 4091 if (ret) 4092 return ret; 4093 4094 ret = intel_pmu_bts_config(event); 4095 if (ret) 4096 return ret; 4097 4098 if (event->attr.freq && event->attr.sample_freq) { 4099 event->hw.sample_period = intel_pmu_freq_start_period(event); 4100 event->hw.last_period = event->hw.sample_period; 4101 local64_set(&event->hw.period_left, event->hw.sample_period); 4102 } 4103 4104 if (event->attr.precise_ip) { 4105 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) 4106 return -EINVAL; 4107 4108 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 4109 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 4110 if (!(event->attr.sample_type & ~intel_pmu_large_pebs_flags(event)) && 4111 !has_aux_action(event)) { 4112 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 4113 event->attach_state |= PERF_ATTACH_SCHED_CB; 4114 } 4115 } 4116 if (x86_pmu.pebs_aliases) 4117 x86_pmu.pebs_aliases(event); 4118 } 4119 4120 if (needs_branch_stack(event)) { 4121 /* Avoid branch stack setup for counting events in SAMPLE READ */ 4122 if (is_sampling_event(event) || 4123 !(event->attr.sample_type & PERF_SAMPLE_READ)) 4124 event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK; 4125 } 4126 4127 if (branch_sample_counters(event)) { 4128 struct perf_event *leader, *sibling; 4129 int num = 0; 4130 4131 if (!(x86_pmu.flags & PMU_FL_BR_CNTR) || 4132 (event->attr.config & ~INTEL_ARCH_EVENT_MASK)) 4133 return -EINVAL; 4134 4135 /* 4136 * The branch counter logging is not supported in the call stack 4137 * mode yet, since we cannot simply flush the LBR during e.g., 4138 * multiplexing. Also, there is no obvious usage with the call 4139 * stack mode. Simply forbids it for now. 4140 * 4141 * If any events in the group enable the branch counter logging 4142 * feature, the group is treated as a branch counter logging 4143 * group, which requires the extra space to store the counters. 4144 */ 4145 leader = event->group_leader; 4146 if (branch_sample_call_stack(leader)) 4147 return -EINVAL; 4148 if (branch_sample_counters(leader)) 4149 num++; 4150 leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS; 4151 4152 for_each_sibling_event(sibling, leader) { 4153 if (branch_sample_call_stack(sibling)) 4154 return -EINVAL; 4155 if (branch_sample_counters(sibling)) 4156 num++; 4157 } 4158 4159 if (num > fls(x86_pmu.lbr_counters)) 4160 return -EINVAL; 4161 /* 4162 * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't 4163 * require any branch stack setup. 4164 * Clear the bit to avoid unnecessary branch stack setup. 4165 */ 4166 if (0 == (event->attr.branch_sample_type & 4167 ~(PERF_SAMPLE_BRANCH_PLM_ALL | 4168 PERF_SAMPLE_BRANCH_COUNTERS))) 4169 event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK; 4170 4171 /* 4172 * Force the leader to be a LBR event. So LBRs can be reset 4173 * with the leader event. See intel_pmu_lbr_del() for details. 4174 */ 4175 if (!intel_pmu_needs_branch_stack(leader)) 4176 return -EINVAL; 4177 } 4178 4179 if (intel_pmu_needs_branch_stack(event)) { 4180 ret = intel_pmu_setup_lbr_filter(event); 4181 if (ret) 4182 return ret; 4183 event->attach_state |= PERF_ATTACH_SCHED_CB; 4184 4185 /* 4186 * BTS is set up earlier in this path, so don't account twice 4187 */ 4188 if (!unlikely(intel_pmu_has_bts(event))) { 4189 /* disallow lbr if conflicting events are present */ 4190 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 4191 return -EBUSY; 4192 4193 event->destroy = hw_perf_lbr_event_destroy; 4194 } 4195 } 4196 4197 if (event->attr.aux_output) { 4198 if (!event->attr.precise_ip) 4199 return -EINVAL; 4200 4201 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 4202 } 4203 4204 if ((event->attr.sample_type & PERF_SAMPLE_READ) && 4205 (x86_pmu.intel_cap.pebs_format >= 6) && 4206 x86_pmu.intel_cap.pebs_baseline && 4207 is_sampling_event(event) && 4208 event->attr.precise_ip) 4209 event->group_leader->hw.flags |= PERF_X86_EVENT_PEBS_CNTR; 4210 4211 if ((event->attr.type == PERF_TYPE_HARDWARE) || 4212 (event->attr.type == PERF_TYPE_HW_CACHE)) 4213 return 0; 4214 4215 /* 4216 * Config Topdown slots and metric events 4217 * 4218 * The slots event on Fixed Counter 3 can support sampling, 4219 * which will be handled normally in x86_perf_event_update(). 4220 * 4221 * Metric events don't support sampling and require being paired 4222 * with a slots event as group leader. When the slots event 4223 * is used in a metrics group, it too cannot support sampling. 4224 */ 4225 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { 4226 /* The metrics_clear can only be set for the slots event */ 4227 if (event->attr.config1 && 4228 (!is_slots_event(event) || (event->attr.config1 & ~INTEL_TD_CFG_METRIC_CLEAR))) 4229 return -EINVAL; 4230 4231 if (event->attr.config2) 4232 return -EINVAL; 4233 4234 /* 4235 * The TopDown metrics events and slots event don't 4236 * support any filters. 4237 */ 4238 if (event->attr.config & X86_ALL_EVENT_FLAGS) 4239 return -EINVAL; 4240 4241 if (is_available_metric_event(event)) { 4242 struct perf_event *leader = event->group_leader; 4243 4244 /* The metric events don't support sampling. */ 4245 if (is_sampling_event(event)) 4246 return -EINVAL; 4247 4248 /* The metric events require a slots group leader. */ 4249 if (!is_slots_event(leader)) 4250 return -EINVAL; 4251 4252 /* 4253 * The leader/SLOTS must not be a sampling event for 4254 * metric use; hardware requires it starts at 0 when used 4255 * in conjunction with MSR_PERF_METRICS. 4256 */ 4257 if (is_sampling_event(leader)) 4258 return -EINVAL; 4259 4260 event->event_caps |= PERF_EV_CAP_SIBLING; 4261 /* 4262 * Only once we have a METRICs sibling do we 4263 * need TopDown magic. 4264 */ 4265 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 4266 event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 4267 } 4268 } 4269 4270 /* 4271 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 4272 * doesn't function quite right. As a work-around it needs to always be 4273 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 4274 * The actual count of this second event is irrelevant it just needs 4275 * to be active to make the first event function correctly. 4276 * 4277 * In a group, the auxiliary event must be in front of the load latency 4278 * event. The rule is to simplify the implementation of the check. 4279 * That's because perf cannot have a complete group at the moment. 4280 */ 4281 if (require_mem_loads_aux_event(event) && 4282 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 4283 is_mem_loads_event(event)) { 4284 struct perf_event *leader = event->group_leader; 4285 struct perf_event *sibling = NULL; 4286 4287 /* 4288 * When this memload event is also the first event (no group 4289 * exists yet), then there is no aux event before it. 4290 */ 4291 if (leader == event) 4292 return -ENODATA; 4293 4294 if (!is_mem_loads_aux_event(leader)) { 4295 for_each_sibling_event(sibling, leader) { 4296 if (is_mem_loads_aux_event(sibling)) 4297 break; 4298 } 4299 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 4300 return -ENODATA; 4301 } 4302 } 4303 4304 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 4305 return 0; 4306 4307 if (x86_pmu.version < 3) 4308 return -EINVAL; 4309 4310 ret = perf_allow_cpu(); 4311 if (ret) 4312 return ret; 4313 4314 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 4315 4316 return 0; 4317 } 4318 4319 /* 4320 * Currently, the only caller of this function is the atomic_switch_perf_msrs(). 4321 * The host perf context helps to prepare the values of the real hardware for 4322 * a set of msrs that need to be switched atomically in a vmx transaction. 4323 * 4324 * For example, the pseudocode needed to add a new msr should look like: 4325 * 4326 * arr[(*nr)++] = (struct perf_guest_switch_msr){ 4327 * .msr = the hardware msr address, 4328 * .host = the value the hardware has when it doesn't run a guest, 4329 * .guest = the value the hardware has when it runs a guest, 4330 * }; 4331 * 4332 * These values have nothing to do with the emulated values the guest sees 4333 * when it uses {RD,WR}MSR, which should be handled by the KVM context, 4334 * specifically in the intel_pmu_{get,set}_msr(). 4335 */ 4336 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) 4337 { 4338 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4339 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4340 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data; 4341 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 4342 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; 4343 int global_ctrl, pebs_enable; 4344 4345 /* 4346 * In addition to obeying exclude_guest/exclude_host, remove bits being 4347 * used for PEBS when running a guest, because PEBS writes to virtual 4348 * addresses (not physical addresses). 4349 */ 4350 *nr = 0; 4351 global_ctrl = (*nr)++; 4352 arr[global_ctrl] = (struct perf_guest_switch_msr){ 4353 .msr = MSR_CORE_PERF_GLOBAL_CTRL, 4354 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask, 4355 .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask, 4356 }; 4357 4358 if (!x86_pmu.pebs) 4359 return arr; 4360 4361 /* 4362 * If PMU counter has PEBS enabled it is not enough to 4363 * disable counter on a guest entry since PEBS memory 4364 * write can overshoot guest entry and corrupt guest 4365 * memory. Disabling PEBS solves the problem. 4366 * 4367 * Don't do this if the CPU already enforces it. 4368 */ 4369 if (x86_pmu.pebs_no_isolation) { 4370 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4371 .msr = MSR_IA32_PEBS_ENABLE, 4372 .host = cpuc->pebs_enabled, 4373 .guest = 0, 4374 }; 4375 return arr; 4376 } 4377 4378 if (!kvm_pmu || !x86_pmu.pebs_ept) 4379 return arr; 4380 4381 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4382 .msr = MSR_IA32_DS_AREA, 4383 .host = (unsigned long)cpuc->ds, 4384 .guest = kvm_pmu->ds_area, 4385 }; 4386 4387 if (x86_pmu.intel_cap.pebs_baseline) { 4388 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4389 .msr = MSR_PEBS_DATA_CFG, 4390 .host = cpuc->active_pebs_data_cfg, 4391 .guest = kvm_pmu->pebs_data_cfg, 4392 }; 4393 } 4394 4395 pebs_enable = (*nr)++; 4396 arr[pebs_enable] = (struct perf_guest_switch_msr){ 4397 .msr = MSR_IA32_PEBS_ENABLE, 4398 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask, 4399 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask & kvm_pmu->pebs_enable, 4400 }; 4401 4402 if (arr[pebs_enable].host) { 4403 /* Disable guest PEBS if host PEBS is enabled. */ 4404 arr[pebs_enable].guest = 0; 4405 } else { 4406 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */ 4407 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask; 4408 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask; 4409 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ 4410 arr[global_ctrl].guest |= arr[pebs_enable].guest; 4411 } 4412 4413 return arr; 4414 } 4415 4416 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data) 4417 { 4418 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4419 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4420 int idx; 4421 4422 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { 4423 struct perf_event *event = cpuc->events[idx]; 4424 4425 arr[idx].msr = x86_pmu_config_addr(idx); 4426 arr[idx].host = arr[idx].guest = 0; 4427 4428 if (!test_bit(idx, cpuc->active_mask)) 4429 continue; 4430 4431 arr[idx].host = arr[idx].guest = 4432 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 4433 4434 if (event->attr.exclude_host) 4435 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4436 else if (event->attr.exclude_guest) 4437 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4438 } 4439 4440 *nr = x86_pmu_max_num_counters(cpuc->pmu); 4441 return arr; 4442 } 4443 4444 static void core_pmu_enable_event(struct perf_event *event) 4445 { 4446 if (!event->attr.exclude_host) 4447 x86_pmu_enable_event(event); 4448 } 4449 4450 static void core_pmu_enable_all(int added) 4451 { 4452 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4453 int idx; 4454 4455 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { 4456 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 4457 4458 if (!test_bit(idx, cpuc->active_mask) || 4459 cpuc->events[idx]->attr.exclude_host) 4460 continue; 4461 4462 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 4463 } 4464 } 4465 4466 static int hsw_hw_config(struct perf_event *event) 4467 { 4468 int ret = intel_pmu_hw_config(event); 4469 4470 if (ret) 4471 return ret; 4472 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 4473 return 0; 4474 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 4475 4476 /* 4477 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 4478 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 4479 * this combination. 4480 */ 4481 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 4482 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 4483 event->attr.precise_ip > 0)) 4484 return -EOPNOTSUPP; 4485 4486 if (event_is_checkpointed(event)) { 4487 /* 4488 * Sampling of checkpointed events can cause situations where 4489 * the CPU constantly aborts because of a overflow, which is 4490 * then checkpointed back and ignored. Forbid checkpointing 4491 * for sampling. 4492 * 4493 * But still allow a long sampling period, so that perf stat 4494 * from KVM works. 4495 */ 4496 if (event->attr.sample_period > 0 && 4497 event->attr.sample_period < 0x7fffffff) 4498 return -EOPNOTSUPP; 4499 } 4500 return 0; 4501 } 4502 4503 static struct event_constraint counter0_constraint = 4504 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 4505 4506 static struct event_constraint counter1_constraint = 4507 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2); 4508 4509 static struct event_constraint counter0_1_constraint = 4510 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3); 4511 4512 static struct event_constraint counter2_constraint = 4513 EVENT_CONSTRAINT(0, 0x4, 0); 4514 4515 static struct event_constraint fixed0_constraint = 4516 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 4517 4518 static struct event_constraint fixed0_counter0_constraint = 4519 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 4520 4521 static struct event_constraint fixed0_counter0_1_constraint = 4522 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL); 4523 4524 static struct event_constraint counters_1_7_constraint = 4525 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL); 4526 4527 static struct event_constraint * 4528 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4529 struct perf_event *event) 4530 { 4531 struct event_constraint *c; 4532 4533 c = intel_get_event_constraints(cpuc, idx, event); 4534 4535 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 4536 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 4537 if (c->idxmsk64 & (1U << 2)) 4538 return &counter2_constraint; 4539 return &emptyconstraint; 4540 } 4541 4542 return c; 4543 } 4544 4545 static struct event_constraint * 4546 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4547 struct perf_event *event) 4548 { 4549 /* 4550 * Fixed counter 0 has less skid. 4551 * Force instruction:ppp in Fixed counter 0 4552 */ 4553 if ((event->attr.precise_ip == 3) && 4554 constraint_match(&fixed0_constraint, event->hw.config)) 4555 return &fixed0_constraint; 4556 4557 return hsw_get_event_constraints(cpuc, idx, event); 4558 } 4559 4560 static struct event_constraint * 4561 glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4562 struct perf_event *event) 4563 { 4564 struct event_constraint *c; 4565 4566 c = icl_get_event_constraints(cpuc, idx, event); 4567 4568 /* 4569 * The :ppp indicates the Precise Distribution (PDist) facility, which 4570 * is only supported on the GP counter 0. If a :ppp event which is not 4571 * available on the GP counter 0, error out. 4572 * Exception: Instruction PDIR is only available on the fixed counter 0. 4573 */ 4574 if ((event->attr.precise_ip == 3) && 4575 !constraint_match(&fixed0_constraint, event->hw.config)) { 4576 if (c->idxmsk64 & BIT_ULL(0)) 4577 return &counter0_constraint; 4578 4579 return &emptyconstraint; 4580 } 4581 4582 return c; 4583 } 4584 4585 static struct event_constraint * 4586 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4587 struct perf_event *event) 4588 { 4589 struct event_constraint *c; 4590 4591 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 4592 if (event->attr.precise_ip == 3) 4593 return &counter0_constraint; 4594 4595 c = intel_get_event_constraints(cpuc, idx, event); 4596 4597 return c; 4598 } 4599 4600 static struct event_constraint * 4601 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4602 struct perf_event *event) 4603 { 4604 struct event_constraint *c; 4605 4606 c = intel_get_event_constraints(cpuc, idx, event); 4607 4608 /* 4609 * :ppp means to do reduced skid PEBS, 4610 * which is available on PMC0 and fixed counter 0. 4611 */ 4612 if (event->attr.precise_ip == 3) { 4613 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 4614 if (constraint_match(&fixed0_constraint, event->hw.config)) 4615 return &fixed0_counter0_constraint; 4616 4617 return &counter0_constraint; 4618 } 4619 4620 return c; 4621 } 4622 4623 static bool allow_tsx_force_abort = true; 4624 4625 static struct event_constraint * 4626 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4627 struct perf_event *event) 4628 { 4629 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 4630 4631 /* 4632 * Without TFA we must not use PMC3. 4633 */ 4634 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 4635 c = dyn_constraint(cpuc, c, idx); 4636 c->idxmsk64 &= ~(1ULL << 3); 4637 c->weight--; 4638 } 4639 4640 return c; 4641 } 4642 4643 static struct event_constraint * 4644 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4645 struct perf_event *event) 4646 { 4647 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4648 4649 if (pmu->pmu_type == hybrid_big) 4650 return glc_get_event_constraints(cpuc, idx, event); 4651 else if (pmu->pmu_type == hybrid_small) 4652 return tnt_get_event_constraints(cpuc, idx, event); 4653 4654 WARN_ON(1); 4655 return &emptyconstraint; 4656 } 4657 4658 static struct event_constraint * 4659 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4660 struct perf_event *event) 4661 { 4662 struct event_constraint *c; 4663 4664 c = intel_get_event_constraints(cpuc, idx, event); 4665 4666 /* 4667 * The :ppp indicates the Precise Distribution (PDist) facility, which 4668 * is only supported on the GP counter 0 & 1 and Fixed counter 0. 4669 * If a :ppp event which is not available on the above eligible counters, 4670 * error out. 4671 */ 4672 if (event->attr.precise_ip == 3) { 4673 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */ 4674 if (constraint_match(&fixed0_constraint, event->hw.config)) { 4675 /* The fixed counter 0 doesn't support LBR event logging. */ 4676 if (branch_sample_counters(event)) 4677 return &counter0_1_constraint; 4678 else 4679 return &fixed0_counter0_1_constraint; 4680 } 4681 4682 switch (c->idxmsk64 & 0x3ull) { 4683 case 0x1: 4684 return &counter0_constraint; 4685 case 0x2: 4686 return &counter1_constraint; 4687 case 0x3: 4688 return &counter0_1_constraint; 4689 } 4690 return &emptyconstraint; 4691 } 4692 4693 return c; 4694 } 4695 4696 static struct event_constraint * 4697 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4698 struct perf_event *event) 4699 { 4700 struct event_constraint *c; 4701 4702 c = glc_get_event_constraints(cpuc, idx, event); 4703 4704 /* The Retire Latency is not supported by the fixed counter 0. */ 4705 if (event->attr.precise_ip && 4706 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) && 4707 constraint_match(&fixed0_constraint, event->hw.config)) { 4708 /* 4709 * The Instruction PDIR is only available 4710 * on the fixed counter 0. Error out for this case. 4711 */ 4712 if (event->attr.precise_ip == 3) 4713 return &emptyconstraint; 4714 return &counters_1_7_constraint; 4715 } 4716 4717 return c; 4718 } 4719 4720 static struct event_constraint * 4721 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4722 struct perf_event *event) 4723 { 4724 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4725 4726 if (pmu->pmu_type == hybrid_big) 4727 return rwc_get_event_constraints(cpuc, idx, event); 4728 if (pmu->pmu_type == hybrid_small) 4729 return cmt_get_event_constraints(cpuc, idx, event); 4730 4731 WARN_ON(1); 4732 return &emptyconstraint; 4733 } 4734 4735 static int adl_hw_config(struct perf_event *event) 4736 { 4737 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4738 4739 if (pmu->pmu_type == hybrid_big) 4740 return hsw_hw_config(event); 4741 else if (pmu->pmu_type == hybrid_small) 4742 return intel_pmu_hw_config(event); 4743 4744 WARN_ON(1); 4745 return -EOPNOTSUPP; 4746 } 4747 4748 static enum intel_cpu_type adl_get_hybrid_cpu_type(void) 4749 { 4750 return INTEL_CPU_TYPE_CORE; 4751 } 4752 4753 static inline bool erratum_hsw11(struct perf_event *event) 4754 { 4755 return (event->hw.config & INTEL_ARCH_EVENT_MASK) == 4756 X86_CONFIG(.event=0xc0, .umask=0x01); 4757 } 4758 4759 static struct event_constraint * 4760 arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4761 struct perf_event *event) 4762 { 4763 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4764 4765 if (pmu->pmu_type == hybrid_tiny) 4766 return cmt_get_event_constraints(cpuc, idx, event); 4767 4768 return mtl_get_event_constraints(cpuc, idx, event); 4769 } 4770 4771 static int arl_h_hw_config(struct perf_event *event) 4772 { 4773 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4774 4775 if (pmu->pmu_type == hybrid_tiny) 4776 return intel_pmu_hw_config(event); 4777 4778 return adl_hw_config(event); 4779 } 4780 4781 /* 4782 * The HSW11 requires a period larger than 100 which is the same as the BDM11. 4783 * A minimum period of 128 is enforced as well for the INST_RETIRED.ALL. 4784 * 4785 * The message 'interrupt took too long' can be observed on any counter which 4786 * was armed with a period < 32 and two events expired in the same NMI. 4787 * A minimum period of 32 is enforced for the rest of the events. 4788 */ 4789 static void hsw_limit_period(struct perf_event *event, s64 *left) 4790 { 4791 *left = max(*left, erratum_hsw11(event) ? 128 : 32); 4792 } 4793 4794 /* 4795 * Broadwell: 4796 * 4797 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 4798 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 4799 * the two to enforce a minimum period of 128 (the smallest value that has bits 4800 * 0-5 cleared and >= 100). 4801 * 4802 * Because of how the code in x86_perf_event_set_period() works, the truncation 4803 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 4804 * to make up for the 'lost' events due to carrying the 'error' in period_left. 4805 * 4806 * Therefore the effective (average) period matches the requested period, 4807 * despite coarser hardware granularity. 4808 */ 4809 static void bdw_limit_period(struct perf_event *event, s64 *left) 4810 { 4811 if (erratum_hsw11(event)) { 4812 if (*left < 128) 4813 *left = 128; 4814 *left &= ~0x3fULL; 4815 } 4816 } 4817 4818 static void nhm_limit_period(struct perf_event *event, s64 *left) 4819 { 4820 *left = max(*left, 32LL); 4821 } 4822 4823 static void glc_limit_period(struct perf_event *event, s64 *left) 4824 { 4825 if (event->attr.precise_ip == 3) 4826 *left = max(*left, 128LL); 4827 } 4828 4829 PMU_FORMAT_ATTR(event, "config:0-7" ); 4830 PMU_FORMAT_ATTR(umask, "config:8-15" ); 4831 PMU_FORMAT_ATTR(edge, "config:18" ); 4832 PMU_FORMAT_ATTR(pc, "config:19" ); 4833 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 4834 PMU_FORMAT_ATTR(inv, "config:23" ); 4835 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 4836 PMU_FORMAT_ATTR(in_tx, "config:32" ); 4837 PMU_FORMAT_ATTR(in_tx_cp, "config:33" ); 4838 PMU_FORMAT_ATTR(eq, "config:36" ); /* v6 + */ 4839 4840 PMU_FORMAT_ATTR(metrics_clear, "config1:0"); /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */ 4841 4842 static ssize_t umask2_show(struct device *dev, 4843 struct device_attribute *attr, 4844 char *page) 4845 { 4846 u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2; 4847 4848 if (mask == ARCH_PERFMON_EVENTSEL_UMASK2) 4849 return sprintf(page, "config:8-15,40-47\n"); 4850 4851 /* Roll back to the old format if umask2 is not supported. */ 4852 return sprintf(page, "config:8-15\n"); 4853 } 4854 4855 static struct device_attribute format_attr_umask2 = 4856 __ATTR(umask, 0444, umask2_show, NULL); 4857 4858 static struct attribute *format_evtsel_ext_attrs[] = { 4859 &format_attr_umask2.attr, 4860 &format_attr_eq.attr, 4861 &format_attr_metrics_clear.attr, 4862 NULL 4863 }; 4864 4865 static umode_t 4866 evtsel_ext_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4867 { 4868 struct device *dev = kobj_to_dev(kobj); 4869 u64 mask; 4870 4871 /* 4872 * The umask and umask2 have different formats but share the 4873 * same attr name. In update mode, the previous value of the 4874 * umask is unconditionally removed before is_visible. If 4875 * umask2 format is not enumerated, it's impossible to roll 4876 * back to the old format. 4877 * Does the check in umask2_show rather than is_visible. 4878 */ 4879 if (i == 0) 4880 return attr->mode; 4881 4882 mask = hybrid(dev_get_drvdata(dev), config_mask); 4883 if (i == 1) 4884 return (mask & ARCH_PERFMON_EVENTSEL_EQ) ? attr->mode : 0; 4885 4886 /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */ 4887 if (i == 2) { 4888 union perf_capabilities intel_cap = hybrid(dev_get_drvdata(dev), intel_cap); 4889 4890 return intel_cap.rdpmc_metrics_clear ? attr->mode : 0; 4891 } 4892 4893 return 0; 4894 } 4895 4896 static struct attribute *intel_arch_formats_attr[] = { 4897 &format_attr_event.attr, 4898 &format_attr_umask.attr, 4899 &format_attr_edge.attr, 4900 &format_attr_pc.attr, 4901 &format_attr_inv.attr, 4902 &format_attr_cmask.attr, 4903 NULL, 4904 }; 4905 4906 ssize_t intel_event_sysfs_show(char *page, u64 config) 4907 { 4908 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 4909 4910 return x86_event_sysfs_show(page, config, event); 4911 } 4912 4913 static struct intel_shared_regs *allocate_shared_regs(int cpu) 4914 { 4915 struct intel_shared_regs *regs; 4916 int i; 4917 4918 regs = kzalloc_node(sizeof(struct intel_shared_regs), 4919 GFP_KERNEL, cpu_to_node(cpu)); 4920 if (regs) { 4921 /* 4922 * initialize the locks to keep lockdep happy 4923 */ 4924 for (i = 0; i < EXTRA_REG_MAX; i++) 4925 raw_spin_lock_init(®s->regs[i].lock); 4926 4927 regs->core_id = -1; 4928 } 4929 return regs; 4930 } 4931 4932 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 4933 { 4934 struct intel_excl_cntrs *c; 4935 4936 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 4937 GFP_KERNEL, cpu_to_node(cpu)); 4938 if (c) { 4939 raw_spin_lock_init(&c->lock); 4940 c->core_id = -1; 4941 } 4942 return c; 4943 } 4944 4945 4946 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 4947 { 4948 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 4949 4950 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 4951 cpuc->shared_regs = allocate_shared_regs(cpu); 4952 if (!cpuc->shared_regs) 4953 goto err; 4954 } 4955 4956 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_BR_CNTR)) { 4957 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 4958 4959 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 4960 if (!cpuc->constraint_list) 4961 goto err_shared_regs; 4962 } 4963 4964 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4965 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 4966 if (!cpuc->excl_cntrs) 4967 goto err_constraint_list; 4968 4969 cpuc->excl_thread_id = 0; 4970 } 4971 4972 return 0; 4973 4974 err_constraint_list: 4975 kfree(cpuc->constraint_list); 4976 cpuc->constraint_list = NULL; 4977 4978 err_shared_regs: 4979 kfree(cpuc->shared_regs); 4980 cpuc->shared_regs = NULL; 4981 4982 err: 4983 return -ENOMEM; 4984 } 4985 4986 static int intel_pmu_cpu_prepare(int cpu) 4987 { 4988 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 4989 } 4990 4991 static void flip_smm_bit(void *data) 4992 { 4993 unsigned long set = *(unsigned long *)data; 4994 4995 if (set > 0) { 4996 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 4997 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4998 } else { 4999 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 5000 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 5001 } 5002 } 5003 5004 static void intel_pmu_check_counters_mask(u64 *cntr_mask, 5005 u64 *fixed_cntr_mask, 5006 u64 *intel_ctrl) 5007 { 5008 unsigned int bit; 5009 5010 bit = fls64(*cntr_mask); 5011 if (bit > INTEL_PMC_MAX_GENERIC) { 5012 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5013 bit, INTEL_PMC_MAX_GENERIC); 5014 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); 5015 } 5016 *intel_ctrl = *cntr_mask; 5017 5018 bit = fls64(*fixed_cntr_mask); 5019 if (bit > INTEL_PMC_MAX_FIXED) { 5020 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5021 bit, INTEL_PMC_MAX_FIXED); 5022 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0); 5023 } 5024 5025 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED; 5026 } 5027 5028 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 5029 u64 cntr_mask, 5030 u64 fixed_cntr_mask, 5031 u64 intel_ctrl); 5032 5033 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs); 5034 5035 static inline bool intel_pmu_broken_perf_cap(void) 5036 { 5037 /* The Perf Metric (Bit 15) is always cleared */ 5038 if (boot_cpu_data.x86_vfm == INTEL_METEORLAKE || 5039 boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L) 5040 return true; 5041 5042 return false; 5043 } 5044 5045 static void update_pmu_cap(struct x86_hybrid_pmu *pmu) 5046 { 5047 unsigned int cntr, fixed_cntr, ecx, edx; 5048 union cpuid35_eax eax; 5049 union cpuid35_ebx ebx; 5050 5051 cpuid(ARCH_PERFMON_EXT_LEAF, &eax.full, &ebx.full, &ecx, &edx); 5052 5053 if (ebx.split.umask2) 5054 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_UMASK2; 5055 if (ebx.split.eq) 5056 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_EQ; 5057 5058 if (eax.split.cntr_subleaf) { 5059 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF, 5060 &cntr, &fixed_cntr, &ecx, &edx); 5061 pmu->cntr_mask64 = cntr; 5062 pmu->fixed_cntr_mask64 = fixed_cntr; 5063 } 5064 5065 if (!intel_pmu_broken_perf_cap()) { 5066 /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */ 5067 rdmsrq(MSR_IA32_PERF_CAPABILITIES, pmu->intel_cap.capabilities); 5068 } 5069 } 5070 5071 static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu) 5072 { 5073 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64, 5074 &pmu->intel_ctrl); 5075 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 5076 pmu->unconstrained = (struct event_constraint) 5077 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 5078 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 5079 5080 if (pmu->intel_cap.perf_metrics) 5081 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 5082 else 5083 pmu->intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 5084 5085 intel_pmu_check_event_constraints(pmu->event_constraints, 5086 pmu->cntr_mask64, 5087 pmu->fixed_cntr_mask64, 5088 pmu->intel_ctrl); 5089 5090 intel_pmu_check_extra_regs(pmu->extra_regs); 5091 } 5092 5093 static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void) 5094 { 5095 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 5096 enum intel_cpu_type cpu_type = c->topo.intel_type; 5097 int i; 5098 5099 /* 5100 * This is running on a CPU model that is known to have hybrid 5101 * configurations. But the CPU told us it is not hybrid, shame 5102 * on it. There should be a fixup function provided for these 5103 * troublesome CPUs (->get_hybrid_cpu_type). 5104 */ 5105 if (cpu_type == INTEL_CPU_TYPE_UNKNOWN) { 5106 if (x86_pmu.get_hybrid_cpu_type) 5107 cpu_type = x86_pmu.get_hybrid_cpu_type(); 5108 else 5109 return NULL; 5110 } 5111 5112 /* 5113 * This essentially just maps between the 'hybrid_cpu_type' 5114 * and 'hybrid_pmu_type' enums except for ARL-H processor 5115 * which needs to compare atom uarch native id since ARL-H 5116 * contains two different atom uarchs. 5117 */ 5118 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 5119 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type; 5120 u32 native_id; 5121 5122 if (cpu_type == INTEL_CPU_TYPE_CORE && pmu_type == hybrid_big) 5123 return &x86_pmu.hybrid_pmu[i]; 5124 if (cpu_type == INTEL_CPU_TYPE_ATOM) { 5125 if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small) 5126 return &x86_pmu.hybrid_pmu[i]; 5127 5128 native_id = c->topo.intel_native_model_id; 5129 if (native_id == INTEL_ATOM_SKT_NATIVE_ID && pmu_type == hybrid_small) 5130 return &x86_pmu.hybrid_pmu[i]; 5131 if (native_id == INTEL_ATOM_CMT_NATIVE_ID && pmu_type == hybrid_tiny) 5132 return &x86_pmu.hybrid_pmu[i]; 5133 } 5134 } 5135 5136 return NULL; 5137 } 5138 5139 static bool init_hybrid_pmu(int cpu) 5140 { 5141 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 5142 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu(); 5143 5144 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { 5145 cpuc->pmu = NULL; 5146 return false; 5147 } 5148 5149 /* Only check and dump the PMU information for the first CPU */ 5150 if (!cpumask_empty(&pmu->supported_cpus)) 5151 goto end; 5152 5153 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) 5154 update_pmu_cap(pmu); 5155 5156 intel_pmu_check_hybrid_pmus(pmu); 5157 5158 if (!check_hw_exists(&pmu->pmu, pmu->cntr_mask, pmu->fixed_cntr_mask)) 5159 return false; 5160 5161 pr_info("%s PMU driver: ", pmu->name); 5162 5163 pr_cont("\n"); 5164 5165 x86_pmu_show_pmu_cap(&pmu->pmu); 5166 5167 end: 5168 cpumask_set_cpu(cpu, &pmu->supported_cpus); 5169 cpuc->pmu = &pmu->pmu; 5170 5171 return true; 5172 } 5173 5174 static void intel_pmu_cpu_starting(int cpu) 5175 { 5176 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 5177 int core_id = topology_core_id(cpu); 5178 int i; 5179 5180 if (is_hybrid() && !init_hybrid_pmu(cpu)) 5181 return; 5182 5183 init_debug_store_on_cpu(cpu); 5184 /* 5185 * Deal with CPUs that don't clear their LBRs on power-up, and that may 5186 * even boot with LBRs enabled. 5187 */ 5188 if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr) 5189 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT); 5190 intel_pmu_lbr_reset(); 5191 5192 cpuc->lbr_sel = NULL; 5193 5194 if (x86_pmu.flags & PMU_FL_TFA) { 5195 WARN_ON_ONCE(cpuc->tfa_shadow); 5196 cpuc->tfa_shadow = ~0ULL; 5197 intel_set_tfa(cpuc, false); 5198 } 5199 5200 if (x86_pmu.version > 1) 5201 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 5202 5203 /* 5204 * Disable perf metrics if any added CPU doesn't support it. 5205 * 5206 * Turn off the check for a hybrid architecture, because the 5207 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate 5208 * the architecture features. The perf metrics is a model-specific 5209 * feature for now. The corresponding bit should always be 0 on 5210 * a hybrid platform, e.g., Alder Lake. 5211 */ 5212 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 5213 union perf_capabilities perf_cap; 5214 5215 rdmsrq(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 5216 if (!perf_cap.perf_metrics) { 5217 x86_pmu.intel_cap.perf_metrics = 0; 5218 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 5219 } 5220 } 5221 5222 if (!cpuc->shared_regs) 5223 return; 5224 5225 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 5226 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 5227 struct intel_shared_regs *pc; 5228 5229 pc = per_cpu(cpu_hw_events, i).shared_regs; 5230 if (pc && pc->core_id == core_id) { 5231 cpuc->kfree_on_online[0] = cpuc->shared_regs; 5232 cpuc->shared_regs = pc; 5233 break; 5234 } 5235 } 5236 cpuc->shared_regs->core_id = core_id; 5237 cpuc->shared_regs->refcnt++; 5238 } 5239 5240 if (x86_pmu.lbr_sel_map) 5241 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 5242 5243 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 5244 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 5245 struct cpu_hw_events *sibling; 5246 struct intel_excl_cntrs *c; 5247 5248 sibling = &per_cpu(cpu_hw_events, i); 5249 c = sibling->excl_cntrs; 5250 if (c && c->core_id == core_id) { 5251 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 5252 cpuc->excl_cntrs = c; 5253 if (!sibling->excl_thread_id) 5254 cpuc->excl_thread_id = 1; 5255 break; 5256 } 5257 } 5258 cpuc->excl_cntrs->core_id = core_id; 5259 cpuc->excl_cntrs->refcnt++; 5260 } 5261 } 5262 5263 static void free_excl_cntrs(struct cpu_hw_events *cpuc) 5264 { 5265 struct intel_excl_cntrs *c; 5266 5267 c = cpuc->excl_cntrs; 5268 if (c) { 5269 if (c->core_id == -1 || --c->refcnt == 0) 5270 kfree(c); 5271 cpuc->excl_cntrs = NULL; 5272 } 5273 5274 kfree(cpuc->constraint_list); 5275 cpuc->constraint_list = NULL; 5276 } 5277 5278 static void intel_pmu_cpu_dying(int cpu) 5279 { 5280 fini_debug_store_on_cpu(cpu); 5281 } 5282 5283 void intel_cpuc_finish(struct cpu_hw_events *cpuc) 5284 { 5285 struct intel_shared_regs *pc; 5286 5287 pc = cpuc->shared_regs; 5288 if (pc) { 5289 if (pc->core_id == -1 || --pc->refcnt == 0) 5290 kfree(pc); 5291 cpuc->shared_regs = NULL; 5292 } 5293 5294 free_excl_cntrs(cpuc); 5295 } 5296 5297 static void intel_pmu_cpu_dead(int cpu) 5298 { 5299 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 5300 5301 intel_cpuc_finish(cpuc); 5302 5303 if (is_hybrid() && cpuc->pmu) 5304 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); 5305 } 5306 5307 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, 5308 struct task_struct *task, bool sched_in) 5309 { 5310 intel_pmu_pebs_sched_task(pmu_ctx, sched_in); 5311 intel_pmu_lbr_sched_task(pmu_ctx, task, sched_in); 5312 } 5313 5314 static int intel_pmu_check_period(struct perf_event *event, u64 value) 5315 { 5316 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 5317 } 5318 5319 static void intel_aux_output_init(void) 5320 { 5321 /* Refer also intel_pmu_aux_output_match() */ 5322 if (x86_pmu.intel_cap.pebs_output_pt_available) 5323 x86_pmu.assign = intel_pmu_assign_event; 5324 } 5325 5326 static int intel_pmu_aux_output_match(struct perf_event *event) 5327 { 5328 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */ 5329 if (!x86_pmu.intel_cap.pebs_output_pt_available) 5330 return 0; 5331 5332 return is_intel_pt_event(event); 5333 } 5334 5335 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret) 5336 { 5337 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu); 5338 5339 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus); 5340 } 5341 5342 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 5343 5344 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 5345 5346 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 5347 5348 PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63"); 5349 5350 static struct attribute *intel_arch3_formats_attr[] = { 5351 &format_attr_event.attr, 5352 &format_attr_umask.attr, 5353 &format_attr_edge.attr, 5354 &format_attr_pc.attr, 5355 &format_attr_any.attr, 5356 &format_attr_inv.attr, 5357 &format_attr_cmask.attr, 5358 NULL, 5359 }; 5360 5361 static struct attribute *hsw_format_attr[] = { 5362 &format_attr_in_tx.attr, 5363 &format_attr_in_tx_cp.attr, 5364 &format_attr_offcore_rsp.attr, 5365 &format_attr_ldlat.attr, 5366 NULL 5367 }; 5368 5369 static struct attribute *nhm_format_attr[] = { 5370 &format_attr_offcore_rsp.attr, 5371 &format_attr_ldlat.attr, 5372 NULL 5373 }; 5374 5375 static struct attribute *slm_format_attr[] = { 5376 &format_attr_offcore_rsp.attr, 5377 NULL 5378 }; 5379 5380 static struct attribute *cmt_format_attr[] = { 5381 &format_attr_offcore_rsp.attr, 5382 &format_attr_ldlat.attr, 5383 &format_attr_snoop_rsp.attr, 5384 NULL 5385 }; 5386 5387 static struct attribute *skl_format_attr[] = { 5388 &format_attr_frontend.attr, 5389 NULL, 5390 }; 5391 5392 static __initconst const struct x86_pmu core_pmu = { 5393 .name = "core", 5394 .handle_irq = x86_pmu_handle_irq, 5395 .disable_all = x86_pmu_disable_all, 5396 .enable_all = core_pmu_enable_all, 5397 .enable = core_pmu_enable_event, 5398 .disable = x86_pmu_disable_event, 5399 .hw_config = core_pmu_hw_config, 5400 .schedule_events = x86_schedule_events, 5401 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 5402 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 5403 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0, 5404 .event_map = intel_pmu_event_map, 5405 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 5406 .apic = 1, 5407 .large_pebs_flags = LARGE_PEBS_FLAGS, 5408 5409 /* 5410 * Intel PMCs cannot be accessed sanely above 32-bit width, 5411 * so we install an artificial 1<<31 period regardless of 5412 * the generic event period: 5413 */ 5414 .max_period = (1ULL<<31) - 1, 5415 .get_event_constraints = intel_get_event_constraints, 5416 .put_event_constraints = intel_put_event_constraints, 5417 .event_constraints = intel_core_event_constraints, 5418 .guest_get_msrs = core_guest_get_msrs, 5419 .format_attrs = intel_arch_formats_attr, 5420 .events_sysfs_show = intel_event_sysfs_show, 5421 5422 /* 5423 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 5424 * together with PMU version 1 and thus be using core_pmu with 5425 * shared_regs. We need following callbacks here to allocate 5426 * it properly. 5427 */ 5428 .cpu_prepare = intel_pmu_cpu_prepare, 5429 .cpu_starting = intel_pmu_cpu_starting, 5430 .cpu_dying = intel_pmu_cpu_dying, 5431 .cpu_dead = intel_pmu_cpu_dead, 5432 5433 .check_period = intel_pmu_check_period, 5434 5435 .lbr_reset = intel_pmu_lbr_reset_64, 5436 .lbr_read = intel_pmu_lbr_read_64, 5437 .lbr_save = intel_pmu_lbr_save, 5438 .lbr_restore = intel_pmu_lbr_restore, 5439 }; 5440 5441 static __initconst const struct x86_pmu intel_pmu = { 5442 .name = "Intel", 5443 .handle_irq = intel_pmu_handle_irq, 5444 .disable_all = intel_pmu_disable_all, 5445 .enable_all = intel_pmu_enable_all, 5446 .enable = intel_pmu_enable_event, 5447 .disable = intel_pmu_disable_event, 5448 .add = intel_pmu_add_event, 5449 .del = intel_pmu_del_event, 5450 .read = intel_pmu_read_event, 5451 .set_period = intel_pmu_set_period, 5452 .update = intel_pmu_update, 5453 .hw_config = intel_pmu_hw_config, 5454 .schedule_events = x86_schedule_events, 5455 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 5456 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 5457 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0, 5458 .event_map = intel_pmu_event_map, 5459 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 5460 .apic = 1, 5461 .large_pebs_flags = LARGE_PEBS_FLAGS, 5462 /* 5463 * Intel PMCs cannot be accessed sanely above 32 bit width, 5464 * so we install an artificial 1<<31 period regardless of 5465 * the generic event period: 5466 */ 5467 .max_period = (1ULL << 31) - 1, 5468 .get_event_constraints = intel_get_event_constraints, 5469 .put_event_constraints = intel_put_event_constraints, 5470 .pebs_aliases = intel_pebs_aliases_core2, 5471 5472 .format_attrs = intel_arch3_formats_attr, 5473 .events_sysfs_show = intel_event_sysfs_show, 5474 5475 .cpu_prepare = intel_pmu_cpu_prepare, 5476 .cpu_starting = intel_pmu_cpu_starting, 5477 .cpu_dying = intel_pmu_cpu_dying, 5478 .cpu_dead = intel_pmu_cpu_dead, 5479 5480 .guest_get_msrs = intel_guest_get_msrs, 5481 .sched_task = intel_pmu_sched_task, 5482 5483 .check_period = intel_pmu_check_period, 5484 5485 .aux_output_match = intel_pmu_aux_output_match, 5486 5487 .lbr_reset = intel_pmu_lbr_reset_64, 5488 .lbr_read = intel_pmu_lbr_read_64, 5489 .lbr_save = intel_pmu_lbr_save, 5490 .lbr_restore = intel_pmu_lbr_restore, 5491 5492 /* 5493 * SMM has access to all 4 rings and while traditionally SMM code only 5494 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM. 5495 * 5496 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction 5497 * between SMM or not, this results in what should be pure userspace 5498 * counters including SMM data. 5499 * 5500 * This is a clear privilege issue, therefore globally disable 5501 * counting SMM by default. 5502 */ 5503 .attr_freeze_on_smi = 1, 5504 }; 5505 5506 static __init void intel_clovertown_quirk(void) 5507 { 5508 /* 5509 * PEBS is unreliable due to: 5510 * 5511 * AJ67 - PEBS may experience CPL leaks 5512 * AJ68 - PEBS PMI may be delayed by one event 5513 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 5514 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 5515 * 5516 * AJ67 could be worked around by restricting the OS/USR flags. 5517 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 5518 * 5519 * AJ106 could possibly be worked around by not allowing LBR 5520 * usage from PEBS, including the fixup. 5521 * AJ68 could possibly be worked around by always programming 5522 * a pebs_event_reset[0] value and coping with the lost events. 5523 * 5524 * But taken together it might just make sense to not enable PEBS on 5525 * these chips. 5526 */ 5527 pr_warn("PEBS disabled due to CPU errata\n"); 5528 x86_pmu.pebs = 0; 5529 x86_pmu.pebs_constraints = NULL; 5530 } 5531 5532 static const struct x86_cpu_id isolation_ucodes[] = { 5533 X86_MATCH_VFM_STEPS(INTEL_HASWELL, 3, 3, 0x0000001f), 5534 X86_MATCH_VFM_STEPS(INTEL_HASWELL_L, 1, 1, 0x0000001e), 5535 X86_MATCH_VFM_STEPS(INTEL_HASWELL_G, 1, 1, 0x00000015), 5536 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 2, 2, 0x00000037), 5537 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 4, 4, 0x0000000a), 5538 X86_MATCH_VFM_STEPS(INTEL_BROADWELL, 4, 4, 0x00000023), 5539 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_G, 1, 1, 0x00000014), 5540 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 2, 2, 0x00000010), 5541 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 3, 3, 0x07000009), 5542 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 4, 4, 0x0f000009), 5543 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 5, 5, 0x0e000002), 5544 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_X, 1, 1, 0x0b000014), 5545 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 3, 3, 0x00000021), 5546 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 4, 7, 0x00000000), 5547 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 11, 11, 0x00000000), 5548 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_L, 3, 3, 0x0000007c), 5549 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE, 3, 3, 0x0000007c), 5550 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE, 9, 13, 0x0000004e), 5551 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE_L, 9, 12, 0x0000004e), 5552 {} 5553 }; 5554 5555 static void intel_check_pebs_isolation(void) 5556 { 5557 x86_pmu.pebs_no_isolation = !x86_match_min_microcode_rev(isolation_ucodes); 5558 } 5559 5560 static __init void intel_pebs_isolation_quirk(void) 5561 { 5562 WARN_ON_ONCE(x86_pmu.check_microcode); 5563 x86_pmu.check_microcode = intel_check_pebs_isolation; 5564 intel_check_pebs_isolation(); 5565 } 5566 5567 static const struct x86_cpu_id pebs_ucodes[] = { 5568 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE, 7, 7, 0x00000028), 5569 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 6, 6, 0x00000618), 5570 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 7, 7, 0x0000070c), 5571 {} 5572 }; 5573 5574 static bool intel_snb_pebs_broken(void) 5575 { 5576 return !x86_match_min_microcode_rev(pebs_ucodes); 5577 } 5578 5579 static void intel_snb_check_microcode(void) 5580 { 5581 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 5582 return; 5583 5584 /* 5585 * Serialized by the microcode lock.. 5586 */ 5587 if (x86_pmu.pebs_broken) { 5588 pr_info("PEBS enabled due to microcode update\n"); 5589 x86_pmu.pebs_broken = 0; 5590 } else { 5591 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 5592 x86_pmu.pebs_broken = 1; 5593 } 5594 } 5595 5596 static bool is_lbr_from(unsigned long msr) 5597 { 5598 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 5599 5600 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 5601 } 5602 5603 /* 5604 * Under certain circumstances, access certain MSR may cause #GP. 5605 * The function tests if the input MSR can be safely accessed. 5606 */ 5607 static bool check_msr(unsigned long msr, u64 mask) 5608 { 5609 u64 val_old, val_new, val_tmp; 5610 5611 /* 5612 * Disable the check for real HW, so we don't 5613 * mess with potentially enabled registers: 5614 */ 5615 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 5616 return true; 5617 5618 /* 5619 * Read the current value, change it and read it back to see if it 5620 * matches, this is needed to detect certain hardware emulators 5621 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 5622 */ 5623 if (rdmsrq_safe(msr, &val_old)) 5624 return false; 5625 5626 /* 5627 * Only change the bits which can be updated by wrmsrq. 5628 */ 5629 val_tmp = val_old ^ mask; 5630 5631 if (is_lbr_from(msr)) 5632 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 5633 5634 if (wrmsrq_safe(msr, val_tmp) || 5635 rdmsrq_safe(msr, &val_new)) 5636 return false; 5637 5638 /* 5639 * Quirk only affects validation in wrmsr(), so wrmsrq()'s value 5640 * should equal rdmsrq()'s even with the quirk. 5641 */ 5642 if (val_new != val_tmp) 5643 return false; 5644 5645 if (is_lbr_from(msr)) 5646 val_old = lbr_from_signext_quirk_wr(val_old); 5647 5648 /* Here it's sure that the MSR can be safely accessed. 5649 * Restore the old value and return. 5650 */ 5651 wrmsrq(msr, val_old); 5652 5653 return true; 5654 } 5655 5656 static __init void intel_sandybridge_quirk(void) 5657 { 5658 x86_pmu.check_microcode = intel_snb_check_microcode; 5659 cpus_read_lock(); 5660 intel_snb_check_microcode(); 5661 cpus_read_unlock(); 5662 } 5663 5664 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 5665 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 5666 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 5667 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 5668 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 5669 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 5670 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 5671 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 5672 }; 5673 5674 static __init void intel_arch_events_quirk(void) 5675 { 5676 int bit; 5677 5678 /* disable event that reported as not present by cpuid */ 5679 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 5680 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 5681 pr_warn("CPUID marked event: \'%s\' unavailable\n", 5682 intel_arch_events_map[bit].name); 5683 } 5684 } 5685 5686 static __init void intel_nehalem_quirk(void) 5687 { 5688 union cpuid10_ebx ebx; 5689 5690 ebx.full = x86_pmu.events_maskl; 5691 if (ebx.split.no_branch_misses_retired) { 5692 /* 5693 * Erratum AAJ80 detected, we work it around by using 5694 * the BR_MISP_EXEC.ANY event. This will over-count 5695 * branch-misses, but it's still much better than the 5696 * architectural event which is often completely bogus: 5697 */ 5698 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 5699 ebx.split.no_branch_misses_retired = 0; 5700 x86_pmu.events_maskl = ebx.full; 5701 pr_info("CPU erratum AAJ80 worked around\n"); 5702 } 5703 } 5704 5705 /* 5706 * enable software workaround for errata: 5707 * SNB: BJ122 5708 * IVB: BV98 5709 * HSW: HSD29 5710 * 5711 * Only needed when HT is enabled. However detecting 5712 * if HT is enabled is difficult (model specific). So instead, 5713 * we enable the workaround in the early boot, and verify if 5714 * it is needed in a later initcall phase once we have valid 5715 * topology information to check if HT is actually enabled 5716 */ 5717 static __init void intel_ht_bug(void) 5718 { 5719 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 5720 5721 x86_pmu.start_scheduling = intel_start_scheduling; 5722 x86_pmu.commit_scheduling = intel_commit_scheduling; 5723 x86_pmu.stop_scheduling = intel_stop_scheduling; 5724 } 5725 5726 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 5727 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 5728 5729 /* Haswell special events */ 5730 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 5731 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 5732 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 5733 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 5734 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 5735 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 5736 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 5737 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 5738 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 5739 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 5740 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 5741 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 5742 5743 static struct attribute *hsw_events_attrs[] = { 5744 EVENT_PTR(td_slots_issued), 5745 EVENT_PTR(td_slots_retired), 5746 EVENT_PTR(td_fetch_bubbles), 5747 EVENT_PTR(td_total_slots), 5748 EVENT_PTR(td_total_slots_scale), 5749 EVENT_PTR(td_recovery_bubbles), 5750 EVENT_PTR(td_recovery_bubbles_scale), 5751 NULL 5752 }; 5753 5754 static struct attribute *hsw_mem_events_attrs[] = { 5755 EVENT_PTR(mem_ld_hsw), 5756 EVENT_PTR(mem_st_hsw), 5757 NULL, 5758 }; 5759 5760 static struct attribute *hsw_tsx_events_attrs[] = { 5761 EVENT_PTR(tx_start), 5762 EVENT_PTR(tx_commit), 5763 EVENT_PTR(tx_abort), 5764 EVENT_PTR(tx_capacity), 5765 EVENT_PTR(tx_conflict), 5766 EVENT_PTR(el_start), 5767 EVENT_PTR(el_commit), 5768 EVENT_PTR(el_abort), 5769 EVENT_PTR(el_capacity), 5770 EVENT_PTR(el_conflict), 5771 EVENT_PTR(cycles_t), 5772 EVENT_PTR(cycles_ct), 5773 NULL 5774 }; 5775 5776 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 5777 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 5778 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 5779 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 5780 5781 static struct attribute *icl_events_attrs[] = { 5782 EVENT_PTR(mem_ld_hsw), 5783 EVENT_PTR(mem_st_hsw), 5784 NULL, 5785 }; 5786 5787 static struct attribute *icl_td_events_attrs[] = { 5788 EVENT_PTR(slots), 5789 EVENT_PTR(td_retiring), 5790 EVENT_PTR(td_bad_spec), 5791 EVENT_PTR(td_fe_bound), 5792 EVENT_PTR(td_be_bound), 5793 NULL, 5794 }; 5795 5796 static struct attribute *icl_tsx_events_attrs[] = { 5797 EVENT_PTR(tx_start), 5798 EVENT_PTR(tx_abort), 5799 EVENT_PTR(tx_commit), 5800 EVENT_PTR(tx_capacity_read), 5801 EVENT_PTR(tx_capacity_write), 5802 EVENT_PTR(tx_conflict), 5803 EVENT_PTR(el_start), 5804 EVENT_PTR(el_abort), 5805 EVENT_PTR(el_commit), 5806 EVENT_PTR(el_capacity_read), 5807 EVENT_PTR(el_capacity_write), 5808 EVENT_PTR(el_conflict), 5809 EVENT_PTR(cycles_t), 5810 EVENT_PTR(cycles_ct), 5811 NULL, 5812 }; 5813 5814 5815 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 5816 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 5817 5818 static struct attribute *glc_events_attrs[] = { 5819 EVENT_PTR(mem_ld_hsw), 5820 EVENT_PTR(mem_st_spr), 5821 EVENT_PTR(mem_ld_aux), 5822 NULL, 5823 }; 5824 5825 static struct attribute *glc_td_events_attrs[] = { 5826 EVENT_PTR(slots), 5827 EVENT_PTR(td_retiring), 5828 EVENT_PTR(td_bad_spec), 5829 EVENT_PTR(td_fe_bound), 5830 EVENT_PTR(td_be_bound), 5831 EVENT_PTR(td_heavy_ops), 5832 EVENT_PTR(td_br_mispredict), 5833 EVENT_PTR(td_fetch_lat), 5834 EVENT_PTR(td_mem_bound), 5835 NULL, 5836 }; 5837 5838 static struct attribute *glc_tsx_events_attrs[] = { 5839 EVENT_PTR(tx_start), 5840 EVENT_PTR(tx_abort), 5841 EVENT_PTR(tx_commit), 5842 EVENT_PTR(tx_capacity_read), 5843 EVENT_PTR(tx_capacity_write), 5844 EVENT_PTR(tx_conflict), 5845 EVENT_PTR(cycles_t), 5846 EVENT_PTR(cycles_ct), 5847 NULL, 5848 }; 5849 5850 static ssize_t freeze_on_smi_show(struct device *cdev, 5851 struct device_attribute *attr, 5852 char *buf) 5853 { 5854 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 5855 } 5856 5857 static DEFINE_MUTEX(freeze_on_smi_mutex); 5858 5859 static ssize_t freeze_on_smi_store(struct device *cdev, 5860 struct device_attribute *attr, 5861 const char *buf, size_t count) 5862 { 5863 unsigned long val; 5864 ssize_t ret; 5865 5866 ret = kstrtoul(buf, 0, &val); 5867 if (ret) 5868 return ret; 5869 5870 if (val > 1) 5871 return -EINVAL; 5872 5873 mutex_lock(&freeze_on_smi_mutex); 5874 5875 if (x86_pmu.attr_freeze_on_smi == val) 5876 goto done; 5877 5878 x86_pmu.attr_freeze_on_smi = val; 5879 5880 cpus_read_lock(); 5881 on_each_cpu(flip_smm_bit, &val, 1); 5882 cpus_read_unlock(); 5883 done: 5884 mutex_unlock(&freeze_on_smi_mutex); 5885 5886 return count; 5887 } 5888 5889 static void update_tfa_sched(void *ignored) 5890 { 5891 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5892 5893 /* 5894 * check if PMC3 is used 5895 * and if so force schedule out for all event types all contexts 5896 */ 5897 if (test_bit(3, cpuc->active_mask)) 5898 perf_pmu_resched(x86_get_pmu(smp_processor_id())); 5899 } 5900 5901 static ssize_t show_sysctl_tfa(struct device *cdev, 5902 struct device_attribute *attr, 5903 char *buf) 5904 { 5905 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 5906 } 5907 5908 static ssize_t set_sysctl_tfa(struct device *cdev, 5909 struct device_attribute *attr, 5910 const char *buf, size_t count) 5911 { 5912 bool val; 5913 ssize_t ret; 5914 5915 ret = kstrtobool(buf, &val); 5916 if (ret) 5917 return ret; 5918 5919 /* no change */ 5920 if (val == allow_tsx_force_abort) 5921 return count; 5922 5923 allow_tsx_force_abort = val; 5924 5925 cpus_read_lock(); 5926 on_each_cpu(update_tfa_sched, NULL, 1); 5927 cpus_read_unlock(); 5928 5929 return count; 5930 } 5931 5932 5933 static DEVICE_ATTR_RW(freeze_on_smi); 5934 5935 static ssize_t branches_show(struct device *cdev, 5936 struct device_attribute *attr, 5937 char *buf) 5938 { 5939 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 5940 } 5941 5942 static DEVICE_ATTR_RO(branches); 5943 5944 static ssize_t branch_counter_nr_show(struct device *cdev, 5945 struct device_attribute *attr, 5946 char *buf) 5947 { 5948 return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_counters)); 5949 } 5950 5951 static DEVICE_ATTR_RO(branch_counter_nr); 5952 5953 static ssize_t branch_counter_width_show(struct device *cdev, 5954 struct device_attribute *attr, 5955 char *buf) 5956 { 5957 return snprintf(buf, PAGE_SIZE, "%d\n", LBR_INFO_BR_CNTR_BITS); 5958 } 5959 5960 static DEVICE_ATTR_RO(branch_counter_width); 5961 5962 static struct attribute *lbr_attrs[] = { 5963 &dev_attr_branches.attr, 5964 &dev_attr_branch_counter_nr.attr, 5965 &dev_attr_branch_counter_width.attr, 5966 NULL 5967 }; 5968 5969 static umode_t 5970 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5971 { 5972 /* branches */ 5973 if (i == 0) 5974 return x86_pmu.lbr_nr ? attr->mode : 0; 5975 5976 return (x86_pmu.flags & PMU_FL_BR_CNTR) ? attr->mode : 0; 5977 } 5978 5979 static char pmu_name_str[30]; 5980 5981 static DEVICE_STRING_ATTR_RO(pmu_name, 0444, pmu_name_str); 5982 5983 static struct attribute *intel_pmu_caps_attrs[] = { 5984 &dev_attr_pmu_name.attr.attr, 5985 NULL 5986 }; 5987 5988 static DEVICE_ATTR(allow_tsx_force_abort, 0644, 5989 show_sysctl_tfa, 5990 set_sysctl_tfa); 5991 5992 static struct attribute *intel_pmu_attrs[] = { 5993 &dev_attr_freeze_on_smi.attr, 5994 &dev_attr_allow_tsx_force_abort.attr, 5995 NULL, 5996 }; 5997 5998 static umode_t 5999 default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6000 { 6001 if (attr == &dev_attr_allow_tsx_force_abort.attr) 6002 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 6003 6004 return attr->mode; 6005 } 6006 6007 static umode_t 6008 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6009 { 6010 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 6011 } 6012 6013 static umode_t 6014 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6015 { 6016 return x86_pmu.pebs ? attr->mode : 0; 6017 } 6018 6019 static umode_t 6020 mem_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6021 { 6022 if (attr == &event_attr_mem_ld_aux.attr.attr) 6023 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0; 6024 6025 return pebs_is_visible(kobj, attr, i); 6026 } 6027 6028 static umode_t 6029 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6030 { 6031 return x86_pmu.version >= 2 ? attr->mode : 0; 6032 } 6033 6034 static umode_t 6035 td_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6036 { 6037 /* 6038 * Hide the perf metrics topdown events 6039 * if the feature is not enumerated. 6040 */ 6041 if (x86_pmu.num_topdown_events) 6042 return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0; 6043 6044 return attr->mode; 6045 } 6046 6047 static struct attribute_group group_events_td = { 6048 .name = "events", 6049 .is_visible = td_is_visible, 6050 }; 6051 6052 static struct attribute_group group_events_mem = { 6053 .name = "events", 6054 .is_visible = mem_is_visible, 6055 }; 6056 6057 static struct attribute_group group_events_tsx = { 6058 .name = "events", 6059 .is_visible = tsx_is_visible, 6060 }; 6061 6062 static struct attribute_group group_caps_gen = { 6063 .name = "caps", 6064 .attrs = intel_pmu_caps_attrs, 6065 }; 6066 6067 static struct attribute_group group_caps_lbr = { 6068 .name = "caps", 6069 .attrs = lbr_attrs, 6070 .is_visible = lbr_is_visible, 6071 }; 6072 6073 static struct attribute_group group_format_extra = { 6074 .name = "format", 6075 .is_visible = exra_is_visible, 6076 }; 6077 6078 static struct attribute_group group_format_extra_skl = { 6079 .name = "format", 6080 .is_visible = exra_is_visible, 6081 }; 6082 6083 static struct attribute_group group_format_evtsel_ext = { 6084 .name = "format", 6085 .attrs = format_evtsel_ext_attrs, 6086 .is_visible = evtsel_ext_is_visible, 6087 }; 6088 6089 static struct attribute_group group_default = { 6090 .attrs = intel_pmu_attrs, 6091 .is_visible = default_is_visible, 6092 }; 6093 6094 static const struct attribute_group *attr_update[] = { 6095 &group_events_td, 6096 &group_events_mem, 6097 &group_events_tsx, 6098 &group_caps_gen, 6099 &group_caps_lbr, 6100 &group_format_extra, 6101 &group_format_extra_skl, 6102 &group_format_evtsel_ext, 6103 &group_default, 6104 NULL, 6105 }; 6106 6107 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); 6108 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); 6109 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); 6110 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); 6111 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); 6112 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); 6113 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); 6114 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); 6115 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); 6116 6117 static struct attribute *adl_hybrid_events_attrs[] = { 6118 EVENT_PTR(slots_adl), 6119 EVENT_PTR(td_retiring_adl), 6120 EVENT_PTR(td_bad_spec_adl), 6121 EVENT_PTR(td_fe_bound_adl), 6122 EVENT_PTR(td_be_bound_adl), 6123 EVENT_PTR(td_heavy_ops_adl), 6124 EVENT_PTR(td_br_mis_adl), 6125 EVENT_PTR(td_fetch_lat_adl), 6126 EVENT_PTR(td_mem_bound_adl), 6127 NULL, 6128 }; 6129 6130 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_lnl, "event=0xc2,umask=0x02;event=0x00,umask=0x80", hybrid_big_small); 6131 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_lnl, "event=0x9c,umask=0x01;event=0x00,umask=0x82", hybrid_big_small); 6132 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_lnl, "event=0xa4,umask=0x02;event=0x00,umask=0x83", hybrid_big_small); 6133 6134 static struct attribute *lnl_hybrid_events_attrs[] = { 6135 EVENT_PTR(slots_adl), 6136 EVENT_PTR(td_retiring_lnl), 6137 EVENT_PTR(td_bad_spec_adl), 6138 EVENT_PTR(td_fe_bound_lnl), 6139 EVENT_PTR(td_be_bound_lnl), 6140 EVENT_PTR(td_heavy_ops_adl), 6141 EVENT_PTR(td_br_mis_adl), 6142 EVENT_PTR(td_fetch_lat_adl), 6143 EVENT_PTR(td_mem_bound_adl), 6144 NULL 6145 }; 6146 6147 /* The event string must be in PMU IDX order. */ 6148 EVENT_ATTR_STR_HYBRID(topdown-retiring, 6149 td_retiring_arl_h, 6150 "event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0", 6151 hybrid_big_small_tiny); 6152 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, 6153 td_bad_spec_arl_h, 6154 "event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0", 6155 hybrid_big_small_tiny); 6156 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, 6157 td_fe_bound_arl_h, 6158 "event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0", 6159 hybrid_big_small_tiny); 6160 EVENT_ATTR_STR_HYBRID(topdown-be-bound, 6161 td_be_bound_arl_h, 6162 "event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0", 6163 hybrid_big_small_tiny); 6164 6165 static struct attribute *arl_h_hybrid_events_attrs[] = { 6166 EVENT_PTR(slots_adl), 6167 EVENT_PTR(td_retiring_arl_h), 6168 EVENT_PTR(td_bad_spec_arl_h), 6169 EVENT_PTR(td_fe_bound_arl_h), 6170 EVENT_PTR(td_be_bound_arl_h), 6171 EVENT_PTR(td_heavy_ops_adl), 6172 EVENT_PTR(td_br_mis_adl), 6173 EVENT_PTR(td_fetch_lat_adl), 6174 EVENT_PTR(td_mem_bound_adl), 6175 NULL, 6176 }; 6177 6178 /* Must be in IDX order */ 6179 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); 6180 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); 6181 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); 6182 6183 static struct attribute *adl_hybrid_mem_attrs[] = { 6184 EVENT_PTR(mem_ld_adl), 6185 EVENT_PTR(mem_st_adl), 6186 EVENT_PTR(mem_ld_aux_adl), 6187 NULL, 6188 }; 6189 6190 static struct attribute *mtl_hybrid_mem_attrs[] = { 6191 EVENT_PTR(mem_ld_adl), 6192 EVENT_PTR(mem_st_adl), 6193 NULL 6194 }; 6195 6196 EVENT_ATTR_STR_HYBRID(mem-loads, 6197 mem_ld_arl_h, 6198 "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3", 6199 hybrid_big_small_tiny); 6200 EVENT_ATTR_STR_HYBRID(mem-stores, 6201 mem_st_arl_h, 6202 "event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6", 6203 hybrid_big_small_tiny); 6204 6205 static struct attribute *arl_h_hybrid_mem_attrs[] = { 6206 EVENT_PTR(mem_ld_arl_h), 6207 EVENT_PTR(mem_st_arl_h), 6208 NULL, 6209 }; 6210 6211 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); 6212 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); 6213 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); 6214 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); 6215 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); 6216 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); 6217 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); 6218 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); 6219 6220 static struct attribute *adl_hybrid_tsx_attrs[] = { 6221 EVENT_PTR(tx_start_adl), 6222 EVENT_PTR(tx_abort_adl), 6223 EVENT_PTR(tx_commit_adl), 6224 EVENT_PTR(tx_capacity_read_adl), 6225 EVENT_PTR(tx_capacity_write_adl), 6226 EVENT_PTR(tx_conflict_adl), 6227 EVENT_PTR(cycles_t_adl), 6228 EVENT_PTR(cycles_ct_adl), 6229 NULL, 6230 }; 6231 6232 FORMAT_ATTR_HYBRID(in_tx, hybrid_big); 6233 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); 6234 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny); 6235 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny); 6236 FORMAT_ATTR_HYBRID(frontend, hybrid_big); 6237 6238 #define ADL_HYBRID_RTM_FORMAT_ATTR \ 6239 FORMAT_HYBRID_PTR(in_tx), \ 6240 FORMAT_HYBRID_PTR(in_tx_cp) 6241 6242 #define ADL_HYBRID_FORMAT_ATTR \ 6243 FORMAT_HYBRID_PTR(offcore_rsp), \ 6244 FORMAT_HYBRID_PTR(ldlat), \ 6245 FORMAT_HYBRID_PTR(frontend) 6246 6247 static struct attribute *adl_hybrid_extra_attr_rtm[] = { 6248 ADL_HYBRID_RTM_FORMAT_ATTR, 6249 ADL_HYBRID_FORMAT_ATTR, 6250 NULL 6251 }; 6252 6253 static struct attribute *adl_hybrid_extra_attr[] = { 6254 ADL_HYBRID_FORMAT_ATTR, 6255 NULL 6256 }; 6257 6258 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_tiny); 6259 6260 static struct attribute *mtl_hybrid_extra_attr_rtm[] = { 6261 ADL_HYBRID_RTM_FORMAT_ATTR, 6262 ADL_HYBRID_FORMAT_ATTR, 6263 FORMAT_HYBRID_PTR(snoop_rsp), 6264 NULL 6265 }; 6266 6267 static struct attribute *mtl_hybrid_extra_attr[] = { 6268 ADL_HYBRID_FORMAT_ATTR, 6269 FORMAT_HYBRID_PTR(snoop_rsp), 6270 NULL 6271 }; 6272 6273 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) 6274 { 6275 struct device *dev = kobj_to_dev(kobj); 6276 struct x86_hybrid_pmu *pmu = 6277 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6278 struct perf_pmu_events_hybrid_attr *pmu_attr = 6279 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); 6280 6281 return pmu->pmu_type & pmu_attr->pmu_type; 6282 } 6283 6284 static umode_t hybrid_events_is_visible(struct kobject *kobj, 6285 struct attribute *attr, int i) 6286 { 6287 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; 6288 } 6289 6290 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) 6291 { 6292 int cpu = cpumask_first(&pmu->supported_cpus); 6293 6294 return (cpu >= nr_cpu_ids) ? -1 : cpu; 6295 } 6296 6297 static umode_t hybrid_tsx_is_visible(struct kobject *kobj, 6298 struct attribute *attr, int i) 6299 { 6300 struct device *dev = kobj_to_dev(kobj); 6301 struct x86_hybrid_pmu *pmu = 6302 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6303 int cpu = hybrid_find_supported_cpu(pmu); 6304 6305 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; 6306 } 6307 6308 static umode_t hybrid_format_is_visible(struct kobject *kobj, 6309 struct attribute *attr, int i) 6310 { 6311 struct device *dev = kobj_to_dev(kobj); 6312 struct x86_hybrid_pmu *pmu = 6313 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6314 struct perf_pmu_format_hybrid_attr *pmu_attr = 6315 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); 6316 int cpu = hybrid_find_supported_cpu(pmu); 6317 6318 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0; 6319 } 6320 6321 static umode_t hybrid_td_is_visible(struct kobject *kobj, 6322 struct attribute *attr, int i) 6323 { 6324 struct device *dev = kobj_to_dev(kobj); 6325 struct x86_hybrid_pmu *pmu = 6326 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6327 6328 if (!is_attr_for_this_pmu(kobj, attr)) 6329 return 0; 6330 6331 6332 /* Only the big core supports perf metrics */ 6333 if (pmu->pmu_type == hybrid_big) 6334 return pmu->intel_cap.perf_metrics ? attr->mode : 0; 6335 6336 return attr->mode; 6337 } 6338 6339 static struct attribute_group hybrid_group_events_td = { 6340 .name = "events", 6341 .is_visible = hybrid_td_is_visible, 6342 }; 6343 6344 static struct attribute_group hybrid_group_events_mem = { 6345 .name = "events", 6346 .is_visible = hybrid_events_is_visible, 6347 }; 6348 6349 static struct attribute_group hybrid_group_events_tsx = { 6350 .name = "events", 6351 .is_visible = hybrid_tsx_is_visible, 6352 }; 6353 6354 static struct attribute_group hybrid_group_format_extra = { 6355 .name = "format", 6356 .is_visible = hybrid_format_is_visible, 6357 }; 6358 6359 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, 6360 struct device_attribute *attr, 6361 char *buf) 6362 { 6363 struct x86_hybrid_pmu *pmu = 6364 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6365 6366 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus); 6367 } 6368 6369 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); 6370 static struct attribute *intel_hybrid_cpus_attrs[] = { 6371 &dev_attr_cpus.attr, 6372 NULL, 6373 }; 6374 6375 static struct attribute_group hybrid_group_cpus = { 6376 .attrs = intel_hybrid_cpus_attrs, 6377 }; 6378 6379 static const struct attribute_group *hybrid_attr_update[] = { 6380 &hybrid_group_events_td, 6381 &hybrid_group_events_mem, 6382 &hybrid_group_events_tsx, 6383 &group_caps_gen, 6384 &group_caps_lbr, 6385 &hybrid_group_format_extra, 6386 &group_format_evtsel_ext, 6387 &group_default, 6388 &hybrid_group_cpus, 6389 NULL, 6390 }; 6391 6392 static struct attribute *empty_attrs; 6393 6394 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 6395 u64 cntr_mask, 6396 u64 fixed_cntr_mask, 6397 u64 intel_ctrl) 6398 { 6399 struct event_constraint *c; 6400 6401 if (!event_constraints) 6402 return; 6403 6404 /* 6405 * event on fixed counter2 (REF_CYCLES) only works on this 6406 * counter, so do not extend mask to generic counters 6407 */ 6408 for_each_event_constraint(c, event_constraints) { 6409 /* 6410 * Don't extend the topdown slots and metrics 6411 * events to the generic counters. 6412 */ 6413 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 6414 /* 6415 * Disable topdown slots and metrics events, 6416 * if slots event is not in CPUID. 6417 */ 6418 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) 6419 c->idxmsk64 = 0; 6420 c->weight = hweight64(c->idxmsk64); 6421 continue; 6422 } 6423 6424 if (c->cmask == FIXED_EVENT_FLAGS) { 6425 /* Disabled fixed counters which are not in CPUID */ 6426 c->idxmsk64 &= intel_ctrl; 6427 6428 /* 6429 * Don't extend the pseudo-encoding to the 6430 * generic counters 6431 */ 6432 if (!use_fixed_pseudo_encoding(c->code)) 6433 c->idxmsk64 |= cntr_mask; 6434 } 6435 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED); 6436 c->weight = hweight64(c->idxmsk64); 6437 } 6438 } 6439 6440 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) 6441 { 6442 struct extra_reg *er; 6443 6444 /* 6445 * Access extra MSR may cause #GP under certain circumstances. 6446 * E.g. KVM doesn't support offcore event 6447 * Check all extra_regs here. 6448 */ 6449 if (!extra_regs) 6450 return; 6451 6452 for (er = extra_regs; er->msr; er++) { 6453 er->extra_msr_access = check_msr(er->msr, 0x11UL); 6454 /* Disable LBR select mapping */ 6455 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 6456 x86_pmu.lbr_sel_map = NULL; 6457 } 6458 } 6459 6460 static inline int intel_pmu_v6_addr_offset(int index, bool eventsel) 6461 { 6462 return MSR_IA32_PMC_V6_STEP * index; 6463 } 6464 6465 static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = { 6466 { hybrid_small, "cpu_atom" }, 6467 { hybrid_big, "cpu_core" }, 6468 { hybrid_tiny, "cpu_lowpower" }, 6469 }; 6470 6471 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus) 6472 { 6473 unsigned long pmus_mask = pmus; 6474 struct x86_hybrid_pmu *pmu; 6475 int idx = 0, bit; 6476 6477 x86_pmu.num_hybrid_pmus = hweight_long(pmus_mask); 6478 x86_pmu.hybrid_pmu = kcalloc(x86_pmu.num_hybrid_pmus, 6479 sizeof(struct x86_hybrid_pmu), 6480 GFP_KERNEL); 6481 if (!x86_pmu.hybrid_pmu) 6482 return -ENOMEM; 6483 6484 static_branch_enable(&perf_is_hybrid); 6485 x86_pmu.filter = intel_pmu_filter; 6486 6487 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) { 6488 pmu = &x86_pmu.hybrid_pmu[idx++]; 6489 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id; 6490 pmu->name = intel_hybrid_pmu_type_map[bit].name; 6491 6492 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 6493 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 6494 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 6495 pmu->config_mask = X86_RAW_EVENT_MASK; 6496 pmu->unconstrained = (struct event_constraint) 6497 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 6498 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 6499 6500 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6501 if (pmu->pmu_type & hybrid_small_tiny) { 6502 pmu->intel_cap.perf_metrics = 0; 6503 pmu->mid_ack = true; 6504 } else if (pmu->pmu_type & hybrid_big) { 6505 pmu->intel_cap.perf_metrics = 1; 6506 pmu->late_ack = true; 6507 } 6508 } 6509 6510 return 0; 6511 } 6512 6513 static __always_inline void intel_pmu_ref_cycles_ext(void) 6514 { 6515 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED))) 6516 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c; 6517 } 6518 6519 static __always_inline void intel_pmu_init_glc(struct pmu *pmu) 6520 { 6521 x86_pmu.late_ack = true; 6522 x86_pmu.limit_period = glc_limit_period; 6523 x86_pmu.pebs_aliases = NULL; 6524 x86_pmu.pebs_prec_dist = true; 6525 x86_pmu.pebs_block = true; 6526 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6527 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6528 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6529 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6530 x86_pmu.lbr_pt_coexist = true; 6531 x86_pmu.num_topdown_events = 8; 6532 static_call_update(intel_pmu_update_topdown_event, 6533 &icl_update_topdown_event); 6534 static_call_update(intel_pmu_set_topdown_event_period, 6535 &icl_set_topdown_event_period); 6536 6537 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6538 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6539 hybrid(pmu, event_constraints) = intel_glc_event_constraints; 6540 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints; 6541 6542 intel_pmu_ref_cycles_ext(); 6543 } 6544 6545 static __always_inline void intel_pmu_init_grt(struct pmu *pmu) 6546 { 6547 x86_pmu.mid_ack = true; 6548 x86_pmu.limit_period = glc_limit_period; 6549 x86_pmu.pebs_aliases = NULL; 6550 x86_pmu.pebs_prec_dist = true; 6551 x86_pmu.pebs_block = true; 6552 x86_pmu.lbr_pt_coexist = true; 6553 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6554 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6555 6556 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6557 memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6558 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6559 hybrid(pmu, event_constraints) = intel_grt_event_constraints; 6560 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints; 6561 hybrid(pmu, extra_regs) = intel_grt_extra_regs; 6562 6563 intel_pmu_ref_cycles_ext(); 6564 } 6565 6566 static __always_inline void intel_pmu_init_lnc(struct pmu *pmu) 6567 { 6568 intel_pmu_init_glc(pmu); 6569 hybrid(pmu, event_constraints) = intel_lnc_event_constraints; 6570 hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints; 6571 hybrid(pmu, extra_regs) = intel_lnc_extra_regs; 6572 } 6573 6574 static __always_inline void intel_pmu_init_skt(struct pmu *pmu) 6575 { 6576 intel_pmu_init_grt(pmu); 6577 hybrid(pmu, event_constraints) = intel_skt_event_constraints; 6578 hybrid(pmu, extra_regs) = intel_cmt_extra_regs; 6579 } 6580 6581 __init int intel_pmu_init(void) 6582 { 6583 struct attribute **extra_skl_attr = &empty_attrs; 6584 struct attribute **extra_attr = &empty_attrs; 6585 struct attribute **td_attr = &empty_attrs; 6586 struct attribute **mem_attr = &empty_attrs; 6587 struct attribute **tsx_attr = &empty_attrs; 6588 union cpuid10_edx edx; 6589 union cpuid10_eax eax; 6590 union cpuid10_ebx ebx; 6591 unsigned int fixed_mask; 6592 bool pmem = false; 6593 int version, i; 6594 char *name; 6595 struct x86_hybrid_pmu *pmu; 6596 6597 /* Architectural Perfmon was introduced starting with Core "Yonah" */ 6598 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 6599 switch (boot_cpu_data.x86) { 6600 case 6: 6601 if (boot_cpu_data.x86_vfm < INTEL_CORE_YONAH) 6602 return p6_pmu_init(); 6603 break; 6604 case 11: 6605 return knc_pmu_init(); 6606 case 15: 6607 return p4_pmu_init(); 6608 } 6609 6610 pr_cont("unsupported CPU family %d model %d ", 6611 boot_cpu_data.x86, boot_cpu_data.x86_model); 6612 return -ENODEV; 6613 } 6614 6615 /* 6616 * Check whether the Architectural PerfMon supports 6617 * Branch Misses Retired hw_event or not. 6618 */ 6619 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); 6620 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 6621 return -ENODEV; 6622 6623 version = eax.split.version_id; 6624 if (version < 2) 6625 x86_pmu = core_pmu; 6626 else 6627 x86_pmu = intel_pmu; 6628 6629 x86_pmu.version = version; 6630 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0); 6631 x86_pmu.cntval_bits = eax.split.bit_width; 6632 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 6633 6634 x86_pmu.events_maskl = ebx.full; 6635 x86_pmu.events_mask_len = eax.split.mask_length; 6636 6637 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64); 6638 x86_pmu.pebs_capable = PEBS_COUNTER_MASK; 6639 6640 /* 6641 * Quirk: v2 perfmon does not report fixed-purpose events, so 6642 * assume at least 3 events, when not running in a hypervisor: 6643 */ 6644 if (version > 1 && version < 5) { 6645 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 6646 6647 x86_pmu.fixed_cntr_mask64 = 6648 GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0); 6649 } else if (version >= 5) 6650 x86_pmu.fixed_cntr_mask64 = fixed_mask; 6651 6652 if (boot_cpu_has(X86_FEATURE_PDCM)) { 6653 u64 capabilities; 6654 6655 rdmsrq(MSR_IA32_PERF_CAPABILITIES, capabilities); 6656 x86_pmu.intel_cap.capabilities = capabilities; 6657 } 6658 6659 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 6660 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 6661 x86_pmu.lbr_read = intel_pmu_lbr_read_32; 6662 } 6663 6664 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 6665 intel_pmu_arch_lbr_init(); 6666 6667 intel_ds_init(); 6668 6669 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 6670 6671 if (version >= 5) { 6672 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 6673 if (x86_pmu.intel_cap.anythread_deprecated) 6674 pr_cont(" AnyThread deprecated, "); 6675 } 6676 6677 /* 6678 * Install the hw-cache-events table: 6679 */ 6680 switch (boot_cpu_data.x86_vfm) { 6681 case INTEL_CORE_YONAH: 6682 pr_cont("Core events, "); 6683 name = "core"; 6684 break; 6685 6686 case INTEL_CORE2_MEROM: 6687 x86_add_quirk(intel_clovertown_quirk); 6688 fallthrough; 6689 6690 case INTEL_CORE2_MEROM_L: 6691 case INTEL_CORE2_PENRYN: 6692 case INTEL_CORE2_DUNNINGTON: 6693 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 6694 sizeof(hw_cache_event_ids)); 6695 6696 intel_pmu_lbr_init_core(); 6697 6698 x86_pmu.event_constraints = intel_core2_event_constraints; 6699 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 6700 pr_cont("Core2 events, "); 6701 name = "core2"; 6702 break; 6703 6704 case INTEL_NEHALEM: 6705 case INTEL_NEHALEM_EP: 6706 case INTEL_NEHALEM_EX: 6707 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 6708 sizeof(hw_cache_event_ids)); 6709 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 6710 sizeof(hw_cache_extra_regs)); 6711 6712 intel_pmu_lbr_init_nhm(); 6713 6714 x86_pmu.event_constraints = intel_nehalem_event_constraints; 6715 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 6716 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 6717 x86_pmu.extra_regs = intel_nehalem_extra_regs; 6718 x86_pmu.limit_period = nhm_limit_period; 6719 6720 mem_attr = nhm_mem_events_attrs; 6721 6722 /* UOPS_ISSUED.STALLED_CYCLES */ 6723 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6724 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6725 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 6726 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6727 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 6728 6729 intel_pmu_pebs_data_source_nhm(); 6730 x86_add_quirk(intel_nehalem_quirk); 6731 x86_pmu.pebs_no_tlb = 1; 6732 extra_attr = nhm_format_attr; 6733 6734 pr_cont("Nehalem events, "); 6735 name = "nehalem"; 6736 break; 6737 6738 case INTEL_ATOM_BONNELL: 6739 case INTEL_ATOM_BONNELL_MID: 6740 case INTEL_ATOM_SALTWELL: 6741 case INTEL_ATOM_SALTWELL_MID: 6742 case INTEL_ATOM_SALTWELL_TABLET: 6743 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 6744 sizeof(hw_cache_event_ids)); 6745 6746 intel_pmu_lbr_init_atom(); 6747 6748 x86_pmu.event_constraints = intel_gen_event_constraints; 6749 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 6750 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 6751 pr_cont("Atom events, "); 6752 name = "bonnell"; 6753 break; 6754 6755 case INTEL_ATOM_SILVERMONT: 6756 case INTEL_ATOM_SILVERMONT_D: 6757 case INTEL_ATOM_SILVERMONT_MID: 6758 case INTEL_ATOM_AIRMONT: 6759 case INTEL_ATOM_SILVERMONT_MID2: 6760 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 6761 sizeof(hw_cache_event_ids)); 6762 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 6763 sizeof(hw_cache_extra_regs)); 6764 6765 intel_pmu_lbr_init_slm(); 6766 6767 x86_pmu.event_constraints = intel_slm_event_constraints; 6768 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 6769 x86_pmu.extra_regs = intel_slm_extra_regs; 6770 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6771 td_attr = slm_events_attrs; 6772 extra_attr = slm_format_attr; 6773 pr_cont("Silvermont events, "); 6774 name = "silvermont"; 6775 break; 6776 6777 case INTEL_ATOM_GOLDMONT: 6778 case INTEL_ATOM_GOLDMONT_D: 6779 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 6780 sizeof(hw_cache_event_ids)); 6781 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 6782 sizeof(hw_cache_extra_regs)); 6783 6784 intel_pmu_lbr_init_skl(); 6785 6786 x86_pmu.event_constraints = intel_slm_event_constraints; 6787 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 6788 x86_pmu.extra_regs = intel_glm_extra_regs; 6789 /* 6790 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 6791 * for precise cycles. 6792 * :pp is identical to :ppp 6793 */ 6794 x86_pmu.pebs_aliases = NULL; 6795 x86_pmu.pebs_prec_dist = true; 6796 x86_pmu.lbr_pt_coexist = true; 6797 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6798 td_attr = glm_events_attrs; 6799 extra_attr = slm_format_attr; 6800 pr_cont("Goldmont events, "); 6801 name = "goldmont"; 6802 break; 6803 6804 case INTEL_ATOM_GOLDMONT_PLUS: 6805 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 6806 sizeof(hw_cache_event_ids)); 6807 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 6808 sizeof(hw_cache_extra_regs)); 6809 6810 intel_pmu_lbr_init_skl(); 6811 6812 x86_pmu.event_constraints = intel_slm_event_constraints; 6813 x86_pmu.extra_regs = intel_glm_extra_regs; 6814 /* 6815 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 6816 * for precise cycles. 6817 */ 6818 x86_pmu.pebs_aliases = NULL; 6819 x86_pmu.pebs_prec_dist = true; 6820 x86_pmu.lbr_pt_coexist = true; 6821 x86_pmu.pebs_capable = ~0ULL; 6822 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6823 x86_pmu.flags |= PMU_FL_PEBS_ALL; 6824 x86_pmu.get_event_constraints = glp_get_event_constraints; 6825 td_attr = glm_events_attrs; 6826 /* Goldmont Plus has 4-wide pipeline */ 6827 event_attr_td_total_slots_scale_glm.event_str = "4"; 6828 extra_attr = slm_format_attr; 6829 pr_cont("Goldmont plus events, "); 6830 name = "goldmont_plus"; 6831 break; 6832 6833 case INTEL_ATOM_TREMONT_D: 6834 case INTEL_ATOM_TREMONT: 6835 case INTEL_ATOM_TREMONT_L: 6836 x86_pmu.late_ack = true; 6837 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 6838 sizeof(hw_cache_event_ids)); 6839 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 6840 sizeof(hw_cache_extra_regs)); 6841 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6842 6843 intel_pmu_lbr_init_skl(); 6844 6845 x86_pmu.event_constraints = intel_slm_event_constraints; 6846 x86_pmu.extra_regs = intel_tnt_extra_regs; 6847 /* 6848 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 6849 * for precise cycles. 6850 */ 6851 x86_pmu.pebs_aliases = NULL; 6852 x86_pmu.pebs_prec_dist = true; 6853 x86_pmu.lbr_pt_coexist = true; 6854 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6855 x86_pmu.get_event_constraints = tnt_get_event_constraints; 6856 td_attr = tnt_events_attrs; 6857 extra_attr = slm_format_attr; 6858 pr_cont("Tremont events, "); 6859 name = "Tremont"; 6860 break; 6861 6862 case INTEL_ATOM_GRACEMONT: 6863 intel_pmu_init_grt(NULL); 6864 intel_pmu_pebs_data_source_grt(); 6865 x86_pmu.pebs_latency_data = grt_latency_data; 6866 x86_pmu.get_event_constraints = tnt_get_event_constraints; 6867 td_attr = tnt_events_attrs; 6868 mem_attr = grt_mem_attrs; 6869 extra_attr = nhm_format_attr; 6870 pr_cont("Gracemont events, "); 6871 name = "gracemont"; 6872 break; 6873 6874 case INTEL_ATOM_CRESTMONT: 6875 case INTEL_ATOM_CRESTMONT_X: 6876 intel_pmu_init_grt(NULL); 6877 x86_pmu.extra_regs = intel_cmt_extra_regs; 6878 intel_pmu_pebs_data_source_cmt(); 6879 x86_pmu.pebs_latency_data = cmt_latency_data; 6880 x86_pmu.get_event_constraints = cmt_get_event_constraints; 6881 td_attr = cmt_events_attrs; 6882 mem_attr = grt_mem_attrs; 6883 extra_attr = cmt_format_attr; 6884 pr_cont("Crestmont events, "); 6885 name = "crestmont"; 6886 break; 6887 6888 case INTEL_WESTMERE: 6889 case INTEL_WESTMERE_EP: 6890 case INTEL_WESTMERE_EX: 6891 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 6892 sizeof(hw_cache_event_ids)); 6893 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 6894 sizeof(hw_cache_extra_regs)); 6895 6896 intel_pmu_lbr_init_nhm(); 6897 6898 x86_pmu.event_constraints = intel_westmere_event_constraints; 6899 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 6900 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 6901 x86_pmu.extra_regs = intel_westmere_extra_regs; 6902 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6903 6904 mem_attr = nhm_mem_events_attrs; 6905 6906 /* UOPS_ISSUED.STALLED_CYCLES */ 6907 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6908 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6909 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 6910 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6911 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 6912 6913 intel_pmu_pebs_data_source_nhm(); 6914 extra_attr = nhm_format_attr; 6915 pr_cont("Westmere events, "); 6916 name = "westmere"; 6917 break; 6918 6919 case INTEL_SANDYBRIDGE: 6920 case INTEL_SANDYBRIDGE_X: 6921 x86_add_quirk(intel_sandybridge_quirk); 6922 x86_add_quirk(intel_ht_bug); 6923 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 6924 sizeof(hw_cache_event_ids)); 6925 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 6926 sizeof(hw_cache_extra_regs)); 6927 6928 intel_pmu_lbr_init_snb(); 6929 6930 x86_pmu.event_constraints = intel_snb_event_constraints; 6931 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 6932 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 6933 if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X) 6934 x86_pmu.extra_regs = intel_snbep_extra_regs; 6935 else 6936 x86_pmu.extra_regs = intel_snb_extra_regs; 6937 6938 6939 /* all extra regs are per-cpu when HT is on */ 6940 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6941 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6942 6943 td_attr = snb_events_attrs; 6944 mem_attr = snb_mem_events_attrs; 6945 6946 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 6947 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6948 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6949 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 6950 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6951 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 6952 6953 extra_attr = nhm_format_attr; 6954 6955 pr_cont("SandyBridge events, "); 6956 name = "sandybridge"; 6957 break; 6958 6959 case INTEL_IVYBRIDGE: 6960 case INTEL_IVYBRIDGE_X: 6961 x86_add_quirk(intel_ht_bug); 6962 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 6963 sizeof(hw_cache_event_ids)); 6964 /* dTLB-load-misses on IVB is different than SNB */ 6965 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 6966 6967 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 6968 sizeof(hw_cache_extra_regs)); 6969 6970 intel_pmu_lbr_init_snb(); 6971 6972 x86_pmu.event_constraints = intel_ivb_event_constraints; 6973 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 6974 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6975 x86_pmu.pebs_prec_dist = true; 6976 if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X) 6977 x86_pmu.extra_regs = intel_snbep_extra_regs; 6978 else 6979 x86_pmu.extra_regs = intel_snb_extra_regs; 6980 /* all extra regs are per-cpu when HT is on */ 6981 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6982 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6983 6984 td_attr = snb_events_attrs; 6985 mem_attr = snb_mem_events_attrs; 6986 6987 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 6988 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6989 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6990 6991 extra_attr = nhm_format_attr; 6992 6993 pr_cont("IvyBridge events, "); 6994 name = "ivybridge"; 6995 break; 6996 6997 6998 case INTEL_HASWELL: 6999 case INTEL_HASWELL_X: 7000 case INTEL_HASWELL_L: 7001 case INTEL_HASWELL_G: 7002 x86_add_quirk(intel_ht_bug); 7003 x86_add_quirk(intel_pebs_isolation_quirk); 7004 x86_pmu.late_ack = true; 7005 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7006 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7007 7008 intel_pmu_lbr_init_hsw(); 7009 7010 x86_pmu.event_constraints = intel_hsw_event_constraints; 7011 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 7012 x86_pmu.extra_regs = intel_snbep_extra_regs; 7013 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 7014 x86_pmu.pebs_prec_dist = true; 7015 /* all extra regs are per-cpu when HT is on */ 7016 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7017 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7018 7019 x86_pmu.hw_config = hsw_hw_config; 7020 x86_pmu.get_event_constraints = hsw_get_event_constraints; 7021 x86_pmu.limit_period = hsw_limit_period; 7022 x86_pmu.lbr_double_abort = true; 7023 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7024 hsw_format_attr : nhm_format_attr; 7025 td_attr = hsw_events_attrs; 7026 mem_attr = hsw_mem_events_attrs; 7027 tsx_attr = hsw_tsx_events_attrs; 7028 pr_cont("Haswell events, "); 7029 name = "haswell"; 7030 break; 7031 7032 case INTEL_BROADWELL: 7033 case INTEL_BROADWELL_D: 7034 case INTEL_BROADWELL_G: 7035 case INTEL_BROADWELL_X: 7036 x86_add_quirk(intel_pebs_isolation_quirk); 7037 x86_pmu.late_ack = true; 7038 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7039 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7040 7041 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 7042 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 7043 BDW_L3_MISS|HSW_SNOOP_DRAM; 7044 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 7045 HSW_SNOOP_DRAM; 7046 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 7047 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 7048 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 7049 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 7050 7051 intel_pmu_lbr_init_hsw(); 7052 7053 x86_pmu.event_constraints = intel_bdw_event_constraints; 7054 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 7055 x86_pmu.extra_regs = intel_snbep_extra_regs; 7056 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 7057 x86_pmu.pebs_prec_dist = true; 7058 /* all extra regs are per-cpu when HT is on */ 7059 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7060 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7061 7062 x86_pmu.hw_config = hsw_hw_config; 7063 x86_pmu.get_event_constraints = hsw_get_event_constraints; 7064 x86_pmu.limit_period = bdw_limit_period; 7065 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7066 hsw_format_attr : nhm_format_attr; 7067 td_attr = hsw_events_attrs; 7068 mem_attr = hsw_mem_events_attrs; 7069 tsx_attr = hsw_tsx_events_attrs; 7070 pr_cont("Broadwell events, "); 7071 name = "broadwell"; 7072 break; 7073 7074 case INTEL_XEON_PHI_KNL: 7075 case INTEL_XEON_PHI_KNM: 7076 memcpy(hw_cache_event_ids, 7077 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7078 memcpy(hw_cache_extra_regs, 7079 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7080 intel_pmu_lbr_init_knl(); 7081 7082 x86_pmu.event_constraints = intel_slm_event_constraints; 7083 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 7084 x86_pmu.extra_regs = intel_knl_extra_regs; 7085 7086 /* all extra regs are per-cpu when HT is on */ 7087 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7088 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7089 extra_attr = slm_format_attr; 7090 pr_cont("Knights Landing/Mill events, "); 7091 name = "knights-landing"; 7092 break; 7093 7094 case INTEL_SKYLAKE_X: 7095 pmem = true; 7096 fallthrough; 7097 case INTEL_SKYLAKE_L: 7098 case INTEL_SKYLAKE: 7099 case INTEL_KABYLAKE_L: 7100 case INTEL_KABYLAKE: 7101 case INTEL_COMETLAKE_L: 7102 case INTEL_COMETLAKE: 7103 x86_add_quirk(intel_pebs_isolation_quirk); 7104 x86_pmu.late_ack = true; 7105 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7106 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7107 intel_pmu_lbr_init_skl(); 7108 7109 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 7110 event_attr_td_recovery_bubbles.event_str_noht = 7111 "event=0xd,umask=0x1,cmask=1"; 7112 event_attr_td_recovery_bubbles.event_str_ht = 7113 "event=0xd,umask=0x1,cmask=1,any=1"; 7114 7115 x86_pmu.event_constraints = intel_skl_event_constraints; 7116 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 7117 x86_pmu.extra_regs = intel_skl_extra_regs; 7118 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 7119 x86_pmu.pebs_prec_dist = true; 7120 /* all extra regs are per-cpu when HT is on */ 7121 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7122 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7123 7124 x86_pmu.hw_config = hsw_hw_config; 7125 x86_pmu.get_event_constraints = hsw_get_event_constraints; 7126 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7127 hsw_format_attr : nhm_format_attr; 7128 extra_skl_attr = skl_format_attr; 7129 td_attr = hsw_events_attrs; 7130 mem_attr = hsw_mem_events_attrs; 7131 tsx_attr = hsw_tsx_events_attrs; 7132 intel_pmu_pebs_data_source_skl(pmem); 7133 7134 /* 7135 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. 7136 * TSX force abort hooks are not required on these systems. Only deploy 7137 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. 7138 */ 7139 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && 7140 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { 7141 x86_pmu.flags |= PMU_FL_TFA; 7142 x86_pmu.get_event_constraints = tfa_get_event_constraints; 7143 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 7144 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 7145 } 7146 7147 pr_cont("Skylake events, "); 7148 name = "skylake"; 7149 break; 7150 7151 case INTEL_ICELAKE_X: 7152 case INTEL_ICELAKE_D: 7153 x86_pmu.pebs_ept = 1; 7154 pmem = true; 7155 fallthrough; 7156 case INTEL_ICELAKE_L: 7157 case INTEL_ICELAKE: 7158 case INTEL_TIGERLAKE_L: 7159 case INTEL_TIGERLAKE: 7160 case INTEL_ROCKETLAKE: 7161 x86_pmu.late_ack = true; 7162 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7163 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7164 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 7165 intel_pmu_lbr_init_skl(); 7166 7167 x86_pmu.event_constraints = intel_icl_event_constraints; 7168 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 7169 x86_pmu.extra_regs = intel_icl_extra_regs; 7170 x86_pmu.pebs_aliases = NULL; 7171 x86_pmu.pebs_prec_dist = true; 7172 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7173 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7174 7175 x86_pmu.hw_config = hsw_hw_config; 7176 x86_pmu.get_event_constraints = icl_get_event_constraints; 7177 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7178 hsw_format_attr : nhm_format_attr; 7179 extra_skl_attr = skl_format_attr; 7180 mem_attr = icl_events_attrs; 7181 td_attr = icl_td_events_attrs; 7182 tsx_attr = icl_tsx_events_attrs; 7183 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 7184 x86_pmu.lbr_pt_coexist = true; 7185 intel_pmu_pebs_data_source_skl(pmem); 7186 x86_pmu.num_topdown_events = 4; 7187 static_call_update(intel_pmu_update_topdown_event, 7188 &icl_update_topdown_event); 7189 static_call_update(intel_pmu_set_topdown_event_period, 7190 &icl_set_topdown_event_period); 7191 pr_cont("Icelake events, "); 7192 name = "icelake"; 7193 break; 7194 7195 case INTEL_SAPPHIRERAPIDS_X: 7196 case INTEL_EMERALDRAPIDS_X: 7197 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 7198 x86_pmu.extra_regs = intel_glc_extra_regs; 7199 pr_cont("Sapphire Rapids events, "); 7200 name = "sapphire_rapids"; 7201 goto glc_common; 7202 7203 case INTEL_GRANITERAPIDS_X: 7204 case INTEL_GRANITERAPIDS_D: 7205 x86_pmu.extra_regs = intel_rwc_extra_regs; 7206 pr_cont("Granite Rapids events, "); 7207 name = "granite_rapids"; 7208 7209 glc_common: 7210 intel_pmu_init_glc(NULL); 7211 x86_pmu.pebs_ept = 1; 7212 x86_pmu.hw_config = hsw_hw_config; 7213 x86_pmu.get_event_constraints = glc_get_event_constraints; 7214 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7215 hsw_format_attr : nhm_format_attr; 7216 extra_skl_attr = skl_format_attr; 7217 mem_attr = glc_events_attrs; 7218 td_attr = glc_td_events_attrs; 7219 tsx_attr = glc_tsx_events_attrs; 7220 intel_pmu_pebs_data_source_skl(true); 7221 break; 7222 7223 case INTEL_ALDERLAKE: 7224 case INTEL_ALDERLAKE_L: 7225 case INTEL_RAPTORLAKE: 7226 case INTEL_RAPTORLAKE_P: 7227 case INTEL_RAPTORLAKE_S: 7228 /* 7229 * Alder Lake has 2 types of CPU, core and atom. 7230 * 7231 * Initialize the common PerfMon capabilities here. 7232 */ 7233 intel_pmu_init_hybrid(hybrid_big_small); 7234 7235 x86_pmu.pebs_latency_data = grt_latency_data; 7236 x86_pmu.get_event_constraints = adl_get_event_constraints; 7237 x86_pmu.hw_config = adl_hw_config; 7238 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; 7239 7240 td_attr = adl_hybrid_events_attrs; 7241 mem_attr = adl_hybrid_mem_attrs; 7242 tsx_attr = adl_hybrid_tsx_attrs; 7243 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7244 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; 7245 7246 /* Initialize big core specific PerfMon capabilities.*/ 7247 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7248 intel_pmu_init_glc(&pmu->pmu); 7249 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 7250 pmu->cntr_mask64 <<= 2; 7251 pmu->cntr_mask64 |= 0x3; 7252 pmu->fixed_cntr_mask64 <<= 1; 7253 pmu->fixed_cntr_mask64 |= 0x1; 7254 } else { 7255 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 7256 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 7257 } 7258 7259 /* 7260 * Quirk: For some Alder Lake machine, when all E-cores are disabled in 7261 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However, 7262 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will 7263 * mistakenly add extra counters for P-cores. Correct the number of 7264 * counters here. 7265 */ 7266 if ((x86_pmu_num_counters(&pmu->pmu) > 8) || (x86_pmu_num_counters_fixed(&pmu->pmu) > 4)) { 7267 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 7268 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 7269 } 7270 7271 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 7272 pmu->unconstrained = (struct event_constraint) 7273 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 7274 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 7275 7276 pmu->extra_regs = intel_glc_extra_regs; 7277 7278 /* Initialize Atom core specific PerfMon capabilities.*/ 7279 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7280 intel_pmu_init_grt(&pmu->pmu); 7281 7282 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 7283 intel_pmu_pebs_data_source_adl(); 7284 pr_cont("Alderlake Hybrid events, "); 7285 name = "alderlake_hybrid"; 7286 break; 7287 7288 case INTEL_METEORLAKE: 7289 case INTEL_METEORLAKE_L: 7290 case INTEL_ARROWLAKE_U: 7291 intel_pmu_init_hybrid(hybrid_big_small); 7292 7293 x86_pmu.pebs_latency_data = cmt_latency_data; 7294 x86_pmu.get_event_constraints = mtl_get_event_constraints; 7295 x86_pmu.hw_config = adl_hw_config; 7296 7297 td_attr = adl_hybrid_events_attrs; 7298 mem_attr = mtl_hybrid_mem_attrs; 7299 tsx_attr = adl_hybrid_tsx_attrs; 7300 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7301 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 7302 7303 /* Initialize big core specific PerfMon capabilities.*/ 7304 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7305 intel_pmu_init_glc(&pmu->pmu); 7306 pmu->extra_regs = intel_rwc_extra_regs; 7307 7308 /* Initialize Atom core specific PerfMon capabilities.*/ 7309 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7310 intel_pmu_init_grt(&pmu->pmu); 7311 pmu->extra_regs = intel_cmt_extra_regs; 7312 7313 intel_pmu_pebs_data_source_mtl(); 7314 pr_cont("Meteorlake Hybrid events, "); 7315 name = "meteorlake_hybrid"; 7316 break; 7317 7318 case INTEL_PANTHERLAKE_L: 7319 pr_cont("Pantherlake Hybrid events, "); 7320 name = "pantherlake_hybrid"; 7321 goto lnl_common; 7322 7323 case INTEL_LUNARLAKE_M: 7324 case INTEL_ARROWLAKE: 7325 pr_cont("Lunarlake Hybrid events, "); 7326 name = "lunarlake_hybrid"; 7327 7328 lnl_common: 7329 intel_pmu_init_hybrid(hybrid_big_small); 7330 7331 x86_pmu.pebs_latency_data = lnl_latency_data; 7332 x86_pmu.get_event_constraints = mtl_get_event_constraints; 7333 x86_pmu.hw_config = adl_hw_config; 7334 7335 td_attr = lnl_hybrid_events_attrs; 7336 mem_attr = mtl_hybrid_mem_attrs; 7337 tsx_attr = adl_hybrid_tsx_attrs; 7338 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7339 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 7340 7341 /* Initialize big core specific PerfMon capabilities.*/ 7342 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7343 intel_pmu_init_lnc(&pmu->pmu); 7344 7345 /* Initialize Atom core specific PerfMon capabilities.*/ 7346 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7347 intel_pmu_init_skt(&pmu->pmu); 7348 7349 intel_pmu_pebs_data_source_lnl(); 7350 break; 7351 7352 case INTEL_ARROWLAKE_H: 7353 intel_pmu_init_hybrid(hybrid_big_small_tiny); 7354 7355 x86_pmu.pebs_latency_data = arl_h_latency_data; 7356 x86_pmu.get_event_constraints = arl_h_get_event_constraints; 7357 x86_pmu.hw_config = arl_h_hw_config; 7358 7359 td_attr = arl_h_hybrid_events_attrs; 7360 mem_attr = arl_h_hybrid_mem_attrs; 7361 tsx_attr = adl_hybrid_tsx_attrs; 7362 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7363 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 7364 7365 /* Initialize big core specific PerfMon capabilities. */ 7366 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7367 intel_pmu_init_lnc(&pmu->pmu); 7368 7369 /* Initialize Atom core specific PerfMon capabilities. */ 7370 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7371 intel_pmu_init_skt(&pmu->pmu); 7372 7373 /* Initialize Lower Power Atom specific PerfMon capabilities. */ 7374 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX]; 7375 intel_pmu_init_grt(&pmu->pmu); 7376 pmu->extra_regs = intel_cmt_extra_regs; 7377 7378 intel_pmu_pebs_data_source_arl_h(); 7379 pr_cont("ArrowLake-H Hybrid events, "); 7380 name = "arrowlake_h_hybrid"; 7381 break; 7382 7383 default: 7384 switch (x86_pmu.version) { 7385 case 1: 7386 x86_pmu.event_constraints = intel_v1_event_constraints; 7387 pr_cont("generic architected perfmon v1, "); 7388 name = "generic_arch_v1"; 7389 break; 7390 case 2: 7391 case 3: 7392 case 4: 7393 /* 7394 * default constraints for v2 and up 7395 */ 7396 x86_pmu.event_constraints = intel_gen_event_constraints; 7397 pr_cont("generic architected perfmon, "); 7398 name = "generic_arch_v2+"; 7399 break; 7400 default: 7401 /* 7402 * The default constraints for v5 and up can support up to 7403 * 16 fixed counters. For the fixed counters 4 and later, 7404 * the pseudo-encoding is applied. 7405 * The constraints may be cut according to the CPUID enumeration 7406 * by inserting the EVENT_CONSTRAINT_END. 7407 */ 7408 if (fls64(x86_pmu.fixed_cntr_mask64) > INTEL_PMC_MAX_FIXED) 7409 x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0); 7410 intel_v5_gen_event_constraints[fls64(x86_pmu.fixed_cntr_mask64)].weight = -1; 7411 x86_pmu.event_constraints = intel_v5_gen_event_constraints; 7412 pr_cont("generic architected perfmon, "); 7413 name = "generic_arch_v5+"; 7414 break; 7415 } 7416 } 7417 7418 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 7419 7420 if (!is_hybrid()) { 7421 group_events_td.attrs = td_attr; 7422 group_events_mem.attrs = mem_attr; 7423 group_events_tsx.attrs = tsx_attr; 7424 group_format_extra.attrs = extra_attr; 7425 group_format_extra_skl.attrs = extra_skl_attr; 7426 7427 x86_pmu.attr_update = attr_update; 7428 } else { 7429 hybrid_group_events_td.attrs = td_attr; 7430 hybrid_group_events_mem.attrs = mem_attr; 7431 hybrid_group_events_tsx.attrs = tsx_attr; 7432 hybrid_group_format_extra.attrs = extra_attr; 7433 7434 x86_pmu.attr_update = hybrid_attr_update; 7435 } 7436 7437 intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64, 7438 &x86_pmu.fixed_cntr_mask64, 7439 &x86_pmu.intel_ctrl); 7440 7441 /* AnyThread may be deprecated on arch perfmon v5 or later */ 7442 if (x86_pmu.intel_cap.anythread_deprecated) 7443 x86_pmu.format_attrs = intel_arch_formats_attr; 7444 7445 intel_pmu_check_event_constraints(x86_pmu.event_constraints, 7446 x86_pmu.cntr_mask64, 7447 x86_pmu.fixed_cntr_mask64, 7448 x86_pmu.intel_ctrl); 7449 /* 7450 * Access LBR MSR may cause #GP under certain circumstances. 7451 * Check all LBR MSR here. 7452 * Disable LBR access if any LBR MSRs can not be accessed. 7453 */ 7454 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 7455 x86_pmu.lbr_nr = 0; 7456 for (i = 0; i < x86_pmu.lbr_nr; i++) { 7457 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 7458 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 7459 x86_pmu.lbr_nr = 0; 7460 } 7461 7462 if (x86_pmu.lbr_nr) { 7463 intel_pmu_lbr_init(); 7464 7465 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 7466 7467 /* only support branch_stack snapshot for perfmon >= v2 */ 7468 if (x86_pmu.disable_all == intel_pmu_disable_all) { 7469 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) { 7470 static_call_update(perf_snapshot_branch_stack, 7471 intel_pmu_snapshot_arch_branch_stack); 7472 } else { 7473 static_call_update(perf_snapshot_branch_stack, 7474 intel_pmu_snapshot_branch_stack); 7475 } 7476 } 7477 } 7478 7479 intel_pmu_check_extra_regs(x86_pmu.extra_regs); 7480 7481 /* Support full width counters using alternative MSR range */ 7482 if (x86_pmu.intel_cap.full_width_write) { 7483 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 7484 x86_pmu.perfctr = MSR_IA32_PMC0; 7485 pr_cont("full-width counters, "); 7486 } 7487 7488 /* Support V6+ MSR Aliasing */ 7489 if (x86_pmu.version >= 6) { 7490 x86_pmu.perfctr = MSR_IA32_PMC_V6_GP0_CTR; 7491 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A; 7492 x86_pmu.fixedctr = MSR_IA32_PMC_V6_FX0_CTR; 7493 x86_pmu.addr_offset = intel_pmu_v6_addr_offset; 7494 } 7495 7496 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 7497 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 7498 7499 if (x86_pmu.intel_cap.pebs_timing_info) 7500 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY; 7501 7502 intel_aux_output_init(); 7503 7504 return 0; 7505 } 7506 7507 /* 7508 * HT bug: phase 2 init 7509 * Called once we have valid topology information to check 7510 * whether or not HT is enabled 7511 * If HT is off, then we disable the workaround 7512 */ 7513 static __init int fixup_ht_bug(void) 7514 { 7515 int c; 7516 /* 7517 * problem not present on this CPU model, nothing to do 7518 */ 7519 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 7520 return 0; 7521 7522 if (topology_max_smt_threads() > 1) { 7523 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 7524 return 0; 7525 } 7526 7527 cpus_read_lock(); 7528 7529 hardlockup_detector_perf_stop(); 7530 7531 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 7532 7533 x86_pmu.start_scheduling = NULL; 7534 x86_pmu.commit_scheduling = NULL; 7535 x86_pmu.stop_scheduling = NULL; 7536 7537 hardlockup_detector_perf_restart(); 7538 7539 for_each_online_cpu(c) 7540 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 7541 7542 cpus_read_unlock(); 7543 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 7544 return 0; 7545 } 7546 subsys_initcall(fixup_ht_bug) 7547