1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Per core/cpu state 4 * 5 * Used to coordinate shared registers between HT threads or 6 * among events on a single PMU. 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/stddef.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/export.h> 16 #include <linux/nmi.h> 17 #include <linux/kvm_host.h> 18 19 #include <asm/cpufeature.h> 20 #include <asm/debugreg.h> 21 #include <asm/hardirq.h> 22 #include <asm/intel-family.h> 23 #include <asm/intel_pt.h> 24 #include <asm/apic.h> 25 #include <asm/cpu_device_id.h> 26 #include <asm/msr.h> 27 28 #include "../perf_event.h" 29 30 /* 31 * Intel PerfMon, used on Core and later. 32 */ 33 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 34 { 35 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 36 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 37 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 38 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 39 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 40 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 41 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 42 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 43 }; 44 45 static struct event_constraint intel_core_event_constraints[] __read_mostly = 46 { 47 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 48 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 49 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 50 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 51 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 52 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 53 EVENT_CONSTRAINT_END 54 }; 55 56 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 57 { 58 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 59 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 60 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 61 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 62 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 63 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 64 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 65 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 66 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 67 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 68 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 69 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 70 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 71 EVENT_CONSTRAINT_END 72 }; 73 74 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 75 { 76 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 77 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 78 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 79 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 80 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 81 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 82 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 83 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 84 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 85 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 86 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 87 EVENT_CONSTRAINT_END 88 }; 89 90 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 91 { 92 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 93 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 94 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 95 EVENT_EXTRA_END 96 }; 97 98 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 99 { 100 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 101 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 102 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 103 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 104 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 105 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 106 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 107 EVENT_CONSTRAINT_END 108 }; 109 110 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 111 { 112 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 113 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 114 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 115 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 116 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 117 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 118 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 119 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 120 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 121 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 122 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 123 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 124 125 /* 126 * When HT is off these events can only run on the bottom 4 counters 127 * When HT is on, they are impacted by the HT bug and require EXCL access 128 */ 129 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 130 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 131 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 132 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 133 134 EVENT_CONSTRAINT_END 135 }; 136 137 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 138 { 139 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 140 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 141 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 142 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 143 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ 144 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 145 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 146 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 147 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 148 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 149 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 150 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 151 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 152 153 /* 154 * When HT is off these events can only run on the bottom 4 counters 155 * When HT is on, they are impacted by the HT bug and require EXCL access 156 */ 157 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 158 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 159 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 160 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 161 162 EVENT_CONSTRAINT_END 163 }; 164 165 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 166 { 167 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 168 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 169 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 170 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 171 EVENT_EXTRA_END 172 }; 173 174 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 175 { 176 EVENT_CONSTRAINT_END 177 }; 178 179 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 180 { 181 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 182 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 183 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 184 EVENT_CONSTRAINT_END 185 }; 186 187 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly = 188 { 189 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 190 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 191 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 192 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 193 FIXED_EVENT_CONSTRAINT(0x0500, 4), 194 FIXED_EVENT_CONSTRAINT(0x0600, 5), 195 FIXED_EVENT_CONSTRAINT(0x0700, 6), 196 FIXED_EVENT_CONSTRAINT(0x0800, 7), 197 FIXED_EVENT_CONSTRAINT(0x0900, 8), 198 FIXED_EVENT_CONSTRAINT(0x0a00, 9), 199 FIXED_EVENT_CONSTRAINT(0x0b00, 10), 200 FIXED_EVENT_CONSTRAINT(0x0c00, 11), 201 FIXED_EVENT_CONSTRAINT(0x0d00, 12), 202 FIXED_EVENT_CONSTRAINT(0x0e00, 13), 203 FIXED_EVENT_CONSTRAINT(0x0f00, 14), 204 FIXED_EVENT_CONSTRAINT(0x1000, 15), 205 EVENT_CONSTRAINT_END 206 }; 207 208 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 209 { 210 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 211 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 212 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 213 EVENT_CONSTRAINT_END 214 }; 215 216 static struct event_constraint intel_grt_event_constraints[] __read_mostly = { 217 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 218 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 219 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 220 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 221 EVENT_CONSTRAINT_END 222 }; 223 224 static struct event_constraint intel_skt_event_constraints[] __read_mostly = { 225 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 226 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 227 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 228 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 229 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */ 230 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */ 231 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */ 232 EVENT_CONSTRAINT_END 233 }; 234 235 static struct event_constraint intel_skl_event_constraints[] = { 236 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 237 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 238 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 239 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 240 241 /* 242 * when HT is off, these can only run on the bottom 4 counters 243 */ 244 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 245 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 246 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 247 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 248 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 249 250 EVENT_CONSTRAINT_END 251 }; 252 253 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 254 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 255 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 256 EVENT_EXTRA_END 257 }; 258 259 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 260 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 261 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 262 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 263 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 264 EVENT_EXTRA_END 265 }; 266 267 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 268 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 269 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 270 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 271 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 272 EVENT_EXTRA_END 273 }; 274 275 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 276 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 277 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 278 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 279 /* 280 * Note the low 8 bits eventsel code is not a continuous field, containing 281 * some #GPing bits. These are masked out. 282 */ 283 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 284 EVENT_EXTRA_END 285 }; 286 287 static struct event_constraint intel_icl_event_constraints[] = { 288 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 289 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ 290 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 291 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 292 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 293 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 294 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 295 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 296 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 297 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 298 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 299 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 300 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 301 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf), 302 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 303 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 304 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 305 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 306 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 307 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 308 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 309 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 310 INTEL_EVENT_CONSTRAINT(0xef, 0xf), 311 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 312 EVENT_CONSTRAINT_END 313 }; 314 315 static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 316 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 317 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 318 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 319 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 320 EVENT_EXTRA_END 321 }; 322 323 static struct extra_reg intel_glc_extra_regs[] __read_mostly = { 324 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 325 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 326 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 327 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 328 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 329 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 330 EVENT_EXTRA_END 331 }; 332 333 static struct event_constraint intel_glc_event_constraints[] = { 334 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 335 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 336 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 337 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 338 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 339 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 340 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 341 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 342 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 343 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 344 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 345 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 346 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 347 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 348 349 INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 350 INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 351 /* 352 * Generally event codes < 0x90 are restricted to counters 0-3. 353 * The 0x2E and 0x3C are exception, which has no restriction. 354 */ 355 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 356 357 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 358 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 359 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 360 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 361 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 362 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 363 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 364 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 365 /* 366 * Generally event codes >= 0x90 are likely to have no restrictions. 367 * The exception are defined as above. 368 */ 369 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 370 371 EVENT_CONSTRAINT_END 372 }; 373 374 static struct extra_reg intel_rwc_extra_regs[] __read_mostly = { 375 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 376 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 377 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 378 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 379 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 380 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 381 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 382 EVENT_EXTRA_END 383 }; 384 385 static struct event_constraint intel_lnc_event_constraints[] = { 386 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 387 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 388 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 389 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 390 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 391 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 392 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 393 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 394 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 395 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 396 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 397 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 398 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 399 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 400 401 INTEL_EVENT_CONSTRAINT(0x20, 0xf), 402 403 INTEL_UEVENT_CONSTRAINT(0x012a, 0xf), 404 INTEL_UEVENT_CONSTRAINT(0x012b, 0xf), 405 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), 406 INTEL_UEVENT_CONSTRAINT(0x0175, 0x4), 407 408 INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff), 409 INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff), 410 411 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 412 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 413 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 414 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 415 INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1), 416 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8), 417 INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc), 418 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3), 419 420 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 421 422 INTEL_UEVENT_CONSTRAINT(0x00e0, 0xf), 423 424 EVENT_CONSTRAINT_END 425 }; 426 427 static struct extra_reg intel_lnc_extra_regs[] __read_mostly = { 428 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0), 429 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1), 430 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 431 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 432 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 433 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE), 434 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 435 EVENT_EXTRA_END 436 }; 437 438 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 439 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 440 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 441 442 static struct attribute *nhm_mem_events_attrs[] = { 443 EVENT_PTR(mem_ld_nhm), 444 NULL, 445 }; 446 447 /* 448 * topdown events for Intel Core CPUs. 449 * 450 * The events are all in slots, which is a free slot in a 4 wide 451 * pipeline. Some events are already reported in slots, for cycle 452 * events we multiply by the pipeline width (4). 453 * 454 * With Hyper Threading on, topdown metrics are either summed or averaged 455 * between the threads of a core: (count_t0 + count_t1). 456 * 457 * For the average case the metric is always scaled to pipeline width, 458 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 459 */ 460 461 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 462 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 463 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 464 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 465 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 466 "event=0xe,umask=0x1"); /* uops_issued.any */ 467 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 468 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 469 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 470 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 471 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 472 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 473 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 474 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 475 "4", "2"); 476 477 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 478 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 479 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 480 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 481 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 482 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 483 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 484 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 485 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 486 487 static struct attribute *snb_events_attrs[] = { 488 EVENT_PTR(td_slots_issued), 489 EVENT_PTR(td_slots_retired), 490 EVENT_PTR(td_fetch_bubbles), 491 EVENT_PTR(td_total_slots), 492 EVENT_PTR(td_total_slots_scale), 493 EVENT_PTR(td_recovery_bubbles), 494 EVENT_PTR(td_recovery_bubbles_scale), 495 NULL, 496 }; 497 498 static struct attribute *snb_mem_events_attrs[] = { 499 EVENT_PTR(mem_ld_snb), 500 EVENT_PTR(mem_st_snb), 501 NULL, 502 }; 503 504 static struct event_constraint intel_hsw_event_constraints[] = { 505 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 506 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 507 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 508 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 509 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 510 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 511 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 512 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 513 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 514 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 515 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 516 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 517 518 /* 519 * When HT is off these events can only run on the bottom 4 counters 520 * When HT is on, they are impacted by the HT bug and require EXCL access 521 */ 522 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 523 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 524 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 525 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 526 527 EVENT_CONSTRAINT_END 528 }; 529 530 static struct event_constraint intel_bdw_event_constraints[] = { 531 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 532 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 533 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 534 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 535 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 536 /* 537 * when HT is off, these can only run on the bottom 4 counters 538 */ 539 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 540 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 541 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 542 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 543 EVENT_CONSTRAINT_END 544 }; 545 546 static u64 intel_pmu_event_map(int hw_event) 547 { 548 return intel_perfmon_event_map[hw_event]; 549 } 550 551 static __initconst const u64 glc_hw_cache_event_ids 552 [PERF_COUNT_HW_CACHE_MAX] 553 [PERF_COUNT_HW_CACHE_OP_MAX] 554 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 555 { 556 [ C(L1D ) ] = { 557 [ C(OP_READ) ] = { 558 [ C(RESULT_ACCESS) ] = 0x81d0, 559 [ C(RESULT_MISS) ] = 0xe124, 560 }, 561 [ C(OP_WRITE) ] = { 562 [ C(RESULT_ACCESS) ] = 0x82d0, 563 }, 564 }, 565 [ C(L1I ) ] = { 566 [ C(OP_READ) ] = { 567 [ C(RESULT_MISS) ] = 0xe424, 568 }, 569 [ C(OP_WRITE) ] = { 570 [ C(RESULT_ACCESS) ] = -1, 571 [ C(RESULT_MISS) ] = -1, 572 }, 573 }, 574 [ C(LL ) ] = { 575 [ C(OP_READ) ] = { 576 [ C(RESULT_ACCESS) ] = 0x12a, 577 [ C(RESULT_MISS) ] = 0x12a, 578 }, 579 [ C(OP_WRITE) ] = { 580 [ C(RESULT_ACCESS) ] = 0x12a, 581 [ C(RESULT_MISS) ] = 0x12a, 582 }, 583 }, 584 [ C(DTLB) ] = { 585 [ C(OP_READ) ] = { 586 [ C(RESULT_ACCESS) ] = 0x81d0, 587 [ C(RESULT_MISS) ] = 0xe12, 588 }, 589 [ C(OP_WRITE) ] = { 590 [ C(RESULT_ACCESS) ] = 0x82d0, 591 [ C(RESULT_MISS) ] = 0xe13, 592 }, 593 }, 594 [ C(ITLB) ] = { 595 [ C(OP_READ) ] = { 596 [ C(RESULT_ACCESS) ] = -1, 597 [ C(RESULT_MISS) ] = 0xe11, 598 }, 599 [ C(OP_WRITE) ] = { 600 [ C(RESULT_ACCESS) ] = -1, 601 [ C(RESULT_MISS) ] = -1, 602 }, 603 [ C(OP_PREFETCH) ] = { 604 [ C(RESULT_ACCESS) ] = -1, 605 [ C(RESULT_MISS) ] = -1, 606 }, 607 }, 608 [ C(BPU ) ] = { 609 [ C(OP_READ) ] = { 610 [ C(RESULT_ACCESS) ] = 0x4c4, 611 [ C(RESULT_MISS) ] = 0x4c5, 612 }, 613 [ C(OP_WRITE) ] = { 614 [ C(RESULT_ACCESS) ] = -1, 615 [ C(RESULT_MISS) ] = -1, 616 }, 617 [ C(OP_PREFETCH) ] = { 618 [ C(RESULT_ACCESS) ] = -1, 619 [ C(RESULT_MISS) ] = -1, 620 }, 621 }, 622 [ C(NODE) ] = { 623 [ C(OP_READ) ] = { 624 [ C(RESULT_ACCESS) ] = 0x12a, 625 [ C(RESULT_MISS) ] = 0x12a, 626 }, 627 }, 628 }; 629 630 static __initconst const u64 glc_hw_cache_extra_regs 631 [PERF_COUNT_HW_CACHE_MAX] 632 [PERF_COUNT_HW_CACHE_OP_MAX] 633 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 634 { 635 [ C(LL ) ] = { 636 [ C(OP_READ) ] = { 637 [ C(RESULT_ACCESS) ] = 0x10001, 638 [ C(RESULT_MISS) ] = 0x3fbfc00001, 639 }, 640 [ C(OP_WRITE) ] = { 641 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, 642 [ C(RESULT_MISS) ] = 0x3f3fc00002, 643 }, 644 }, 645 [ C(NODE) ] = { 646 [ C(OP_READ) ] = { 647 [ C(RESULT_ACCESS) ] = 0x10c000001, 648 [ C(RESULT_MISS) ] = 0x3fb3000001, 649 }, 650 }, 651 }; 652 653 /* 654 * Notes on the events: 655 * - data reads do not include code reads (comparable to earlier tables) 656 * - data counts include speculative execution (except L1 write, dtlb, bpu) 657 * - remote node access includes remote memory, remote cache, remote mmio. 658 * - prefetches are not included in the counts. 659 * - icache miss does not include decoded icache 660 */ 661 662 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 663 #define SKL_DEMAND_RFO BIT_ULL(1) 664 #define SKL_ANY_RESPONSE BIT_ULL(16) 665 #define SKL_SUPPLIER_NONE BIT_ULL(17) 666 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 667 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 668 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 669 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 670 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 671 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 672 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 673 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 674 #define SKL_SPL_HIT BIT_ULL(30) 675 #define SKL_SNOOP_NONE BIT_ULL(31) 676 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 677 #define SKL_SNOOP_MISS BIT_ULL(33) 678 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 679 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 680 #define SKL_SNOOP_HITM BIT_ULL(36) 681 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 682 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 683 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 684 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 685 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 686 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 687 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 688 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 689 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 690 SKL_SNOOP_HITM|SKL_SPL_HIT) 691 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 692 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 693 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 694 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 695 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 696 697 static __initconst const u64 skl_hw_cache_event_ids 698 [PERF_COUNT_HW_CACHE_MAX] 699 [PERF_COUNT_HW_CACHE_OP_MAX] 700 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 701 { 702 [ C(L1D ) ] = { 703 [ C(OP_READ) ] = { 704 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 705 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 706 }, 707 [ C(OP_WRITE) ] = { 708 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 709 [ C(RESULT_MISS) ] = 0x0, 710 }, 711 [ C(OP_PREFETCH) ] = { 712 [ C(RESULT_ACCESS) ] = 0x0, 713 [ C(RESULT_MISS) ] = 0x0, 714 }, 715 }, 716 [ C(L1I ) ] = { 717 [ C(OP_READ) ] = { 718 [ C(RESULT_ACCESS) ] = 0x0, 719 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 720 }, 721 [ C(OP_WRITE) ] = { 722 [ C(RESULT_ACCESS) ] = -1, 723 [ C(RESULT_MISS) ] = -1, 724 }, 725 [ C(OP_PREFETCH) ] = { 726 [ C(RESULT_ACCESS) ] = 0x0, 727 [ C(RESULT_MISS) ] = 0x0, 728 }, 729 }, 730 [ C(LL ) ] = { 731 [ C(OP_READ) ] = { 732 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 733 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 734 }, 735 [ C(OP_WRITE) ] = { 736 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 737 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 738 }, 739 [ C(OP_PREFETCH) ] = { 740 [ C(RESULT_ACCESS) ] = 0x0, 741 [ C(RESULT_MISS) ] = 0x0, 742 }, 743 }, 744 [ C(DTLB) ] = { 745 [ C(OP_READ) ] = { 746 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 747 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 748 }, 749 [ C(OP_WRITE) ] = { 750 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 751 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 752 }, 753 [ C(OP_PREFETCH) ] = { 754 [ C(RESULT_ACCESS) ] = 0x0, 755 [ C(RESULT_MISS) ] = 0x0, 756 }, 757 }, 758 [ C(ITLB) ] = { 759 [ C(OP_READ) ] = { 760 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 761 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 762 }, 763 [ C(OP_WRITE) ] = { 764 [ C(RESULT_ACCESS) ] = -1, 765 [ C(RESULT_MISS) ] = -1, 766 }, 767 [ C(OP_PREFETCH) ] = { 768 [ C(RESULT_ACCESS) ] = -1, 769 [ C(RESULT_MISS) ] = -1, 770 }, 771 }, 772 [ C(BPU ) ] = { 773 [ C(OP_READ) ] = { 774 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 775 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 776 }, 777 [ C(OP_WRITE) ] = { 778 [ C(RESULT_ACCESS) ] = -1, 779 [ C(RESULT_MISS) ] = -1, 780 }, 781 [ C(OP_PREFETCH) ] = { 782 [ C(RESULT_ACCESS) ] = -1, 783 [ C(RESULT_MISS) ] = -1, 784 }, 785 }, 786 [ C(NODE) ] = { 787 [ C(OP_READ) ] = { 788 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 789 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 790 }, 791 [ C(OP_WRITE) ] = { 792 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 793 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 794 }, 795 [ C(OP_PREFETCH) ] = { 796 [ C(RESULT_ACCESS) ] = 0x0, 797 [ C(RESULT_MISS) ] = 0x0, 798 }, 799 }, 800 }; 801 802 static __initconst const u64 skl_hw_cache_extra_regs 803 [PERF_COUNT_HW_CACHE_MAX] 804 [PERF_COUNT_HW_CACHE_OP_MAX] 805 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 806 { 807 [ C(LL ) ] = { 808 [ C(OP_READ) ] = { 809 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 810 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 811 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 812 SKL_L3_MISS|SKL_ANY_SNOOP| 813 SKL_SUPPLIER_NONE, 814 }, 815 [ C(OP_WRITE) ] = { 816 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 817 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 818 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 819 SKL_L3_MISS|SKL_ANY_SNOOP| 820 SKL_SUPPLIER_NONE, 821 }, 822 [ C(OP_PREFETCH) ] = { 823 [ C(RESULT_ACCESS) ] = 0x0, 824 [ C(RESULT_MISS) ] = 0x0, 825 }, 826 }, 827 [ C(NODE) ] = { 828 [ C(OP_READ) ] = { 829 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 830 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 831 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 832 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 833 }, 834 [ C(OP_WRITE) ] = { 835 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 836 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 837 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 838 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 839 }, 840 [ C(OP_PREFETCH) ] = { 841 [ C(RESULT_ACCESS) ] = 0x0, 842 [ C(RESULT_MISS) ] = 0x0, 843 }, 844 }, 845 }; 846 847 #define SNB_DMND_DATA_RD (1ULL << 0) 848 #define SNB_DMND_RFO (1ULL << 1) 849 #define SNB_DMND_IFETCH (1ULL << 2) 850 #define SNB_DMND_WB (1ULL << 3) 851 #define SNB_PF_DATA_RD (1ULL << 4) 852 #define SNB_PF_RFO (1ULL << 5) 853 #define SNB_PF_IFETCH (1ULL << 6) 854 #define SNB_LLC_DATA_RD (1ULL << 7) 855 #define SNB_LLC_RFO (1ULL << 8) 856 #define SNB_LLC_IFETCH (1ULL << 9) 857 #define SNB_BUS_LOCKS (1ULL << 10) 858 #define SNB_STRM_ST (1ULL << 11) 859 #define SNB_OTHER (1ULL << 15) 860 #define SNB_RESP_ANY (1ULL << 16) 861 #define SNB_NO_SUPP (1ULL << 17) 862 #define SNB_LLC_HITM (1ULL << 18) 863 #define SNB_LLC_HITE (1ULL << 19) 864 #define SNB_LLC_HITS (1ULL << 20) 865 #define SNB_LLC_HITF (1ULL << 21) 866 #define SNB_LOCAL (1ULL << 22) 867 #define SNB_REMOTE (0xffULL << 23) 868 #define SNB_SNP_NONE (1ULL << 31) 869 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 870 #define SNB_SNP_MISS (1ULL << 33) 871 #define SNB_NO_FWD (1ULL << 34) 872 #define SNB_SNP_FWD (1ULL << 35) 873 #define SNB_HITM (1ULL << 36) 874 #define SNB_NON_DRAM (1ULL << 37) 875 876 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 877 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 878 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 879 880 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 881 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 882 SNB_HITM) 883 884 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 885 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 886 887 #define SNB_L3_ACCESS SNB_RESP_ANY 888 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 889 890 static __initconst const u64 snb_hw_cache_extra_regs 891 [PERF_COUNT_HW_CACHE_MAX] 892 [PERF_COUNT_HW_CACHE_OP_MAX] 893 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 894 { 895 [ C(LL ) ] = { 896 [ C(OP_READ) ] = { 897 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 898 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 899 }, 900 [ C(OP_WRITE) ] = { 901 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 902 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 903 }, 904 [ C(OP_PREFETCH) ] = { 905 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 906 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 907 }, 908 }, 909 [ C(NODE) ] = { 910 [ C(OP_READ) ] = { 911 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 912 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 913 }, 914 [ C(OP_WRITE) ] = { 915 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 916 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 917 }, 918 [ C(OP_PREFETCH) ] = { 919 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 920 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 921 }, 922 }, 923 }; 924 925 static __initconst const u64 snb_hw_cache_event_ids 926 [PERF_COUNT_HW_CACHE_MAX] 927 [PERF_COUNT_HW_CACHE_OP_MAX] 928 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 929 { 930 [ C(L1D) ] = { 931 [ C(OP_READ) ] = { 932 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 933 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 934 }, 935 [ C(OP_WRITE) ] = { 936 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 937 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 938 }, 939 [ C(OP_PREFETCH) ] = { 940 [ C(RESULT_ACCESS) ] = 0x0, 941 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 942 }, 943 }, 944 [ C(L1I ) ] = { 945 [ C(OP_READ) ] = { 946 [ C(RESULT_ACCESS) ] = 0x0, 947 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 948 }, 949 [ C(OP_WRITE) ] = { 950 [ C(RESULT_ACCESS) ] = -1, 951 [ C(RESULT_MISS) ] = -1, 952 }, 953 [ C(OP_PREFETCH) ] = { 954 [ C(RESULT_ACCESS) ] = 0x0, 955 [ C(RESULT_MISS) ] = 0x0, 956 }, 957 }, 958 [ C(LL ) ] = { 959 [ C(OP_READ) ] = { 960 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 961 [ C(RESULT_ACCESS) ] = 0x01b7, 962 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 963 [ C(RESULT_MISS) ] = 0x01b7, 964 }, 965 [ C(OP_WRITE) ] = { 966 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 967 [ C(RESULT_ACCESS) ] = 0x01b7, 968 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 969 [ C(RESULT_MISS) ] = 0x01b7, 970 }, 971 [ C(OP_PREFETCH) ] = { 972 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 973 [ C(RESULT_ACCESS) ] = 0x01b7, 974 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 975 [ C(RESULT_MISS) ] = 0x01b7, 976 }, 977 }, 978 [ C(DTLB) ] = { 979 [ C(OP_READ) ] = { 980 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 981 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 982 }, 983 [ C(OP_WRITE) ] = { 984 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 985 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 986 }, 987 [ C(OP_PREFETCH) ] = { 988 [ C(RESULT_ACCESS) ] = 0x0, 989 [ C(RESULT_MISS) ] = 0x0, 990 }, 991 }, 992 [ C(ITLB) ] = { 993 [ C(OP_READ) ] = { 994 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 995 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 996 }, 997 [ C(OP_WRITE) ] = { 998 [ C(RESULT_ACCESS) ] = -1, 999 [ C(RESULT_MISS) ] = -1, 1000 }, 1001 [ C(OP_PREFETCH) ] = { 1002 [ C(RESULT_ACCESS) ] = -1, 1003 [ C(RESULT_MISS) ] = -1, 1004 }, 1005 }, 1006 [ C(BPU ) ] = { 1007 [ C(OP_READ) ] = { 1008 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1009 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1010 }, 1011 [ C(OP_WRITE) ] = { 1012 [ C(RESULT_ACCESS) ] = -1, 1013 [ C(RESULT_MISS) ] = -1, 1014 }, 1015 [ C(OP_PREFETCH) ] = { 1016 [ C(RESULT_ACCESS) ] = -1, 1017 [ C(RESULT_MISS) ] = -1, 1018 }, 1019 }, 1020 [ C(NODE) ] = { 1021 [ C(OP_READ) ] = { 1022 [ C(RESULT_ACCESS) ] = 0x01b7, 1023 [ C(RESULT_MISS) ] = 0x01b7, 1024 }, 1025 [ C(OP_WRITE) ] = { 1026 [ C(RESULT_ACCESS) ] = 0x01b7, 1027 [ C(RESULT_MISS) ] = 0x01b7, 1028 }, 1029 [ C(OP_PREFETCH) ] = { 1030 [ C(RESULT_ACCESS) ] = 0x01b7, 1031 [ C(RESULT_MISS) ] = 0x01b7, 1032 }, 1033 }, 1034 1035 }; 1036 1037 /* 1038 * Notes on the events: 1039 * - data reads do not include code reads (comparable to earlier tables) 1040 * - data counts include speculative execution (except L1 write, dtlb, bpu) 1041 * - remote node access includes remote memory, remote cache, remote mmio. 1042 * - prefetches are not included in the counts because they are not 1043 * reliably counted. 1044 */ 1045 1046 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 1047 #define HSW_DEMAND_RFO BIT_ULL(1) 1048 #define HSW_ANY_RESPONSE BIT_ULL(16) 1049 #define HSW_SUPPLIER_NONE BIT_ULL(17) 1050 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 1051 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 1052 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 1053 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 1054 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 1055 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 1056 HSW_L3_MISS_REMOTE_HOP2P) 1057 #define HSW_SNOOP_NONE BIT_ULL(31) 1058 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 1059 #define HSW_SNOOP_MISS BIT_ULL(33) 1060 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 1061 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 1062 #define HSW_SNOOP_HITM BIT_ULL(36) 1063 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 1064 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 1065 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 1066 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 1067 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 1068 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 1069 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 1070 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 1071 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 1072 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 1073 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 1074 1075 #define BDW_L3_MISS_LOCAL BIT(26) 1076 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 1077 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 1078 HSW_L3_MISS_REMOTE_HOP2P) 1079 1080 1081 static __initconst const u64 hsw_hw_cache_event_ids 1082 [PERF_COUNT_HW_CACHE_MAX] 1083 [PERF_COUNT_HW_CACHE_OP_MAX] 1084 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1085 { 1086 [ C(L1D ) ] = { 1087 [ C(OP_READ) ] = { 1088 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1089 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 1090 }, 1091 [ C(OP_WRITE) ] = { 1092 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1093 [ C(RESULT_MISS) ] = 0x0, 1094 }, 1095 [ C(OP_PREFETCH) ] = { 1096 [ C(RESULT_ACCESS) ] = 0x0, 1097 [ C(RESULT_MISS) ] = 0x0, 1098 }, 1099 }, 1100 [ C(L1I ) ] = { 1101 [ C(OP_READ) ] = { 1102 [ C(RESULT_ACCESS) ] = 0x0, 1103 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 1104 }, 1105 [ C(OP_WRITE) ] = { 1106 [ C(RESULT_ACCESS) ] = -1, 1107 [ C(RESULT_MISS) ] = -1, 1108 }, 1109 [ C(OP_PREFETCH) ] = { 1110 [ C(RESULT_ACCESS) ] = 0x0, 1111 [ C(RESULT_MISS) ] = 0x0, 1112 }, 1113 }, 1114 [ C(LL ) ] = { 1115 [ C(OP_READ) ] = { 1116 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1117 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1118 }, 1119 [ C(OP_WRITE) ] = { 1120 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1121 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1122 }, 1123 [ C(OP_PREFETCH) ] = { 1124 [ C(RESULT_ACCESS) ] = 0x0, 1125 [ C(RESULT_MISS) ] = 0x0, 1126 }, 1127 }, 1128 [ C(DTLB) ] = { 1129 [ C(OP_READ) ] = { 1130 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1131 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1132 }, 1133 [ C(OP_WRITE) ] = { 1134 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1135 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1136 }, 1137 [ C(OP_PREFETCH) ] = { 1138 [ C(RESULT_ACCESS) ] = 0x0, 1139 [ C(RESULT_MISS) ] = 0x0, 1140 }, 1141 }, 1142 [ C(ITLB) ] = { 1143 [ C(OP_READ) ] = { 1144 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1145 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1146 }, 1147 [ C(OP_WRITE) ] = { 1148 [ C(RESULT_ACCESS) ] = -1, 1149 [ C(RESULT_MISS) ] = -1, 1150 }, 1151 [ C(OP_PREFETCH) ] = { 1152 [ C(RESULT_ACCESS) ] = -1, 1153 [ C(RESULT_MISS) ] = -1, 1154 }, 1155 }, 1156 [ C(BPU ) ] = { 1157 [ C(OP_READ) ] = { 1158 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1159 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1160 }, 1161 [ C(OP_WRITE) ] = { 1162 [ C(RESULT_ACCESS) ] = -1, 1163 [ C(RESULT_MISS) ] = -1, 1164 }, 1165 [ C(OP_PREFETCH) ] = { 1166 [ C(RESULT_ACCESS) ] = -1, 1167 [ C(RESULT_MISS) ] = -1, 1168 }, 1169 }, 1170 [ C(NODE) ] = { 1171 [ C(OP_READ) ] = { 1172 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1173 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1174 }, 1175 [ C(OP_WRITE) ] = { 1176 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1177 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1178 }, 1179 [ C(OP_PREFETCH) ] = { 1180 [ C(RESULT_ACCESS) ] = 0x0, 1181 [ C(RESULT_MISS) ] = 0x0, 1182 }, 1183 }, 1184 }; 1185 1186 static __initconst const u64 hsw_hw_cache_extra_regs 1187 [PERF_COUNT_HW_CACHE_MAX] 1188 [PERF_COUNT_HW_CACHE_OP_MAX] 1189 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1190 { 1191 [ C(LL ) ] = { 1192 [ C(OP_READ) ] = { 1193 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1194 HSW_LLC_ACCESS, 1195 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1196 HSW_L3_MISS|HSW_ANY_SNOOP, 1197 }, 1198 [ C(OP_WRITE) ] = { 1199 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1200 HSW_LLC_ACCESS, 1201 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1202 HSW_L3_MISS|HSW_ANY_SNOOP, 1203 }, 1204 [ C(OP_PREFETCH) ] = { 1205 [ C(RESULT_ACCESS) ] = 0x0, 1206 [ C(RESULT_MISS) ] = 0x0, 1207 }, 1208 }, 1209 [ C(NODE) ] = { 1210 [ C(OP_READ) ] = { 1211 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1212 HSW_L3_MISS_LOCAL_DRAM| 1213 HSW_SNOOP_DRAM, 1214 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1215 HSW_L3_MISS_REMOTE| 1216 HSW_SNOOP_DRAM, 1217 }, 1218 [ C(OP_WRITE) ] = { 1219 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1220 HSW_L3_MISS_LOCAL_DRAM| 1221 HSW_SNOOP_DRAM, 1222 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1223 HSW_L3_MISS_REMOTE| 1224 HSW_SNOOP_DRAM, 1225 }, 1226 [ C(OP_PREFETCH) ] = { 1227 [ C(RESULT_ACCESS) ] = 0x0, 1228 [ C(RESULT_MISS) ] = 0x0, 1229 }, 1230 }, 1231 }; 1232 1233 static __initconst const u64 westmere_hw_cache_event_ids 1234 [PERF_COUNT_HW_CACHE_MAX] 1235 [PERF_COUNT_HW_CACHE_OP_MAX] 1236 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1237 { 1238 [ C(L1D) ] = { 1239 [ C(OP_READ) ] = { 1240 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1241 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1242 }, 1243 [ C(OP_WRITE) ] = { 1244 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1245 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1246 }, 1247 [ C(OP_PREFETCH) ] = { 1248 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1249 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1250 }, 1251 }, 1252 [ C(L1I ) ] = { 1253 [ C(OP_READ) ] = { 1254 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1255 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1256 }, 1257 [ C(OP_WRITE) ] = { 1258 [ C(RESULT_ACCESS) ] = -1, 1259 [ C(RESULT_MISS) ] = -1, 1260 }, 1261 [ C(OP_PREFETCH) ] = { 1262 [ C(RESULT_ACCESS) ] = 0x0, 1263 [ C(RESULT_MISS) ] = 0x0, 1264 }, 1265 }, 1266 [ C(LL ) ] = { 1267 [ C(OP_READ) ] = { 1268 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1269 [ C(RESULT_ACCESS) ] = 0x01b7, 1270 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1271 [ C(RESULT_MISS) ] = 0x01b7, 1272 }, 1273 /* 1274 * Use RFO, not WRITEBACK, because a write miss would typically occur 1275 * on RFO. 1276 */ 1277 [ C(OP_WRITE) ] = { 1278 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1279 [ C(RESULT_ACCESS) ] = 0x01b7, 1280 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1281 [ C(RESULT_MISS) ] = 0x01b7, 1282 }, 1283 [ C(OP_PREFETCH) ] = { 1284 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1285 [ C(RESULT_ACCESS) ] = 0x01b7, 1286 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1287 [ C(RESULT_MISS) ] = 0x01b7, 1288 }, 1289 }, 1290 [ C(DTLB) ] = { 1291 [ C(OP_READ) ] = { 1292 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1293 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1294 }, 1295 [ C(OP_WRITE) ] = { 1296 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1297 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1298 }, 1299 [ C(OP_PREFETCH) ] = { 1300 [ C(RESULT_ACCESS) ] = 0x0, 1301 [ C(RESULT_MISS) ] = 0x0, 1302 }, 1303 }, 1304 [ C(ITLB) ] = { 1305 [ C(OP_READ) ] = { 1306 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1307 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1308 }, 1309 [ C(OP_WRITE) ] = { 1310 [ C(RESULT_ACCESS) ] = -1, 1311 [ C(RESULT_MISS) ] = -1, 1312 }, 1313 [ C(OP_PREFETCH) ] = { 1314 [ C(RESULT_ACCESS) ] = -1, 1315 [ C(RESULT_MISS) ] = -1, 1316 }, 1317 }, 1318 [ C(BPU ) ] = { 1319 [ C(OP_READ) ] = { 1320 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1321 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1322 }, 1323 [ C(OP_WRITE) ] = { 1324 [ C(RESULT_ACCESS) ] = -1, 1325 [ C(RESULT_MISS) ] = -1, 1326 }, 1327 [ C(OP_PREFETCH) ] = { 1328 [ C(RESULT_ACCESS) ] = -1, 1329 [ C(RESULT_MISS) ] = -1, 1330 }, 1331 }, 1332 [ C(NODE) ] = { 1333 [ C(OP_READ) ] = { 1334 [ C(RESULT_ACCESS) ] = 0x01b7, 1335 [ C(RESULT_MISS) ] = 0x01b7, 1336 }, 1337 [ C(OP_WRITE) ] = { 1338 [ C(RESULT_ACCESS) ] = 0x01b7, 1339 [ C(RESULT_MISS) ] = 0x01b7, 1340 }, 1341 [ C(OP_PREFETCH) ] = { 1342 [ C(RESULT_ACCESS) ] = 0x01b7, 1343 [ C(RESULT_MISS) ] = 0x01b7, 1344 }, 1345 }, 1346 }; 1347 1348 /* 1349 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1350 * See IA32 SDM Vol 3B 30.6.1.3 1351 */ 1352 1353 #define NHM_DMND_DATA_RD (1 << 0) 1354 #define NHM_DMND_RFO (1 << 1) 1355 #define NHM_DMND_IFETCH (1 << 2) 1356 #define NHM_DMND_WB (1 << 3) 1357 #define NHM_PF_DATA_RD (1 << 4) 1358 #define NHM_PF_DATA_RFO (1 << 5) 1359 #define NHM_PF_IFETCH (1 << 6) 1360 #define NHM_OFFCORE_OTHER (1 << 7) 1361 #define NHM_UNCORE_HIT (1 << 8) 1362 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1363 #define NHM_OTHER_CORE_HITM (1 << 10) 1364 /* reserved */ 1365 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1366 #define NHM_REMOTE_DRAM (1 << 13) 1367 #define NHM_LOCAL_DRAM (1 << 14) 1368 #define NHM_NON_DRAM (1 << 15) 1369 1370 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1371 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1372 1373 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1374 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1375 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1376 1377 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1378 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1379 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1380 1381 static __initconst const u64 nehalem_hw_cache_extra_regs 1382 [PERF_COUNT_HW_CACHE_MAX] 1383 [PERF_COUNT_HW_CACHE_OP_MAX] 1384 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1385 { 1386 [ C(LL ) ] = { 1387 [ C(OP_READ) ] = { 1388 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1389 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1390 }, 1391 [ C(OP_WRITE) ] = { 1392 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1393 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1394 }, 1395 [ C(OP_PREFETCH) ] = { 1396 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1397 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1398 }, 1399 }, 1400 [ C(NODE) ] = { 1401 [ C(OP_READ) ] = { 1402 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1403 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1404 }, 1405 [ C(OP_WRITE) ] = { 1406 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1407 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1408 }, 1409 [ C(OP_PREFETCH) ] = { 1410 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1411 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1412 }, 1413 }, 1414 }; 1415 1416 static __initconst const u64 nehalem_hw_cache_event_ids 1417 [PERF_COUNT_HW_CACHE_MAX] 1418 [PERF_COUNT_HW_CACHE_OP_MAX] 1419 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1420 { 1421 [ C(L1D) ] = { 1422 [ C(OP_READ) ] = { 1423 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1424 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1425 }, 1426 [ C(OP_WRITE) ] = { 1427 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1428 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1429 }, 1430 [ C(OP_PREFETCH) ] = { 1431 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1432 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1433 }, 1434 }, 1435 [ C(L1I ) ] = { 1436 [ C(OP_READ) ] = { 1437 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1438 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1439 }, 1440 [ C(OP_WRITE) ] = { 1441 [ C(RESULT_ACCESS) ] = -1, 1442 [ C(RESULT_MISS) ] = -1, 1443 }, 1444 [ C(OP_PREFETCH) ] = { 1445 [ C(RESULT_ACCESS) ] = 0x0, 1446 [ C(RESULT_MISS) ] = 0x0, 1447 }, 1448 }, 1449 [ C(LL ) ] = { 1450 [ C(OP_READ) ] = { 1451 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1452 [ C(RESULT_ACCESS) ] = 0x01b7, 1453 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1454 [ C(RESULT_MISS) ] = 0x01b7, 1455 }, 1456 /* 1457 * Use RFO, not WRITEBACK, because a write miss would typically occur 1458 * on RFO. 1459 */ 1460 [ C(OP_WRITE) ] = { 1461 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1462 [ C(RESULT_ACCESS) ] = 0x01b7, 1463 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1464 [ C(RESULT_MISS) ] = 0x01b7, 1465 }, 1466 [ C(OP_PREFETCH) ] = { 1467 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1468 [ C(RESULT_ACCESS) ] = 0x01b7, 1469 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1470 [ C(RESULT_MISS) ] = 0x01b7, 1471 }, 1472 }, 1473 [ C(DTLB) ] = { 1474 [ C(OP_READ) ] = { 1475 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1476 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1477 }, 1478 [ C(OP_WRITE) ] = { 1479 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1480 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1481 }, 1482 [ C(OP_PREFETCH) ] = { 1483 [ C(RESULT_ACCESS) ] = 0x0, 1484 [ C(RESULT_MISS) ] = 0x0, 1485 }, 1486 }, 1487 [ C(ITLB) ] = { 1488 [ C(OP_READ) ] = { 1489 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1490 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1491 }, 1492 [ C(OP_WRITE) ] = { 1493 [ C(RESULT_ACCESS) ] = -1, 1494 [ C(RESULT_MISS) ] = -1, 1495 }, 1496 [ C(OP_PREFETCH) ] = { 1497 [ C(RESULT_ACCESS) ] = -1, 1498 [ C(RESULT_MISS) ] = -1, 1499 }, 1500 }, 1501 [ C(BPU ) ] = { 1502 [ C(OP_READ) ] = { 1503 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1504 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1505 }, 1506 [ C(OP_WRITE) ] = { 1507 [ C(RESULT_ACCESS) ] = -1, 1508 [ C(RESULT_MISS) ] = -1, 1509 }, 1510 [ C(OP_PREFETCH) ] = { 1511 [ C(RESULT_ACCESS) ] = -1, 1512 [ C(RESULT_MISS) ] = -1, 1513 }, 1514 }, 1515 [ C(NODE) ] = { 1516 [ C(OP_READ) ] = { 1517 [ C(RESULT_ACCESS) ] = 0x01b7, 1518 [ C(RESULT_MISS) ] = 0x01b7, 1519 }, 1520 [ C(OP_WRITE) ] = { 1521 [ C(RESULT_ACCESS) ] = 0x01b7, 1522 [ C(RESULT_MISS) ] = 0x01b7, 1523 }, 1524 [ C(OP_PREFETCH) ] = { 1525 [ C(RESULT_ACCESS) ] = 0x01b7, 1526 [ C(RESULT_MISS) ] = 0x01b7, 1527 }, 1528 }, 1529 }; 1530 1531 static __initconst const u64 core2_hw_cache_event_ids 1532 [PERF_COUNT_HW_CACHE_MAX] 1533 [PERF_COUNT_HW_CACHE_OP_MAX] 1534 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1535 { 1536 [ C(L1D) ] = { 1537 [ C(OP_READ) ] = { 1538 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1539 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1540 }, 1541 [ C(OP_WRITE) ] = { 1542 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1543 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1544 }, 1545 [ C(OP_PREFETCH) ] = { 1546 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1547 [ C(RESULT_MISS) ] = 0, 1548 }, 1549 }, 1550 [ C(L1I ) ] = { 1551 [ C(OP_READ) ] = { 1552 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1553 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1554 }, 1555 [ C(OP_WRITE) ] = { 1556 [ C(RESULT_ACCESS) ] = -1, 1557 [ C(RESULT_MISS) ] = -1, 1558 }, 1559 [ C(OP_PREFETCH) ] = { 1560 [ C(RESULT_ACCESS) ] = 0, 1561 [ C(RESULT_MISS) ] = 0, 1562 }, 1563 }, 1564 [ C(LL ) ] = { 1565 [ C(OP_READ) ] = { 1566 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1567 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1568 }, 1569 [ C(OP_WRITE) ] = { 1570 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1571 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1572 }, 1573 [ C(OP_PREFETCH) ] = { 1574 [ C(RESULT_ACCESS) ] = 0, 1575 [ C(RESULT_MISS) ] = 0, 1576 }, 1577 }, 1578 [ C(DTLB) ] = { 1579 [ C(OP_READ) ] = { 1580 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1581 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1582 }, 1583 [ C(OP_WRITE) ] = { 1584 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1585 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1586 }, 1587 [ C(OP_PREFETCH) ] = { 1588 [ C(RESULT_ACCESS) ] = 0, 1589 [ C(RESULT_MISS) ] = 0, 1590 }, 1591 }, 1592 [ C(ITLB) ] = { 1593 [ C(OP_READ) ] = { 1594 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1595 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1596 }, 1597 [ C(OP_WRITE) ] = { 1598 [ C(RESULT_ACCESS) ] = -1, 1599 [ C(RESULT_MISS) ] = -1, 1600 }, 1601 [ C(OP_PREFETCH) ] = { 1602 [ C(RESULT_ACCESS) ] = -1, 1603 [ C(RESULT_MISS) ] = -1, 1604 }, 1605 }, 1606 [ C(BPU ) ] = { 1607 [ C(OP_READ) ] = { 1608 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1609 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1610 }, 1611 [ C(OP_WRITE) ] = { 1612 [ C(RESULT_ACCESS) ] = -1, 1613 [ C(RESULT_MISS) ] = -1, 1614 }, 1615 [ C(OP_PREFETCH) ] = { 1616 [ C(RESULT_ACCESS) ] = -1, 1617 [ C(RESULT_MISS) ] = -1, 1618 }, 1619 }, 1620 }; 1621 1622 static __initconst const u64 atom_hw_cache_event_ids 1623 [PERF_COUNT_HW_CACHE_MAX] 1624 [PERF_COUNT_HW_CACHE_OP_MAX] 1625 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1626 { 1627 [ C(L1D) ] = { 1628 [ C(OP_READ) ] = { 1629 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1630 [ C(RESULT_MISS) ] = 0, 1631 }, 1632 [ C(OP_WRITE) ] = { 1633 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1634 [ C(RESULT_MISS) ] = 0, 1635 }, 1636 [ C(OP_PREFETCH) ] = { 1637 [ C(RESULT_ACCESS) ] = 0x0, 1638 [ C(RESULT_MISS) ] = 0, 1639 }, 1640 }, 1641 [ C(L1I ) ] = { 1642 [ C(OP_READ) ] = { 1643 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1644 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1645 }, 1646 [ C(OP_WRITE) ] = { 1647 [ C(RESULT_ACCESS) ] = -1, 1648 [ C(RESULT_MISS) ] = -1, 1649 }, 1650 [ C(OP_PREFETCH) ] = { 1651 [ C(RESULT_ACCESS) ] = 0, 1652 [ C(RESULT_MISS) ] = 0, 1653 }, 1654 }, 1655 [ C(LL ) ] = { 1656 [ C(OP_READ) ] = { 1657 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1658 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1659 }, 1660 [ C(OP_WRITE) ] = { 1661 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1662 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1663 }, 1664 [ C(OP_PREFETCH) ] = { 1665 [ C(RESULT_ACCESS) ] = 0, 1666 [ C(RESULT_MISS) ] = 0, 1667 }, 1668 }, 1669 [ C(DTLB) ] = { 1670 [ C(OP_READ) ] = { 1671 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1672 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1673 }, 1674 [ C(OP_WRITE) ] = { 1675 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1676 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1677 }, 1678 [ C(OP_PREFETCH) ] = { 1679 [ C(RESULT_ACCESS) ] = 0, 1680 [ C(RESULT_MISS) ] = 0, 1681 }, 1682 }, 1683 [ C(ITLB) ] = { 1684 [ C(OP_READ) ] = { 1685 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1686 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1687 }, 1688 [ C(OP_WRITE) ] = { 1689 [ C(RESULT_ACCESS) ] = -1, 1690 [ C(RESULT_MISS) ] = -1, 1691 }, 1692 [ C(OP_PREFETCH) ] = { 1693 [ C(RESULT_ACCESS) ] = -1, 1694 [ C(RESULT_MISS) ] = -1, 1695 }, 1696 }, 1697 [ C(BPU ) ] = { 1698 [ C(OP_READ) ] = { 1699 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1700 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1701 }, 1702 [ C(OP_WRITE) ] = { 1703 [ C(RESULT_ACCESS) ] = -1, 1704 [ C(RESULT_MISS) ] = -1, 1705 }, 1706 [ C(OP_PREFETCH) ] = { 1707 [ C(RESULT_ACCESS) ] = -1, 1708 [ C(RESULT_MISS) ] = -1, 1709 }, 1710 }, 1711 }; 1712 1713 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1714 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1715 /* no_alloc_cycles.not_delivered */ 1716 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1717 "event=0xca,umask=0x50"); 1718 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1719 /* uops_retired.all */ 1720 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1721 "event=0xc2,umask=0x10"); 1722 /* uops_retired.all */ 1723 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1724 "event=0xc2,umask=0x10"); 1725 1726 static struct attribute *slm_events_attrs[] = { 1727 EVENT_PTR(td_total_slots_slm), 1728 EVENT_PTR(td_total_slots_scale_slm), 1729 EVENT_PTR(td_fetch_bubbles_slm), 1730 EVENT_PTR(td_fetch_bubbles_scale_slm), 1731 EVENT_PTR(td_slots_issued_slm), 1732 EVENT_PTR(td_slots_retired_slm), 1733 NULL 1734 }; 1735 1736 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1737 { 1738 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1739 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1740 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1741 EVENT_EXTRA_END 1742 }; 1743 1744 #define SLM_DMND_READ SNB_DMND_DATA_RD 1745 #define SLM_DMND_WRITE SNB_DMND_RFO 1746 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1747 1748 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1749 #define SLM_LLC_ACCESS SNB_RESP_ANY 1750 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1751 1752 static __initconst const u64 slm_hw_cache_extra_regs 1753 [PERF_COUNT_HW_CACHE_MAX] 1754 [PERF_COUNT_HW_CACHE_OP_MAX] 1755 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1756 { 1757 [ C(LL ) ] = { 1758 [ C(OP_READ) ] = { 1759 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1760 [ C(RESULT_MISS) ] = 0, 1761 }, 1762 [ C(OP_WRITE) ] = { 1763 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1764 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1765 }, 1766 [ C(OP_PREFETCH) ] = { 1767 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1768 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1769 }, 1770 }, 1771 }; 1772 1773 static __initconst const u64 slm_hw_cache_event_ids 1774 [PERF_COUNT_HW_CACHE_MAX] 1775 [PERF_COUNT_HW_CACHE_OP_MAX] 1776 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1777 { 1778 [ C(L1D) ] = { 1779 [ C(OP_READ) ] = { 1780 [ C(RESULT_ACCESS) ] = 0, 1781 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1782 }, 1783 [ C(OP_WRITE) ] = { 1784 [ C(RESULT_ACCESS) ] = 0, 1785 [ C(RESULT_MISS) ] = 0, 1786 }, 1787 [ C(OP_PREFETCH) ] = { 1788 [ C(RESULT_ACCESS) ] = 0, 1789 [ C(RESULT_MISS) ] = 0, 1790 }, 1791 }, 1792 [ C(L1I ) ] = { 1793 [ C(OP_READ) ] = { 1794 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1795 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1796 }, 1797 [ C(OP_WRITE) ] = { 1798 [ C(RESULT_ACCESS) ] = -1, 1799 [ C(RESULT_MISS) ] = -1, 1800 }, 1801 [ C(OP_PREFETCH) ] = { 1802 [ C(RESULT_ACCESS) ] = 0, 1803 [ C(RESULT_MISS) ] = 0, 1804 }, 1805 }, 1806 [ C(LL ) ] = { 1807 [ C(OP_READ) ] = { 1808 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1809 [ C(RESULT_ACCESS) ] = 0x01b7, 1810 [ C(RESULT_MISS) ] = 0, 1811 }, 1812 [ C(OP_WRITE) ] = { 1813 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1814 [ C(RESULT_ACCESS) ] = 0x01b7, 1815 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1816 [ C(RESULT_MISS) ] = 0x01b7, 1817 }, 1818 [ C(OP_PREFETCH) ] = { 1819 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1820 [ C(RESULT_ACCESS) ] = 0x01b7, 1821 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1822 [ C(RESULT_MISS) ] = 0x01b7, 1823 }, 1824 }, 1825 [ C(DTLB) ] = { 1826 [ C(OP_READ) ] = { 1827 [ C(RESULT_ACCESS) ] = 0, 1828 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1829 }, 1830 [ C(OP_WRITE) ] = { 1831 [ C(RESULT_ACCESS) ] = 0, 1832 [ C(RESULT_MISS) ] = 0, 1833 }, 1834 [ C(OP_PREFETCH) ] = { 1835 [ C(RESULT_ACCESS) ] = 0, 1836 [ C(RESULT_MISS) ] = 0, 1837 }, 1838 }, 1839 [ C(ITLB) ] = { 1840 [ C(OP_READ) ] = { 1841 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1842 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1843 }, 1844 [ C(OP_WRITE) ] = { 1845 [ C(RESULT_ACCESS) ] = -1, 1846 [ C(RESULT_MISS) ] = -1, 1847 }, 1848 [ C(OP_PREFETCH) ] = { 1849 [ C(RESULT_ACCESS) ] = -1, 1850 [ C(RESULT_MISS) ] = -1, 1851 }, 1852 }, 1853 [ C(BPU ) ] = { 1854 [ C(OP_READ) ] = { 1855 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1856 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1857 }, 1858 [ C(OP_WRITE) ] = { 1859 [ C(RESULT_ACCESS) ] = -1, 1860 [ C(RESULT_MISS) ] = -1, 1861 }, 1862 [ C(OP_PREFETCH) ] = { 1863 [ C(RESULT_ACCESS) ] = -1, 1864 [ C(RESULT_MISS) ] = -1, 1865 }, 1866 }, 1867 }; 1868 1869 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1870 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1871 /* UOPS_NOT_DELIVERED.ANY */ 1872 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1873 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1874 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1875 /* UOPS_RETIRED.ANY */ 1876 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1877 /* UOPS_ISSUED.ANY */ 1878 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1879 1880 static struct attribute *glm_events_attrs[] = { 1881 EVENT_PTR(td_total_slots_glm), 1882 EVENT_PTR(td_total_slots_scale_glm), 1883 EVENT_PTR(td_fetch_bubbles_glm), 1884 EVENT_PTR(td_recovery_bubbles_glm), 1885 EVENT_PTR(td_slots_issued_glm), 1886 EVENT_PTR(td_slots_retired_glm), 1887 NULL 1888 }; 1889 1890 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1891 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1892 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1893 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1894 EVENT_EXTRA_END 1895 }; 1896 1897 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 1898 #define GLM_DEMAND_RFO BIT_ULL(1) 1899 #define GLM_ANY_RESPONSE BIT_ULL(16) 1900 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1901 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1902 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1903 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1904 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1905 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1906 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1907 1908 static __initconst const u64 glm_hw_cache_event_ids 1909 [PERF_COUNT_HW_CACHE_MAX] 1910 [PERF_COUNT_HW_CACHE_OP_MAX] 1911 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1912 [C(L1D)] = { 1913 [C(OP_READ)] = { 1914 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1915 [C(RESULT_MISS)] = 0x0, 1916 }, 1917 [C(OP_WRITE)] = { 1918 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1919 [C(RESULT_MISS)] = 0x0, 1920 }, 1921 [C(OP_PREFETCH)] = { 1922 [C(RESULT_ACCESS)] = 0x0, 1923 [C(RESULT_MISS)] = 0x0, 1924 }, 1925 }, 1926 [C(L1I)] = { 1927 [C(OP_READ)] = { 1928 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1929 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1930 }, 1931 [C(OP_WRITE)] = { 1932 [C(RESULT_ACCESS)] = -1, 1933 [C(RESULT_MISS)] = -1, 1934 }, 1935 [C(OP_PREFETCH)] = { 1936 [C(RESULT_ACCESS)] = 0x0, 1937 [C(RESULT_MISS)] = 0x0, 1938 }, 1939 }, 1940 [C(LL)] = { 1941 [C(OP_READ)] = { 1942 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1943 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1944 }, 1945 [C(OP_WRITE)] = { 1946 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1947 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1948 }, 1949 [C(OP_PREFETCH)] = { 1950 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1951 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1952 }, 1953 }, 1954 [C(DTLB)] = { 1955 [C(OP_READ)] = { 1956 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1957 [C(RESULT_MISS)] = 0x0, 1958 }, 1959 [C(OP_WRITE)] = { 1960 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1961 [C(RESULT_MISS)] = 0x0, 1962 }, 1963 [C(OP_PREFETCH)] = { 1964 [C(RESULT_ACCESS)] = 0x0, 1965 [C(RESULT_MISS)] = 0x0, 1966 }, 1967 }, 1968 [C(ITLB)] = { 1969 [C(OP_READ)] = { 1970 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1971 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1972 }, 1973 [C(OP_WRITE)] = { 1974 [C(RESULT_ACCESS)] = -1, 1975 [C(RESULT_MISS)] = -1, 1976 }, 1977 [C(OP_PREFETCH)] = { 1978 [C(RESULT_ACCESS)] = -1, 1979 [C(RESULT_MISS)] = -1, 1980 }, 1981 }, 1982 [C(BPU)] = { 1983 [C(OP_READ)] = { 1984 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1985 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1986 }, 1987 [C(OP_WRITE)] = { 1988 [C(RESULT_ACCESS)] = -1, 1989 [C(RESULT_MISS)] = -1, 1990 }, 1991 [C(OP_PREFETCH)] = { 1992 [C(RESULT_ACCESS)] = -1, 1993 [C(RESULT_MISS)] = -1, 1994 }, 1995 }, 1996 }; 1997 1998 static __initconst const u64 glm_hw_cache_extra_regs 1999 [PERF_COUNT_HW_CACHE_MAX] 2000 [PERF_COUNT_HW_CACHE_OP_MAX] 2001 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2002 [C(LL)] = { 2003 [C(OP_READ)] = { 2004 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2005 GLM_LLC_ACCESS, 2006 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2007 GLM_LLC_MISS, 2008 }, 2009 [C(OP_WRITE)] = { 2010 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2011 GLM_LLC_ACCESS, 2012 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2013 GLM_LLC_MISS, 2014 }, 2015 [C(OP_PREFETCH)] = { 2016 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 2017 GLM_LLC_ACCESS, 2018 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 2019 GLM_LLC_MISS, 2020 }, 2021 }, 2022 }; 2023 2024 static __initconst const u64 glp_hw_cache_event_ids 2025 [PERF_COUNT_HW_CACHE_MAX] 2026 [PERF_COUNT_HW_CACHE_OP_MAX] 2027 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2028 [C(L1D)] = { 2029 [C(OP_READ)] = { 2030 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2031 [C(RESULT_MISS)] = 0x0, 2032 }, 2033 [C(OP_WRITE)] = { 2034 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2035 [C(RESULT_MISS)] = 0x0, 2036 }, 2037 [C(OP_PREFETCH)] = { 2038 [C(RESULT_ACCESS)] = 0x0, 2039 [C(RESULT_MISS)] = 0x0, 2040 }, 2041 }, 2042 [C(L1I)] = { 2043 [C(OP_READ)] = { 2044 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 2045 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 2046 }, 2047 [C(OP_WRITE)] = { 2048 [C(RESULT_ACCESS)] = -1, 2049 [C(RESULT_MISS)] = -1, 2050 }, 2051 [C(OP_PREFETCH)] = { 2052 [C(RESULT_ACCESS)] = 0x0, 2053 [C(RESULT_MISS)] = 0x0, 2054 }, 2055 }, 2056 [C(LL)] = { 2057 [C(OP_READ)] = { 2058 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2059 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2060 }, 2061 [C(OP_WRITE)] = { 2062 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2063 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2064 }, 2065 [C(OP_PREFETCH)] = { 2066 [C(RESULT_ACCESS)] = 0x0, 2067 [C(RESULT_MISS)] = 0x0, 2068 }, 2069 }, 2070 [C(DTLB)] = { 2071 [C(OP_READ)] = { 2072 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2073 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 2074 }, 2075 [C(OP_WRITE)] = { 2076 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2077 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 2078 }, 2079 [C(OP_PREFETCH)] = { 2080 [C(RESULT_ACCESS)] = 0x0, 2081 [C(RESULT_MISS)] = 0x0, 2082 }, 2083 }, 2084 [C(ITLB)] = { 2085 [C(OP_READ)] = { 2086 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 2087 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 2088 }, 2089 [C(OP_WRITE)] = { 2090 [C(RESULT_ACCESS)] = -1, 2091 [C(RESULT_MISS)] = -1, 2092 }, 2093 [C(OP_PREFETCH)] = { 2094 [C(RESULT_ACCESS)] = -1, 2095 [C(RESULT_MISS)] = -1, 2096 }, 2097 }, 2098 [C(BPU)] = { 2099 [C(OP_READ)] = { 2100 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 2101 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 2102 }, 2103 [C(OP_WRITE)] = { 2104 [C(RESULT_ACCESS)] = -1, 2105 [C(RESULT_MISS)] = -1, 2106 }, 2107 [C(OP_PREFETCH)] = { 2108 [C(RESULT_ACCESS)] = -1, 2109 [C(RESULT_MISS)] = -1, 2110 }, 2111 }, 2112 }; 2113 2114 static __initconst const u64 glp_hw_cache_extra_regs 2115 [PERF_COUNT_HW_CACHE_MAX] 2116 [PERF_COUNT_HW_CACHE_OP_MAX] 2117 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2118 [C(LL)] = { 2119 [C(OP_READ)] = { 2120 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2121 GLM_LLC_ACCESS, 2122 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2123 GLM_LLC_MISS, 2124 }, 2125 [C(OP_WRITE)] = { 2126 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2127 GLM_LLC_ACCESS, 2128 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2129 GLM_LLC_MISS, 2130 }, 2131 [C(OP_PREFETCH)] = { 2132 [C(RESULT_ACCESS)] = 0x0, 2133 [C(RESULT_MISS)] = 0x0, 2134 }, 2135 }, 2136 }; 2137 2138 #define TNT_LOCAL_DRAM BIT_ULL(26) 2139 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 2140 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 2141 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 2142 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 2143 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 2144 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 2145 2146 static __initconst const u64 tnt_hw_cache_extra_regs 2147 [PERF_COUNT_HW_CACHE_MAX] 2148 [PERF_COUNT_HW_CACHE_OP_MAX] 2149 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2150 [C(LL)] = { 2151 [C(OP_READ)] = { 2152 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 2153 TNT_LLC_ACCESS, 2154 [C(RESULT_MISS)] = TNT_DEMAND_READ| 2155 TNT_LLC_MISS, 2156 }, 2157 [C(OP_WRITE)] = { 2158 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 2159 TNT_LLC_ACCESS, 2160 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 2161 TNT_LLC_MISS, 2162 }, 2163 [C(OP_PREFETCH)] = { 2164 [C(RESULT_ACCESS)] = 0x0, 2165 [C(RESULT_MISS)] = 0x0, 2166 }, 2167 }, 2168 }; 2169 2170 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2171 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2172 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2173 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2174 2175 static struct attribute *tnt_events_attrs[] = { 2176 EVENT_PTR(td_fe_bound_tnt), 2177 EVENT_PTR(td_retiring_tnt), 2178 EVENT_PTR(td_bad_spec_tnt), 2179 EVENT_PTR(td_be_bound_tnt), 2180 NULL, 2181 }; 2182 2183 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 2184 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2185 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 2186 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 2187 EVENT_EXTRA_END 2188 }; 2189 2190 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3"); 2191 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6"); 2192 2193 static struct attribute *grt_mem_attrs[] = { 2194 EVENT_PTR(mem_ld_grt), 2195 EVENT_PTR(mem_st_grt), 2196 NULL 2197 }; 2198 2199 static struct extra_reg intel_grt_extra_regs[] __read_mostly = { 2200 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2201 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 2202 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 2203 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2204 EVENT_EXTRA_END 2205 }; 2206 2207 EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0"); 2208 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0"); 2209 2210 static struct attribute *cmt_events_attrs[] = { 2211 EVENT_PTR(td_fe_bound_tnt), 2212 EVENT_PTR(td_retiring_cmt), 2213 EVENT_PTR(td_bad_spec_cmt), 2214 EVENT_PTR(td_be_bound_tnt), 2215 NULL 2216 }; 2217 2218 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = { 2219 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2220 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0), 2221 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1), 2222 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2223 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0), 2224 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1), 2225 EVENT_EXTRA_END 2226 }; 2227 2228 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_skt, "event=0x9c,umask=0x01"); 2229 EVENT_ATTR_STR(topdown-retiring, td_retiring_skt, "event=0xc2,umask=0x02"); 2230 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_skt, "event=0xa4,umask=0x02"); 2231 2232 static struct attribute *skt_events_attrs[] = { 2233 EVENT_PTR(td_fe_bound_skt), 2234 EVENT_PTR(td_retiring_skt), 2235 EVENT_PTR(td_bad_spec_cmt), 2236 EVENT_PTR(td_be_bound_skt), 2237 NULL, 2238 }; 2239 2240 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2241 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2242 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 2243 #define KNL_MCDRAM_FAR BIT_ULL(22) 2244 #define KNL_DDR_LOCAL BIT_ULL(23) 2245 #define KNL_DDR_FAR BIT_ULL(24) 2246 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2247 KNL_DDR_LOCAL | KNL_DDR_FAR) 2248 #define KNL_L2_READ SLM_DMND_READ 2249 #define KNL_L2_WRITE SLM_DMND_WRITE 2250 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2251 #define KNL_L2_ACCESS SLM_LLC_ACCESS 2252 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2253 KNL_DRAM_ANY | SNB_SNP_ANY | \ 2254 SNB_NON_DRAM) 2255 2256 static __initconst const u64 knl_hw_cache_extra_regs 2257 [PERF_COUNT_HW_CACHE_MAX] 2258 [PERF_COUNT_HW_CACHE_OP_MAX] 2259 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2260 [C(LL)] = { 2261 [C(OP_READ)] = { 2262 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2263 [C(RESULT_MISS)] = 0, 2264 }, 2265 [C(OP_WRITE)] = { 2266 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2267 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2268 }, 2269 [C(OP_PREFETCH)] = { 2270 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2271 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2272 }, 2273 }, 2274 }; 2275 2276 /* 2277 * Used from PMIs where the LBRs are already disabled. 2278 * 2279 * This function could be called consecutively. It is required to remain in 2280 * disabled state if called consecutively. 2281 * 2282 * During consecutive calls, the same disable value will be written to related 2283 * registers, so the PMU state remains unchanged. 2284 * 2285 * intel_bts events don't coexist with intel PMU's BTS events because of 2286 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2287 * disabled around intel PMU's event batching etc, only inside the PMI handler. 2288 * 2289 * Avoid PEBS_ENABLE MSR access in PMIs. 2290 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 2291 * It doesn't matter if the PEBS is enabled or not. 2292 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 2293 * access PEBS_ENABLE MSR in disable_all()/enable_all(). 2294 * However, there are some cases which may change PEBS status, e.g. PMI 2295 * throttle. The PEBS_ENABLE should be updated where the status changes. 2296 */ 2297 static __always_inline void __intel_pmu_disable_all(bool bts) 2298 { 2299 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2300 2301 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2302 2303 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2304 intel_pmu_disable_bts(); 2305 } 2306 2307 static __always_inline void intel_pmu_disable_all(void) 2308 { 2309 __intel_pmu_disable_all(true); 2310 static_call_cond(x86_pmu_pebs_disable_all)(); 2311 intel_pmu_lbr_disable_all(); 2312 } 2313 2314 static void __intel_pmu_enable_all(int added, bool pmi) 2315 { 2316 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2317 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2318 2319 intel_pmu_lbr_enable_all(pmi); 2320 2321 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) { 2322 wrmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val); 2323 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val; 2324 } 2325 2326 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 2327 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2328 2329 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2330 struct perf_event *event = 2331 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2332 2333 if (WARN_ON_ONCE(!event)) 2334 return; 2335 2336 intel_pmu_enable_bts(event->hw.config); 2337 } 2338 } 2339 2340 static void intel_pmu_enable_all(int added) 2341 { 2342 static_call_cond(x86_pmu_pebs_enable_all)(); 2343 __intel_pmu_enable_all(added, false); 2344 } 2345 2346 static noinline int 2347 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, 2348 unsigned int cnt, unsigned long flags) 2349 { 2350 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2351 2352 intel_pmu_lbr_read(); 2353 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); 2354 2355 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); 2356 intel_pmu_enable_all(0); 2357 local_irq_restore(flags); 2358 return cnt; 2359 } 2360 2361 static int 2362 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2363 { 2364 unsigned long flags; 2365 2366 /* must not have branches... */ 2367 local_irq_save(flags); 2368 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2369 __intel_pmu_lbr_disable(); 2370 /* ... until here */ 2371 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2372 } 2373 2374 static int 2375 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2376 { 2377 unsigned long flags; 2378 2379 /* must not have branches... */ 2380 local_irq_save(flags); 2381 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2382 __intel_pmu_arch_lbr_disable(); 2383 /* ... until here */ 2384 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2385 } 2386 2387 /* 2388 * Workaround for: 2389 * Intel Errata AAK100 (model 26) 2390 * Intel Errata AAP53 (model 30) 2391 * Intel Errata BD53 (model 44) 2392 * 2393 * The official story: 2394 * These chips need to be 'reset' when adding counters by programming the 2395 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2396 * in sequence on the same PMC or on different PMCs. 2397 * 2398 * In practice it appears some of these events do in fact count, and 2399 * we need to program all 4 events. 2400 */ 2401 static void intel_pmu_nhm_workaround(void) 2402 { 2403 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2404 static const unsigned long nhm_magic[4] = { 2405 0x4300B5, 2406 0x4300D2, 2407 0x4300B1, 2408 0x4300B1 2409 }; 2410 struct perf_event *event; 2411 int i; 2412 2413 /* 2414 * The Errata requires below steps: 2415 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2416 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2417 * the corresponding PMCx; 2418 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2419 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2420 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2421 */ 2422 2423 /* 2424 * The real steps we choose are a little different from above. 2425 * A) To reduce MSR operations, we don't run step 1) as they 2426 * are already cleared before this function is called; 2427 * B) Call x86_perf_event_update to save PMCx before configuring 2428 * PERFEVTSELx with magic number; 2429 * C) With step 5), we do clear only when the PERFEVTSELx is 2430 * not used currently. 2431 * D) Call x86_perf_event_set_period to restore PMCx; 2432 */ 2433 2434 /* We always operate 4 pairs of PERF Counters */ 2435 for (i = 0; i < 4; i++) { 2436 event = cpuc->events[i]; 2437 if (event) 2438 static_call(x86_pmu_update)(event); 2439 } 2440 2441 for (i = 0; i < 4; i++) { 2442 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2443 wrmsrq(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2444 } 2445 2446 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2447 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2448 2449 for (i = 0; i < 4; i++) { 2450 event = cpuc->events[i]; 2451 2452 if (event) { 2453 static_call(x86_pmu_set_period)(event); 2454 __x86_pmu_enable_event(&event->hw, 2455 ARCH_PERFMON_EVENTSEL_ENABLE); 2456 } else 2457 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2458 } 2459 } 2460 2461 static void intel_pmu_nhm_enable_all(int added) 2462 { 2463 if (added) 2464 intel_pmu_nhm_workaround(); 2465 intel_pmu_enable_all(added); 2466 } 2467 2468 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2469 { 2470 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2471 2472 if (cpuc->tfa_shadow != val) { 2473 cpuc->tfa_shadow = val; 2474 wrmsrq(MSR_TSX_FORCE_ABORT, val); 2475 } 2476 } 2477 2478 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2479 { 2480 /* 2481 * We're going to use PMC3, make sure TFA is set before we touch it. 2482 */ 2483 if (cntr == 3) 2484 intel_set_tfa(cpuc, true); 2485 } 2486 2487 static void intel_tfa_pmu_enable_all(int added) 2488 { 2489 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2490 2491 /* 2492 * If we find PMC3 is no longer used when we enable the PMU, we can 2493 * clear TFA. 2494 */ 2495 if (!test_bit(3, cpuc->active_mask)) 2496 intel_set_tfa(cpuc, false); 2497 2498 intel_pmu_enable_all(added); 2499 } 2500 2501 static inline u64 intel_pmu_get_status(void) 2502 { 2503 u64 status; 2504 2505 rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status); 2506 2507 return status; 2508 } 2509 2510 static inline void intel_pmu_ack_status(u64 ack) 2511 { 2512 wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2513 } 2514 2515 static inline bool event_is_checkpointed(struct perf_event *event) 2516 { 2517 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2518 } 2519 2520 static inline void intel_set_masks(struct perf_event *event, int idx) 2521 { 2522 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2523 2524 if (event->attr.exclude_host) 2525 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2526 if (event->attr.exclude_guest) 2527 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2528 if (event_is_checkpointed(event)) 2529 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2530 } 2531 2532 static inline void intel_clear_masks(struct perf_event *event, int idx) 2533 { 2534 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2535 2536 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2537 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2538 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2539 } 2540 2541 static void intel_pmu_disable_fixed(struct perf_event *event) 2542 { 2543 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2544 struct hw_perf_event *hwc = &event->hw; 2545 int idx = hwc->idx; 2546 u64 mask; 2547 2548 if (is_topdown_idx(idx)) { 2549 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2550 2551 /* 2552 * When there are other active TopDown events, 2553 * don't disable the fixed counter 3. 2554 */ 2555 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2556 return; 2557 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2558 } 2559 2560 intel_clear_masks(event, idx); 2561 2562 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK); 2563 cpuc->fixed_ctrl_val &= ~mask; 2564 } 2565 2566 static void intel_pmu_disable_event(struct perf_event *event) 2567 { 2568 struct hw_perf_event *hwc = &event->hw; 2569 int idx = hwc->idx; 2570 2571 switch (idx) { 2572 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2573 intel_clear_masks(event, idx); 2574 x86_pmu_disable_event(event); 2575 break; 2576 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2577 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2578 intel_pmu_disable_fixed(event); 2579 break; 2580 case INTEL_PMC_IDX_FIXED_BTS: 2581 intel_pmu_disable_bts(); 2582 intel_pmu_drain_bts_buffer(); 2583 return; 2584 case INTEL_PMC_IDX_FIXED_VLBR: 2585 intel_clear_masks(event, idx); 2586 break; 2587 default: 2588 intel_clear_masks(event, idx); 2589 pr_warn("Failed to disable the event with invalid index %d\n", 2590 idx); 2591 return; 2592 } 2593 2594 /* 2595 * Needs to be called after x86_pmu_disable_event, 2596 * so we don't trigger the event without PEBS bit set. 2597 */ 2598 if (unlikely(event->attr.precise_ip)) 2599 static_call(x86_pmu_pebs_disable)(event); 2600 } 2601 2602 static void intel_pmu_assign_event(struct perf_event *event, int idx) 2603 { 2604 if (is_pebs_pt(event)) 2605 perf_report_aux_output_id(event, idx); 2606 } 2607 2608 static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event) 2609 { 2610 return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK; 2611 } 2612 2613 static void intel_pmu_del_event(struct perf_event *event) 2614 { 2615 if (intel_pmu_needs_branch_stack(event)) 2616 intel_pmu_lbr_del(event); 2617 if (event->attr.precise_ip) 2618 intel_pmu_pebs_del(event); 2619 if (is_pebs_counter_event_group(event) || 2620 is_acr_event_group(event)) 2621 this_cpu_ptr(&cpu_hw_events)->n_late_setup--; 2622 } 2623 2624 static int icl_set_topdown_event_period(struct perf_event *event) 2625 { 2626 struct hw_perf_event *hwc = &event->hw; 2627 s64 left = local64_read(&hwc->period_left); 2628 2629 /* 2630 * The values in PERF_METRICS MSR are derived from fixed counter 3. 2631 * Software should start both registers, PERF_METRICS and fixed 2632 * counter 3, from zero. 2633 * Clear PERF_METRICS and Fixed counter 3 in initialization. 2634 * After that, both MSRs will be cleared for each read. 2635 * Don't need to clear them again. 2636 */ 2637 if (left == x86_pmu.max_period) { 2638 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0); 2639 wrmsrq(MSR_PERF_METRICS, 0); 2640 hwc->saved_slots = 0; 2641 hwc->saved_metric = 0; 2642 } 2643 2644 if ((hwc->saved_slots) && is_slots_event(event)) { 2645 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2646 wrmsrq(MSR_PERF_METRICS, hwc->saved_metric); 2647 } 2648 2649 perf_event_update_userpage(event); 2650 2651 return 0; 2652 } 2653 2654 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period); 2655 2656 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 2657 { 2658 u32 val; 2659 2660 /* 2661 * The metric is reported as an 8bit integer fraction 2662 * summing up to 0xff. 2663 * slots-in-metric = (Metric / 0xff) * slots 2664 */ 2665 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 2666 return mul_u64_u32_div(slots, val, 0xff); 2667 } 2668 2669 static u64 icl_get_topdown_value(struct perf_event *event, 2670 u64 slots, u64 metrics) 2671 { 2672 int idx = event->hw.idx; 2673 u64 delta; 2674 2675 if (is_metric_idx(idx)) 2676 delta = icl_get_metrics_event_value(metrics, slots, idx); 2677 else 2678 delta = slots; 2679 2680 return delta; 2681 } 2682 2683 static void __icl_update_topdown_event(struct perf_event *event, 2684 u64 slots, u64 metrics, 2685 u64 last_slots, u64 last_metrics) 2686 { 2687 u64 delta, last = 0; 2688 2689 delta = icl_get_topdown_value(event, slots, metrics); 2690 if (last_slots) 2691 last = icl_get_topdown_value(event, last_slots, last_metrics); 2692 2693 /* 2694 * The 8bit integer fraction of metric may be not accurate, 2695 * especially when the changes is very small. 2696 * For example, if only a few bad_spec happens, the fraction 2697 * may be reduced from 1 to 0. If so, the bad_spec event value 2698 * will be 0 which is definitely less than the last value. 2699 * Avoid update event->count for this case. 2700 */ 2701 if (delta > last) { 2702 delta -= last; 2703 local64_add(delta, &event->count); 2704 } 2705 } 2706 2707 static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 2708 u64 metrics, int metric_end) 2709 { 2710 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2711 struct perf_event *other; 2712 int idx; 2713 2714 event->hw.saved_slots = slots; 2715 event->hw.saved_metric = metrics; 2716 2717 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2718 if (!is_topdown_idx(idx)) 2719 continue; 2720 other = cpuc->events[idx]; 2721 other->hw.saved_slots = slots; 2722 other->hw.saved_metric = metrics; 2723 } 2724 } 2725 2726 /* 2727 * Update all active Topdown events. 2728 * 2729 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 2730 * modify by a NMI. PMU has to be disabled before calling this function. 2731 */ 2732 2733 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end, u64 *val) 2734 { 2735 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2736 struct perf_event *other; 2737 u64 slots, metrics; 2738 bool reset = true; 2739 int idx; 2740 2741 if (!val) { 2742 /* read Fixed counter 3 */ 2743 slots = rdpmc(3 | INTEL_PMC_FIXED_RDPMC_BASE); 2744 if (!slots) 2745 return 0; 2746 2747 /* read PERF_METRICS */ 2748 metrics = rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS); 2749 } else { 2750 slots = val[0]; 2751 metrics = val[1]; 2752 /* 2753 * Don't reset the PERF_METRICS and Fixed counter 3 2754 * for each PEBS record read. Utilize the RDPMC metrics 2755 * clear mode. 2756 */ 2757 reset = false; 2758 } 2759 2760 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2761 if (!is_topdown_idx(idx)) 2762 continue; 2763 other = cpuc->events[idx]; 2764 __icl_update_topdown_event(other, slots, metrics, 2765 event ? event->hw.saved_slots : 0, 2766 event ? event->hw.saved_metric : 0); 2767 } 2768 2769 /* 2770 * Check and update this event, which may have been cleared 2771 * in active_mask e.g. x86_pmu_stop() 2772 */ 2773 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 2774 __icl_update_topdown_event(event, slots, metrics, 2775 event->hw.saved_slots, 2776 event->hw.saved_metric); 2777 2778 /* 2779 * In x86_pmu_stop(), the event is cleared in active_mask first, 2780 * then drain the delta, which indicates context switch for 2781 * counting. 2782 * Save metric and slots for context switch. 2783 * Don't need to reset the PERF_METRICS and Fixed counter 3. 2784 * Because the values will be restored in next schedule in. 2785 */ 2786 update_saved_topdown_regs(event, slots, metrics, metric_end); 2787 reset = false; 2788 } 2789 2790 if (reset) { 2791 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 2792 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0); 2793 wrmsrq(MSR_PERF_METRICS, 0); 2794 if (event) 2795 update_saved_topdown_regs(event, 0, 0, metric_end); 2796 } 2797 2798 return slots; 2799 } 2800 2801 static u64 icl_update_topdown_event(struct perf_event *event, u64 *val) 2802 { 2803 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 2804 x86_pmu.num_topdown_events - 1, 2805 val); 2806 } 2807 2808 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, intel_pmu_topdown_event_update); 2809 2810 static void intel_pmu_read_event(struct perf_event *event) 2811 { 2812 if (event->hw.flags & (PERF_X86_EVENT_AUTO_RELOAD | PERF_X86_EVENT_TOPDOWN) || 2813 is_pebs_counter_event_group(event)) { 2814 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2815 bool pmu_enabled = cpuc->enabled; 2816 2817 /* Only need to call update_topdown_event() once for group read. */ 2818 if (is_metric_event(event) && (cpuc->txn_flags & PERF_PMU_TXN_READ)) 2819 return; 2820 2821 cpuc->enabled = 0; 2822 if (pmu_enabled) 2823 intel_pmu_disable_all(); 2824 2825 /* 2826 * If the PEBS counters snapshotting is enabled, 2827 * the topdown event is available in PEBS records. 2828 */ 2829 if (is_topdown_event(event) && !is_pebs_counter_event_group(event)) 2830 static_call(intel_pmu_update_topdown_event)(event, NULL); 2831 else 2832 intel_pmu_drain_pebs_buffer(); 2833 2834 cpuc->enabled = pmu_enabled; 2835 if (pmu_enabled) 2836 intel_pmu_enable_all(0); 2837 2838 return; 2839 } 2840 2841 x86_perf_event_update(event); 2842 } 2843 2844 static void intel_pmu_enable_fixed(struct perf_event *event) 2845 { 2846 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2847 struct hw_perf_event *hwc = &event->hw; 2848 u64 mask, bits = 0; 2849 int idx = hwc->idx; 2850 2851 if (is_topdown_idx(idx)) { 2852 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2853 /* 2854 * When there are other active TopDown events, 2855 * don't enable the fixed counter 3 again. 2856 */ 2857 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2858 return; 2859 2860 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2861 2862 if (event->attr.config1 & INTEL_TD_CFG_METRIC_CLEAR) 2863 bits |= INTEL_FIXED_3_METRICS_CLEAR; 2864 } 2865 2866 intel_set_masks(event, idx); 2867 2868 /* 2869 * Enable IRQ generation (0x8), if not PEBS, 2870 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2871 * if requested: 2872 */ 2873 if (!event->attr.precise_ip) 2874 bits |= INTEL_FIXED_0_ENABLE_PMI; 2875 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2876 bits |= INTEL_FIXED_0_USER; 2877 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2878 bits |= INTEL_FIXED_0_KERNEL; 2879 2880 /* 2881 * ANY bit is supported in v3 and up 2882 */ 2883 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2884 bits |= INTEL_FIXED_0_ANYTHREAD; 2885 2886 idx -= INTEL_PMC_IDX_FIXED; 2887 bits = intel_fixed_bits_by_idx(idx, bits); 2888 mask = intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK); 2889 2890 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2891 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); 2892 mask |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); 2893 } 2894 2895 cpuc->fixed_ctrl_val &= ~mask; 2896 cpuc->fixed_ctrl_val |= bits; 2897 } 2898 2899 static void intel_pmu_config_acr(int idx, u64 mask, u32 reload) 2900 { 2901 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2902 int msr_b, msr_c; 2903 2904 if (!mask && !cpuc->acr_cfg_b[idx]) 2905 return; 2906 2907 if (idx < INTEL_PMC_IDX_FIXED) { 2908 msr_b = MSR_IA32_PMC_V6_GP0_CFG_B; 2909 msr_c = MSR_IA32_PMC_V6_GP0_CFG_C; 2910 } else { 2911 msr_b = MSR_IA32_PMC_V6_FX0_CFG_B; 2912 msr_c = MSR_IA32_PMC_V6_FX0_CFG_C; 2913 idx -= INTEL_PMC_IDX_FIXED; 2914 } 2915 2916 if (cpuc->acr_cfg_b[idx] != mask) { 2917 wrmsrl(msr_b + x86_pmu.addr_offset(idx, false), mask); 2918 cpuc->acr_cfg_b[idx] = mask; 2919 } 2920 /* Only need to update the reload value when there is a valid config value. */ 2921 if (mask && cpuc->acr_cfg_c[idx] != reload) { 2922 wrmsrl(msr_c + x86_pmu.addr_offset(idx, false), reload); 2923 cpuc->acr_cfg_c[idx] = reload; 2924 } 2925 } 2926 2927 static void intel_pmu_enable_acr(struct perf_event *event) 2928 { 2929 struct hw_perf_event *hwc = &event->hw; 2930 2931 if (!is_acr_event_group(event) || !event->attr.config2) { 2932 /* 2933 * The disable doesn't clear the ACR CFG register. 2934 * Check and clear the ACR CFG register. 2935 */ 2936 intel_pmu_config_acr(hwc->idx, 0, 0); 2937 return; 2938 } 2939 2940 intel_pmu_config_acr(hwc->idx, hwc->config1, -hwc->sample_period); 2941 } 2942 2943 DEFINE_STATIC_CALL_NULL(intel_pmu_enable_acr_event, intel_pmu_enable_acr); 2944 2945 static void intel_pmu_enable_event(struct perf_event *event) 2946 { 2947 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE; 2948 struct hw_perf_event *hwc = &event->hw; 2949 int idx = hwc->idx; 2950 2951 if (unlikely(event->attr.precise_ip)) 2952 static_call(x86_pmu_pebs_enable)(event); 2953 2954 switch (idx) { 2955 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2956 if (branch_sample_counters(event)) 2957 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR; 2958 intel_set_masks(event, idx); 2959 static_call_cond(intel_pmu_enable_acr_event)(event); 2960 __x86_pmu_enable_event(hwc, enable_mask); 2961 break; 2962 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2963 static_call_cond(intel_pmu_enable_acr_event)(event); 2964 fallthrough; 2965 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2966 intel_pmu_enable_fixed(event); 2967 break; 2968 case INTEL_PMC_IDX_FIXED_BTS: 2969 if (!__this_cpu_read(cpu_hw_events.enabled)) 2970 return; 2971 intel_pmu_enable_bts(hwc->config); 2972 break; 2973 case INTEL_PMC_IDX_FIXED_VLBR: 2974 intel_set_masks(event, idx); 2975 break; 2976 default: 2977 pr_warn("Failed to enable the event with invalid index %d\n", 2978 idx); 2979 } 2980 } 2981 2982 static void intel_pmu_acr_late_setup(struct cpu_hw_events *cpuc) 2983 { 2984 struct perf_event *event, *leader; 2985 int i, j, idx; 2986 2987 for (i = 0; i < cpuc->n_events; i++) { 2988 leader = cpuc->event_list[i]; 2989 if (!is_acr_event_group(leader)) 2990 continue; 2991 2992 /* The ACR events must be contiguous. */ 2993 for (j = i; j < cpuc->n_events; j++) { 2994 event = cpuc->event_list[j]; 2995 if (event->group_leader != leader->group_leader) 2996 break; 2997 for_each_set_bit(idx, (unsigned long *)&event->attr.config2, X86_PMC_IDX_MAX) { 2998 if (WARN_ON_ONCE(i + idx > cpuc->n_events)) 2999 return; 3000 __set_bit(cpuc->assign[i + idx], (unsigned long *)&event->hw.config1); 3001 } 3002 } 3003 i = j - 1; 3004 } 3005 } 3006 3007 void intel_pmu_late_setup(void) 3008 { 3009 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3010 3011 if (!cpuc->n_late_setup) 3012 return; 3013 3014 intel_pmu_pebs_late_setup(cpuc); 3015 intel_pmu_acr_late_setup(cpuc); 3016 } 3017 3018 static void intel_pmu_add_event(struct perf_event *event) 3019 { 3020 if (event->attr.precise_ip) 3021 intel_pmu_pebs_add(event); 3022 if (intel_pmu_needs_branch_stack(event)) 3023 intel_pmu_lbr_add(event); 3024 if (is_pebs_counter_event_group(event) || 3025 is_acr_event_group(event)) 3026 this_cpu_ptr(&cpu_hw_events)->n_late_setup++; 3027 } 3028 3029 /* 3030 * Save and restart an expired event. Called by NMI contexts, 3031 * so it has to be careful about preempting normal event ops: 3032 */ 3033 int intel_pmu_save_and_restart(struct perf_event *event) 3034 { 3035 static_call(x86_pmu_update)(event); 3036 /* 3037 * For a checkpointed counter always reset back to 0. This 3038 * avoids a situation where the counter overflows, aborts the 3039 * transaction and is then set back to shortly before the 3040 * overflow, and overflows and aborts again. 3041 */ 3042 if (unlikely(event_is_checkpointed(event))) { 3043 /* No race with NMIs because the counter should not be armed */ 3044 wrmsrq(event->hw.event_base, 0); 3045 local64_set(&event->hw.prev_count, 0); 3046 } 3047 return static_call(x86_pmu_set_period)(event); 3048 } 3049 3050 static int intel_pmu_set_period(struct perf_event *event) 3051 { 3052 if (unlikely(is_topdown_count(event))) 3053 return static_call(intel_pmu_set_topdown_event_period)(event); 3054 3055 return x86_perf_event_set_period(event); 3056 } 3057 3058 static u64 intel_pmu_update(struct perf_event *event) 3059 { 3060 if (unlikely(is_topdown_count(event))) 3061 return static_call(intel_pmu_update_topdown_event)(event, NULL); 3062 3063 return x86_perf_event_update(event); 3064 } 3065 3066 static void intel_pmu_reset(void) 3067 { 3068 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 3069 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3070 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask); 3071 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask); 3072 unsigned long flags; 3073 int idx; 3074 3075 if (!*(u64 *)cntr_mask) 3076 return; 3077 3078 local_irq_save(flags); 3079 3080 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 3081 3082 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) { 3083 wrmsrq_safe(x86_pmu_config_addr(idx), 0ull); 3084 wrmsrq_safe(x86_pmu_event_addr(idx), 0ull); 3085 } 3086 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) { 3087 if (fixed_counter_disabled(idx, cpuc->pmu)) 3088 continue; 3089 wrmsrq_safe(x86_pmu_fixed_ctr_addr(idx), 0ull); 3090 } 3091 3092 if (ds) 3093 ds->bts_index = ds->bts_buffer_base; 3094 3095 /* Ack all overflows and disable fixed counters */ 3096 if (x86_pmu.version >= 2) { 3097 intel_pmu_ack_status(intel_pmu_get_status()); 3098 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0); 3099 } 3100 3101 /* Reset LBRs and LBR freezing */ 3102 if (x86_pmu.lbr_nr) { 3103 update_debugctlmsr(get_debugctlmsr() & 3104 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 3105 } 3106 3107 local_irq_restore(flags); 3108 } 3109 3110 /* 3111 * We may be running with guest PEBS events created by KVM, and the 3112 * PEBS records are logged into the guest's DS and invisible to host. 3113 * 3114 * In the case of guest PEBS overflow, we only trigger a fake event 3115 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM. 3116 * The guest will then vm-entry and check the guest DS area to read 3117 * the guest PEBS records. 3118 * 3119 * The contents and other behavior of the guest event do not matter. 3120 */ 3121 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs, 3122 struct perf_sample_data *data) 3123 { 3124 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3125 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask; 3126 struct perf_event *event = NULL; 3127 int bit; 3128 3129 if (!unlikely(perf_guest_state())) 3130 return; 3131 3132 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active || 3133 !guest_pebs_idxs) 3134 return; 3135 3136 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) { 3137 event = cpuc->events[bit]; 3138 if (!event->attr.precise_ip) 3139 continue; 3140 3141 perf_sample_data_init(data, 0, event->hw.last_period); 3142 perf_event_overflow(event, data, regs); 3143 3144 /* Inject one fake event is enough. */ 3145 break; 3146 } 3147 } 3148 3149 static int handle_pmi_common(struct pt_regs *regs, u64 status) 3150 { 3151 struct perf_sample_data data; 3152 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3153 int bit; 3154 int handled = 0; 3155 3156 inc_irq_stat(apic_perf_irqs); 3157 3158 /* 3159 * Ignore a range of extra bits in status that do not indicate 3160 * overflow by themselves. 3161 */ 3162 status &= ~(GLOBAL_STATUS_COND_CHG | 3163 GLOBAL_STATUS_ASIF | 3164 GLOBAL_STATUS_LBRS_FROZEN); 3165 if (!status) 3166 return 0; 3167 /* 3168 * In case multiple PEBS events are sampled at the same time, 3169 * it is possible to have GLOBAL_STATUS bit 62 set indicating 3170 * PEBS buffer overflow and also seeing at most 3 PEBS counters 3171 * having their bits set in the status register. This is a sign 3172 * that there was at least one PEBS record pending at the time 3173 * of the PMU interrupt. PEBS counters must only be processed 3174 * via the drain_pebs() calls and not via the regular sample 3175 * processing loop coming after that the function, otherwise 3176 * phony regular samples may be generated in the sampling buffer 3177 * not marked with the EXACT tag. Another possibility is to have 3178 * one PEBS event and at least one non-PEBS event which overflows 3179 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 3180 * not be set, yet the overflow status bit for the PEBS counter will 3181 * be on Skylake. 3182 * 3183 * To avoid this problem, we systematically ignore the PEBS-enabled 3184 * counters from the GLOBAL_STATUS mask and we always process PEBS 3185 * events via drain_pebs(). 3186 */ 3187 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable); 3188 3189 /* 3190 * PEBS overflow sets bit 62 in the global status register 3191 */ 3192 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 3193 u64 pebs_enabled = cpuc->pebs_enabled; 3194 3195 handled++; 3196 x86_pmu_handle_guest_pebs(regs, &data); 3197 static_call(x86_pmu_drain_pebs)(regs, &data); 3198 3199 /* 3200 * PMI throttle may be triggered, which stops the PEBS event. 3201 * Although cpuc->pebs_enabled is updated accordingly, the 3202 * MSR_IA32_PEBS_ENABLE is not updated. Because the 3203 * cpuc->enabled has been forced to 0 in PMI. 3204 * Update the MSR if pebs_enabled is changed. 3205 */ 3206 if (pebs_enabled != cpuc->pebs_enabled) 3207 wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 3208 3209 /* 3210 * Above PEBS handler (PEBS counters snapshotting) has updated fixed 3211 * counter 3 and perf metrics counts if they are in counter group, 3212 * unnecessary to update again. 3213 */ 3214 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] && 3215 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS])) 3216 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT; 3217 } 3218 3219 /* 3220 * Intel PT 3221 */ 3222 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 3223 handled++; 3224 if (!perf_guest_handle_intel_pt_intr()) 3225 intel_pt_interrupt(); 3226 } 3227 3228 /* 3229 * Intel Perf metrics 3230 */ 3231 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 3232 handled++; 3233 static_call(intel_pmu_update_topdown_event)(NULL, NULL); 3234 } 3235 3236 status &= hybrid(cpuc->pmu, intel_ctrl); 3237 3238 /* 3239 * Checkpointed counters can lead to 'spurious' PMIs because the 3240 * rollback caused by the PMI will have cleared the overflow status 3241 * bit. Therefore always force probe these counters. 3242 */ 3243 status |= cpuc->intel_cp_status; 3244 3245 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 3246 struct perf_event *event = cpuc->events[bit]; 3247 u64 last_period; 3248 3249 handled++; 3250 3251 if (!test_bit(bit, cpuc->active_mask)) 3252 continue; 3253 3254 /* 3255 * There may be unprocessed PEBS records in the PEBS buffer, 3256 * which still stores the previous values. 3257 * Process those records first before handling the latest value. 3258 * For example, 3259 * A is a regular counter 3260 * B is a PEBS event which reads A 3261 * C is a PEBS event 3262 * 3263 * The following can happen: 3264 * B-assist A=1 3265 * C A=2 3266 * B-assist A=3 3267 * A-overflow-PMI A=4 3268 * C-assist-PMI (PEBS buffer) A=5 3269 * 3270 * The PEBS buffer has to be drained before handling the A-PMI 3271 */ 3272 if (is_pebs_counter_event_group(event)) 3273 x86_pmu.drain_pebs(regs, &data); 3274 3275 last_period = event->hw.last_period; 3276 3277 if (!intel_pmu_save_and_restart(event)) 3278 continue; 3279 3280 perf_sample_data_init(&data, 0, last_period); 3281 3282 if (has_branch_stack(event)) 3283 intel_pmu_lbr_save_brstack(&data, cpuc, event); 3284 3285 perf_event_overflow(event, &data, regs); 3286 } 3287 3288 return handled; 3289 } 3290 3291 /* 3292 * This handler is triggered by the local APIC, so the APIC IRQ handling 3293 * rules apply: 3294 */ 3295 static int intel_pmu_handle_irq(struct pt_regs *regs) 3296 { 3297 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3298 bool late_ack = hybrid_bit(cpuc->pmu, late_ack); 3299 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); 3300 int loops; 3301 u64 status; 3302 int handled; 3303 int pmu_enabled; 3304 3305 /* 3306 * Save the PMU state. 3307 * It needs to be restored when leaving the handler. 3308 */ 3309 pmu_enabled = cpuc->enabled; 3310 /* 3311 * In general, the early ACK is only applied for old platforms. 3312 * For the big core starts from Haswell, the late ACK should be 3313 * applied. 3314 * For the small core after Tremont, we have to do the ACK right 3315 * before re-enabling counters, which is in the middle of the 3316 * NMI handler. 3317 */ 3318 if (!late_ack && !mid_ack) 3319 apic_write(APIC_LVTPC, APIC_DM_NMI); 3320 intel_bts_disable_local(); 3321 cpuc->enabled = 0; 3322 __intel_pmu_disable_all(true); 3323 handled = intel_pmu_drain_bts_buffer(); 3324 handled += intel_bts_interrupt(); 3325 status = intel_pmu_get_status(); 3326 if (!status) 3327 goto done; 3328 3329 loops = 0; 3330 again: 3331 intel_pmu_lbr_read(); 3332 intel_pmu_ack_status(status); 3333 if (++loops > 100) { 3334 static bool warned; 3335 3336 if (!warned) { 3337 WARN(1, "perfevents: irq loop stuck!\n"); 3338 perf_event_print_debug(); 3339 warned = true; 3340 } 3341 intel_pmu_reset(); 3342 goto done; 3343 } 3344 3345 handled += handle_pmi_common(regs, status); 3346 3347 /* 3348 * Repeat if there is more work to be done: 3349 */ 3350 status = intel_pmu_get_status(); 3351 if (status) 3352 goto again; 3353 3354 done: 3355 if (mid_ack) 3356 apic_write(APIC_LVTPC, APIC_DM_NMI); 3357 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 3358 cpuc->enabled = pmu_enabled; 3359 if (pmu_enabled) 3360 __intel_pmu_enable_all(0, true); 3361 intel_bts_enable_local(); 3362 3363 /* 3364 * Only unmask the NMI after the overflow counters 3365 * have been reset. This avoids spurious NMIs on 3366 * Haswell CPUs. 3367 */ 3368 if (late_ack) 3369 apic_write(APIC_LVTPC, APIC_DM_NMI); 3370 return handled; 3371 } 3372 3373 static struct event_constraint * 3374 intel_bts_constraints(struct perf_event *event) 3375 { 3376 if (unlikely(intel_pmu_has_bts(event))) 3377 return &bts_constraint; 3378 3379 return NULL; 3380 } 3381 3382 /* 3383 * Note: matches a fake event, like Fixed2. 3384 */ 3385 static struct event_constraint * 3386 intel_vlbr_constraints(struct perf_event *event) 3387 { 3388 struct event_constraint *c = &vlbr_constraint; 3389 3390 if (unlikely(constraint_match(c, event->hw.config))) { 3391 event->hw.flags |= c->flags; 3392 return c; 3393 } 3394 3395 return NULL; 3396 } 3397 3398 static int intel_alt_er(struct cpu_hw_events *cpuc, 3399 int idx, u64 config) 3400 { 3401 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); 3402 int alt_idx = idx; 3403 3404 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 3405 return idx; 3406 3407 if (idx == EXTRA_REG_RSP_0) 3408 alt_idx = EXTRA_REG_RSP_1; 3409 3410 if (idx == EXTRA_REG_RSP_1) 3411 alt_idx = EXTRA_REG_RSP_0; 3412 3413 if (config & ~extra_regs[alt_idx].valid_mask) 3414 return idx; 3415 3416 return alt_idx; 3417 } 3418 3419 static void intel_fixup_er(struct perf_event *event, int idx) 3420 { 3421 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); 3422 event->hw.extra_reg.idx = idx; 3423 3424 if (idx == EXTRA_REG_RSP_0) { 3425 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3426 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event; 3427 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 3428 } else if (idx == EXTRA_REG_RSP_1) { 3429 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3430 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event; 3431 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 3432 } 3433 } 3434 3435 /* 3436 * manage allocation of shared extra msr for certain events 3437 * 3438 * sharing can be: 3439 * per-cpu: to be shared between the various events on a single PMU 3440 * per-core: per-cpu + shared by HT threads 3441 */ 3442 static struct event_constraint * 3443 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 3444 struct perf_event *event, 3445 struct hw_perf_event_extra *reg) 3446 { 3447 struct event_constraint *c = &emptyconstraint; 3448 struct er_account *era; 3449 unsigned long flags; 3450 int idx = reg->idx; 3451 3452 /* 3453 * reg->alloc can be set due to existing state, so for fake cpuc we 3454 * need to ignore this, otherwise we might fail to allocate proper fake 3455 * state for this extra reg constraint. Also see the comment below. 3456 */ 3457 if (reg->alloc && !cpuc->is_fake) 3458 return NULL; /* call x86_get_event_constraint() */ 3459 3460 again: 3461 era = &cpuc->shared_regs->regs[idx]; 3462 /* 3463 * we use spin_lock_irqsave() to avoid lockdep issues when 3464 * passing a fake cpuc 3465 */ 3466 raw_spin_lock_irqsave(&era->lock, flags); 3467 3468 if (!atomic_read(&era->ref) || era->config == reg->config) { 3469 3470 /* 3471 * If its a fake cpuc -- as per validate_{group,event}() we 3472 * shouldn't touch event state and we can avoid doing so 3473 * since both will only call get_event_constraints() once 3474 * on each event, this avoids the need for reg->alloc. 3475 * 3476 * Not doing the ER fixup will only result in era->reg being 3477 * wrong, but since we won't actually try and program hardware 3478 * this isn't a problem either. 3479 */ 3480 if (!cpuc->is_fake) { 3481 if (idx != reg->idx) 3482 intel_fixup_er(event, idx); 3483 3484 /* 3485 * x86_schedule_events() can call get_event_constraints() 3486 * multiple times on events in the case of incremental 3487 * scheduling(). reg->alloc ensures we only do the ER 3488 * allocation once. 3489 */ 3490 reg->alloc = 1; 3491 } 3492 3493 /* lock in msr value */ 3494 era->config = reg->config; 3495 era->reg = reg->reg; 3496 3497 /* one more user */ 3498 atomic_inc(&era->ref); 3499 3500 /* 3501 * need to call x86_get_event_constraint() 3502 * to check if associated event has constraints 3503 */ 3504 c = NULL; 3505 } else { 3506 idx = intel_alt_er(cpuc, idx, reg->config); 3507 if (idx != reg->idx) { 3508 raw_spin_unlock_irqrestore(&era->lock, flags); 3509 goto again; 3510 } 3511 } 3512 raw_spin_unlock_irqrestore(&era->lock, flags); 3513 3514 return c; 3515 } 3516 3517 static void 3518 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3519 struct hw_perf_event_extra *reg) 3520 { 3521 struct er_account *era; 3522 3523 /* 3524 * Only put constraint if extra reg was actually allocated. Also takes 3525 * care of event which do not use an extra shared reg. 3526 * 3527 * Also, if this is a fake cpuc we shouldn't touch any event state 3528 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3529 * either since it'll be thrown out. 3530 */ 3531 if (!reg->alloc || cpuc->is_fake) 3532 return; 3533 3534 era = &cpuc->shared_regs->regs[reg->idx]; 3535 3536 /* one fewer user */ 3537 atomic_dec(&era->ref); 3538 3539 /* allocate again next time */ 3540 reg->alloc = 0; 3541 } 3542 3543 static struct event_constraint * 3544 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3545 struct perf_event *event) 3546 { 3547 struct event_constraint *c = NULL, *d; 3548 struct hw_perf_event_extra *xreg, *breg; 3549 3550 xreg = &event->hw.extra_reg; 3551 if (xreg->idx != EXTRA_REG_NONE) { 3552 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3553 if (c == &emptyconstraint) 3554 return c; 3555 } 3556 breg = &event->hw.branch_reg; 3557 if (breg->idx != EXTRA_REG_NONE) { 3558 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3559 if (d == &emptyconstraint) { 3560 __intel_shared_reg_put_constraints(cpuc, xreg); 3561 c = d; 3562 } 3563 } 3564 return c; 3565 } 3566 3567 struct event_constraint * 3568 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3569 struct perf_event *event) 3570 { 3571 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); 3572 struct event_constraint *c; 3573 3574 if (event_constraints) { 3575 for_each_event_constraint(c, event_constraints) { 3576 if (constraint_match(c, event->hw.config)) { 3577 event->hw.flags |= c->flags; 3578 return c; 3579 } 3580 } 3581 } 3582 3583 return &hybrid_var(cpuc->pmu, unconstrained); 3584 } 3585 3586 static struct event_constraint * 3587 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3588 struct perf_event *event) 3589 { 3590 struct event_constraint *c; 3591 3592 c = intel_vlbr_constraints(event); 3593 if (c) 3594 return c; 3595 3596 c = intel_bts_constraints(event); 3597 if (c) 3598 return c; 3599 3600 c = intel_shared_regs_constraints(cpuc, event); 3601 if (c) 3602 return c; 3603 3604 c = intel_pebs_constraints(event); 3605 if (c) 3606 return c; 3607 3608 return x86_get_event_constraints(cpuc, idx, event); 3609 } 3610 3611 static void 3612 intel_start_scheduling(struct cpu_hw_events *cpuc) 3613 { 3614 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3615 struct intel_excl_states *xl; 3616 int tid = cpuc->excl_thread_id; 3617 3618 /* 3619 * nothing needed if in group validation mode 3620 */ 3621 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3622 return; 3623 3624 /* 3625 * no exclusion needed 3626 */ 3627 if (WARN_ON_ONCE(!excl_cntrs)) 3628 return; 3629 3630 xl = &excl_cntrs->states[tid]; 3631 3632 xl->sched_started = true; 3633 /* 3634 * lock shared state until we are done scheduling 3635 * in stop_event_scheduling() 3636 * makes scheduling appear as a transaction 3637 */ 3638 raw_spin_lock(&excl_cntrs->lock); 3639 } 3640 3641 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3642 { 3643 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3644 struct event_constraint *c = cpuc->event_constraint[idx]; 3645 struct intel_excl_states *xl; 3646 int tid = cpuc->excl_thread_id; 3647 3648 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3649 return; 3650 3651 if (WARN_ON_ONCE(!excl_cntrs)) 3652 return; 3653 3654 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3655 return; 3656 3657 xl = &excl_cntrs->states[tid]; 3658 3659 lockdep_assert_held(&excl_cntrs->lock); 3660 3661 if (c->flags & PERF_X86_EVENT_EXCL) 3662 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3663 else 3664 xl->state[cntr] = INTEL_EXCL_SHARED; 3665 } 3666 3667 static void 3668 intel_stop_scheduling(struct cpu_hw_events *cpuc) 3669 { 3670 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3671 struct intel_excl_states *xl; 3672 int tid = cpuc->excl_thread_id; 3673 3674 /* 3675 * nothing needed if in group validation mode 3676 */ 3677 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3678 return; 3679 /* 3680 * no exclusion needed 3681 */ 3682 if (WARN_ON_ONCE(!excl_cntrs)) 3683 return; 3684 3685 xl = &excl_cntrs->states[tid]; 3686 3687 xl->sched_started = false; 3688 /* 3689 * release shared state lock (acquired in intel_start_scheduling()) 3690 */ 3691 raw_spin_unlock(&excl_cntrs->lock); 3692 } 3693 3694 static struct event_constraint * 3695 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 3696 { 3697 WARN_ON_ONCE(!cpuc->constraint_list); 3698 3699 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 3700 struct event_constraint *cx; 3701 3702 /* 3703 * grab pre-allocated constraint entry 3704 */ 3705 cx = &cpuc->constraint_list[idx]; 3706 3707 /* 3708 * initialize dynamic constraint 3709 * with static constraint 3710 */ 3711 *cx = *c; 3712 3713 /* 3714 * mark constraint as dynamic 3715 */ 3716 cx->flags |= PERF_X86_EVENT_DYNAMIC; 3717 c = cx; 3718 } 3719 3720 return c; 3721 } 3722 3723 static struct event_constraint * 3724 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3725 int idx, struct event_constraint *c) 3726 { 3727 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3728 struct intel_excl_states *xlo; 3729 int tid = cpuc->excl_thread_id; 3730 int is_excl, i, w; 3731 3732 /* 3733 * validating a group does not require 3734 * enforcing cross-thread exclusion 3735 */ 3736 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3737 return c; 3738 3739 /* 3740 * no exclusion needed 3741 */ 3742 if (WARN_ON_ONCE(!excl_cntrs)) 3743 return c; 3744 3745 /* 3746 * because we modify the constraint, we need 3747 * to make a copy. Static constraints come 3748 * from static const tables. 3749 * 3750 * only needed when constraint has not yet 3751 * been cloned (marked dynamic) 3752 */ 3753 c = dyn_constraint(cpuc, c, idx); 3754 3755 /* 3756 * From here on, the constraint is dynamic. 3757 * Either it was just allocated above, or it 3758 * was allocated during a earlier invocation 3759 * of this function 3760 */ 3761 3762 /* 3763 * state of sibling HT 3764 */ 3765 xlo = &excl_cntrs->states[tid ^ 1]; 3766 3767 /* 3768 * event requires exclusive counter access 3769 * across HT threads 3770 */ 3771 is_excl = c->flags & PERF_X86_EVENT_EXCL; 3772 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3773 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3774 if (!cpuc->n_excl++) 3775 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3776 } 3777 3778 /* 3779 * Modify static constraint with current dynamic 3780 * state of thread 3781 * 3782 * EXCLUSIVE: sibling counter measuring exclusive event 3783 * SHARED : sibling counter measuring non-exclusive event 3784 * UNUSED : sibling counter unused 3785 */ 3786 w = c->weight; 3787 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3788 /* 3789 * exclusive event in sibling counter 3790 * our corresponding counter cannot be used 3791 * regardless of our event 3792 */ 3793 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3794 __clear_bit(i, c->idxmsk); 3795 w--; 3796 continue; 3797 } 3798 /* 3799 * if measuring an exclusive event, sibling 3800 * measuring non-exclusive, then counter cannot 3801 * be used 3802 */ 3803 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3804 __clear_bit(i, c->idxmsk); 3805 w--; 3806 continue; 3807 } 3808 } 3809 3810 /* 3811 * if we return an empty mask, then switch 3812 * back to static empty constraint to avoid 3813 * the cost of freeing later on 3814 */ 3815 if (!w) 3816 c = &emptyconstraint; 3817 3818 c->weight = w; 3819 3820 return c; 3821 } 3822 3823 static struct event_constraint * 3824 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3825 struct perf_event *event) 3826 { 3827 struct event_constraint *c1, *c2; 3828 3829 c1 = cpuc->event_constraint[idx]; 3830 3831 /* 3832 * first time only 3833 * - static constraint: no change across incremental scheduling calls 3834 * - dynamic constraint: handled by intel_get_excl_constraints() 3835 */ 3836 c2 = __intel_get_event_constraints(cpuc, idx, event); 3837 if (c1) { 3838 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3839 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3840 c1->weight = c2->weight; 3841 c2 = c1; 3842 } 3843 3844 if (cpuc->excl_cntrs) 3845 return intel_get_excl_constraints(cpuc, event, idx, c2); 3846 3847 if (event->hw.dyn_constraint != ~0ULL) { 3848 c2 = dyn_constraint(cpuc, c2, idx); 3849 c2->idxmsk64 &= event->hw.dyn_constraint; 3850 c2->weight = hweight64(c2->idxmsk64); 3851 } 3852 3853 return c2; 3854 } 3855 3856 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3857 struct perf_event *event) 3858 { 3859 struct hw_perf_event *hwc = &event->hw; 3860 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3861 int tid = cpuc->excl_thread_id; 3862 struct intel_excl_states *xl; 3863 3864 /* 3865 * nothing needed if in group validation mode 3866 */ 3867 if (cpuc->is_fake) 3868 return; 3869 3870 if (WARN_ON_ONCE(!excl_cntrs)) 3871 return; 3872 3873 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3874 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3875 if (!--cpuc->n_excl) 3876 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3877 } 3878 3879 /* 3880 * If event was actually assigned, then mark the counter state as 3881 * unused now. 3882 */ 3883 if (hwc->idx >= 0) { 3884 xl = &excl_cntrs->states[tid]; 3885 3886 /* 3887 * put_constraint may be called from x86_schedule_events() 3888 * which already has the lock held so here make locking 3889 * conditional. 3890 */ 3891 if (!xl->sched_started) 3892 raw_spin_lock(&excl_cntrs->lock); 3893 3894 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3895 3896 if (!xl->sched_started) 3897 raw_spin_unlock(&excl_cntrs->lock); 3898 } 3899 } 3900 3901 static void 3902 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3903 struct perf_event *event) 3904 { 3905 struct hw_perf_event_extra *reg; 3906 3907 reg = &event->hw.extra_reg; 3908 if (reg->idx != EXTRA_REG_NONE) 3909 __intel_shared_reg_put_constraints(cpuc, reg); 3910 3911 reg = &event->hw.branch_reg; 3912 if (reg->idx != EXTRA_REG_NONE) 3913 __intel_shared_reg_put_constraints(cpuc, reg); 3914 } 3915 3916 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3917 struct perf_event *event) 3918 { 3919 intel_put_shared_regs_event_constraints(cpuc, event); 3920 3921 /* 3922 * is PMU has exclusive counter restrictions, then 3923 * all events are subject to and must call the 3924 * put_excl_constraints() routine 3925 */ 3926 if (cpuc->excl_cntrs) 3927 intel_put_excl_constraints(cpuc, event); 3928 } 3929 3930 static void intel_pebs_aliases_core2(struct perf_event *event) 3931 { 3932 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3933 /* 3934 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3935 * (0x003c) so that we can use it with PEBS. 3936 * 3937 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3938 * PEBS capable. However we can use INST_RETIRED.ANY_P 3939 * (0x00c0), which is a PEBS capable event, to get the same 3940 * count. 3941 * 3942 * INST_RETIRED.ANY_P counts the number of cycles that retires 3943 * CNTMASK instructions. By setting CNTMASK to a value (16) 3944 * larger than the maximum number of instructions that can be 3945 * retired per cycle (4) and then inverting the condition, we 3946 * count all cycles that retire 16 or less instructions, which 3947 * is every cycle. 3948 * 3949 * Thereby we gain a PEBS capable cycle counter. 3950 */ 3951 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3952 3953 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3954 event->hw.config = alt_config; 3955 } 3956 } 3957 3958 static void intel_pebs_aliases_snb(struct perf_event *event) 3959 { 3960 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3961 /* 3962 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3963 * (0x003c) so that we can use it with PEBS. 3964 * 3965 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3966 * PEBS capable. However we can use UOPS_RETIRED.ALL 3967 * (0x01c2), which is a PEBS capable event, to get the same 3968 * count. 3969 * 3970 * UOPS_RETIRED.ALL counts the number of cycles that retires 3971 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3972 * larger than the maximum number of micro-ops that can be 3973 * retired per cycle (4) and then inverting the condition, we 3974 * count all cycles that retire 16 or less micro-ops, which 3975 * is every cycle. 3976 * 3977 * Thereby we gain a PEBS capable cycle counter. 3978 */ 3979 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3980 3981 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3982 event->hw.config = alt_config; 3983 } 3984 } 3985 3986 static void intel_pebs_aliases_precdist(struct perf_event *event) 3987 { 3988 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3989 /* 3990 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3991 * (0x003c) so that we can use it with PEBS. 3992 * 3993 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3994 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3995 * (0x01c0), which is a PEBS capable event, to get the same 3996 * count. 3997 * 3998 * The PREC_DIST event has special support to minimize sample 3999 * shadowing effects. One drawback is that it can be 4000 * only programmed on counter 1, but that seems like an 4001 * acceptable trade off. 4002 */ 4003 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 4004 4005 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 4006 event->hw.config = alt_config; 4007 } 4008 } 4009 4010 static void intel_pebs_aliases_ivb(struct perf_event *event) 4011 { 4012 if (event->attr.precise_ip < 3) 4013 return intel_pebs_aliases_snb(event); 4014 return intel_pebs_aliases_precdist(event); 4015 } 4016 4017 static void intel_pebs_aliases_skl(struct perf_event *event) 4018 { 4019 if (event->attr.precise_ip < 3) 4020 return intel_pebs_aliases_core2(event); 4021 return intel_pebs_aliases_precdist(event); 4022 } 4023 4024 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 4025 { 4026 unsigned long flags = x86_pmu.large_pebs_flags; 4027 4028 if (event->attr.use_clockid) 4029 flags &= ~PERF_SAMPLE_TIME; 4030 if (!event->attr.exclude_kernel) 4031 flags &= ~PERF_SAMPLE_REGS_USER; 4032 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 4033 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 4034 return flags; 4035 } 4036 4037 static int intel_pmu_bts_config(struct perf_event *event) 4038 { 4039 struct perf_event_attr *attr = &event->attr; 4040 4041 if (unlikely(intel_pmu_has_bts(event))) { 4042 /* BTS is not supported by this architecture. */ 4043 if (!x86_pmu.bts_active) 4044 return -EOPNOTSUPP; 4045 4046 /* BTS is currently only allowed for user-mode. */ 4047 if (!attr->exclude_kernel) 4048 return -EOPNOTSUPP; 4049 4050 /* BTS is not allowed for precise events. */ 4051 if (attr->precise_ip) 4052 return -EOPNOTSUPP; 4053 4054 /* disallow bts if conflicting events are present */ 4055 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 4056 return -EBUSY; 4057 4058 event->destroy = hw_perf_lbr_event_destroy; 4059 } 4060 4061 return 0; 4062 } 4063 4064 static int core_pmu_hw_config(struct perf_event *event) 4065 { 4066 int ret = x86_pmu_hw_config(event); 4067 4068 if (ret) 4069 return ret; 4070 4071 return intel_pmu_bts_config(event); 4072 } 4073 4074 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 4075 ((x86_pmu.num_topdown_events - 1) << 8)) 4076 4077 static bool is_available_metric_event(struct perf_event *event) 4078 { 4079 return is_metric_event(event) && 4080 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 4081 } 4082 4083 static inline bool is_mem_loads_event(struct perf_event *event) 4084 { 4085 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 4086 } 4087 4088 static inline bool is_mem_loads_aux_event(struct perf_event *event) 4089 { 4090 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 4091 } 4092 4093 static inline bool require_mem_loads_aux_event(struct perf_event *event) 4094 { 4095 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) 4096 return false; 4097 4098 if (is_hybrid()) 4099 return hybrid_pmu(event->pmu)->pmu_type == hybrid_big; 4100 4101 return true; 4102 } 4103 4104 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) 4105 { 4106 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); 4107 4108 return test_bit(idx, (unsigned long *)&intel_cap->capabilities); 4109 } 4110 4111 static u64 intel_pmu_freq_start_period(struct perf_event *event) 4112 { 4113 int type = event->attr.type; 4114 u64 config, factor; 4115 s64 start; 4116 4117 /* 4118 * The 127 is the lowest possible recommended SAV (sample after value) 4119 * for a 4000 freq (default freq), according to the event list JSON file. 4120 * Also, assume the workload is idle 50% time. 4121 */ 4122 factor = 64 * 4000; 4123 if (type != PERF_TYPE_HARDWARE && type != PERF_TYPE_HW_CACHE) 4124 goto end; 4125 4126 /* 4127 * The estimation of the start period in the freq mode is 4128 * based on the below assumption. 4129 * 4130 * For a cycles or an instructions event, 1GHZ of the 4131 * underlying platform, 1 IPC. The workload is idle 50% time. 4132 * The start period = 1,000,000,000 * 1 / freq / 2. 4133 * = 500,000,000 / freq 4134 * 4135 * Usually, the branch-related events occur less than the 4136 * instructions event. According to the Intel event list JSON 4137 * file, the SAV (sample after value) of a branch-related event 4138 * is usually 1/4 of an instruction event. 4139 * The start period of branch-related events = 125,000,000 / freq. 4140 * 4141 * The cache-related events occurs even less. The SAV is usually 4142 * 1/20 of an instruction event. 4143 * The start period of cache-related events = 25,000,000 / freq. 4144 */ 4145 config = event->attr.config & PERF_HW_EVENT_MASK; 4146 if (type == PERF_TYPE_HARDWARE) { 4147 switch (config) { 4148 case PERF_COUNT_HW_CPU_CYCLES: 4149 case PERF_COUNT_HW_INSTRUCTIONS: 4150 case PERF_COUNT_HW_BUS_CYCLES: 4151 case PERF_COUNT_HW_STALLED_CYCLES_FRONTEND: 4152 case PERF_COUNT_HW_STALLED_CYCLES_BACKEND: 4153 case PERF_COUNT_HW_REF_CPU_CYCLES: 4154 factor = 500000000; 4155 break; 4156 case PERF_COUNT_HW_BRANCH_INSTRUCTIONS: 4157 case PERF_COUNT_HW_BRANCH_MISSES: 4158 factor = 125000000; 4159 break; 4160 case PERF_COUNT_HW_CACHE_REFERENCES: 4161 case PERF_COUNT_HW_CACHE_MISSES: 4162 factor = 25000000; 4163 break; 4164 default: 4165 goto end; 4166 } 4167 } 4168 4169 if (type == PERF_TYPE_HW_CACHE) 4170 factor = 25000000; 4171 end: 4172 /* 4173 * Usually, a prime or a number with less factors (close to prime) 4174 * is chosen as an SAV, which makes it less likely that the sampling 4175 * period synchronizes with some periodic event in the workload. 4176 * Minus 1 to make it at least avoiding values near power of twos 4177 * for the default freq. 4178 */ 4179 start = DIV_ROUND_UP_ULL(factor, event->attr.sample_freq) - 1; 4180 4181 if (start > x86_pmu.max_period) 4182 start = x86_pmu.max_period; 4183 4184 if (x86_pmu.limit_period) 4185 x86_pmu.limit_period(event, &start); 4186 4187 return start; 4188 } 4189 4190 static inline bool intel_pmu_has_acr(struct pmu *pmu) 4191 { 4192 return !!hybrid(pmu, acr_cause_mask64); 4193 } 4194 4195 static bool intel_pmu_is_acr_group(struct perf_event *event) 4196 { 4197 /* The group leader has the ACR flag set */ 4198 if (is_acr_event_group(event)) 4199 return true; 4200 4201 /* The acr_mask is set */ 4202 if (event->attr.config2) 4203 return true; 4204 4205 return false; 4206 } 4207 4208 static inline void intel_pmu_set_acr_cntr_constr(struct perf_event *event, 4209 u64 *cause_mask, int *num) 4210 { 4211 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cntr_mask64); 4212 *cause_mask |= event->attr.config2; 4213 *num += 1; 4214 } 4215 4216 static inline void intel_pmu_set_acr_caused_constr(struct perf_event *event, 4217 int idx, u64 cause_mask) 4218 { 4219 if (test_bit(idx, (unsigned long *)&cause_mask)) 4220 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cause_mask64); 4221 } 4222 4223 static int intel_pmu_hw_config(struct perf_event *event) 4224 { 4225 int ret = x86_pmu_hw_config(event); 4226 4227 if (ret) 4228 return ret; 4229 4230 ret = intel_pmu_bts_config(event); 4231 if (ret) 4232 return ret; 4233 4234 if (event->attr.freq && event->attr.sample_freq) { 4235 event->hw.sample_period = intel_pmu_freq_start_period(event); 4236 event->hw.last_period = event->hw.sample_period; 4237 local64_set(&event->hw.period_left, event->hw.sample_period); 4238 } 4239 4240 if (event->attr.precise_ip) { 4241 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) 4242 return -EINVAL; 4243 4244 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 4245 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 4246 if (!(event->attr.sample_type & ~intel_pmu_large_pebs_flags(event)) && 4247 !has_aux_action(event)) { 4248 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 4249 event->attach_state |= PERF_ATTACH_SCHED_CB; 4250 } 4251 } 4252 if (x86_pmu.pebs_aliases) 4253 x86_pmu.pebs_aliases(event); 4254 } 4255 4256 if (needs_branch_stack(event)) { 4257 /* Avoid branch stack setup for counting events in SAMPLE READ */ 4258 if (is_sampling_event(event) || 4259 !(event->attr.sample_type & PERF_SAMPLE_READ)) 4260 event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK; 4261 } 4262 4263 if (branch_sample_counters(event)) { 4264 struct perf_event *leader, *sibling; 4265 int num = 0; 4266 4267 if (!(x86_pmu.flags & PMU_FL_BR_CNTR) || 4268 (event->attr.config & ~INTEL_ARCH_EVENT_MASK)) 4269 return -EINVAL; 4270 4271 /* 4272 * The branch counter logging is not supported in the call stack 4273 * mode yet, since we cannot simply flush the LBR during e.g., 4274 * multiplexing. Also, there is no obvious usage with the call 4275 * stack mode. Simply forbids it for now. 4276 * 4277 * If any events in the group enable the branch counter logging 4278 * feature, the group is treated as a branch counter logging 4279 * group, which requires the extra space to store the counters. 4280 */ 4281 leader = event->group_leader; 4282 if (branch_sample_call_stack(leader)) 4283 return -EINVAL; 4284 if (branch_sample_counters(leader)) { 4285 num++; 4286 leader->hw.dyn_constraint &= x86_pmu.lbr_counters; 4287 } 4288 leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS; 4289 4290 for_each_sibling_event(sibling, leader) { 4291 if (branch_sample_call_stack(sibling)) 4292 return -EINVAL; 4293 if (branch_sample_counters(sibling)) { 4294 num++; 4295 sibling->hw.dyn_constraint &= x86_pmu.lbr_counters; 4296 } 4297 } 4298 4299 if (num > fls(x86_pmu.lbr_counters)) 4300 return -EINVAL; 4301 /* 4302 * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't 4303 * require any branch stack setup. 4304 * Clear the bit to avoid unnecessary branch stack setup. 4305 */ 4306 if (0 == (event->attr.branch_sample_type & 4307 ~(PERF_SAMPLE_BRANCH_PLM_ALL | 4308 PERF_SAMPLE_BRANCH_COUNTERS))) 4309 event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK; 4310 4311 /* 4312 * Force the leader to be a LBR event. So LBRs can be reset 4313 * with the leader event. See intel_pmu_lbr_del() for details. 4314 */ 4315 if (!intel_pmu_needs_branch_stack(leader)) 4316 return -EINVAL; 4317 } 4318 4319 if (intel_pmu_needs_branch_stack(event)) { 4320 ret = intel_pmu_setup_lbr_filter(event); 4321 if (ret) 4322 return ret; 4323 event->attach_state |= PERF_ATTACH_SCHED_CB; 4324 4325 /* 4326 * BTS is set up earlier in this path, so don't account twice 4327 */ 4328 if (!unlikely(intel_pmu_has_bts(event))) { 4329 /* disallow lbr if conflicting events are present */ 4330 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 4331 return -EBUSY; 4332 4333 event->destroy = hw_perf_lbr_event_destroy; 4334 } 4335 } 4336 4337 if (event->attr.aux_output) { 4338 if (!event->attr.precise_ip) 4339 return -EINVAL; 4340 4341 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 4342 } 4343 4344 if ((event->attr.sample_type & PERF_SAMPLE_READ) && 4345 (x86_pmu.intel_cap.pebs_format >= 6) && 4346 x86_pmu.intel_cap.pebs_baseline && 4347 is_sampling_event(event) && 4348 event->attr.precise_ip) 4349 event->group_leader->hw.flags |= PERF_X86_EVENT_PEBS_CNTR; 4350 4351 if (intel_pmu_has_acr(event->pmu) && intel_pmu_is_acr_group(event)) { 4352 struct perf_event *sibling, *leader = event->group_leader; 4353 struct pmu *pmu = event->pmu; 4354 bool has_sw_event = false; 4355 int num = 0, idx = 0; 4356 u64 cause_mask = 0; 4357 4358 /* Not support perf metrics */ 4359 if (is_metric_event(event)) 4360 return -EINVAL; 4361 4362 /* Not support freq mode */ 4363 if (event->attr.freq) 4364 return -EINVAL; 4365 4366 /* PDist is not supported */ 4367 if (event->attr.config2 && event->attr.precise_ip > 2) 4368 return -EINVAL; 4369 4370 /* The reload value cannot exceeds the max period */ 4371 if (event->attr.sample_period > x86_pmu.max_period) 4372 return -EINVAL; 4373 /* 4374 * The counter-constraints of each event cannot be finalized 4375 * unless the whole group is scanned. However, it's hard 4376 * to know whether the event is the last one of the group. 4377 * Recalculate the counter-constraints for each event when 4378 * adding a new event. 4379 * 4380 * The group is traversed twice, which may be optimized later. 4381 * In the first round, 4382 * - Find all events which do reload when other events 4383 * overflow and set the corresponding counter-constraints 4384 * - Add all events, which can cause other events reload, 4385 * in the cause_mask 4386 * - Error out if the number of events exceeds the HW limit 4387 * - The ACR events must be contiguous. 4388 * Error out if there are non-X86 events between ACR events. 4389 * This is not a HW limit, but a SW limit. 4390 * With the assumption, the intel_pmu_acr_late_setup() can 4391 * easily convert the event idx to counter idx without 4392 * traversing the whole event list. 4393 */ 4394 if (!is_x86_event(leader)) 4395 return -EINVAL; 4396 4397 if (leader->attr.config2) 4398 intel_pmu_set_acr_cntr_constr(leader, &cause_mask, &num); 4399 4400 if (leader->nr_siblings) { 4401 for_each_sibling_event(sibling, leader) { 4402 if (!is_x86_event(sibling)) { 4403 has_sw_event = true; 4404 continue; 4405 } 4406 if (!sibling->attr.config2) 4407 continue; 4408 if (has_sw_event) 4409 return -EINVAL; 4410 intel_pmu_set_acr_cntr_constr(sibling, &cause_mask, &num); 4411 } 4412 } 4413 if (leader != event && event->attr.config2) { 4414 if (has_sw_event) 4415 return -EINVAL; 4416 intel_pmu_set_acr_cntr_constr(event, &cause_mask, &num); 4417 } 4418 4419 if (hweight64(cause_mask) > hweight64(hybrid(pmu, acr_cause_mask64)) || 4420 num > hweight64(hybrid(event->pmu, acr_cntr_mask64))) 4421 return -EINVAL; 4422 /* 4423 * In the second round, apply the counter-constraints for 4424 * the events which can cause other events reload. 4425 */ 4426 intel_pmu_set_acr_caused_constr(leader, idx++, cause_mask); 4427 4428 if (leader->nr_siblings) { 4429 for_each_sibling_event(sibling, leader) 4430 intel_pmu_set_acr_caused_constr(sibling, idx++, cause_mask); 4431 } 4432 4433 if (leader != event) 4434 intel_pmu_set_acr_caused_constr(event, idx, cause_mask); 4435 4436 leader->hw.flags |= PERF_X86_EVENT_ACR; 4437 } 4438 4439 if ((event->attr.type == PERF_TYPE_HARDWARE) || 4440 (event->attr.type == PERF_TYPE_HW_CACHE)) 4441 return 0; 4442 4443 /* 4444 * Config Topdown slots and metric events 4445 * 4446 * The slots event on Fixed Counter 3 can support sampling, 4447 * which will be handled normally in x86_perf_event_update(). 4448 * 4449 * Metric events don't support sampling and require being paired 4450 * with a slots event as group leader. When the slots event 4451 * is used in a metrics group, it too cannot support sampling. 4452 */ 4453 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { 4454 /* The metrics_clear can only be set for the slots event */ 4455 if (event->attr.config1 && 4456 (!is_slots_event(event) || (event->attr.config1 & ~INTEL_TD_CFG_METRIC_CLEAR))) 4457 return -EINVAL; 4458 4459 if (event->attr.config2) 4460 return -EINVAL; 4461 4462 /* 4463 * The TopDown metrics events and slots event don't 4464 * support any filters. 4465 */ 4466 if (event->attr.config & X86_ALL_EVENT_FLAGS) 4467 return -EINVAL; 4468 4469 if (is_available_metric_event(event)) { 4470 struct perf_event *leader = event->group_leader; 4471 4472 /* The metric events don't support sampling. */ 4473 if (is_sampling_event(event)) 4474 return -EINVAL; 4475 4476 /* The metric events require a slots group leader. */ 4477 if (!is_slots_event(leader)) 4478 return -EINVAL; 4479 4480 /* 4481 * The leader/SLOTS must not be a sampling event for 4482 * metric use; hardware requires it starts at 0 when used 4483 * in conjunction with MSR_PERF_METRICS. 4484 */ 4485 if (is_sampling_event(leader)) 4486 return -EINVAL; 4487 4488 event->event_caps |= PERF_EV_CAP_SIBLING; 4489 /* 4490 * Only once we have a METRICs sibling do we 4491 * need TopDown magic. 4492 */ 4493 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 4494 event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 4495 } 4496 } 4497 4498 /* 4499 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 4500 * doesn't function quite right. As a work-around it needs to always be 4501 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 4502 * The actual count of this second event is irrelevant it just needs 4503 * to be active to make the first event function correctly. 4504 * 4505 * In a group, the auxiliary event must be in front of the load latency 4506 * event. The rule is to simplify the implementation of the check. 4507 * That's because perf cannot have a complete group at the moment. 4508 */ 4509 if (require_mem_loads_aux_event(event) && 4510 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 4511 is_mem_loads_event(event)) { 4512 struct perf_event *leader = event->group_leader; 4513 struct perf_event *sibling = NULL; 4514 4515 /* 4516 * When this memload event is also the first event (no group 4517 * exists yet), then there is no aux event before it. 4518 */ 4519 if (leader == event) 4520 return -ENODATA; 4521 4522 if (!is_mem_loads_aux_event(leader)) { 4523 for_each_sibling_event(sibling, leader) { 4524 if (is_mem_loads_aux_event(sibling)) 4525 break; 4526 } 4527 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 4528 return -ENODATA; 4529 } 4530 } 4531 4532 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 4533 return 0; 4534 4535 if (x86_pmu.version < 3) 4536 return -EINVAL; 4537 4538 ret = perf_allow_cpu(); 4539 if (ret) 4540 return ret; 4541 4542 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 4543 4544 return 0; 4545 } 4546 4547 /* 4548 * Currently, the only caller of this function is the atomic_switch_perf_msrs(). 4549 * The host perf context helps to prepare the values of the real hardware for 4550 * a set of msrs that need to be switched atomically in a vmx transaction. 4551 * 4552 * For example, the pseudocode needed to add a new msr should look like: 4553 * 4554 * arr[(*nr)++] = (struct perf_guest_switch_msr){ 4555 * .msr = the hardware msr address, 4556 * .host = the value the hardware has when it doesn't run a guest, 4557 * .guest = the value the hardware has when it runs a guest, 4558 * }; 4559 * 4560 * These values have nothing to do with the emulated values the guest sees 4561 * when it uses {RD,WR}MSR, which should be handled by the KVM context, 4562 * specifically in the intel_pmu_{get,set}_msr(). 4563 */ 4564 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) 4565 { 4566 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4567 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4568 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data; 4569 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 4570 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; 4571 int global_ctrl, pebs_enable; 4572 4573 /* 4574 * In addition to obeying exclude_guest/exclude_host, remove bits being 4575 * used for PEBS when running a guest, because PEBS writes to virtual 4576 * addresses (not physical addresses). 4577 */ 4578 *nr = 0; 4579 global_ctrl = (*nr)++; 4580 arr[global_ctrl] = (struct perf_guest_switch_msr){ 4581 .msr = MSR_CORE_PERF_GLOBAL_CTRL, 4582 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask, 4583 .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask, 4584 }; 4585 4586 if (!x86_pmu.ds_pebs) 4587 return arr; 4588 4589 /* 4590 * If PMU counter has PEBS enabled it is not enough to 4591 * disable counter on a guest entry since PEBS memory 4592 * write can overshoot guest entry and corrupt guest 4593 * memory. Disabling PEBS solves the problem. 4594 * 4595 * Don't do this if the CPU already enforces it. 4596 */ 4597 if (x86_pmu.pebs_no_isolation) { 4598 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4599 .msr = MSR_IA32_PEBS_ENABLE, 4600 .host = cpuc->pebs_enabled, 4601 .guest = 0, 4602 }; 4603 return arr; 4604 } 4605 4606 if (!kvm_pmu || !x86_pmu.pebs_ept) 4607 return arr; 4608 4609 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4610 .msr = MSR_IA32_DS_AREA, 4611 .host = (unsigned long)cpuc->ds, 4612 .guest = kvm_pmu->ds_area, 4613 }; 4614 4615 if (x86_pmu.intel_cap.pebs_baseline) { 4616 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4617 .msr = MSR_PEBS_DATA_CFG, 4618 .host = cpuc->active_pebs_data_cfg, 4619 .guest = kvm_pmu->pebs_data_cfg, 4620 }; 4621 } 4622 4623 pebs_enable = (*nr)++; 4624 arr[pebs_enable] = (struct perf_guest_switch_msr){ 4625 .msr = MSR_IA32_PEBS_ENABLE, 4626 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask, 4627 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask & kvm_pmu->pebs_enable, 4628 }; 4629 4630 if (arr[pebs_enable].host) { 4631 /* Disable guest PEBS if host PEBS is enabled. */ 4632 arr[pebs_enable].guest = 0; 4633 } else { 4634 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */ 4635 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask; 4636 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask; 4637 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ 4638 arr[global_ctrl].guest |= arr[pebs_enable].guest; 4639 } 4640 4641 return arr; 4642 } 4643 4644 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data) 4645 { 4646 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4647 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4648 int idx; 4649 4650 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { 4651 struct perf_event *event = cpuc->events[idx]; 4652 4653 arr[idx].msr = x86_pmu_config_addr(idx); 4654 arr[idx].host = arr[idx].guest = 0; 4655 4656 if (!test_bit(idx, cpuc->active_mask)) 4657 continue; 4658 4659 arr[idx].host = arr[idx].guest = 4660 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 4661 4662 if (event->attr.exclude_host) 4663 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4664 else if (event->attr.exclude_guest) 4665 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4666 } 4667 4668 *nr = x86_pmu_max_num_counters(cpuc->pmu); 4669 return arr; 4670 } 4671 4672 static void core_pmu_enable_event(struct perf_event *event) 4673 { 4674 if (!event->attr.exclude_host) 4675 x86_pmu_enable_event(event); 4676 } 4677 4678 static void core_pmu_enable_all(int added) 4679 { 4680 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4681 int idx; 4682 4683 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { 4684 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 4685 4686 if (!test_bit(idx, cpuc->active_mask) || 4687 cpuc->events[idx]->attr.exclude_host) 4688 continue; 4689 4690 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 4691 } 4692 } 4693 4694 static int hsw_hw_config(struct perf_event *event) 4695 { 4696 int ret = intel_pmu_hw_config(event); 4697 4698 if (ret) 4699 return ret; 4700 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 4701 return 0; 4702 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 4703 4704 /* 4705 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 4706 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 4707 * this combination. 4708 */ 4709 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 4710 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 4711 event->attr.precise_ip > 0)) 4712 return -EOPNOTSUPP; 4713 4714 if (event_is_checkpointed(event)) { 4715 /* 4716 * Sampling of checkpointed events can cause situations where 4717 * the CPU constantly aborts because of a overflow, which is 4718 * then checkpointed back and ignored. Forbid checkpointing 4719 * for sampling. 4720 * 4721 * But still allow a long sampling period, so that perf stat 4722 * from KVM works. 4723 */ 4724 if (event->attr.sample_period > 0 && 4725 event->attr.sample_period < 0x7fffffff) 4726 return -EOPNOTSUPP; 4727 } 4728 return 0; 4729 } 4730 4731 static struct event_constraint counter0_constraint = 4732 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 4733 4734 static struct event_constraint counter1_constraint = 4735 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2); 4736 4737 static struct event_constraint counter0_1_constraint = 4738 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3); 4739 4740 static struct event_constraint counter2_constraint = 4741 EVENT_CONSTRAINT(0, 0x4, 0); 4742 4743 static struct event_constraint fixed0_constraint = 4744 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 4745 4746 static struct event_constraint fixed0_counter0_constraint = 4747 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 4748 4749 static struct event_constraint fixed0_counter0_1_constraint = 4750 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL); 4751 4752 static struct event_constraint counters_1_7_constraint = 4753 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL); 4754 4755 static struct event_constraint * 4756 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4757 struct perf_event *event) 4758 { 4759 struct event_constraint *c; 4760 4761 c = intel_get_event_constraints(cpuc, idx, event); 4762 4763 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 4764 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 4765 if (c->idxmsk64 & (1U << 2)) 4766 return &counter2_constraint; 4767 return &emptyconstraint; 4768 } 4769 4770 return c; 4771 } 4772 4773 static struct event_constraint * 4774 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4775 struct perf_event *event) 4776 { 4777 /* 4778 * Fixed counter 0 has less skid. 4779 * Force instruction:ppp in Fixed counter 0 4780 */ 4781 if ((event->attr.precise_ip == 3) && 4782 constraint_match(&fixed0_constraint, event->hw.config)) 4783 return &fixed0_constraint; 4784 4785 return hsw_get_event_constraints(cpuc, idx, event); 4786 } 4787 4788 static struct event_constraint * 4789 glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4790 struct perf_event *event) 4791 { 4792 struct event_constraint *c; 4793 4794 c = icl_get_event_constraints(cpuc, idx, event); 4795 4796 /* 4797 * The :ppp indicates the Precise Distribution (PDist) facility, which 4798 * is only supported on the GP counter 0. If a :ppp event which is not 4799 * available on the GP counter 0, error out. 4800 * Exception: Instruction PDIR is only available on the fixed counter 0. 4801 */ 4802 if ((event->attr.precise_ip == 3) && 4803 !constraint_match(&fixed0_constraint, event->hw.config)) { 4804 if (c->idxmsk64 & BIT_ULL(0)) 4805 return &counter0_constraint; 4806 4807 return &emptyconstraint; 4808 } 4809 4810 return c; 4811 } 4812 4813 static struct event_constraint * 4814 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4815 struct perf_event *event) 4816 { 4817 struct event_constraint *c; 4818 4819 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 4820 if (event->attr.precise_ip == 3) 4821 return &counter0_constraint; 4822 4823 c = intel_get_event_constraints(cpuc, idx, event); 4824 4825 return c; 4826 } 4827 4828 static struct event_constraint * 4829 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4830 struct perf_event *event) 4831 { 4832 struct event_constraint *c; 4833 4834 c = intel_get_event_constraints(cpuc, idx, event); 4835 4836 /* 4837 * :ppp means to do reduced skid PEBS, 4838 * which is available on PMC0 and fixed counter 0. 4839 */ 4840 if (event->attr.precise_ip == 3) { 4841 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 4842 if (constraint_match(&fixed0_constraint, event->hw.config)) 4843 return &fixed0_counter0_constraint; 4844 4845 return &counter0_constraint; 4846 } 4847 4848 return c; 4849 } 4850 4851 static bool allow_tsx_force_abort = true; 4852 4853 static struct event_constraint * 4854 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4855 struct perf_event *event) 4856 { 4857 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 4858 4859 /* 4860 * Without TFA we must not use PMC3. 4861 */ 4862 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 4863 c = dyn_constraint(cpuc, c, idx); 4864 c->idxmsk64 &= ~(1ULL << 3); 4865 c->weight--; 4866 } 4867 4868 return c; 4869 } 4870 4871 static struct event_constraint * 4872 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4873 struct perf_event *event) 4874 { 4875 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4876 4877 if (pmu->pmu_type == hybrid_big) 4878 return glc_get_event_constraints(cpuc, idx, event); 4879 else if (pmu->pmu_type == hybrid_small) 4880 return tnt_get_event_constraints(cpuc, idx, event); 4881 4882 WARN_ON(1); 4883 return &emptyconstraint; 4884 } 4885 4886 static struct event_constraint * 4887 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4888 struct perf_event *event) 4889 { 4890 struct event_constraint *c; 4891 4892 c = intel_get_event_constraints(cpuc, idx, event); 4893 4894 /* 4895 * The :ppp indicates the Precise Distribution (PDist) facility, which 4896 * is only supported on the GP counter 0 & 1 and Fixed counter 0. 4897 * If a :ppp event which is not available on the above eligible counters, 4898 * error out. 4899 */ 4900 if (event->attr.precise_ip == 3) { 4901 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */ 4902 if (constraint_match(&fixed0_constraint, event->hw.config)) { 4903 /* The fixed counter 0 doesn't support LBR event logging. */ 4904 if (branch_sample_counters(event)) 4905 return &counter0_1_constraint; 4906 else 4907 return &fixed0_counter0_1_constraint; 4908 } 4909 4910 switch (c->idxmsk64 & 0x3ull) { 4911 case 0x1: 4912 return &counter0_constraint; 4913 case 0x2: 4914 return &counter1_constraint; 4915 case 0x3: 4916 return &counter0_1_constraint; 4917 } 4918 return &emptyconstraint; 4919 } 4920 4921 return c; 4922 } 4923 4924 static struct event_constraint * 4925 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4926 struct perf_event *event) 4927 { 4928 struct event_constraint *c; 4929 4930 c = glc_get_event_constraints(cpuc, idx, event); 4931 4932 /* The Retire Latency is not supported by the fixed counter 0. */ 4933 if (event->attr.precise_ip && 4934 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) && 4935 constraint_match(&fixed0_constraint, event->hw.config)) { 4936 /* 4937 * The Instruction PDIR is only available 4938 * on the fixed counter 0. Error out for this case. 4939 */ 4940 if (event->attr.precise_ip == 3) 4941 return &emptyconstraint; 4942 return &counters_1_7_constraint; 4943 } 4944 4945 return c; 4946 } 4947 4948 static struct event_constraint * 4949 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4950 struct perf_event *event) 4951 { 4952 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4953 4954 if (pmu->pmu_type == hybrid_big) 4955 return rwc_get_event_constraints(cpuc, idx, event); 4956 if (pmu->pmu_type == hybrid_small) 4957 return cmt_get_event_constraints(cpuc, idx, event); 4958 4959 WARN_ON(1); 4960 return &emptyconstraint; 4961 } 4962 4963 static int adl_hw_config(struct perf_event *event) 4964 { 4965 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4966 4967 if (pmu->pmu_type == hybrid_big) 4968 return hsw_hw_config(event); 4969 else if (pmu->pmu_type == hybrid_small) 4970 return intel_pmu_hw_config(event); 4971 4972 WARN_ON(1); 4973 return -EOPNOTSUPP; 4974 } 4975 4976 static enum intel_cpu_type adl_get_hybrid_cpu_type(void) 4977 { 4978 return INTEL_CPU_TYPE_CORE; 4979 } 4980 4981 static inline bool erratum_hsw11(struct perf_event *event) 4982 { 4983 return (event->hw.config & INTEL_ARCH_EVENT_MASK) == 4984 X86_CONFIG(.event=0xc0, .umask=0x01); 4985 } 4986 4987 static struct event_constraint * 4988 arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4989 struct perf_event *event) 4990 { 4991 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4992 4993 if (pmu->pmu_type == hybrid_tiny) 4994 return cmt_get_event_constraints(cpuc, idx, event); 4995 4996 return mtl_get_event_constraints(cpuc, idx, event); 4997 } 4998 4999 static int arl_h_hw_config(struct perf_event *event) 5000 { 5001 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5002 5003 if (pmu->pmu_type == hybrid_tiny) 5004 return intel_pmu_hw_config(event); 5005 5006 return adl_hw_config(event); 5007 } 5008 5009 /* 5010 * The HSW11 requires a period larger than 100 which is the same as the BDM11. 5011 * A minimum period of 128 is enforced as well for the INST_RETIRED.ALL. 5012 * 5013 * The message 'interrupt took too long' can be observed on any counter which 5014 * was armed with a period < 32 and two events expired in the same NMI. 5015 * A minimum period of 32 is enforced for the rest of the events. 5016 */ 5017 static void hsw_limit_period(struct perf_event *event, s64 *left) 5018 { 5019 *left = max(*left, erratum_hsw11(event) ? 128 : 32); 5020 } 5021 5022 /* 5023 * Broadwell: 5024 * 5025 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 5026 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 5027 * the two to enforce a minimum period of 128 (the smallest value that has bits 5028 * 0-5 cleared and >= 100). 5029 * 5030 * Because of how the code in x86_perf_event_set_period() works, the truncation 5031 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 5032 * to make up for the 'lost' events due to carrying the 'error' in period_left. 5033 * 5034 * Therefore the effective (average) period matches the requested period, 5035 * despite coarser hardware granularity. 5036 */ 5037 static void bdw_limit_period(struct perf_event *event, s64 *left) 5038 { 5039 if (erratum_hsw11(event)) { 5040 if (*left < 128) 5041 *left = 128; 5042 *left &= ~0x3fULL; 5043 } 5044 } 5045 5046 static void nhm_limit_period(struct perf_event *event, s64 *left) 5047 { 5048 *left = max(*left, 32LL); 5049 } 5050 5051 static void glc_limit_period(struct perf_event *event, s64 *left) 5052 { 5053 if (event->attr.precise_ip == 3) 5054 *left = max(*left, 128LL); 5055 } 5056 5057 PMU_FORMAT_ATTR(event, "config:0-7" ); 5058 PMU_FORMAT_ATTR(umask, "config:8-15" ); 5059 PMU_FORMAT_ATTR(edge, "config:18" ); 5060 PMU_FORMAT_ATTR(pc, "config:19" ); 5061 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 5062 PMU_FORMAT_ATTR(inv, "config:23" ); 5063 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 5064 PMU_FORMAT_ATTR(in_tx, "config:32" ); 5065 PMU_FORMAT_ATTR(in_tx_cp, "config:33" ); 5066 PMU_FORMAT_ATTR(eq, "config:36" ); /* v6 + */ 5067 5068 PMU_FORMAT_ATTR(metrics_clear, "config1:0"); /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */ 5069 5070 static ssize_t umask2_show(struct device *dev, 5071 struct device_attribute *attr, 5072 char *page) 5073 { 5074 u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2; 5075 5076 if (mask == ARCH_PERFMON_EVENTSEL_UMASK2) 5077 return sprintf(page, "config:8-15,40-47\n"); 5078 5079 /* Roll back to the old format if umask2 is not supported. */ 5080 return sprintf(page, "config:8-15\n"); 5081 } 5082 5083 static struct device_attribute format_attr_umask2 = 5084 __ATTR(umask, 0444, umask2_show, NULL); 5085 5086 static struct attribute *format_evtsel_ext_attrs[] = { 5087 &format_attr_umask2.attr, 5088 &format_attr_eq.attr, 5089 &format_attr_metrics_clear.attr, 5090 NULL 5091 }; 5092 5093 static umode_t 5094 evtsel_ext_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5095 { 5096 struct device *dev = kobj_to_dev(kobj); 5097 u64 mask; 5098 5099 /* 5100 * The umask and umask2 have different formats but share the 5101 * same attr name. In update mode, the previous value of the 5102 * umask is unconditionally removed before is_visible. If 5103 * umask2 format is not enumerated, it's impossible to roll 5104 * back to the old format. 5105 * Does the check in umask2_show rather than is_visible. 5106 */ 5107 if (i == 0) 5108 return attr->mode; 5109 5110 mask = hybrid(dev_get_drvdata(dev), config_mask); 5111 if (i == 1) 5112 return (mask & ARCH_PERFMON_EVENTSEL_EQ) ? attr->mode : 0; 5113 5114 /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */ 5115 if (i == 2) { 5116 union perf_capabilities intel_cap = hybrid(dev_get_drvdata(dev), intel_cap); 5117 5118 return intel_cap.rdpmc_metrics_clear ? attr->mode : 0; 5119 } 5120 5121 return 0; 5122 } 5123 5124 static struct attribute *intel_arch_formats_attr[] = { 5125 &format_attr_event.attr, 5126 &format_attr_umask.attr, 5127 &format_attr_edge.attr, 5128 &format_attr_pc.attr, 5129 &format_attr_inv.attr, 5130 &format_attr_cmask.attr, 5131 NULL, 5132 }; 5133 5134 ssize_t intel_event_sysfs_show(char *page, u64 config) 5135 { 5136 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 5137 5138 return x86_event_sysfs_show(page, config, event); 5139 } 5140 5141 static struct intel_shared_regs *allocate_shared_regs(int cpu) 5142 { 5143 struct intel_shared_regs *regs; 5144 int i; 5145 5146 regs = kzalloc_node(sizeof(struct intel_shared_regs), 5147 GFP_KERNEL, cpu_to_node(cpu)); 5148 if (regs) { 5149 /* 5150 * initialize the locks to keep lockdep happy 5151 */ 5152 for (i = 0; i < EXTRA_REG_MAX; i++) 5153 raw_spin_lock_init(®s->regs[i].lock); 5154 5155 regs->core_id = -1; 5156 } 5157 return regs; 5158 } 5159 5160 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 5161 { 5162 struct intel_excl_cntrs *c; 5163 5164 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 5165 GFP_KERNEL, cpu_to_node(cpu)); 5166 if (c) { 5167 raw_spin_lock_init(&c->lock); 5168 c->core_id = -1; 5169 } 5170 return c; 5171 } 5172 5173 5174 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 5175 { 5176 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 5177 5178 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 5179 cpuc->shared_regs = allocate_shared_regs(cpu); 5180 if (!cpuc->shared_regs) 5181 goto err; 5182 } 5183 5184 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_DYN_CONSTRAINT)) { 5185 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 5186 5187 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 5188 if (!cpuc->constraint_list) 5189 goto err_shared_regs; 5190 } 5191 5192 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 5193 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 5194 if (!cpuc->excl_cntrs) 5195 goto err_constraint_list; 5196 5197 cpuc->excl_thread_id = 0; 5198 } 5199 5200 return 0; 5201 5202 err_constraint_list: 5203 kfree(cpuc->constraint_list); 5204 cpuc->constraint_list = NULL; 5205 5206 err_shared_regs: 5207 kfree(cpuc->shared_regs); 5208 cpuc->shared_regs = NULL; 5209 5210 err: 5211 return -ENOMEM; 5212 } 5213 5214 static int intel_pmu_cpu_prepare(int cpu) 5215 { 5216 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 5217 } 5218 5219 static void flip_smm_bit(void *data) 5220 { 5221 unsigned long set = *(unsigned long *)data; 5222 5223 if (set > 0) { 5224 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 5225 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 5226 } else { 5227 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 5228 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 5229 } 5230 } 5231 5232 static void intel_pmu_check_counters_mask(u64 *cntr_mask, 5233 u64 *fixed_cntr_mask, 5234 u64 *intel_ctrl) 5235 { 5236 unsigned int bit; 5237 5238 bit = fls64(*cntr_mask); 5239 if (bit > INTEL_PMC_MAX_GENERIC) { 5240 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5241 bit, INTEL_PMC_MAX_GENERIC); 5242 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); 5243 } 5244 *intel_ctrl = *cntr_mask; 5245 5246 bit = fls64(*fixed_cntr_mask); 5247 if (bit > INTEL_PMC_MAX_FIXED) { 5248 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5249 bit, INTEL_PMC_MAX_FIXED); 5250 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0); 5251 } 5252 5253 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED; 5254 } 5255 5256 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 5257 u64 cntr_mask, 5258 u64 fixed_cntr_mask, 5259 u64 intel_ctrl); 5260 5261 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs); 5262 5263 static inline bool intel_pmu_broken_perf_cap(void) 5264 { 5265 /* The Perf Metric (Bit 15) is always cleared */ 5266 if (boot_cpu_data.x86_vfm == INTEL_METEORLAKE || 5267 boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L) 5268 return true; 5269 5270 return false; 5271 } 5272 5273 static void update_pmu_cap(struct pmu *pmu) 5274 { 5275 unsigned int cntr, fixed_cntr, ecx, edx; 5276 union cpuid35_eax eax; 5277 union cpuid35_ebx ebx; 5278 5279 cpuid(ARCH_PERFMON_EXT_LEAF, &eax.full, &ebx.full, &ecx, &edx); 5280 5281 if (ebx.split.umask2) 5282 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_UMASK2; 5283 if (ebx.split.eq) 5284 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_EQ; 5285 5286 if (eax.split.cntr_subleaf) { 5287 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF, 5288 &cntr, &fixed_cntr, &ecx, &edx); 5289 hybrid(pmu, cntr_mask64) = cntr; 5290 hybrid(pmu, fixed_cntr_mask64) = fixed_cntr; 5291 } 5292 5293 if (eax.split.acr_subleaf) { 5294 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_ACR_LEAF, 5295 &cntr, &fixed_cntr, &ecx, &edx); 5296 /* The mask of the counters which can be reloaded */ 5297 hybrid(pmu, acr_cntr_mask64) = cntr | ((u64)fixed_cntr << INTEL_PMC_IDX_FIXED); 5298 5299 /* The mask of the counters which can cause a reload of reloadable counters */ 5300 hybrid(pmu, acr_cause_mask64) = ecx | ((u64)edx << INTEL_PMC_IDX_FIXED); 5301 } 5302 5303 if (!intel_pmu_broken_perf_cap()) { 5304 /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */ 5305 rdmsrq(MSR_IA32_PERF_CAPABILITIES, hybrid(pmu, intel_cap).capabilities); 5306 } 5307 } 5308 5309 static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu) 5310 { 5311 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64, 5312 &pmu->intel_ctrl); 5313 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 5314 pmu->unconstrained = (struct event_constraint) 5315 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 5316 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 5317 5318 if (pmu->intel_cap.perf_metrics) 5319 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 5320 else 5321 pmu->intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 5322 5323 intel_pmu_check_event_constraints(pmu->event_constraints, 5324 pmu->cntr_mask64, 5325 pmu->fixed_cntr_mask64, 5326 pmu->intel_ctrl); 5327 5328 intel_pmu_check_extra_regs(pmu->extra_regs); 5329 } 5330 5331 static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void) 5332 { 5333 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 5334 enum intel_cpu_type cpu_type = c->topo.intel_type; 5335 int i; 5336 5337 /* 5338 * This is running on a CPU model that is known to have hybrid 5339 * configurations. But the CPU told us it is not hybrid, shame 5340 * on it. There should be a fixup function provided for these 5341 * troublesome CPUs (->get_hybrid_cpu_type). 5342 */ 5343 if (cpu_type == INTEL_CPU_TYPE_UNKNOWN) { 5344 if (x86_pmu.get_hybrid_cpu_type) 5345 cpu_type = x86_pmu.get_hybrid_cpu_type(); 5346 else 5347 return NULL; 5348 } 5349 5350 /* 5351 * This essentially just maps between the 'hybrid_cpu_type' 5352 * and 'hybrid_pmu_type' enums except for ARL-H processor 5353 * which needs to compare atom uarch native id since ARL-H 5354 * contains two different atom uarchs. 5355 */ 5356 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 5357 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type; 5358 u32 native_id; 5359 5360 if (cpu_type == INTEL_CPU_TYPE_CORE && pmu_type == hybrid_big) 5361 return &x86_pmu.hybrid_pmu[i]; 5362 if (cpu_type == INTEL_CPU_TYPE_ATOM) { 5363 if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small) 5364 return &x86_pmu.hybrid_pmu[i]; 5365 5366 native_id = c->topo.intel_native_model_id; 5367 if (native_id == INTEL_ATOM_SKT_NATIVE_ID && pmu_type == hybrid_small) 5368 return &x86_pmu.hybrid_pmu[i]; 5369 if (native_id == INTEL_ATOM_CMT_NATIVE_ID && pmu_type == hybrid_tiny) 5370 return &x86_pmu.hybrid_pmu[i]; 5371 } 5372 } 5373 5374 return NULL; 5375 } 5376 5377 static bool init_hybrid_pmu(int cpu) 5378 { 5379 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 5380 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu(); 5381 5382 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { 5383 cpuc->pmu = NULL; 5384 return false; 5385 } 5386 5387 /* Only check and dump the PMU information for the first CPU */ 5388 if (!cpumask_empty(&pmu->supported_cpus)) 5389 goto end; 5390 5391 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) 5392 update_pmu_cap(&pmu->pmu); 5393 5394 intel_pmu_check_hybrid_pmus(pmu); 5395 5396 if (!check_hw_exists(&pmu->pmu, pmu->cntr_mask, pmu->fixed_cntr_mask)) 5397 return false; 5398 5399 pr_info("%s PMU driver: ", pmu->name); 5400 5401 pr_cont("\n"); 5402 5403 x86_pmu_show_pmu_cap(&pmu->pmu); 5404 5405 end: 5406 cpumask_set_cpu(cpu, &pmu->supported_cpus); 5407 cpuc->pmu = &pmu->pmu; 5408 5409 return true; 5410 } 5411 5412 static void intel_pmu_cpu_starting(int cpu) 5413 { 5414 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 5415 int core_id = topology_core_id(cpu); 5416 int i; 5417 5418 if (is_hybrid() && !init_hybrid_pmu(cpu)) 5419 return; 5420 5421 init_debug_store_on_cpu(cpu); 5422 /* 5423 * Deal with CPUs that don't clear their LBRs on power-up, and that may 5424 * even boot with LBRs enabled. 5425 */ 5426 if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr) 5427 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT); 5428 intel_pmu_lbr_reset(); 5429 5430 cpuc->lbr_sel = NULL; 5431 5432 if (x86_pmu.flags & PMU_FL_TFA) { 5433 WARN_ON_ONCE(cpuc->tfa_shadow); 5434 cpuc->tfa_shadow = ~0ULL; 5435 intel_set_tfa(cpuc, false); 5436 } 5437 5438 if (x86_pmu.version > 1) 5439 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 5440 5441 /* 5442 * Disable perf metrics if any added CPU doesn't support it. 5443 * 5444 * Turn off the check for a hybrid architecture, because the 5445 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate 5446 * the architecture features. The perf metrics is a model-specific 5447 * feature for now. The corresponding bit should always be 0 on 5448 * a hybrid platform, e.g., Alder Lake. 5449 */ 5450 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 5451 union perf_capabilities perf_cap; 5452 5453 rdmsrq(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 5454 if (!perf_cap.perf_metrics) { 5455 x86_pmu.intel_cap.perf_metrics = 0; 5456 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 5457 } 5458 } 5459 5460 if (!cpuc->shared_regs) 5461 return; 5462 5463 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 5464 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 5465 struct intel_shared_regs *pc; 5466 5467 pc = per_cpu(cpu_hw_events, i).shared_regs; 5468 if (pc && pc->core_id == core_id) { 5469 cpuc->kfree_on_online[0] = cpuc->shared_regs; 5470 cpuc->shared_regs = pc; 5471 break; 5472 } 5473 } 5474 cpuc->shared_regs->core_id = core_id; 5475 cpuc->shared_regs->refcnt++; 5476 } 5477 5478 if (x86_pmu.lbr_sel_map) 5479 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 5480 5481 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 5482 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 5483 struct cpu_hw_events *sibling; 5484 struct intel_excl_cntrs *c; 5485 5486 sibling = &per_cpu(cpu_hw_events, i); 5487 c = sibling->excl_cntrs; 5488 if (c && c->core_id == core_id) { 5489 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 5490 cpuc->excl_cntrs = c; 5491 if (!sibling->excl_thread_id) 5492 cpuc->excl_thread_id = 1; 5493 break; 5494 } 5495 } 5496 cpuc->excl_cntrs->core_id = core_id; 5497 cpuc->excl_cntrs->refcnt++; 5498 } 5499 } 5500 5501 static void free_excl_cntrs(struct cpu_hw_events *cpuc) 5502 { 5503 struct intel_excl_cntrs *c; 5504 5505 c = cpuc->excl_cntrs; 5506 if (c) { 5507 if (c->core_id == -1 || --c->refcnt == 0) 5508 kfree(c); 5509 cpuc->excl_cntrs = NULL; 5510 } 5511 5512 kfree(cpuc->constraint_list); 5513 cpuc->constraint_list = NULL; 5514 } 5515 5516 static void intel_pmu_cpu_dying(int cpu) 5517 { 5518 fini_debug_store_on_cpu(cpu); 5519 } 5520 5521 void intel_cpuc_finish(struct cpu_hw_events *cpuc) 5522 { 5523 struct intel_shared_regs *pc; 5524 5525 pc = cpuc->shared_regs; 5526 if (pc) { 5527 if (pc->core_id == -1 || --pc->refcnt == 0) 5528 kfree(pc); 5529 cpuc->shared_regs = NULL; 5530 } 5531 5532 free_excl_cntrs(cpuc); 5533 } 5534 5535 static void intel_pmu_cpu_dead(int cpu) 5536 { 5537 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 5538 5539 intel_cpuc_finish(cpuc); 5540 5541 if (is_hybrid() && cpuc->pmu) 5542 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); 5543 } 5544 5545 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, 5546 struct task_struct *task, bool sched_in) 5547 { 5548 intel_pmu_pebs_sched_task(pmu_ctx, sched_in); 5549 intel_pmu_lbr_sched_task(pmu_ctx, task, sched_in); 5550 } 5551 5552 static int intel_pmu_check_period(struct perf_event *event, u64 value) 5553 { 5554 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 5555 } 5556 5557 static void intel_aux_output_init(void) 5558 { 5559 /* Refer also intel_pmu_aux_output_match() */ 5560 if (x86_pmu.intel_cap.pebs_output_pt_available) 5561 x86_pmu.assign = intel_pmu_assign_event; 5562 } 5563 5564 static int intel_pmu_aux_output_match(struct perf_event *event) 5565 { 5566 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */ 5567 if (!x86_pmu.intel_cap.pebs_output_pt_available) 5568 return 0; 5569 5570 return is_intel_pt_event(event); 5571 } 5572 5573 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret) 5574 { 5575 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu); 5576 5577 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus); 5578 } 5579 5580 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 5581 5582 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 5583 5584 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 5585 5586 PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63"); 5587 5588 static struct attribute *intel_arch3_formats_attr[] = { 5589 &format_attr_event.attr, 5590 &format_attr_umask.attr, 5591 &format_attr_edge.attr, 5592 &format_attr_pc.attr, 5593 &format_attr_any.attr, 5594 &format_attr_inv.attr, 5595 &format_attr_cmask.attr, 5596 NULL, 5597 }; 5598 5599 static struct attribute *hsw_format_attr[] = { 5600 &format_attr_in_tx.attr, 5601 &format_attr_in_tx_cp.attr, 5602 &format_attr_offcore_rsp.attr, 5603 &format_attr_ldlat.attr, 5604 NULL 5605 }; 5606 5607 static struct attribute *nhm_format_attr[] = { 5608 &format_attr_offcore_rsp.attr, 5609 &format_attr_ldlat.attr, 5610 NULL 5611 }; 5612 5613 static struct attribute *slm_format_attr[] = { 5614 &format_attr_offcore_rsp.attr, 5615 NULL 5616 }; 5617 5618 static struct attribute *cmt_format_attr[] = { 5619 &format_attr_offcore_rsp.attr, 5620 &format_attr_ldlat.attr, 5621 &format_attr_snoop_rsp.attr, 5622 NULL 5623 }; 5624 5625 static struct attribute *skl_format_attr[] = { 5626 &format_attr_frontend.attr, 5627 NULL, 5628 }; 5629 5630 static __initconst const struct x86_pmu core_pmu = { 5631 .name = "core", 5632 .handle_irq = x86_pmu_handle_irq, 5633 .disable_all = x86_pmu_disable_all, 5634 .enable_all = core_pmu_enable_all, 5635 .enable = core_pmu_enable_event, 5636 .disable = x86_pmu_disable_event, 5637 .hw_config = core_pmu_hw_config, 5638 .schedule_events = x86_schedule_events, 5639 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 5640 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 5641 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0, 5642 .event_map = intel_pmu_event_map, 5643 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 5644 .apic = 1, 5645 .large_pebs_flags = LARGE_PEBS_FLAGS, 5646 5647 /* 5648 * Intel PMCs cannot be accessed sanely above 32-bit width, 5649 * so we install an artificial 1<<31 period regardless of 5650 * the generic event period: 5651 */ 5652 .max_period = (1ULL<<31) - 1, 5653 .get_event_constraints = intel_get_event_constraints, 5654 .put_event_constraints = intel_put_event_constraints, 5655 .event_constraints = intel_core_event_constraints, 5656 .guest_get_msrs = core_guest_get_msrs, 5657 .format_attrs = intel_arch_formats_attr, 5658 .events_sysfs_show = intel_event_sysfs_show, 5659 5660 /* 5661 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 5662 * together with PMU version 1 and thus be using core_pmu with 5663 * shared_regs. We need following callbacks here to allocate 5664 * it properly. 5665 */ 5666 .cpu_prepare = intel_pmu_cpu_prepare, 5667 .cpu_starting = intel_pmu_cpu_starting, 5668 .cpu_dying = intel_pmu_cpu_dying, 5669 .cpu_dead = intel_pmu_cpu_dead, 5670 5671 .check_period = intel_pmu_check_period, 5672 5673 .lbr_reset = intel_pmu_lbr_reset_64, 5674 .lbr_read = intel_pmu_lbr_read_64, 5675 .lbr_save = intel_pmu_lbr_save, 5676 .lbr_restore = intel_pmu_lbr_restore, 5677 }; 5678 5679 static __initconst const struct x86_pmu intel_pmu = { 5680 .name = "Intel", 5681 .handle_irq = intel_pmu_handle_irq, 5682 .disable_all = intel_pmu_disable_all, 5683 .enable_all = intel_pmu_enable_all, 5684 .enable = intel_pmu_enable_event, 5685 .disable = intel_pmu_disable_event, 5686 .add = intel_pmu_add_event, 5687 .del = intel_pmu_del_event, 5688 .read = intel_pmu_read_event, 5689 .set_period = intel_pmu_set_period, 5690 .update = intel_pmu_update, 5691 .hw_config = intel_pmu_hw_config, 5692 .schedule_events = x86_schedule_events, 5693 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 5694 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 5695 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0, 5696 .event_map = intel_pmu_event_map, 5697 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 5698 .apic = 1, 5699 .large_pebs_flags = LARGE_PEBS_FLAGS, 5700 /* 5701 * Intel PMCs cannot be accessed sanely above 32 bit width, 5702 * so we install an artificial 1<<31 period regardless of 5703 * the generic event period: 5704 */ 5705 .max_period = (1ULL << 31) - 1, 5706 .get_event_constraints = intel_get_event_constraints, 5707 .put_event_constraints = intel_put_event_constraints, 5708 .pebs_aliases = intel_pebs_aliases_core2, 5709 5710 .format_attrs = intel_arch3_formats_attr, 5711 .events_sysfs_show = intel_event_sysfs_show, 5712 5713 .cpu_prepare = intel_pmu_cpu_prepare, 5714 .cpu_starting = intel_pmu_cpu_starting, 5715 .cpu_dying = intel_pmu_cpu_dying, 5716 .cpu_dead = intel_pmu_cpu_dead, 5717 5718 .guest_get_msrs = intel_guest_get_msrs, 5719 .sched_task = intel_pmu_sched_task, 5720 5721 .check_period = intel_pmu_check_period, 5722 5723 .aux_output_match = intel_pmu_aux_output_match, 5724 5725 .lbr_reset = intel_pmu_lbr_reset_64, 5726 .lbr_read = intel_pmu_lbr_read_64, 5727 .lbr_save = intel_pmu_lbr_save, 5728 .lbr_restore = intel_pmu_lbr_restore, 5729 5730 /* 5731 * SMM has access to all 4 rings and while traditionally SMM code only 5732 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM. 5733 * 5734 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction 5735 * between SMM or not, this results in what should be pure userspace 5736 * counters including SMM data. 5737 * 5738 * This is a clear privilege issue, therefore globally disable 5739 * counting SMM by default. 5740 */ 5741 .attr_freeze_on_smi = 1, 5742 }; 5743 5744 static __init void intel_clovertown_quirk(void) 5745 { 5746 /* 5747 * PEBS is unreliable due to: 5748 * 5749 * AJ67 - PEBS may experience CPL leaks 5750 * AJ68 - PEBS PMI may be delayed by one event 5751 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 5752 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 5753 * 5754 * AJ67 could be worked around by restricting the OS/USR flags. 5755 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 5756 * 5757 * AJ106 could possibly be worked around by not allowing LBR 5758 * usage from PEBS, including the fixup. 5759 * AJ68 could possibly be worked around by always programming 5760 * a pebs_event_reset[0] value and coping with the lost events. 5761 * 5762 * But taken together it might just make sense to not enable PEBS on 5763 * these chips. 5764 */ 5765 pr_warn("PEBS disabled due to CPU errata\n"); 5766 x86_pmu.ds_pebs = 0; 5767 x86_pmu.pebs_constraints = NULL; 5768 } 5769 5770 static const struct x86_cpu_id isolation_ucodes[] = { 5771 X86_MATCH_VFM_STEPS(INTEL_HASWELL, 3, 3, 0x0000001f), 5772 X86_MATCH_VFM_STEPS(INTEL_HASWELL_L, 1, 1, 0x0000001e), 5773 X86_MATCH_VFM_STEPS(INTEL_HASWELL_G, 1, 1, 0x00000015), 5774 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 2, 2, 0x00000037), 5775 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 4, 4, 0x0000000a), 5776 X86_MATCH_VFM_STEPS(INTEL_BROADWELL, 4, 4, 0x00000023), 5777 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_G, 1, 1, 0x00000014), 5778 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 2, 2, 0x00000010), 5779 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 3, 3, 0x07000009), 5780 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 4, 4, 0x0f000009), 5781 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 5, 5, 0x0e000002), 5782 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_X, 1, 1, 0x0b000014), 5783 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 3, 3, 0x00000021), 5784 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 4, 7, 0x00000000), 5785 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 11, 11, 0x00000000), 5786 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_L, 3, 3, 0x0000007c), 5787 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE, 3, 3, 0x0000007c), 5788 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE, 9, 13, 0x0000004e), 5789 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE_L, 9, 12, 0x0000004e), 5790 {} 5791 }; 5792 5793 static void intel_check_pebs_isolation(void) 5794 { 5795 x86_pmu.pebs_no_isolation = !x86_match_min_microcode_rev(isolation_ucodes); 5796 } 5797 5798 static __init void intel_pebs_isolation_quirk(void) 5799 { 5800 WARN_ON_ONCE(x86_pmu.check_microcode); 5801 x86_pmu.check_microcode = intel_check_pebs_isolation; 5802 intel_check_pebs_isolation(); 5803 } 5804 5805 static const struct x86_cpu_id pebs_ucodes[] = { 5806 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE, 7, 7, 0x00000028), 5807 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 6, 6, 0x00000618), 5808 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 7, 7, 0x0000070c), 5809 {} 5810 }; 5811 5812 static bool intel_snb_pebs_broken(void) 5813 { 5814 return !x86_match_min_microcode_rev(pebs_ucodes); 5815 } 5816 5817 static void intel_snb_check_microcode(void) 5818 { 5819 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 5820 return; 5821 5822 /* 5823 * Serialized by the microcode lock.. 5824 */ 5825 if (x86_pmu.pebs_broken) { 5826 pr_info("PEBS enabled due to microcode update\n"); 5827 x86_pmu.pebs_broken = 0; 5828 } else { 5829 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 5830 x86_pmu.pebs_broken = 1; 5831 } 5832 } 5833 5834 static bool is_lbr_from(unsigned long msr) 5835 { 5836 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 5837 5838 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 5839 } 5840 5841 /* 5842 * Under certain circumstances, access certain MSR may cause #GP. 5843 * The function tests if the input MSR can be safely accessed. 5844 */ 5845 static bool check_msr(unsigned long msr, u64 mask) 5846 { 5847 u64 val_old, val_new, val_tmp; 5848 5849 /* 5850 * Disable the check for real HW, so we don't 5851 * mess with potentially enabled registers: 5852 */ 5853 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 5854 return true; 5855 5856 /* 5857 * Read the current value, change it and read it back to see if it 5858 * matches, this is needed to detect certain hardware emulators 5859 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 5860 */ 5861 if (rdmsrq_safe(msr, &val_old)) 5862 return false; 5863 5864 /* 5865 * Only change the bits which can be updated by wrmsrq. 5866 */ 5867 val_tmp = val_old ^ mask; 5868 5869 if (is_lbr_from(msr)) 5870 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 5871 5872 if (wrmsrq_safe(msr, val_tmp) || 5873 rdmsrq_safe(msr, &val_new)) 5874 return false; 5875 5876 /* 5877 * Quirk only affects validation in wrmsr(), so wrmsrq()'s value 5878 * should equal rdmsrq()'s even with the quirk. 5879 */ 5880 if (val_new != val_tmp) 5881 return false; 5882 5883 if (is_lbr_from(msr)) 5884 val_old = lbr_from_signext_quirk_wr(val_old); 5885 5886 /* Here it's sure that the MSR can be safely accessed. 5887 * Restore the old value and return. 5888 */ 5889 wrmsrq(msr, val_old); 5890 5891 return true; 5892 } 5893 5894 static __init void intel_sandybridge_quirk(void) 5895 { 5896 x86_pmu.check_microcode = intel_snb_check_microcode; 5897 cpus_read_lock(); 5898 intel_snb_check_microcode(); 5899 cpus_read_unlock(); 5900 } 5901 5902 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 5903 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 5904 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 5905 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 5906 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 5907 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 5908 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 5909 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 5910 }; 5911 5912 static __init void intel_arch_events_quirk(void) 5913 { 5914 int bit; 5915 5916 /* disable event that reported as not present by cpuid */ 5917 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 5918 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 5919 pr_warn("CPUID marked event: \'%s\' unavailable\n", 5920 intel_arch_events_map[bit].name); 5921 } 5922 } 5923 5924 static __init void intel_nehalem_quirk(void) 5925 { 5926 union cpuid10_ebx ebx; 5927 5928 ebx.full = x86_pmu.events_maskl; 5929 if (ebx.split.no_branch_misses_retired) { 5930 /* 5931 * Erratum AAJ80 detected, we work it around by using 5932 * the BR_MISP_EXEC.ANY event. This will over-count 5933 * branch-misses, but it's still much better than the 5934 * architectural event which is often completely bogus: 5935 */ 5936 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 5937 ebx.split.no_branch_misses_retired = 0; 5938 x86_pmu.events_maskl = ebx.full; 5939 pr_info("CPU erratum AAJ80 worked around\n"); 5940 } 5941 } 5942 5943 /* 5944 * enable software workaround for errata: 5945 * SNB: BJ122 5946 * IVB: BV98 5947 * HSW: HSD29 5948 * 5949 * Only needed when HT is enabled. However detecting 5950 * if HT is enabled is difficult (model specific). So instead, 5951 * we enable the workaround in the early boot, and verify if 5952 * it is needed in a later initcall phase once we have valid 5953 * topology information to check if HT is actually enabled 5954 */ 5955 static __init void intel_ht_bug(void) 5956 { 5957 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 5958 5959 x86_pmu.start_scheduling = intel_start_scheduling; 5960 x86_pmu.commit_scheduling = intel_commit_scheduling; 5961 x86_pmu.stop_scheduling = intel_stop_scheduling; 5962 } 5963 5964 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 5965 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 5966 5967 /* Haswell special events */ 5968 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 5969 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 5970 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 5971 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 5972 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 5973 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 5974 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 5975 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 5976 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 5977 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 5978 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 5979 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 5980 5981 static struct attribute *hsw_events_attrs[] = { 5982 EVENT_PTR(td_slots_issued), 5983 EVENT_PTR(td_slots_retired), 5984 EVENT_PTR(td_fetch_bubbles), 5985 EVENT_PTR(td_total_slots), 5986 EVENT_PTR(td_total_slots_scale), 5987 EVENT_PTR(td_recovery_bubbles), 5988 EVENT_PTR(td_recovery_bubbles_scale), 5989 NULL 5990 }; 5991 5992 static struct attribute *hsw_mem_events_attrs[] = { 5993 EVENT_PTR(mem_ld_hsw), 5994 EVENT_PTR(mem_st_hsw), 5995 NULL, 5996 }; 5997 5998 static struct attribute *hsw_tsx_events_attrs[] = { 5999 EVENT_PTR(tx_start), 6000 EVENT_PTR(tx_commit), 6001 EVENT_PTR(tx_abort), 6002 EVENT_PTR(tx_capacity), 6003 EVENT_PTR(tx_conflict), 6004 EVENT_PTR(el_start), 6005 EVENT_PTR(el_commit), 6006 EVENT_PTR(el_abort), 6007 EVENT_PTR(el_capacity), 6008 EVENT_PTR(el_conflict), 6009 EVENT_PTR(cycles_t), 6010 EVENT_PTR(cycles_ct), 6011 NULL 6012 }; 6013 6014 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 6015 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 6016 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 6017 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 6018 6019 static struct attribute *icl_events_attrs[] = { 6020 EVENT_PTR(mem_ld_hsw), 6021 EVENT_PTR(mem_st_hsw), 6022 NULL, 6023 }; 6024 6025 static struct attribute *icl_td_events_attrs[] = { 6026 EVENT_PTR(slots), 6027 EVENT_PTR(td_retiring), 6028 EVENT_PTR(td_bad_spec), 6029 EVENT_PTR(td_fe_bound), 6030 EVENT_PTR(td_be_bound), 6031 NULL, 6032 }; 6033 6034 static struct attribute *icl_tsx_events_attrs[] = { 6035 EVENT_PTR(tx_start), 6036 EVENT_PTR(tx_abort), 6037 EVENT_PTR(tx_commit), 6038 EVENT_PTR(tx_capacity_read), 6039 EVENT_PTR(tx_capacity_write), 6040 EVENT_PTR(tx_conflict), 6041 EVENT_PTR(el_start), 6042 EVENT_PTR(el_abort), 6043 EVENT_PTR(el_commit), 6044 EVENT_PTR(el_capacity_read), 6045 EVENT_PTR(el_capacity_write), 6046 EVENT_PTR(el_conflict), 6047 EVENT_PTR(cycles_t), 6048 EVENT_PTR(cycles_ct), 6049 NULL, 6050 }; 6051 6052 6053 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 6054 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 6055 6056 static struct attribute *glc_events_attrs[] = { 6057 EVENT_PTR(mem_ld_hsw), 6058 EVENT_PTR(mem_st_spr), 6059 EVENT_PTR(mem_ld_aux), 6060 NULL, 6061 }; 6062 6063 static struct attribute *glc_td_events_attrs[] = { 6064 EVENT_PTR(slots), 6065 EVENT_PTR(td_retiring), 6066 EVENT_PTR(td_bad_spec), 6067 EVENT_PTR(td_fe_bound), 6068 EVENT_PTR(td_be_bound), 6069 EVENT_PTR(td_heavy_ops), 6070 EVENT_PTR(td_br_mispredict), 6071 EVENT_PTR(td_fetch_lat), 6072 EVENT_PTR(td_mem_bound), 6073 NULL, 6074 }; 6075 6076 static struct attribute *glc_tsx_events_attrs[] = { 6077 EVENT_PTR(tx_start), 6078 EVENT_PTR(tx_abort), 6079 EVENT_PTR(tx_commit), 6080 EVENT_PTR(tx_capacity_read), 6081 EVENT_PTR(tx_capacity_write), 6082 EVENT_PTR(tx_conflict), 6083 EVENT_PTR(cycles_t), 6084 EVENT_PTR(cycles_ct), 6085 NULL, 6086 }; 6087 6088 static ssize_t freeze_on_smi_show(struct device *cdev, 6089 struct device_attribute *attr, 6090 char *buf) 6091 { 6092 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 6093 } 6094 6095 static DEFINE_MUTEX(freeze_on_smi_mutex); 6096 6097 static ssize_t freeze_on_smi_store(struct device *cdev, 6098 struct device_attribute *attr, 6099 const char *buf, size_t count) 6100 { 6101 unsigned long val; 6102 ssize_t ret; 6103 6104 ret = kstrtoul(buf, 0, &val); 6105 if (ret) 6106 return ret; 6107 6108 if (val > 1) 6109 return -EINVAL; 6110 6111 mutex_lock(&freeze_on_smi_mutex); 6112 6113 if (x86_pmu.attr_freeze_on_smi == val) 6114 goto done; 6115 6116 x86_pmu.attr_freeze_on_smi = val; 6117 6118 cpus_read_lock(); 6119 on_each_cpu(flip_smm_bit, &val, 1); 6120 cpus_read_unlock(); 6121 done: 6122 mutex_unlock(&freeze_on_smi_mutex); 6123 6124 return count; 6125 } 6126 6127 static void update_tfa_sched(void *ignored) 6128 { 6129 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 6130 6131 /* 6132 * check if PMC3 is used 6133 * and if so force schedule out for all event types all contexts 6134 */ 6135 if (test_bit(3, cpuc->active_mask)) 6136 perf_pmu_resched(x86_get_pmu(smp_processor_id())); 6137 } 6138 6139 static ssize_t show_sysctl_tfa(struct device *cdev, 6140 struct device_attribute *attr, 6141 char *buf) 6142 { 6143 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 6144 } 6145 6146 static ssize_t set_sysctl_tfa(struct device *cdev, 6147 struct device_attribute *attr, 6148 const char *buf, size_t count) 6149 { 6150 bool val; 6151 ssize_t ret; 6152 6153 ret = kstrtobool(buf, &val); 6154 if (ret) 6155 return ret; 6156 6157 /* no change */ 6158 if (val == allow_tsx_force_abort) 6159 return count; 6160 6161 allow_tsx_force_abort = val; 6162 6163 cpus_read_lock(); 6164 on_each_cpu(update_tfa_sched, NULL, 1); 6165 cpus_read_unlock(); 6166 6167 return count; 6168 } 6169 6170 6171 static DEVICE_ATTR_RW(freeze_on_smi); 6172 6173 static ssize_t branches_show(struct device *cdev, 6174 struct device_attribute *attr, 6175 char *buf) 6176 { 6177 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 6178 } 6179 6180 static DEVICE_ATTR_RO(branches); 6181 6182 static ssize_t branch_counter_nr_show(struct device *cdev, 6183 struct device_attribute *attr, 6184 char *buf) 6185 { 6186 return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_counters)); 6187 } 6188 6189 static DEVICE_ATTR_RO(branch_counter_nr); 6190 6191 static ssize_t branch_counter_width_show(struct device *cdev, 6192 struct device_attribute *attr, 6193 char *buf) 6194 { 6195 return snprintf(buf, PAGE_SIZE, "%d\n", LBR_INFO_BR_CNTR_BITS); 6196 } 6197 6198 static DEVICE_ATTR_RO(branch_counter_width); 6199 6200 static struct attribute *lbr_attrs[] = { 6201 &dev_attr_branches.attr, 6202 &dev_attr_branch_counter_nr.attr, 6203 &dev_attr_branch_counter_width.attr, 6204 NULL 6205 }; 6206 6207 static umode_t 6208 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6209 { 6210 /* branches */ 6211 if (i == 0) 6212 return x86_pmu.lbr_nr ? attr->mode : 0; 6213 6214 return (x86_pmu.flags & PMU_FL_BR_CNTR) ? attr->mode : 0; 6215 } 6216 6217 static char pmu_name_str[30]; 6218 6219 static DEVICE_STRING_ATTR_RO(pmu_name, 0444, pmu_name_str); 6220 6221 static struct attribute *intel_pmu_caps_attrs[] = { 6222 &dev_attr_pmu_name.attr.attr, 6223 NULL 6224 }; 6225 6226 static DEVICE_ATTR(allow_tsx_force_abort, 0644, 6227 show_sysctl_tfa, 6228 set_sysctl_tfa); 6229 6230 static struct attribute *intel_pmu_attrs[] = { 6231 &dev_attr_freeze_on_smi.attr, 6232 &dev_attr_allow_tsx_force_abort.attr, 6233 NULL, 6234 }; 6235 6236 static umode_t 6237 default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6238 { 6239 if (attr == &dev_attr_allow_tsx_force_abort.attr) 6240 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 6241 6242 return attr->mode; 6243 } 6244 6245 static umode_t 6246 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6247 { 6248 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 6249 } 6250 6251 static umode_t 6252 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6253 { 6254 return x86_pmu.ds_pebs ? attr->mode : 0; 6255 } 6256 6257 static umode_t 6258 mem_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6259 { 6260 if (attr == &event_attr_mem_ld_aux.attr.attr) 6261 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0; 6262 6263 return pebs_is_visible(kobj, attr, i); 6264 } 6265 6266 static umode_t 6267 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6268 { 6269 return x86_pmu.version >= 2 ? attr->mode : 0; 6270 } 6271 6272 static umode_t 6273 td_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6274 { 6275 /* 6276 * Hide the perf metrics topdown events 6277 * if the feature is not enumerated. 6278 */ 6279 if (x86_pmu.num_topdown_events) 6280 return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0; 6281 6282 return attr->mode; 6283 } 6284 6285 PMU_FORMAT_ATTR(acr_mask, "config2:0-63"); 6286 6287 static struct attribute *format_acr_attrs[] = { 6288 &format_attr_acr_mask.attr, 6289 NULL 6290 }; 6291 6292 static umode_t 6293 acr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6294 { 6295 struct device *dev = kobj_to_dev(kobj); 6296 6297 return intel_pmu_has_acr(dev_get_drvdata(dev)) ? attr->mode : 0; 6298 } 6299 6300 static struct attribute_group group_events_td = { 6301 .name = "events", 6302 .is_visible = td_is_visible, 6303 }; 6304 6305 static struct attribute_group group_events_mem = { 6306 .name = "events", 6307 .is_visible = mem_is_visible, 6308 }; 6309 6310 static struct attribute_group group_events_tsx = { 6311 .name = "events", 6312 .is_visible = tsx_is_visible, 6313 }; 6314 6315 static struct attribute_group group_caps_gen = { 6316 .name = "caps", 6317 .attrs = intel_pmu_caps_attrs, 6318 }; 6319 6320 static struct attribute_group group_caps_lbr = { 6321 .name = "caps", 6322 .attrs = lbr_attrs, 6323 .is_visible = lbr_is_visible, 6324 }; 6325 6326 static struct attribute_group group_format_extra = { 6327 .name = "format", 6328 .is_visible = exra_is_visible, 6329 }; 6330 6331 static struct attribute_group group_format_extra_skl = { 6332 .name = "format", 6333 .is_visible = exra_is_visible, 6334 }; 6335 6336 static struct attribute_group group_format_evtsel_ext = { 6337 .name = "format", 6338 .attrs = format_evtsel_ext_attrs, 6339 .is_visible = evtsel_ext_is_visible, 6340 }; 6341 6342 static struct attribute_group group_format_acr = { 6343 .name = "format", 6344 .attrs = format_acr_attrs, 6345 .is_visible = acr_is_visible, 6346 }; 6347 6348 static struct attribute_group group_default = { 6349 .attrs = intel_pmu_attrs, 6350 .is_visible = default_is_visible, 6351 }; 6352 6353 static const struct attribute_group *attr_update[] = { 6354 &group_events_td, 6355 &group_events_mem, 6356 &group_events_tsx, 6357 &group_caps_gen, 6358 &group_caps_lbr, 6359 &group_format_extra, 6360 &group_format_extra_skl, 6361 &group_format_evtsel_ext, 6362 &group_format_acr, 6363 &group_default, 6364 NULL, 6365 }; 6366 6367 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); 6368 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); 6369 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); 6370 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); 6371 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); 6372 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); 6373 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); 6374 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); 6375 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); 6376 6377 static struct attribute *adl_hybrid_events_attrs[] = { 6378 EVENT_PTR(slots_adl), 6379 EVENT_PTR(td_retiring_adl), 6380 EVENT_PTR(td_bad_spec_adl), 6381 EVENT_PTR(td_fe_bound_adl), 6382 EVENT_PTR(td_be_bound_adl), 6383 EVENT_PTR(td_heavy_ops_adl), 6384 EVENT_PTR(td_br_mis_adl), 6385 EVENT_PTR(td_fetch_lat_adl), 6386 EVENT_PTR(td_mem_bound_adl), 6387 NULL, 6388 }; 6389 6390 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_lnl, "event=0xc2,umask=0x02;event=0x00,umask=0x80", hybrid_big_small); 6391 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_lnl, "event=0x9c,umask=0x01;event=0x00,umask=0x82", hybrid_big_small); 6392 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_lnl, "event=0xa4,umask=0x02;event=0x00,umask=0x83", hybrid_big_small); 6393 6394 static struct attribute *lnl_hybrid_events_attrs[] = { 6395 EVENT_PTR(slots_adl), 6396 EVENT_PTR(td_retiring_lnl), 6397 EVENT_PTR(td_bad_spec_adl), 6398 EVENT_PTR(td_fe_bound_lnl), 6399 EVENT_PTR(td_be_bound_lnl), 6400 EVENT_PTR(td_heavy_ops_adl), 6401 EVENT_PTR(td_br_mis_adl), 6402 EVENT_PTR(td_fetch_lat_adl), 6403 EVENT_PTR(td_mem_bound_adl), 6404 NULL 6405 }; 6406 6407 /* The event string must be in PMU IDX order. */ 6408 EVENT_ATTR_STR_HYBRID(topdown-retiring, 6409 td_retiring_arl_h, 6410 "event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0", 6411 hybrid_big_small_tiny); 6412 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, 6413 td_bad_spec_arl_h, 6414 "event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0", 6415 hybrid_big_small_tiny); 6416 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, 6417 td_fe_bound_arl_h, 6418 "event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0", 6419 hybrid_big_small_tiny); 6420 EVENT_ATTR_STR_HYBRID(topdown-be-bound, 6421 td_be_bound_arl_h, 6422 "event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0", 6423 hybrid_big_small_tiny); 6424 6425 static struct attribute *arl_h_hybrid_events_attrs[] = { 6426 EVENT_PTR(slots_adl), 6427 EVENT_PTR(td_retiring_arl_h), 6428 EVENT_PTR(td_bad_spec_arl_h), 6429 EVENT_PTR(td_fe_bound_arl_h), 6430 EVENT_PTR(td_be_bound_arl_h), 6431 EVENT_PTR(td_heavy_ops_adl), 6432 EVENT_PTR(td_br_mis_adl), 6433 EVENT_PTR(td_fetch_lat_adl), 6434 EVENT_PTR(td_mem_bound_adl), 6435 NULL, 6436 }; 6437 6438 /* Must be in IDX order */ 6439 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); 6440 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); 6441 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); 6442 6443 static struct attribute *adl_hybrid_mem_attrs[] = { 6444 EVENT_PTR(mem_ld_adl), 6445 EVENT_PTR(mem_st_adl), 6446 EVENT_PTR(mem_ld_aux_adl), 6447 NULL, 6448 }; 6449 6450 static struct attribute *mtl_hybrid_mem_attrs[] = { 6451 EVENT_PTR(mem_ld_adl), 6452 EVENT_PTR(mem_st_adl), 6453 NULL 6454 }; 6455 6456 EVENT_ATTR_STR_HYBRID(mem-loads, 6457 mem_ld_arl_h, 6458 "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3", 6459 hybrid_big_small_tiny); 6460 EVENT_ATTR_STR_HYBRID(mem-stores, 6461 mem_st_arl_h, 6462 "event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6", 6463 hybrid_big_small_tiny); 6464 6465 static struct attribute *arl_h_hybrid_mem_attrs[] = { 6466 EVENT_PTR(mem_ld_arl_h), 6467 EVENT_PTR(mem_st_arl_h), 6468 NULL, 6469 }; 6470 6471 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); 6472 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); 6473 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); 6474 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); 6475 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); 6476 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); 6477 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); 6478 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); 6479 6480 static struct attribute *adl_hybrid_tsx_attrs[] = { 6481 EVENT_PTR(tx_start_adl), 6482 EVENT_PTR(tx_abort_adl), 6483 EVENT_PTR(tx_commit_adl), 6484 EVENT_PTR(tx_capacity_read_adl), 6485 EVENT_PTR(tx_capacity_write_adl), 6486 EVENT_PTR(tx_conflict_adl), 6487 EVENT_PTR(cycles_t_adl), 6488 EVENT_PTR(cycles_ct_adl), 6489 NULL, 6490 }; 6491 6492 FORMAT_ATTR_HYBRID(in_tx, hybrid_big); 6493 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); 6494 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny); 6495 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny); 6496 FORMAT_ATTR_HYBRID(frontend, hybrid_big); 6497 6498 #define ADL_HYBRID_RTM_FORMAT_ATTR \ 6499 FORMAT_HYBRID_PTR(in_tx), \ 6500 FORMAT_HYBRID_PTR(in_tx_cp) 6501 6502 #define ADL_HYBRID_FORMAT_ATTR \ 6503 FORMAT_HYBRID_PTR(offcore_rsp), \ 6504 FORMAT_HYBRID_PTR(ldlat), \ 6505 FORMAT_HYBRID_PTR(frontend) 6506 6507 static struct attribute *adl_hybrid_extra_attr_rtm[] = { 6508 ADL_HYBRID_RTM_FORMAT_ATTR, 6509 ADL_HYBRID_FORMAT_ATTR, 6510 NULL 6511 }; 6512 6513 static struct attribute *adl_hybrid_extra_attr[] = { 6514 ADL_HYBRID_FORMAT_ATTR, 6515 NULL 6516 }; 6517 6518 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_tiny); 6519 6520 static struct attribute *mtl_hybrid_extra_attr_rtm[] = { 6521 ADL_HYBRID_RTM_FORMAT_ATTR, 6522 ADL_HYBRID_FORMAT_ATTR, 6523 FORMAT_HYBRID_PTR(snoop_rsp), 6524 NULL 6525 }; 6526 6527 static struct attribute *mtl_hybrid_extra_attr[] = { 6528 ADL_HYBRID_FORMAT_ATTR, 6529 FORMAT_HYBRID_PTR(snoop_rsp), 6530 NULL 6531 }; 6532 6533 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) 6534 { 6535 struct device *dev = kobj_to_dev(kobj); 6536 struct x86_hybrid_pmu *pmu = 6537 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6538 struct perf_pmu_events_hybrid_attr *pmu_attr = 6539 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); 6540 6541 return pmu->pmu_type & pmu_attr->pmu_type; 6542 } 6543 6544 static umode_t hybrid_events_is_visible(struct kobject *kobj, 6545 struct attribute *attr, int i) 6546 { 6547 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; 6548 } 6549 6550 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) 6551 { 6552 int cpu = cpumask_first(&pmu->supported_cpus); 6553 6554 return (cpu >= nr_cpu_ids) ? -1 : cpu; 6555 } 6556 6557 static umode_t hybrid_tsx_is_visible(struct kobject *kobj, 6558 struct attribute *attr, int i) 6559 { 6560 struct device *dev = kobj_to_dev(kobj); 6561 struct x86_hybrid_pmu *pmu = 6562 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6563 int cpu = hybrid_find_supported_cpu(pmu); 6564 6565 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; 6566 } 6567 6568 static umode_t hybrid_format_is_visible(struct kobject *kobj, 6569 struct attribute *attr, int i) 6570 { 6571 struct device *dev = kobj_to_dev(kobj); 6572 struct x86_hybrid_pmu *pmu = 6573 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6574 struct perf_pmu_format_hybrid_attr *pmu_attr = 6575 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); 6576 int cpu = hybrid_find_supported_cpu(pmu); 6577 6578 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0; 6579 } 6580 6581 static umode_t hybrid_td_is_visible(struct kobject *kobj, 6582 struct attribute *attr, int i) 6583 { 6584 struct device *dev = kobj_to_dev(kobj); 6585 struct x86_hybrid_pmu *pmu = 6586 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6587 6588 if (!is_attr_for_this_pmu(kobj, attr)) 6589 return 0; 6590 6591 6592 /* Only the big core supports perf metrics */ 6593 if (pmu->pmu_type == hybrid_big) 6594 return pmu->intel_cap.perf_metrics ? attr->mode : 0; 6595 6596 return attr->mode; 6597 } 6598 6599 static struct attribute_group hybrid_group_events_td = { 6600 .name = "events", 6601 .is_visible = hybrid_td_is_visible, 6602 }; 6603 6604 static struct attribute_group hybrid_group_events_mem = { 6605 .name = "events", 6606 .is_visible = hybrid_events_is_visible, 6607 }; 6608 6609 static struct attribute_group hybrid_group_events_tsx = { 6610 .name = "events", 6611 .is_visible = hybrid_tsx_is_visible, 6612 }; 6613 6614 static struct attribute_group hybrid_group_format_extra = { 6615 .name = "format", 6616 .is_visible = hybrid_format_is_visible, 6617 }; 6618 6619 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, 6620 struct device_attribute *attr, 6621 char *buf) 6622 { 6623 struct x86_hybrid_pmu *pmu = 6624 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6625 6626 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus); 6627 } 6628 6629 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); 6630 static struct attribute *intel_hybrid_cpus_attrs[] = { 6631 &dev_attr_cpus.attr, 6632 NULL, 6633 }; 6634 6635 static struct attribute_group hybrid_group_cpus = { 6636 .attrs = intel_hybrid_cpus_attrs, 6637 }; 6638 6639 static const struct attribute_group *hybrid_attr_update[] = { 6640 &hybrid_group_events_td, 6641 &hybrid_group_events_mem, 6642 &hybrid_group_events_tsx, 6643 &group_caps_gen, 6644 &group_caps_lbr, 6645 &hybrid_group_format_extra, 6646 &group_format_evtsel_ext, 6647 &group_format_acr, 6648 &group_default, 6649 &hybrid_group_cpus, 6650 NULL, 6651 }; 6652 6653 static struct attribute *empty_attrs; 6654 6655 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 6656 u64 cntr_mask, 6657 u64 fixed_cntr_mask, 6658 u64 intel_ctrl) 6659 { 6660 struct event_constraint *c; 6661 6662 if (!event_constraints) 6663 return; 6664 6665 /* 6666 * event on fixed counter2 (REF_CYCLES) only works on this 6667 * counter, so do not extend mask to generic counters 6668 */ 6669 for_each_event_constraint(c, event_constraints) { 6670 /* 6671 * Don't extend the topdown slots and metrics 6672 * events to the generic counters. 6673 */ 6674 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 6675 /* 6676 * Disable topdown slots and metrics events, 6677 * if slots event is not in CPUID. 6678 */ 6679 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) 6680 c->idxmsk64 = 0; 6681 c->weight = hweight64(c->idxmsk64); 6682 continue; 6683 } 6684 6685 if (c->cmask == FIXED_EVENT_FLAGS) { 6686 /* Disabled fixed counters which are not in CPUID */ 6687 c->idxmsk64 &= intel_ctrl; 6688 6689 /* 6690 * Don't extend the pseudo-encoding to the 6691 * generic counters 6692 */ 6693 if (!use_fixed_pseudo_encoding(c->code)) 6694 c->idxmsk64 |= cntr_mask; 6695 } 6696 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED); 6697 c->weight = hweight64(c->idxmsk64); 6698 } 6699 } 6700 6701 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) 6702 { 6703 struct extra_reg *er; 6704 6705 /* 6706 * Access extra MSR may cause #GP under certain circumstances. 6707 * E.g. KVM doesn't support offcore event 6708 * Check all extra_regs here. 6709 */ 6710 if (!extra_regs) 6711 return; 6712 6713 for (er = extra_regs; er->msr; er++) { 6714 er->extra_msr_access = check_msr(er->msr, 0x11UL); 6715 /* Disable LBR select mapping */ 6716 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 6717 x86_pmu.lbr_sel_map = NULL; 6718 } 6719 } 6720 6721 static inline int intel_pmu_v6_addr_offset(int index, bool eventsel) 6722 { 6723 return MSR_IA32_PMC_V6_STEP * index; 6724 } 6725 6726 static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = { 6727 { hybrid_small, "cpu_atom" }, 6728 { hybrid_big, "cpu_core" }, 6729 { hybrid_tiny, "cpu_lowpower" }, 6730 }; 6731 6732 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus) 6733 { 6734 unsigned long pmus_mask = pmus; 6735 struct x86_hybrid_pmu *pmu; 6736 int idx = 0, bit; 6737 6738 x86_pmu.num_hybrid_pmus = hweight_long(pmus_mask); 6739 x86_pmu.hybrid_pmu = kcalloc(x86_pmu.num_hybrid_pmus, 6740 sizeof(struct x86_hybrid_pmu), 6741 GFP_KERNEL); 6742 if (!x86_pmu.hybrid_pmu) 6743 return -ENOMEM; 6744 6745 static_branch_enable(&perf_is_hybrid); 6746 x86_pmu.filter = intel_pmu_filter; 6747 6748 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) { 6749 pmu = &x86_pmu.hybrid_pmu[idx++]; 6750 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id; 6751 pmu->name = intel_hybrid_pmu_type_map[bit].name; 6752 6753 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 6754 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 6755 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 6756 pmu->config_mask = X86_RAW_EVENT_MASK; 6757 pmu->unconstrained = (struct event_constraint) 6758 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 6759 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 6760 6761 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6762 if (pmu->pmu_type & hybrid_small_tiny) { 6763 pmu->intel_cap.perf_metrics = 0; 6764 pmu->mid_ack = true; 6765 } else if (pmu->pmu_type & hybrid_big) { 6766 pmu->intel_cap.perf_metrics = 1; 6767 pmu->late_ack = true; 6768 } 6769 } 6770 6771 return 0; 6772 } 6773 6774 static __always_inline void intel_pmu_ref_cycles_ext(void) 6775 { 6776 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED))) 6777 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c; 6778 } 6779 6780 static __always_inline void intel_pmu_init_glc(struct pmu *pmu) 6781 { 6782 x86_pmu.late_ack = true; 6783 x86_pmu.limit_period = glc_limit_period; 6784 x86_pmu.pebs_aliases = NULL; 6785 x86_pmu.pebs_prec_dist = true; 6786 x86_pmu.pebs_block = true; 6787 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6788 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6789 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6790 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6791 x86_pmu.lbr_pt_coexist = true; 6792 x86_pmu.num_topdown_events = 8; 6793 static_call_update(intel_pmu_update_topdown_event, 6794 &icl_update_topdown_event); 6795 static_call_update(intel_pmu_set_topdown_event_period, 6796 &icl_set_topdown_event_period); 6797 6798 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6799 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6800 hybrid(pmu, event_constraints) = intel_glc_event_constraints; 6801 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints; 6802 6803 intel_pmu_ref_cycles_ext(); 6804 } 6805 6806 static __always_inline void intel_pmu_init_grt(struct pmu *pmu) 6807 { 6808 x86_pmu.mid_ack = true; 6809 x86_pmu.limit_period = glc_limit_period; 6810 x86_pmu.pebs_aliases = NULL; 6811 x86_pmu.pebs_prec_dist = true; 6812 x86_pmu.pebs_block = true; 6813 x86_pmu.lbr_pt_coexist = true; 6814 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6815 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6816 6817 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6818 memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6819 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6820 hybrid(pmu, event_constraints) = intel_grt_event_constraints; 6821 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints; 6822 hybrid(pmu, extra_regs) = intel_grt_extra_regs; 6823 6824 intel_pmu_ref_cycles_ext(); 6825 } 6826 6827 static __always_inline void intel_pmu_init_lnc(struct pmu *pmu) 6828 { 6829 intel_pmu_init_glc(pmu); 6830 hybrid(pmu, event_constraints) = intel_lnc_event_constraints; 6831 hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints; 6832 hybrid(pmu, extra_regs) = intel_lnc_extra_regs; 6833 } 6834 6835 static __always_inline void intel_pmu_init_skt(struct pmu *pmu) 6836 { 6837 intel_pmu_init_grt(pmu); 6838 hybrid(pmu, event_constraints) = intel_skt_event_constraints; 6839 hybrid(pmu, extra_regs) = intel_cmt_extra_regs; 6840 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); 6841 } 6842 6843 __init int intel_pmu_init(void) 6844 { 6845 struct attribute **extra_skl_attr = &empty_attrs; 6846 struct attribute **extra_attr = &empty_attrs; 6847 struct attribute **td_attr = &empty_attrs; 6848 struct attribute **mem_attr = &empty_attrs; 6849 struct attribute **tsx_attr = &empty_attrs; 6850 union cpuid10_edx edx; 6851 union cpuid10_eax eax; 6852 union cpuid10_ebx ebx; 6853 unsigned int fixed_mask; 6854 bool pmem = false; 6855 int version, i; 6856 char *name; 6857 struct x86_hybrid_pmu *pmu; 6858 6859 /* Architectural Perfmon was introduced starting with Core "Yonah" */ 6860 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 6861 switch (boot_cpu_data.x86) { 6862 case 6: 6863 if (boot_cpu_data.x86_vfm < INTEL_CORE_YONAH) 6864 return p6_pmu_init(); 6865 break; 6866 case 11: 6867 return knc_pmu_init(); 6868 case 15: 6869 return p4_pmu_init(); 6870 } 6871 6872 pr_cont("unsupported CPU family %d model %d ", 6873 boot_cpu_data.x86, boot_cpu_data.x86_model); 6874 return -ENODEV; 6875 } 6876 6877 /* 6878 * Check whether the Architectural PerfMon supports 6879 * Branch Misses Retired hw_event or not. 6880 */ 6881 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); 6882 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 6883 return -ENODEV; 6884 6885 version = eax.split.version_id; 6886 if (version < 2) 6887 x86_pmu = core_pmu; 6888 else 6889 x86_pmu = intel_pmu; 6890 6891 x86_pmu.version = version; 6892 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0); 6893 x86_pmu.cntval_bits = eax.split.bit_width; 6894 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 6895 6896 x86_pmu.events_maskl = ebx.full; 6897 x86_pmu.events_mask_len = eax.split.mask_length; 6898 6899 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64); 6900 x86_pmu.pebs_capable = PEBS_COUNTER_MASK; 6901 x86_pmu.config_mask = X86_RAW_EVENT_MASK; 6902 6903 /* 6904 * Quirk: v2 perfmon does not report fixed-purpose events, so 6905 * assume at least 3 events, when not running in a hypervisor: 6906 */ 6907 if (version > 1 && version < 5) { 6908 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 6909 6910 x86_pmu.fixed_cntr_mask64 = 6911 GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0); 6912 } else if (version >= 5) 6913 x86_pmu.fixed_cntr_mask64 = fixed_mask; 6914 6915 if (boot_cpu_has(X86_FEATURE_PDCM)) { 6916 u64 capabilities; 6917 6918 rdmsrq(MSR_IA32_PERF_CAPABILITIES, capabilities); 6919 x86_pmu.intel_cap.capabilities = capabilities; 6920 } 6921 6922 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 6923 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 6924 x86_pmu.lbr_read = intel_pmu_lbr_read_32; 6925 } 6926 6927 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 6928 intel_pmu_arch_lbr_init(); 6929 6930 intel_pebs_init(); 6931 6932 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 6933 6934 if (version >= 5) { 6935 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 6936 if (x86_pmu.intel_cap.anythread_deprecated) 6937 pr_cont(" AnyThread deprecated, "); 6938 } 6939 6940 /* 6941 * Many features on and after V6 require dynamic constraint, 6942 * e.g., Arch PEBS, ACR. 6943 */ 6944 if (version >= 6) 6945 x86_pmu.flags |= PMU_FL_DYN_CONSTRAINT; 6946 /* 6947 * Install the hw-cache-events table: 6948 */ 6949 switch (boot_cpu_data.x86_vfm) { 6950 case INTEL_CORE_YONAH: 6951 pr_cont("Core events, "); 6952 name = "core"; 6953 break; 6954 6955 case INTEL_CORE2_MEROM: 6956 x86_add_quirk(intel_clovertown_quirk); 6957 fallthrough; 6958 6959 case INTEL_CORE2_MEROM_L: 6960 case INTEL_CORE2_PENRYN: 6961 case INTEL_CORE2_DUNNINGTON: 6962 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 6963 sizeof(hw_cache_event_ids)); 6964 6965 intel_pmu_lbr_init_core(); 6966 6967 x86_pmu.event_constraints = intel_core2_event_constraints; 6968 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 6969 pr_cont("Core2 events, "); 6970 name = "core2"; 6971 break; 6972 6973 case INTEL_NEHALEM: 6974 case INTEL_NEHALEM_EP: 6975 case INTEL_NEHALEM_EX: 6976 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 6977 sizeof(hw_cache_event_ids)); 6978 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 6979 sizeof(hw_cache_extra_regs)); 6980 6981 intel_pmu_lbr_init_nhm(); 6982 6983 x86_pmu.event_constraints = intel_nehalem_event_constraints; 6984 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 6985 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 6986 x86_pmu.extra_regs = intel_nehalem_extra_regs; 6987 x86_pmu.limit_period = nhm_limit_period; 6988 6989 mem_attr = nhm_mem_events_attrs; 6990 6991 /* UOPS_ISSUED.STALLED_CYCLES */ 6992 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6993 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6994 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 6995 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6996 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 6997 6998 intel_pmu_pebs_data_source_nhm(); 6999 x86_add_quirk(intel_nehalem_quirk); 7000 x86_pmu.pebs_no_tlb = 1; 7001 extra_attr = nhm_format_attr; 7002 7003 pr_cont("Nehalem events, "); 7004 name = "nehalem"; 7005 break; 7006 7007 case INTEL_ATOM_BONNELL: 7008 case INTEL_ATOM_BONNELL_MID: 7009 case INTEL_ATOM_SALTWELL: 7010 case INTEL_ATOM_SALTWELL_MID: 7011 case INTEL_ATOM_SALTWELL_TABLET: 7012 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 7013 sizeof(hw_cache_event_ids)); 7014 7015 intel_pmu_lbr_init_atom(); 7016 7017 x86_pmu.event_constraints = intel_gen_event_constraints; 7018 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 7019 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 7020 pr_cont("Atom events, "); 7021 name = "bonnell"; 7022 break; 7023 7024 case INTEL_ATOM_SILVERMONT: 7025 case INTEL_ATOM_SILVERMONT_D: 7026 case INTEL_ATOM_SILVERMONT_MID: 7027 case INTEL_ATOM_AIRMONT: 7028 case INTEL_ATOM_SILVERMONT_MID2: 7029 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 7030 sizeof(hw_cache_event_ids)); 7031 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 7032 sizeof(hw_cache_extra_regs)); 7033 7034 intel_pmu_lbr_init_slm(); 7035 7036 x86_pmu.event_constraints = intel_slm_event_constraints; 7037 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 7038 x86_pmu.extra_regs = intel_slm_extra_regs; 7039 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7040 td_attr = slm_events_attrs; 7041 extra_attr = slm_format_attr; 7042 pr_cont("Silvermont events, "); 7043 name = "silvermont"; 7044 break; 7045 7046 case INTEL_ATOM_GOLDMONT: 7047 case INTEL_ATOM_GOLDMONT_D: 7048 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 7049 sizeof(hw_cache_event_ids)); 7050 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 7051 sizeof(hw_cache_extra_regs)); 7052 7053 intel_pmu_lbr_init_skl(); 7054 7055 x86_pmu.event_constraints = intel_slm_event_constraints; 7056 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 7057 x86_pmu.extra_regs = intel_glm_extra_regs; 7058 /* 7059 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 7060 * for precise cycles. 7061 * :pp is identical to :ppp 7062 */ 7063 x86_pmu.pebs_aliases = NULL; 7064 x86_pmu.pebs_prec_dist = true; 7065 x86_pmu.lbr_pt_coexist = true; 7066 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7067 td_attr = glm_events_attrs; 7068 extra_attr = slm_format_attr; 7069 pr_cont("Goldmont events, "); 7070 name = "goldmont"; 7071 break; 7072 7073 case INTEL_ATOM_GOLDMONT_PLUS: 7074 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 7075 sizeof(hw_cache_event_ids)); 7076 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 7077 sizeof(hw_cache_extra_regs)); 7078 7079 intel_pmu_lbr_init_skl(); 7080 7081 x86_pmu.event_constraints = intel_slm_event_constraints; 7082 x86_pmu.extra_regs = intel_glm_extra_regs; 7083 /* 7084 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 7085 * for precise cycles. 7086 */ 7087 x86_pmu.pebs_aliases = NULL; 7088 x86_pmu.pebs_prec_dist = true; 7089 x86_pmu.lbr_pt_coexist = true; 7090 x86_pmu.pebs_capable = ~0ULL; 7091 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7092 x86_pmu.flags |= PMU_FL_PEBS_ALL; 7093 x86_pmu.get_event_constraints = glp_get_event_constraints; 7094 td_attr = glm_events_attrs; 7095 /* Goldmont Plus has 4-wide pipeline */ 7096 event_attr_td_total_slots_scale_glm.event_str = "4"; 7097 extra_attr = slm_format_attr; 7098 pr_cont("Goldmont plus events, "); 7099 name = "goldmont_plus"; 7100 break; 7101 7102 case INTEL_ATOM_TREMONT_D: 7103 case INTEL_ATOM_TREMONT: 7104 case INTEL_ATOM_TREMONT_L: 7105 x86_pmu.late_ack = true; 7106 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 7107 sizeof(hw_cache_event_ids)); 7108 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 7109 sizeof(hw_cache_extra_regs)); 7110 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 7111 7112 intel_pmu_lbr_init_skl(); 7113 7114 x86_pmu.event_constraints = intel_slm_event_constraints; 7115 x86_pmu.extra_regs = intel_tnt_extra_regs; 7116 /* 7117 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 7118 * for precise cycles. 7119 */ 7120 x86_pmu.pebs_aliases = NULL; 7121 x86_pmu.pebs_prec_dist = true; 7122 x86_pmu.lbr_pt_coexist = true; 7123 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7124 x86_pmu.get_event_constraints = tnt_get_event_constraints; 7125 td_attr = tnt_events_attrs; 7126 extra_attr = slm_format_attr; 7127 pr_cont("Tremont events, "); 7128 name = "Tremont"; 7129 break; 7130 7131 case INTEL_ATOM_GRACEMONT: 7132 intel_pmu_init_grt(NULL); 7133 intel_pmu_pebs_data_source_grt(); 7134 x86_pmu.pebs_latency_data = grt_latency_data; 7135 x86_pmu.get_event_constraints = tnt_get_event_constraints; 7136 td_attr = tnt_events_attrs; 7137 mem_attr = grt_mem_attrs; 7138 extra_attr = nhm_format_attr; 7139 pr_cont("Gracemont events, "); 7140 name = "gracemont"; 7141 break; 7142 7143 case INTEL_ATOM_CRESTMONT: 7144 case INTEL_ATOM_CRESTMONT_X: 7145 intel_pmu_init_grt(NULL); 7146 x86_pmu.extra_regs = intel_cmt_extra_regs; 7147 intel_pmu_pebs_data_source_cmt(); 7148 x86_pmu.pebs_latency_data = cmt_latency_data; 7149 x86_pmu.get_event_constraints = cmt_get_event_constraints; 7150 td_attr = cmt_events_attrs; 7151 mem_attr = grt_mem_attrs; 7152 extra_attr = cmt_format_attr; 7153 pr_cont("Crestmont events, "); 7154 name = "crestmont"; 7155 break; 7156 7157 case INTEL_ATOM_DARKMONT_X: 7158 intel_pmu_init_skt(NULL); 7159 intel_pmu_pebs_data_source_cmt(); 7160 x86_pmu.pebs_latency_data = cmt_latency_data; 7161 x86_pmu.get_event_constraints = cmt_get_event_constraints; 7162 td_attr = skt_events_attrs; 7163 mem_attr = grt_mem_attrs; 7164 extra_attr = cmt_format_attr; 7165 pr_cont("Darkmont events, "); 7166 name = "darkmont"; 7167 break; 7168 7169 case INTEL_WESTMERE: 7170 case INTEL_WESTMERE_EP: 7171 case INTEL_WESTMERE_EX: 7172 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 7173 sizeof(hw_cache_event_ids)); 7174 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 7175 sizeof(hw_cache_extra_regs)); 7176 7177 intel_pmu_lbr_init_nhm(); 7178 7179 x86_pmu.event_constraints = intel_westmere_event_constraints; 7180 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 7181 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 7182 x86_pmu.extra_regs = intel_westmere_extra_regs; 7183 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7184 7185 mem_attr = nhm_mem_events_attrs; 7186 7187 /* UOPS_ISSUED.STALLED_CYCLES */ 7188 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 7189 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 7190 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 7191 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 7192 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 7193 7194 intel_pmu_pebs_data_source_nhm(); 7195 extra_attr = nhm_format_attr; 7196 pr_cont("Westmere events, "); 7197 name = "westmere"; 7198 break; 7199 7200 case INTEL_SANDYBRIDGE: 7201 case INTEL_SANDYBRIDGE_X: 7202 x86_add_quirk(intel_sandybridge_quirk); 7203 x86_add_quirk(intel_ht_bug); 7204 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 7205 sizeof(hw_cache_event_ids)); 7206 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 7207 sizeof(hw_cache_extra_regs)); 7208 7209 intel_pmu_lbr_init_snb(); 7210 7211 x86_pmu.event_constraints = intel_snb_event_constraints; 7212 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 7213 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 7214 if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X) 7215 x86_pmu.extra_regs = intel_snbep_extra_regs; 7216 else 7217 x86_pmu.extra_regs = intel_snb_extra_regs; 7218 7219 7220 /* all extra regs are per-cpu when HT is on */ 7221 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7222 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7223 7224 td_attr = snb_events_attrs; 7225 mem_attr = snb_mem_events_attrs; 7226 7227 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 7228 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 7229 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 7230 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 7231 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 7232 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 7233 7234 extra_attr = nhm_format_attr; 7235 7236 pr_cont("SandyBridge events, "); 7237 name = "sandybridge"; 7238 break; 7239 7240 case INTEL_IVYBRIDGE: 7241 case INTEL_IVYBRIDGE_X: 7242 x86_add_quirk(intel_ht_bug); 7243 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 7244 sizeof(hw_cache_event_ids)); 7245 /* dTLB-load-misses on IVB is different than SNB */ 7246 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 7247 7248 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 7249 sizeof(hw_cache_extra_regs)); 7250 7251 intel_pmu_lbr_init_snb(); 7252 7253 x86_pmu.event_constraints = intel_ivb_event_constraints; 7254 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 7255 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 7256 x86_pmu.pebs_prec_dist = true; 7257 if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X) 7258 x86_pmu.extra_regs = intel_snbep_extra_regs; 7259 else 7260 x86_pmu.extra_regs = intel_snb_extra_regs; 7261 /* all extra regs are per-cpu when HT is on */ 7262 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7263 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7264 7265 td_attr = snb_events_attrs; 7266 mem_attr = snb_mem_events_attrs; 7267 7268 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 7269 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 7270 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 7271 7272 extra_attr = nhm_format_attr; 7273 7274 pr_cont("IvyBridge events, "); 7275 name = "ivybridge"; 7276 break; 7277 7278 7279 case INTEL_HASWELL: 7280 case INTEL_HASWELL_X: 7281 case INTEL_HASWELL_L: 7282 case INTEL_HASWELL_G: 7283 x86_add_quirk(intel_ht_bug); 7284 x86_add_quirk(intel_pebs_isolation_quirk); 7285 x86_pmu.late_ack = true; 7286 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7287 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7288 7289 intel_pmu_lbr_init_hsw(); 7290 7291 x86_pmu.event_constraints = intel_hsw_event_constraints; 7292 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 7293 x86_pmu.extra_regs = intel_snbep_extra_regs; 7294 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 7295 x86_pmu.pebs_prec_dist = true; 7296 /* all extra regs are per-cpu when HT is on */ 7297 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7298 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7299 7300 x86_pmu.hw_config = hsw_hw_config; 7301 x86_pmu.get_event_constraints = hsw_get_event_constraints; 7302 x86_pmu.limit_period = hsw_limit_period; 7303 x86_pmu.lbr_double_abort = true; 7304 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7305 hsw_format_attr : nhm_format_attr; 7306 td_attr = hsw_events_attrs; 7307 mem_attr = hsw_mem_events_attrs; 7308 tsx_attr = hsw_tsx_events_attrs; 7309 pr_cont("Haswell events, "); 7310 name = "haswell"; 7311 break; 7312 7313 case INTEL_BROADWELL: 7314 case INTEL_BROADWELL_D: 7315 case INTEL_BROADWELL_G: 7316 case INTEL_BROADWELL_X: 7317 x86_add_quirk(intel_pebs_isolation_quirk); 7318 x86_pmu.late_ack = true; 7319 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7320 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7321 7322 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 7323 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 7324 BDW_L3_MISS|HSW_SNOOP_DRAM; 7325 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 7326 HSW_SNOOP_DRAM; 7327 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 7328 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 7329 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 7330 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 7331 7332 intel_pmu_lbr_init_hsw(); 7333 7334 x86_pmu.event_constraints = intel_bdw_event_constraints; 7335 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 7336 x86_pmu.extra_regs = intel_snbep_extra_regs; 7337 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 7338 x86_pmu.pebs_prec_dist = true; 7339 /* all extra regs are per-cpu when HT is on */ 7340 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7341 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7342 7343 x86_pmu.hw_config = hsw_hw_config; 7344 x86_pmu.get_event_constraints = hsw_get_event_constraints; 7345 x86_pmu.limit_period = bdw_limit_period; 7346 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7347 hsw_format_attr : nhm_format_attr; 7348 td_attr = hsw_events_attrs; 7349 mem_attr = hsw_mem_events_attrs; 7350 tsx_attr = hsw_tsx_events_attrs; 7351 pr_cont("Broadwell events, "); 7352 name = "broadwell"; 7353 break; 7354 7355 case INTEL_XEON_PHI_KNL: 7356 case INTEL_XEON_PHI_KNM: 7357 memcpy(hw_cache_event_ids, 7358 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7359 memcpy(hw_cache_extra_regs, 7360 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7361 intel_pmu_lbr_init_knl(); 7362 7363 x86_pmu.event_constraints = intel_slm_event_constraints; 7364 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 7365 x86_pmu.extra_regs = intel_knl_extra_regs; 7366 7367 /* all extra regs are per-cpu when HT is on */ 7368 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7369 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7370 extra_attr = slm_format_attr; 7371 pr_cont("Knights Landing/Mill events, "); 7372 name = "knights-landing"; 7373 break; 7374 7375 case INTEL_SKYLAKE_X: 7376 pmem = true; 7377 fallthrough; 7378 case INTEL_SKYLAKE_L: 7379 case INTEL_SKYLAKE: 7380 case INTEL_KABYLAKE_L: 7381 case INTEL_KABYLAKE: 7382 case INTEL_COMETLAKE_L: 7383 case INTEL_COMETLAKE: 7384 x86_add_quirk(intel_pebs_isolation_quirk); 7385 x86_pmu.late_ack = true; 7386 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7387 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7388 intel_pmu_lbr_init_skl(); 7389 7390 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 7391 event_attr_td_recovery_bubbles.event_str_noht = 7392 "event=0xd,umask=0x1,cmask=1"; 7393 event_attr_td_recovery_bubbles.event_str_ht = 7394 "event=0xd,umask=0x1,cmask=1,any=1"; 7395 7396 x86_pmu.event_constraints = intel_skl_event_constraints; 7397 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 7398 x86_pmu.extra_regs = intel_skl_extra_regs; 7399 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 7400 x86_pmu.pebs_prec_dist = true; 7401 /* all extra regs are per-cpu when HT is on */ 7402 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7403 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7404 7405 x86_pmu.hw_config = hsw_hw_config; 7406 x86_pmu.get_event_constraints = hsw_get_event_constraints; 7407 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7408 hsw_format_attr : nhm_format_attr; 7409 extra_skl_attr = skl_format_attr; 7410 td_attr = hsw_events_attrs; 7411 mem_attr = hsw_mem_events_attrs; 7412 tsx_attr = hsw_tsx_events_attrs; 7413 intel_pmu_pebs_data_source_skl(pmem); 7414 7415 /* 7416 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. 7417 * TSX force abort hooks are not required on these systems. Only deploy 7418 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. 7419 */ 7420 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && 7421 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { 7422 x86_pmu.flags |= PMU_FL_TFA; 7423 x86_pmu.get_event_constraints = tfa_get_event_constraints; 7424 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 7425 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 7426 } 7427 7428 pr_cont("Skylake events, "); 7429 name = "skylake"; 7430 break; 7431 7432 case INTEL_ICELAKE_X: 7433 case INTEL_ICELAKE_D: 7434 x86_pmu.pebs_ept = 1; 7435 pmem = true; 7436 fallthrough; 7437 case INTEL_ICELAKE_L: 7438 case INTEL_ICELAKE: 7439 case INTEL_TIGERLAKE_L: 7440 case INTEL_TIGERLAKE: 7441 case INTEL_ROCKETLAKE: 7442 x86_pmu.late_ack = true; 7443 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7444 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7445 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 7446 intel_pmu_lbr_init_skl(); 7447 7448 x86_pmu.event_constraints = intel_icl_event_constraints; 7449 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 7450 x86_pmu.extra_regs = intel_icl_extra_regs; 7451 x86_pmu.pebs_aliases = NULL; 7452 x86_pmu.pebs_prec_dist = true; 7453 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7454 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7455 7456 x86_pmu.hw_config = hsw_hw_config; 7457 x86_pmu.get_event_constraints = icl_get_event_constraints; 7458 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7459 hsw_format_attr : nhm_format_attr; 7460 extra_skl_attr = skl_format_attr; 7461 mem_attr = icl_events_attrs; 7462 td_attr = icl_td_events_attrs; 7463 tsx_attr = icl_tsx_events_attrs; 7464 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 7465 x86_pmu.lbr_pt_coexist = true; 7466 intel_pmu_pebs_data_source_skl(pmem); 7467 x86_pmu.num_topdown_events = 4; 7468 static_call_update(intel_pmu_update_topdown_event, 7469 &icl_update_topdown_event); 7470 static_call_update(intel_pmu_set_topdown_event_period, 7471 &icl_set_topdown_event_period); 7472 pr_cont("Icelake events, "); 7473 name = "icelake"; 7474 break; 7475 7476 case INTEL_SAPPHIRERAPIDS_X: 7477 case INTEL_EMERALDRAPIDS_X: 7478 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 7479 x86_pmu.extra_regs = intel_glc_extra_regs; 7480 pr_cont("Sapphire Rapids events, "); 7481 name = "sapphire_rapids"; 7482 goto glc_common; 7483 7484 case INTEL_GRANITERAPIDS_X: 7485 case INTEL_GRANITERAPIDS_D: 7486 x86_pmu.extra_regs = intel_rwc_extra_regs; 7487 pr_cont("Granite Rapids events, "); 7488 name = "granite_rapids"; 7489 7490 glc_common: 7491 intel_pmu_init_glc(NULL); 7492 x86_pmu.pebs_ept = 1; 7493 x86_pmu.hw_config = hsw_hw_config; 7494 x86_pmu.get_event_constraints = glc_get_event_constraints; 7495 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7496 hsw_format_attr : nhm_format_attr; 7497 extra_skl_attr = skl_format_attr; 7498 mem_attr = glc_events_attrs; 7499 td_attr = glc_td_events_attrs; 7500 tsx_attr = glc_tsx_events_attrs; 7501 intel_pmu_pebs_data_source_skl(true); 7502 break; 7503 7504 case INTEL_ALDERLAKE: 7505 case INTEL_ALDERLAKE_L: 7506 case INTEL_RAPTORLAKE: 7507 case INTEL_RAPTORLAKE_P: 7508 case INTEL_RAPTORLAKE_S: 7509 /* 7510 * Alder Lake has 2 types of CPU, core and atom. 7511 * 7512 * Initialize the common PerfMon capabilities here. 7513 */ 7514 intel_pmu_init_hybrid(hybrid_big_small); 7515 7516 x86_pmu.pebs_latency_data = grt_latency_data; 7517 x86_pmu.get_event_constraints = adl_get_event_constraints; 7518 x86_pmu.hw_config = adl_hw_config; 7519 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; 7520 7521 td_attr = adl_hybrid_events_attrs; 7522 mem_attr = adl_hybrid_mem_attrs; 7523 tsx_attr = adl_hybrid_tsx_attrs; 7524 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7525 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; 7526 7527 /* Initialize big core specific PerfMon capabilities.*/ 7528 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7529 intel_pmu_init_glc(&pmu->pmu); 7530 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 7531 pmu->cntr_mask64 <<= 2; 7532 pmu->cntr_mask64 |= 0x3; 7533 pmu->fixed_cntr_mask64 <<= 1; 7534 pmu->fixed_cntr_mask64 |= 0x1; 7535 } else { 7536 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 7537 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 7538 } 7539 7540 /* 7541 * Quirk: For some Alder Lake machine, when all E-cores are disabled in 7542 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However, 7543 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will 7544 * mistakenly add extra counters for P-cores. Correct the number of 7545 * counters here. 7546 */ 7547 if ((x86_pmu_num_counters(&pmu->pmu) > 8) || (x86_pmu_num_counters_fixed(&pmu->pmu) > 4)) { 7548 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 7549 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 7550 } 7551 7552 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 7553 pmu->unconstrained = (struct event_constraint) 7554 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 7555 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 7556 7557 pmu->extra_regs = intel_glc_extra_regs; 7558 7559 /* Initialize Atom core specific PerfMon capabilities.*/ 7560 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7561 intel_pmu_init_grt(&pmu->pmu); 7562 7563 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 7564 intel_pmu_pebs_data_source_adl(); 7565 pr_cont("Alderlake Hybrid events, "); 7566 name = "alderlake_hybrid"; 7567 break; 7568 7569 case INTEL_METEORLAKE: 7570 case INTEL_METEORLAKE_L: 7571 case INTEL_ARROWLAKE_U: 7572 intel_pmu_init_hybrid(hybrid_big_small); 7573 7574 x86_pmu.pebs_latency_data = cmt_latency_data; 7575 x86_pmu.get_event_constraints = mtl_get_event_constraints; 7576 x86_pmu.hw_config = adl_hw_config; 7577 7578 td_attr = adl_hybrid_events_attrs; 7579 mem_attr = mtl_hybrid_mem_attrs; 7580 tsx_attr = adl_hybrid_tsx_attrs; 7581 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7582 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 7583 7584 /* Initialize big core specific PerfMon capabilities.*/ 7585 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7586 intel_pmu_init_glc(&pmu->pmu); 7587 pmu->extra_regs = intel_rwc_extra_regs; 7588 7589 /* Initialize Atom core specific PerfMon capabilities.*/ 7590 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7591 intel_pmu_init_grt(&pmu->pmu); 7592 pmu->extra_regs = intel_cmt_extra_regs; 7593 7594 intel_pmu_pebs_data_source_mtl(); 7595 pr_cont("Meteorlake Hybrid events, "); 7596 name = "meteorlake_hybrid"; 7597 break; 7598 7599 case INTEL_PANTHERLAKE_L: 7600 pr_cont("Pantherlake Hybrid events, "); 7601 name = "pantherlake_hybrid"; 7602 goto lnl_common; 7603 7604 case INTEL_LUNARLAKE_M: 7605 case INTEL_ARROWLAKE: 7606 pr_cont("Lunarlake Hybrid events, "); 7607 name = "lunarlake_hybrid"; 7608 7609 lnl_common: 7610 intel_pmu_init_hybrid(hybrid_big_small); 7611 7612 x86_pmu.pebs_latency_data = lnl_latency_data; 7613 x86_pmu.get_event_constraints = mtl_get_event_constraints; 7614 x86_pmu.hw_config = adl_hw_config; 7615 7616 td_attr = lnl_hybrid_events_attrs; 7617 mem_attr = mtl_hybrid_mem_attrs; 7618 tsx_attr = adl_hybrid_tsx_attrs; 7619 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7620 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 7621 7622 /* Initialize big core specific PerfMon capabilities.*/ 7623 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7624 intel_pmu_init_lnc(&pmu->pmu); 7625 7626 /* Initialize Atom core specific PerfMon capabilities.*/ 7627 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7628 intel_pmu_init_skt(&pmu->pmu); 7629 7630 intel_pmu_pebs_data_source_lnl(); 7631 break; 7632 7633 case INTEL_ARROWLAKE_H: 7634 intel_pmu_init_hybrid(hybrid_big_small_tiny); 7635 7636 x86_pmu.pebs_latency_data = arl_h_latency_data; 7637 x86_pmu.get_event_constraints = arl_h_get_event_constraints; 7638 x86_pmu.hw_config = arl_h_hw_config; 7639 7640 td_attr = arl_h_hybrid_events_attrs; 7641 mem_attr = arl_h_hybrid_mem_attrs; 7642 tsx_attr = adl_hybrid_tsx_attrs; 7643 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7644 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 7645 7646 /* Initialize big core specific PerfMon capabilities. */ 7647 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7648 intel_pmu_init_lnc(&pmu->pmu); 7649 7650 /* Initialize Atom core specific PerfMon capabilities. */ 7651 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7652 intel_pmu_init_skt(&pmu->pmu); 7653 7654 /* Initialize Lower Power Atom specific PerfMon capabilities. */ 7655 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX]; 7656 intel_pmu_init_grt(&pmu->pmu); 7657 pmu->extra_regs = intel_cmt_extra_regs; 7658 7659 intel_pmu_pebs_data_source_arl_h(); 7660 pr_cont("ArrowLake-H Hybrid events, "); 7661 name = "arrowlake_h_hybrid"; 7662 break; 7663 7664 default: 7665 switch (x86_pmu.version) { 7666 case 1: 7667 x86_pmu.event_constraints = intel_v1_event_constraints; 7668 pr_cont("generic architected perfmon v1, "); 7669 name = "generic_arch_v1"; 7670 break; 7671 case 2: 7672 case 3: 7673 case 4: 7674 /* 7675 * default constraints for v2 and up 7676 */ 7677 x86_pmu.event_constraints = intel_gen_event_constraints; 7678 pr_cont("generic architected perfmon, "); 7679 name = "generic_arch_v2+"; 7680 break; 7681 default: 7682 /* 7683 * The default constraints for v5 and up can support up to 7684 * 16 fixed counters. For the fixed counters 4 and later, 7685 * the pseudo-encoding is applied. 7686 * The constraints may be cut according to the CPUID enumeration 7687 * by inserting the EVENT_CONSTRAINT_END. 7688 */ 7689 if (fls64(x86_pmu.fixed_cntr_mask64) > INTEL_PMC_MAX_FIXED) 7690 x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0); 7691 intel_v5_gen_event_constraints[fls64(x86_pmu.fixed_cntr_mask64)].weight = -1; 7692 x86_pmu.event_constraints = intel_v5_gen_event_constraints; 7693 pr_cont("generic architected perfmon, "); 7694 name = "generic_arch_v5+"; 7695 break; 7696 } 7697 } 7698 7699 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 7700 7701 if (!is_hybrid()) { 7702 group_events_td.attrs = td_attr; 7703 group_events_mem.attrs = mem_attr; 7704 group_events_tsx.attrs = tsx_attr; 7705 group_format_extra.attrs = extra_attr; 7706 group_format_extra_skl.attrs = extra_skl_attr; 7707 7708 x86_pmu.attr_update = attr_update; 7709 } else { 7710 hybrid_group_events_td.attrs = td_attr; 7711 hybrid_group_events_mem.attrs = mem_attr; 7712 hybrid_group_events_tsx.attrs = tsx_attr; 7713 hybrid_group_format_extra.attrs = extra_attr; 7714 7715 x86_pmu.attr_update = hybrid_attr_update; 7716 } 7717 7718 /* 7719 * The archPerfmonExt (0x23) includes an enhanced enumeration of 7720 * PMU architectural features with a per-core view. For non-hybrid, 7721 * each core has the same PMU capabilities. It's good enough to 7722 * update the x86_pmu from the booting CPU. For hybrid, the x86_pmu 7723 * is used to keep the common capabilities. Still keep the values 7724 * from the leaf 0xa. The core specific update will be done later 7725 * when a new type is online. 7726 */ 7727 if (!is_hybrid() && boot_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) 7728 update_pmu_cap(NULL); 7729 7730 intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64, 7731 &x86_pmu.fixed_cntr_mask64, 7732 &x86_pmu.intel_ctrl); 7733 7734 /* AnyThread may be deprecated on arch perfmon v5 or later */ 7735 if (x86_pmu.intel_cap.anythread_deprecated) 7736 x86_pmu.format_attrs = intel_arch_formats_attr; 7737 7738 intel_pmu_check_event_constraints(x86_pmu.event_constraints, 7739 x86_pmu.cntr_mask64, 7740 x86_pmu.fixed_cntr_mask64, 7741 x86_pmu.intel_ctrl); 7742 /* 7743 * Access LBR MSR may cause #GP under certain circumstances. 7744 * Check all LBR MSR here. 7745 * Disable LBR access if any LBR MSRs can not be accessed. 7746 */ 7747 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 7748 x86_pmu.lbr_nr = 0; 7749 for (i = 0; i < x86_pmu.lbr_nr; i++) { 7750 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 7751 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 7752 x86_pmu.lbr_nr = 0; 7753 } 7754 7755 if (x86_pmu.lbr_nr) { 7756 intel_pmu_lbr_init(); 7757 7758 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 7759 7760 /* only support branch_stack snapshot for perfmon >= v2 */ 7761 if (x86_pmu.disable_all == intel_pmu_disable_all) { 7762 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) { 7763 static_call_update(perf_snapshot_branch_stack, 7764 intel_pmu_snapshot_arch_branch_stack); 7765 } else { 7766 static_call_update(perf_snapshot_branch_stack, 7767 intel_pmu_snapshot_branch_stack); 7768 } 7769 } 7770 } 7771 7772 intel_pmu_check_extra_regs(x86_pmu.extra_regs); 7773 7774 /* Support full width counters using alternative MSR range */ 7775 if (x86_pmu.intel_cap.full_width_write) { 7776 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 7777 x86_pmu.perfctr = MSR_IA32_PMC0; 7778 pr_cont("full-width counters, "); 7779 } 7780 7781 /* Support V6+ MSR Aliasing */ 7782 if (x86_pmu.version >= 6) { 7783 x86_pmu.perfctr = MSR_IA32_PMC_V6_GP0_CTR; 7784 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A; 7785 x86_pmu.fixedctr = MSR_IA32_PMC_V6_FX0_CTR; 7786 x86_pmu.addr_offset = intel_pmu_v6_addr_offset; 7787 } 7788 7789 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 7790 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 7791 7792 if (x86_pmu.intel_cap.pebs_timing_info) 7793 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY; 7794 7795 intel_aux_output_init(); 7796 7797 return 0; 7798 } 7799 7800 /* 7801 * HT bug: phase 2 init 7802 * Called once we have valid topology information to check 7803 * whether or not HT is enabled 7804 * If HT is off, then we disable the workaround 7805 */ 7806 static __init int fixup_ht_bug(void) 7807 { 7808 int c; 7809 /* 7810 * problem not present on this CPU model, nothing to do 7811 */ 7812 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 7813 return 0; 7814 7815 if (topology_max_smt_threads() > 1) { 7816 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 7817 return 0; 7818 } 7819 7820 cpus_read_lock(); 7821 7822 hardlockup_detector_perf_stop(); 7823 7824 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 7825 7826 x86_pmu.start_scheduling = NULL; 7827 x86_pmu.commit_scheduling = NULL; 7828 x86_pmu.stop_scheduling = NULL; 7829 7830 hardlockup_detector_perf_restart(); 7831 7832 for_each_online_cpu(c) 7833 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 7834 7835 cpus_read_unlock(); 7836 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 7837 return 0; 7838 } 7839 subsys_initcall(fixup_ht_bug) 7840