1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Per core/cpu state 4 * 5 * Used to coordinate shared registers between HT threads or 6 * among events on a single PMU. 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/stddef.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/export.h> 16 #include <linux/nmi.h> 17 #include <linux/kvm_host.h> 18 19 #include <asm/cpufeature.h> 20 #include <asm/debugreg.h> 21 #include <asm/hardirq.h> 22 #include <asm/intel-family.h> 23 #include <asm/intel_pt.h> 24 #include <asm/apic.h> 25 #include <asm/cpu_device_id.h> 26 27 #include "../perf_event.h" 28 29 /* 30 * Intel PerfMon, used on Core and later. 31 */ 32 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 33 { 34 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 35 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 36 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 37 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 38 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 39 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 40 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 41 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 42 }; 43 44 static struct event_constraint intel_core_event_constraints[] __read_mostly = 45 { 46 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 47 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 48 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 49 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 50 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 51 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 52 EVENT_CONSTRAINT_END 53 }; 54 55 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 56 { 57 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 58 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 59 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 60 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 61 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 62 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 63 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 64 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 65 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 66 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 67 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 68 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 69 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 70 EVENT_CONSTRAINT_END 71 }; 72 73 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 74 { 75 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 76 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 77 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 78 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 79 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 80 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 81 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 82 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 83 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 84 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 85 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 86 EVENT_CONSTRAINT_END 87 }; 88 89 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 90 { 91 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 92 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 93 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 94 EVENT_EXTRA_END 95 }; 96 97 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 98 { 99 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 100 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 101 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 102 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 103 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 104 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 105 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 106 EVENT_CONSTRAINT_END 107 }; 108 109 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 110 { 111 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 112 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 113 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 114 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 115 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 116 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 117 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 118 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 119 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 120 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 121 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 122 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 123 124 /* 125 * When HT is off these events can only run on the bottom 4 counters 126 * When HT is on, they are impacted by the HT bug and require EXCL access 127 */ 128 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 129 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 130 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 131 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 132 133 EVENT_CONSTRAINT_END 134 }; 135 136 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 137 { 138 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 139 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 140 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 141 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 142 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ 143 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 144 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 145 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 146 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 147 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 148 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 149 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 150 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 151 152 /* 153 * When HT is off these events can only run on the bottom 4 counters 154 * When HT is on, they are impacted by the HT bug and require EXCL access 155 */ 156 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 157 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 158 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 159 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 160 161 EVENT_CONSTRAINT_END 162 }; 163 164 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 165 { 166 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 167 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 168 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 169 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 170 EVENT_EXTRA_END 171 }; 172 173 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 174 { 175 EVENT_CONSTRAINT_END 176 }; 177 178 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 179 { 180 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 181 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 182 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 183 EVENT_CONSTRAINT_END 184 }; 185 186 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly = 187 { 188 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 189 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 190 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 191 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 192 FIXED_EVENT_CONSTRAINT(0x0500, 4), 193 FIXED_EVENT_CONSTRAINT(0x0600, 5), 194 FIXED_EVENT_CONSTRAINT(0x0700, 6), 195 FIXED_EVENT_CONSTRAINT(0x0800, 7), 196 FIXED_EVENT_CONSTRAINT(0x0900, 8), 197 FIXED_EVENT_CONSTRAINT(0x0a00, 9), 198 FIXED_EVENT_CONSTRAINT(0x0b00, 10), 199 FIXED_EVENT_CONSTRAINT(0x0c00, 11), 200 FIXED_EVENT_CONSTRAINT(0x0d00, 12), 201 FIXED_EVENT_CONSTRAINT(0x0e00, 13), 202 FIXED_EVENT_CONSTRAINT(0x0f00, 14), 203 FIXED_EVENT_CONSTRAINT(0x1000, 15), 204 EVENT_CONSTRAINT_END 205 }; 206 207 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 208 { 209 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 210 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 211 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 212 EVENT_CONSTRAINT_END 213 }; 214 215 static struct event_constraint intel_grt_event_constraints[] __read_mostly = { 216 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 217 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 218 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 219 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 220 EVENT_CONSTRAINT_END 221 }; 222 223 static struct event_constraint intel_skt_event_constraints[] __read_mostly = { 224 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 225 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 226 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 227 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 228 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */ 229 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */ 230 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */ 231 EVENT_CONSTRAINT_END 232 }; 233 234 static struct event_constraint intel_skl_event_constraints[] = { 235 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 236 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 237 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 238 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 239 240 /* 241 * when HT is off, these can only run on the bottom 4 counters 242 */ 243 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 244 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 245 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 246 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 247 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 248 249 EVENT_CONSTRAINT_END 250 }; 251 252 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 253 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 254 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 255 EVENT_EXTRA_END 256 }; 257 258 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 259 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 260 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 261 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 262 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 263 EVENT_EXTRA_END 264 }; 265 266 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 267 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 268 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 269 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 270 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 271 EVENT_EXTRA_END 272 }; 273 274 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 275 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 276 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 277 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 278 /* 279 * Note the low 8 bits eventsel code is not a continuous field, containing 280 * some #GPing bits. These are masked out. 281 */ 282 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 283 EVENT_EXTRA_END 284 }; 285 286 static struct event_constraint intel_icl_event_constraints[] = { 287 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 288 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ 289 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 290 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 291 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 292 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 293 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 294 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 295 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 296 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 297 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 298 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 299 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 300 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf), 301 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 302 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 303 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 304 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 305 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 306 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 307 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 308 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 309 INTEL_EVENT_CONSTRAINT(0xef, 0xf), 310 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 311 EVENT_CONSTRAINT_END 312 }; 313 314 static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 315 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 316 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 317 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 318 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 319 EVENT_EXTRA_END 320 }; 321 322 static struct extra_reg intel_glc_extra_regs[] __read_mostly = { 323 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 324 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 325 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 326 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 327 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 328 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 329 EVENT_EXTRA_END 330 }; 331 332 static struct event_constraint intel_glc_event_constraints[] = { 333 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 334 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 335 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 336 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 337 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 338 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 339 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 340 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 341 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 342 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 343 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 344 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 345 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 346 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 347 348 INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 349 INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 350 /* 351 * Generally event codes < 0x90 are restricted to counters 0-3. 352 * The 0x2E and 0x3C are exception, which has no restriction. 353 */ 354 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 355 356 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 357 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 358 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 359 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 360 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 361 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 362 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 363 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 364 /* 365 * Generally event codes >= 0x90 are likely to have no restrictions. 366 * The exception are defined as above. 367 */ 368 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 369 370 EVENT_CONSTRAINT_END 371 }; 372 373 static struct extra_reg intel_rwc_extra_regs[] __read_mostly = { 374 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 375 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 376 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 377 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 378 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 379 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 380 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 381 EVENT_EXTRA_END 382 }; 383 384 static struct event_constraint intel_lnc_event_constraints[] = { 385 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 386 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 387 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 388 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 389 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 390 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 391 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 392 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 393 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 394 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 395 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 396 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 397 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 398 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 399 400 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), 401 INTEL_UEVENT_CONSTRAINT(0x0175, 0x4), 402 403 INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff), 404 INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff), 405 /* 406 * Generally event codes < 0x90 are restricted to counters 0-3. 407 * The 0x2E and 0x3C are exception, which has no restriction. 408 */ 409 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 410 411 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 412 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 413 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 414 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 415 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 416 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 417 INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1), 418 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8), 419 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3), 420 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 421 422 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 423 /* 424 * Generally event codes >= 0x90 are likely to have no restrictions. 425 * The exception are defined as above. 426 */ 427 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0x3ff), 428 429 EVENT_CONSTRAINT_END 430 }; 431 432 static struct extra_reg intel_lnc_extra_regs[] __read_mostly = { 433 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0), 434 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1), 435 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 436 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 437 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 438 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE), 439 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 440 EVENT_EXTRA_END 441 }; 442 443 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 444 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 445 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 446 447 static struct attribute *nhm_mem_events_attrs[] = { 448 EVENT_PTR(mem_ld_nhm), 449 NULL, 450 }; 451 452 /* 453 * topdown events for Intel Core CPUs. 454 * 455 * The events are all in slots, which is a free slot in a 4 wide 456 * pipeline. Some events are already reported in slots, for cycle 457 * events we multiply by the pipeline width (4). 458 * 459 * With Hyper Threading on, topdown metrics are either summed or averaged 460 * between the threads of a core: (count_t0 + count_t1). 461 * 462 * For the average case the metric is always scaled to pipeline width, 463 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 464 */ 465 466 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 467 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 468 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 469 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 470 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 471 "event=0xe,umask=0x1"); /* uops_issued.any */ 472 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 473 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 474 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 475 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 476 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 477 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 478 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 479 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 480 "4", "2"); 481 482 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 483 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 484 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 485 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 486 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 487 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 488 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 489 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 490 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 491 492 static struct attribute *snb_events_attrs[] = { 493 EVENT_PTR(td_slots_issued), 494 EVENT_PTR(td_slots_retired), 495 EVENT_PTR(td_fetch_bubbles), 496 EVENT_PTR(td_total_slots), 497 EVENT_PTR(td_total_slots_scale), 498 EVENT_PTR(td_recovery_bubbles), 499 EVENT_PTR(td_recovery_bubbles_scale), 500 NULL, 501 }; 502 503 static struct attribute *snb_mem_events_attrs[] = { 504 EVENT_PTR(mem_ld_snb), 505 EVENT_PTR(mem_st_snb), 506 NULL, 507 }; 508 509 static struct event_constraint intel_hsw_event_constraints[] = { 510 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 511 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 512 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 513 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 514 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 515 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 516 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 517 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 518 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 519 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 520 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 521 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 522 523 /* 524 * When HT is off these events can only run on the bottom 4 counters 525 * When HT is on, they are impacted by the HT bug and require EXCL access 526 */ 527 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 528 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 529 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 530 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 531 532 EVENT_CONSTRAINT_END 533 }; 534 535 static struct event_constraint intel_bdw_event_constraints[] = { 536 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 537 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 538 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 539 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 540 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 541 /* 542 * when HT is off, these can only run on the bottom 4 counters 543 */ 544 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 545 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 546 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 547 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 548 EVENT_CONSTRAINT_END 549 }; 550 551 static u64 intel_pmu_event_map(int hw_event) 552 { 553 return intel_perfmon_event_map[hw_event]; 554 } 555 556 static __initconst const u64 glc_hw_cache_event_ids 557 [PERF_COUNT_HW_CACHE_MAX] 558 [PERF_COUNT_HW_CACHE_OP_MAX] 559 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 560 { 561 [ C(L1D ) ] = { 562 [ C(OP_READ) ] = { 563 [ C(RESULT_ACCESS) ] = 0x81d0, 564 [ C(RESULT_MISS) ] = 0xe124, 565 }, 566 [ C(OP_WRITE) ] = { 567 [ C(RESULT_ACCESS) ] = 0x82d0, 568 }, 569 }, 570 [ C(L1I ) ] = { 571 [ C(OP_READ) ] = { 572 [ C(RESULT_MISS) ] = 0xe424, 573 }, 574 [ C(OP_WRITE) ] = { 575 [ C(RESULT_ACCESS) ] = -1, 576 [ C(RESULT_MISS) ] = -1, 577 }, 578 }, 579 [ C(LL ) ] = { 580 [ C(OP_READ) ] = { 581 [ C(RESULT_ACCESS) ] = 0x12a, 582 [ C(RESULT_MISS) ] = 0x12a, 583 }, 584 [ C(OP_WRITE) ] = { 585 [ C(RESULT_ACCESS) ] = 0x12a, 586 [ C(RESULT_MISS) ] = 0x12a, 587 }, 588 }, 589 [ C(DTLB) ] = { 590 [ C(OP_READ) ] = { 591 [ C(RESULT_ACCESS) ] = 0x81d0, 592 [ C(RESULT_MISS) ] = 0xe12, 593 }, 594 [ C(OP_WRITE) ] = { 595 [ C(RESULT_ACCESS) ] = 0x82d0, 596 [ C(RESULT_MISS) ] = 0xe13, 597 }, 598 }, 599 [ C(ITLB) ] = { 600 [ C(OP_READ) ] = { 601 [ C(RESULT_ACCESS) ] = -1, 602 [ C(RESULT_MISS) ] = 0xe11, 603 }, 604 [ C(OP_WRITE) ] = { 605 [ C(RESULT_ACCESS) ] = -1, 606 [ C(RESULT_MISS) ] = -1, 607 }, 608 [ C(OP_PREFETCH) ] = { 609 [ C(RESULT_ACCESS) ] = -1, 610 [ C(RESULT_MISS) ] = -1, 611 }, 612 }, 613 [ C(BPU ) ] = { 614 [ C(OP_READ) ] = { 615 [ C(RESULT_ACCESS) ] = 0x4c4, 616 [ C(RESULT_MISS) ] = 0x4c5, 617 }, 618 [ C(OP_WRITE) ] = { 619 [ C(RESULT_ACCESS) ] = -1, 620 [ C(RESULT_MISS) ] = -1, 621 }, 622 [ C(OP_PREFETCH) ] = { 623 [ C(RESULT_ACCESS) ] = -1, 624 [ C(RESULT_MISS) ] = -1, 625 }, 626 }, 627 [ C(NODE) ] = { 628 [ C(OP_READ) ] = { 629 [ C(RESULT_ACCESS) ] = 0x12a, 630 [ C(RESULT_MISS) ] = 0x12a, 631 }, 632 }, 633 }; 634 635 static __initconst const u64 glc_hw_cache_extra_regs 636 [PERF_COUNT_HW_CACHE_MAX] 637 [PERF_COUNT_HW_CACHE_OP_MAX] 638 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 639 { 640 [ C(LL ) ] = { 641 [ C(OP_READ) ] = { 642 [ C(RESULT_ACCESS) ] = 0x10001, 643 [ C(RESULT_MISS) ] = 0x3fbfc00001, 644 }, 645 [ C(OP_WRITE) ] = { 646 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, 647 [ C(RESULT_MISS) ] = 0x3f3fc00002, 648 }, 649 }, 650 [ C(NODE) ] = { 651 [ C(OP_READ) ] = { 652 [ C(RESULT_ACCESS) ] = 0x10c000001, 653 [ C(RESULT_MISS) ] = 0x3fb3000001, 654 }, 655 }, 656 }; 657 658 /* 659 * Notes on the events: 660 * - data reads do not include code reads (comparable to earlier tables) 661 * - data counts include speculative execution (except L1 write, dtlb, bpu) 662 * - remote node access includes remote memory, remote cache, remote mmio. 663 * - prefetches are not included in the counts. 664 * - icache miss does not include decoded icache 665 */ 666 667 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 668 #define SKL_DEMAND_RFO BIT_ULL(1) 669 #define SKL_ANY_RESPONSE BIT_ULL(16) 670 #define SKL_SUPPLIER_NONE BIT_ULL(17) 671 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 672 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 673 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 674 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 675 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 676 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 677 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 678 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 679 #define SKL_SPL_HIT BIT_ULL(30) 680 #define SKL_SNOOP_NONE BIT_ULL(31) 681 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 682 #define SKL_SNOOP_MISS BIT_ULL(33) 683 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 684 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 685 #define SKL_SNOOP_HITM BIT_ULL(36) 686 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 687 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 688 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 689 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 690 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 691 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 692 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 693 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 694 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 695 SKL_SNOOP_HITM|SKL_SPL_HIT) 696 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 697 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 698 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 699 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 700 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 701 702 static __initconst const u64 skl_hw_cache_event_ids 703 [PERF_COUNT_HW_CACHE_MAX] 704 [PERF_COUNT_HW_CACHE_OP_MAX] 705 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 706 { 707 [ C(L1D ) ] = { 708 [ C(OP_READ) ] = { 709 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 710 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 711 }, 712 [ C(OP_WRITE) ] = { 713 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 714 [ C(RESULT_MISS) ] = 0x0, 715 }, 716 [ C(OP_PREFETCH) ] = { 717 [ C(RESULT_ACCESS) ] = 0x0, 718 [ C(RESULT_MISS) ] = 0x0, 719 }, 720 }, 721 [ C(L1I ) ] = { 722 [ C(OP_READ) ] = { 723 [ C(RESULT_ACCESS) ] = 0x0, 724 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 725 }, 726 [ C(OP_WRITE) ] = { 727 [ C(RESULT_ACCESS) ] = -1, 728 [ C(RESULT_MISS) ] = -1, 729 }, 730 [ C(OP_PREFETCH) ] = { 731 [ C(RESULT_ACCESS) ] = 0x0, 732 [ C(RESULT_MISS) ] = 0x0, 733 }, 734 }, 735 [ C(LL ) ] = { 736 [ C(OP_READ) ] = { 737 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 738 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 739 }, 740 [ C(OP_WRITE) ] = { 741 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 742 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 743 }, 744 [ C(OP_PREFETCH) ] = { 745 [ C(RESULT_ACCESS) ] = 0x0, 746 [ C(RESULT_MISS) ] = 0x0, 747 }, 748 }, 749 [ C(DTLB) ] = { 750 [ C(OP_READ) ] = { 751 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 752 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 753 }, 754 [ C(OP_WRITE) ] = { 755 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 756 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 757 }, 758 [ C(OP_PREFETCH) ] = { 759 [ C(RESULT_ACCESS) ] = 0x0, 760 [ C(RESULT_MISS) ] = 0x0, 761 }, 762 }, 763 [ C(ITLB) ] = { 764 [ C(OP_READ) ] = { 765 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 766 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 767 }, 768 [ C(OP_WRITE) ] = { 769 [ C(RESULT_ACCESS) ] = -1, 770 [ C(RESULT_MISS) ] = -1, 771 }, 772 [ C(OP_PREFETCH) ] = { 773 [ C(RESULT_ACCESS) ] = -1, 774 [ C(RESULT_MISS) ] = -1, 775 }, 776 }, 777 [ C(BPU ) ] = { 778 [ C(OP_READ) ] = { 779 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 780 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 781 }, 782 [ C(OP_WRITE) ] = { 783 [ C(RESULT_ACCESS) ] = -1, 784 [ C(RESULT_MISS) ] = -1, 785 }, 786 [ C(OP_PREFETCH) ] = { 787 [ C(RESULT_ACCESS) ] = -1, 788 [ C(RESULT_MISS) ] = -1, 789 }, 790 }, 791 [ C(NODE) ] = { 792 [ C(OP_READ) ] = { 793 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 794 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 795 }, 796 [ C(OP_WRITE) ] = { 797 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 798 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 799 }, 800 [ C(OP_PREFETCH) ] = { 801 [ C(RESULT_ACCESS) ] = 0x0, 802 [ C(RESULT_MISS) ] = 0x0, 803 }, 804 }, 805 }; 806 807 static __initconst const u64 skl_hw_cache_extra_regs 808 [PERF_COUNT_HW_CACHE_MAX] 809 [PERF_COUNT_HW_CACHE_OP_MAX] 810 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 811 { 812 [ C(LL ) ] = { 813 [ C(OP_READ) ] = { 814 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 815 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 816 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 817 SKL_L3_MISS|SKL_ANY_SNOOP| 818 SKL_SUPPLIER_NONE, 819 }, 820 [ C(OP_WRITE) ] = { 821 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 822 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 823 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 824 SKL_L3_MISS|SKL_ANY_SNOOP| 825 SKL_SUPPLIER_NONE, 826 }, 827 [ C(OP_PREFETCH) ] = { 828 [ C(RESULT_ACCESS) ] = 0x0, 829 [ C(RESULT_MISS) ] = 0x0, 830 }, 831 }, 832 [ C(NODE) ] = { 833 [ C(OP_READ) ] = { 834 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 835 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 836 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 837 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 838 }, 839 [ C(OP_WRITE) ] = { 840 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 841 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 842 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 843 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 844 }, 845 [ C(OP_PREFETCH) ] = { 846 [ C(RESULT_ACCESS) ] = 0x0, 847 [ C(RESULT_MISS) ] = 0x0, 848 }, 849 }, 850 }; 851 852 #define SNB_DMND_DATA_RD (1ULL << 0) 853 #define SNB_DMND_RFO (1ULL << 1) 854 #define SNB_DMND_IFETCH (1ULL << 2) 855 #define SNB_DMND_WB (1ULL << 3) 856 #define SNB_PF_DATA_RD (1ULL << 4) 857 #define SNB_PF_RFO (1ULL << 5) 858 #define SNB_PF_IFETCH (1ULL << 6) 859 #define SNB_LLC_DATA_RD (1ULL << 7) 860 #define SNB_LLC_RFO (1ULL << 8) 861 #define SNB_LLC_IFETCH (1ULL << 9) 862 #define SNB_BUS_LOCKS (1ULL << 10) 863 #define SNB_STRM_ST (1ULL << 11) 864 #define SNB_OTHER (1ULL << 15) 865 #define SNB_RESP_ANY (1ULL << 16) 866 #define SNB_NO_SUPP (1ULL << 17) 867 #define SNB_LLC_HITM (1ULL << 18) 868 #define SNB_LLC_HITE (1ULL << 19) 869 #define SNB_LLC_HITS (1ULL << 20) 870 #define SNB_LLC_HITF (1ULL << 21) 871 #define SNB_LOCAL (1ULL << 22) 872 #define SNB_REMOTE (0xffULL << 23) 873 #define SNB_SNP_NONE (1ULL << 31) 874 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 875 #define SNB_SNP_MISS (1ULL << 33) 876 #define SNB_NO_FWD (1ULL << 34) 877 #define SNB_SNP_FWD (1ULL << 35) 878 #define SNB_HITM (1ULL << 36) 879 #define SNB_NON_DRAM (1ULL << 37) 880 881 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 882 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 883 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 884 885 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 886 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 887 SNB_HITM) 888 889 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 890 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 891 892 #define SNB_L3_ACCESS SNB_RESP_ANY 893 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 894 895 static __initconst const u64 snb_hw_cache_extra_regs 896 [PERF_COUNT_HW_CACHE_MAX] 897 [PERF_COUNT_HW_CACHE_OP_MAX] 898 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 899 { 900 [ C(LL ) ] = { 901 [ C(OP_READ) ] = { 902 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 903 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 904 }, 905 [ C(OP_WRITE) ] = { 906 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 907 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 908 }, 909 [ C(OP_PREFETCH) ] = { 910 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 911 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 912 }, 913 }, 914 [ C(NODE) ] = { 915 [ C(OP_READ) ] = { 916 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 917 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 918 }, 919 [ C(OP_WRITE) ] = { 920 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 921 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 922 }, 923 [ C(OP_PREFETCH) ] = { 924 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 925 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 926 }, 927 }, 928 }; 929 930 static __initconst const u64 snb_hw_cache_event_ids 931 [PERF_COUNT_HW_CACHE_MAX] 932 [PERF_COUNT_HW_CACHE_OP_MAX] 933 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 934 { 935 [ C(L1D) ] = { 936 [ C(OP_READ) ] = { 937 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 938 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 939 }, 940 [ C(OP_WRITE) ] = { 941 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 942 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 943 }, 944 [ C(OP_PREFETCH) ] = { 945 [ C(RESULT_ACCESS) ] = 0x0, 946 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 947 }, 948 }, 949 [ C(L1I ) ] = { 950 [ C(OP_READ) ] = { 951 [ C(RESULT_ACCESS) ] = 0x0, 952 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 953 }, 954 [ C(OP_WRITE) ] = { 955 [ C(RESULT_ACCESS) ] = -1, 956 [ C(RESULT_MISS) ] = -1, 957 }, 958 [ C(OP_PREFETCH) ] = { 959 [ C(RESULT_ACCESS) ] = 0x0, 960 [ C(RESULT_MISS) ] = 0x0, 961 }, 962 }, 963 [ C(LL ) ] = { 964 [ C(OP_READ) ] = { 965 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 966 [ C(RESULT_ACCESS) ] = 0x01b7, 967 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 968 [ C(RESULT_MISS) ] = 0x01b7, 969 }, 970 [ C(OP_WRITE) ] = { 971 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 972 [ C(RESULT_ACCESS) ] = 0x01b7, 973 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 974 [ C(RESULT_MISS) ] = 0x01b7, 975 }, 976 [ C(OP_PREFETCH) ] = { 977 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 978 [ C(RESULT_ACCESS) ] = 0x01b7, 979 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 980 [ C(RESULT_MISS) ] = 0x01b7, 981 }, 982 }, 983 [ C(DTLB) ] = { 984 [ C(OP_READ) ] = { 985 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 986 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 987 }, 988 [ C(OP_WRITE) ] = { 989 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 990 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 991 }, 992 [ C(OP_PREFETCH) ] = { 993 [ C(RESULT_ACCESS) ] = 0x0, 994 [ C(RESULT_MISS) ] = 0x0, 995 }, 996 }, 997 [ C(ITLB) ] = { 998 [ C(OP_READ) ] = { 999 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 1000 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 1001 }, 1002 [ C(OP_WRITE) ] = { 1003 [ C(RESULT_ACCESS) ] = -1, 1004 [ C(RESULT_MISS) ] = -1, 1005 }, 1006 [ C(OP_PREFETCH) ] = { 1007 [ C(RESULT_ACCESS) ] = -1, 1008 [ C(RESULT_MISS) ] = -1, 1009 }, 1010 }, 1011 [ C(BPU ) ] = { 1012 [ C(OP_READ) ] = { 1013 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1014 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1015 }, 1016 [ C(OP_WRITE) ] = { 1017 [ C(RESULT_ACCESS) ] = -1, 1018 [ C(RESULT_MISS) ] = -1, 1019 }, 1020 [ C(OP_PREFETCH) ] = { 1021 [ C(RESULT_ACCESS) ] = -1, 1022 [ C(RESULT_MISS) ] = -1, 1023 }, 1024 }, 1025 [ C(NODE) ] = { 1026 [ C(OP_READ) ] = { 1027 [ C(RESULT_ACCESS) ] = 0x01b7, 1028 [ C(RESULT_MISS) ] = 0x01b7, 1029 }, 1030 [ C(OP_WRITE) ] = { 1031 [ C(RESULT_ACCESS) ] = 0x01b7, 1032 [ C(RESULT_MISS) ] = 0x01b7, 1033 }, 1034 [ C(OP_PREFETCH) ] = { 1035 [ C(RESULT_ACCESS) ] = 0x01b7, 1036 [ C(RESULT_MISS) ] = 0x01b7, 1037 }, 1038 }, 1039 1040 }; 1041 1042 /* 1043 * Notes on the events: 1044 * - data reads do not include code reads (comparable to earlier tables) 1045 * - data counts include speculative execution (except L1 write, dtlb, bpu) 1046 * - remote node access includes remote memory, remote cache, remote mmio. 1047 * - prefetches are not included in the counts because they are not 1048 * reliably counted. 1049 */ 1050 1051 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 1052 #define HSW_DEMAND_RFO BIT_ULL(1) 1053 #define HSW_ANY_RESPONSE BIT_ULL(16) 1054 #define HSW_SUPPLIER_NONE BIT_ULL(17) 1055 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 1056 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 1057 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 1058 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 1059 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 1060 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 1061 HSW_L3_MISS_REMOTE_HOP2P) 1062 #define HSW_SNOOP_NONE BIT_ULL(31) 1063 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 1064 #define HSW_SNOOP_MISS BIT_ULL(33) 1065 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 1066 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 1067 #define HSW_SNOOP_HITM BIT_ULL(36) 1068 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 1069 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 1070 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 1071 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 1072 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 1073 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 1074 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 1075 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 1076 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 1077 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 1078 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 1079 1080 #define BDW_L3_MISS_LOCAL BIT(26) 1081 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 1082 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 1083 HSW_L3_MISS_REMOTE_HOP2P) 1084 1085 1086 static __initconst const u64 hsw_hw_cache_event_ids 1087 [PERF_COUNT_HW_CACHE_MAX] 1088 [PERF_COUNT_HW_CACHE_OP_MAX] 1089 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1090 { 1091 [ C(L1D ) ] = { 1092 [ C(OP_READ) ] = { 1093 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1094 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 1095 }, 1096 [ C(OP_WRITE) ] = { 1097 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1098 [ C(RESULT_MISS) ] = 0x0, 1099 }, 1100 [ C(OP_PREFETCH) ] = { 1101 [ C(RESULT_ACCESS) ] = 0x0, 1102 [ C(RESULT_MISS) ] = 0x0, 1103 }, 1104 }, 1105 [ C(L1I ) ] = { 1106 [ C(OP_READ) ] = { 1107 [ C(RESULT_ACCESS) ] = 0x0, 1108 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 1109 }, 1110 [ C(OP_WRITE) ] = { 1111 [ C(RESULT_ACCESS) ] = -1, 1112 [ C(RESULT_MISS) ] = -1, 1113 }, 1114 [ C(OP_PREFETCH) ] = { 1115 [ C(RESULT_ACCESS) ] = 0x0, 1116 [ C(RESULT_MISS) ] = 0x0, 1117 }, 1118 }, 1119 [ C(LL ) ] = { 1120 [ C(OP_READ) ] = { 1121 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1122 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1123 }, 1124 [ C(OP_WRITE) ] = { 1125 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1126 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1127 }, 1128 [ C(OP_PREFETCH) ] = { 1129 [ C(RESULT_ACCESS) ] = 0x0, 1130 [ C(RESULT_MISS) ] = 0x0, 1131 }, 1132 }, 1133 [ C(DTLB) ] = { 1134 [ C(OP_READ) ] = { 1135 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1136 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1137 }, 1138 [ C(OP_WRITE) ] = { 1139 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1140 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1141 }, 1142 [ C(OP_PREFETCH) ] = { 1143 [ C(RESULT_ACCESS) ] = 0x0, 1144 [ C(RESULT_MISS) ] = 0x0, 1145 }, 1146 }, 1147 [ C(ITLB) ] = { 1148 [ C(OP_READ) ] = { 1149 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1150 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1151 }, 1152 [ C(OP_WRITE) ] = { 1153 [ C(RESULT_ACCESS) ] = -1, 1154 [ C(RESULT_MISS) ] = -1, 1155 }, 1156 [ C(OP_PREFETCH) ] = { 1157 [ C(RESULT_ACCESS) ] = -1, 1158 [ C(RESULT_MISS) ] = -1, 1159 }, 1160 }, 1161 [ C(BPU ) ] = { 1162 [ C(OP_READ) ] = { 1163 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1164 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1165 }, 1166 [ C(OP_WRITE) ] = { 1167 [ C(RESULT_ACCESS) ] = -1, 1168 [ C(RESULT_MISS) ] = -1, 1169 }, 1170 [ C(OP_PREFETCH) ] = { 1171 [ C(RESULT_ACCESS) ] = -1, 1172 [ C(RESULT_MISS) ] = -1, 1173 }, 1174 }, 1175 [ C(NODE) ] = { 1176 [ C(OP_READ) ] = { 1177 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1178 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1179 }, 1180 [ C(OP_WRITE) ] = { 1181 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1182 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1183 }, 1184 [ C(OP_PREFETCH) ] = { 1185 [ C(RESULT_ACCESS) ] = 0x0, 1186 [ C(RESULT_MISS) ] = 0x0, 1187 }, 1188 }, 1189 }; 1190 1191 static __initconst const u64 hsw_hw_cache_extra_regs 1192 [PERF_COUNT_HW_CACHE_MAX] 1193 [PERF_COUNT_HW_CACHE_OP_MAX] 1194 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1195 { 1196 [ C(LL ) ] = { 1197 [ C(OP_READ) ] = { 1198 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1199 HSW_LLC_ACCESS, 1200 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1201 HSW_L3_MISS|HSW_ANY_SNOOP, 1202 }, 1203 [ C(OP_WRITE) ] = { 1204 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1205 HSW_LLC_ACCESS, 1206 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1207 HSW_L3_MISS|HSW_ANY_SNOOP, 1208 }, 1209 [ C(OP_PREFETCH) ] = { 1210 [ C(RESULT_ACCESS) ] = 0x0, 1211 [ C(RESULT_MISS) ] = 0x0, 1212 }, 1213 }, 1214 [ C(NODE) ] = { 1215 [ C(OP_READ) ] = { 1216 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1217 HSW_L3_MISS_LOCAL_DRAM| 1218 HSW_SNOOP_DRAM, 1219 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1220 HSW_L3_MISS_REMOTE| 1221 HSW_SNOOP_DRAM, 1222 }, 1223 [ C(OP_WRITE) ] = { 1224 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1225 HSW_L3_MISS_LOCAL_DRAM| 1226 HSW_SNOOP_DRAM, 1227 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1228 HSW_L3_MISS_REMOTE| 1229 HSW_SNOOP_DRAM, 1230 }, 1231 [ C(OP_PREFETCH) ] = { 1232 [ C(RESULT_ACCESS) ] = 0x0, 1233 [ C(RESULT_MISS) ] = 0x0, 1234 }, 1235 }, 1236 }; 1237 1238 static __initconst const u64 westmere_hw_cache_event_ids 1239 [PERF_COUNT_HW_CACHE_MAX] 1240 [PERF_COUNT_HW_CACHE_OP_MAX] 1241 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1242 { 1243 [ C(L1D) ] = { 1244 [ C(OP_READ) ] = { 1245 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1246 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1247 }, 1248 [ C(OP_WRITE) ] = { 1249 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1250 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1251 }, 1252 [ C(OP_PREFETCH) ] = { 1253 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1254 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1255 }, 1256 }, 1257 [ C(L1I ) ] = { 1258 [ C(OP_READ) ] = { 1259 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1260 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1261 }, 1262 [ C(OP_WRITE) ] = { 1263 [ C(RESULT_ACCESS) ] = -1, 1264 [ C(RESULT_MISS) ] = -1, 1265 }, 1266 [ C(OP_PREFETCH) ] = { 1267 [ C(RESULT_ACCESS) ] = 0x0, 1268 [ C(RESULT_MISS) ] = 0x0, 1269 }, 1270 }, 1271 [ C(LL ) ] = { 1272 [ C(OP_READ) ] = { 1273 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1274 [ C(RESULT_ACCESS) ] = 0x01b7, 1275 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1276 [ C(RESULT_MISS) ] = 0x01b7, 1277 }, 1278 /* 1279 * Use RFO, not WRITEBACK, because a write miss would typically occur 1280 * on RFO. 1281 */ 1282 [ C(OP_WRITE) ] = { 1283 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1284 [ C(RESULT_ACCESS) ] = 0x01b7, 1285 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1286 [ C(RESULT_MISS) ] = 0x01b7, 1287 }, 1288 [ C(OP_PREFETCH) ] = { 1289 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1290 [ C(RESULT_ACCESS) ] = 0x01b7, 1291 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1292 [ C(RESULT_MISS) ] = 0x01b7, 1293 }, 1294 }, 1295 [ C(DTLB) ] = { 1296 [ C(OP_READ) ] = { 1297 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1298 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1299 }, 1300 [ C(OP_WRITE) ] = { 1301 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1302 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1303 }, 1304 [ C(OP_PREFETCH) ] = { 1305 [ C(RESULT_ACCESS) ] = 0x0, 1306 [ C(RESULT_MISS) ] = 0x0, 1307 }, 1308 }, 1309 [ C(ITLB) ] = { 1310 [ C(OP_READ) ] = { 1311 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1312 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1313 }, 1314 [ C(OP_WRITE) ] = { 1315 [ C(RESULT_ACCESS) ] = -1, 1316 [ C(RESULT_MISS) ] = -1, 1317 }, 1318 [ C(OP_PREFETCH) ] = { 1319 [ C(RESULT_ACCESS) ] = -1, 1320 [ C(RESULT_MISS) ] = -1, 1321 }, 1322 }, 1323 [ C(BPU ) ] = { 1324 [ C(OP_READ) ] = { 1325 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1326 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1327 }, 1328 [ C(OP_WRITE) ] = { 1329 [ C(RESULT_ACCESS) ] = -1, 1330 [ C(RESULT_MISS) ] = -1, 1331 }, 1332 [ C(OP_PREFETCH) ] = { 1333 [ C(RESULT_ACCESS) ] = -1, 1334 [ C(RESULT_MISS) ] = -1, 1335 }, 1336 }, 1337 [ C(NODE) ] = { 1338 [ C(OP_READ) ] = { 1339 [ C(RESULT_ACCESS) ] = 0x01b7, 1340 [ C(RESULT_MISS) ] = 0x01b7, 1341 }, 1342 [ C(OP_WRITE) ] = { 1343 [ C(RESULT_ACCESS) ] = 0x01b7, 1344 [ C(RESULT_MISS) ] = 0x01b7, 1345 }, 1346 [ C(OP_PREFETCH) ] = { 1347 [ C(RESULT_ACCESS) ] = 0x01b7, 1348 [ C(RESULT_MISS) ] = 0x01b7, 1349 }, 1350 }, 1351 }; 1352 1353 /* 1354 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1355 * See IA32 SDM Vol 3B 30.6.1.3 1356 */ 1357 1358 #define NHM_DMND_DATA_RD (1 << 0) 1359 #define NHM_DMND_RFO (1 << 1) 1360 #define NHM_DMND_IFETCH (1 << 2) 1361 #define NHM_DMND_WB (1 << 3) 1362 #define NHM_PF_DATA_RD (1 << 4) 1363 #define NHM_PF_DATA_RFO (1 << 5) 1364 #define NHM_PF_IFETCH (1 << 6) 1365 #define NHM_OFFCORE_OTHER (1 << 7) 1366 #define NHM_UNCORE_HIT (1 << 8) 1367 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1368 #define NHM_OTHER_CORE_HITM (1 << 10) 1369 /* reserved */ 1370 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1371 #define NHM_REMOTE_DRAM (1 << 13) 1372 #define NHM_LOCAL_DRAM (1 << 14) 1373 #define NHM_NON_DRAM (1 << 15) 1374 1375 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1376 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1377 1378 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1379 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1380 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1381 1382 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1383 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1384 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1385 1386 static __initconst const u64 nehalem_hw_cache_extra_regs 1387 [PERF_COUNT_HW_CACHE_MAX] 1388 [PERF_COUNT_HW_CACHE_OP_MAX] 1389 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1390 { 1391 [ C(LL ) ] = { 1392 [ C(OP_READ) ] = { 1393 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1394 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1395 }, 1396 [ C(OP_WRITE) ] = { 1397 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1398 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1399 }, 1400 [ C(OP_PREFETCH) ] = { 1401 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1402 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1403 }, 1404 }, 1405 [ C(NODE) ] = { 1406 [ C(OP_READ) ] = { 1407 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1408 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1409 }, 1410 [ C(OP_WRITE) ] = { 1411 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1412 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1413 }, 1414 [ C(OP_PREFETCH) ] = { 1415 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1416 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1417 }, 1418 }, 1419 }; 1420 1421 static __initconst const u64 nehalem_hw_cache_event_ids 1422 [PERF_COUNT_HW_CACHE_MAX] 1423 [PERF_COUNT_HW_CACHE_OP_MAX] 1424 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1425 { 1426 [ C(L1D) ] = { 1427 [ C(OP_READ) ] = { 1428 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1429 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1430 }, 1431 [ C(OP_WRITE) ] = { 1432 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1433 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1434 }, 1435 [ C(OP_PREFETCH) ] = { 1436 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1437 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1438 }, 1439 }, 1440 [ C(L1I ) ] = { 1441 [ C(OP_READ) ] = { 1442 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1443 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1444 }, 1445 [ C(OP_WRITE) ] = { 1446 [ C(RESULT_ACCESS) ] = -1, 1447 [ C(RESULT_MISS) ] = -1, 1448 }, 1449 [ C(OP_PREFETCH) ] = { 1450 [ C(RESULT_ACCESS) ] = 0x0, 1451 [ C(RESULT_MISS) ] = 0x0, 1452 }, 1453 }, 1454 [ C(LL ) ] = { 1455 [ C(OP_READ) ] = { 1456 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1457 [ C(RESULT_ACCESS) ] = 0x01b7, 1458 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1459 [ C(RESULT_MISS) ] = 0x01b7, 1460 }, 1461 /* 1462 * Use RFO, not WRITEBACK, because a write miss would typically occur 1463 * on RFO. 1464 */ 1465 [ C(OP_WRITE) ] = { 1466 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1467 [ C(RESULT_ACCESS) ] = 0x01b7, 1468 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1469 [ C(RESULT_MISS) ] = 0x01b7, 1470 }, 1471 [ C(OP_PREFETCH) ] = { 1472 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1473 [ C(RESULT_ACCESS) ] = 0x01b7, 1474 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1475 [ C(RESULT_MISS) ] = 0x01b7, 1476 }, 1477 }, 1478 [ C(DTLB) ] = { 1479 [ C(OP_READ) ] = { 1480 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1481 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1482 }, 1483 [ C(OP_WRITE) ] = { 1484 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1485 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1486 }, 1487 [ C(OP_PREFETCH) ] = { 1488 [ C(RESULT_ACCESS) ] = 0x0, 1489 [ C(RESULT_MISS) ] = 0x0, 1490 }, 1491 }, 1492 [ C(ITLB) ] = { 1493 [ C(OP_READ) ] = { 1494 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1495 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1496 }, 1497 [ C(OP_WRITE) ] = { 1498 [ C(RESULT_ACCESS) ] = -1, 1499 [ C(RESULT_MISS) ] = -1, 1500 }, 1501 [ C(OP_PREFETCH) ] = { 1502 [ C(RESULT_ACCESS) ] = -1, 1503 [ C(RESULT_MISS) ] = -1, 1504 }, 1505 }, 1506 [ C(BPU ) ] = { 1507 [ C(OP_READ) ] = { 1508 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1509 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1510 }, 1511 [ C(OP_WRITE) ] = { 1512 [ C(RESULT_ACCESS) ] = -1, 1513 [ C(RESULT_MISS) ] = -1, 1514 }, 1515 [ C(OP_PREFETCH) ] = { 1516 [ C(RESULT_ACCESS) ] = -1, 1517 [ C(RESULT_MISS) ] = -1, 1518 }, 1519 }, 1520 [ C(NODE) ] = { 1521 [ C(OP_READ) ] = { 1522 [ C(RESULT_ACCESS) ] = 0x01b7, 1523 [ C(RESULT_MISS) ] = 0x01b7, 1524 }, 1525 [ C(OP_WRITE) ] = { 1526 [ C(RESULT_ACCESS) ] = 0x01b7, 1527 [ C(RESULT_MISS) ] = 0x01b7, 1528 }, 1529 [ C(OP_PREFETCH) ] = { 1530 [ C(RESULT_ACCESS) ] = 0x01b7, 1531 [ C(RESULT_MISS) ] = 0x01b7, 1532 }, 1533 }, 1534 }; 1535 1536 static __initconst const u64 core2_hw_cache_event_ids 1537 [PERF_COUNT_HW_CACHE_MAX] 1538 [PERF_COUNT_HW_CACHE_OP_MAX] 1539 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1540 { 1541 [ C(L1D) ] = { 1542 [ C(OP_READ) ] = { 1543 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1544 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1545 }, 1546 [ C(OP_WRITE) ] = { 1547 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1548 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1549 }, 1550 [ C(OP_PREFETCH) ] = { 1551 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1552 [ C(RESULT_MISS) ] = 0, 1553 }, 1554 }, 1555 [ C(L1I ) ] = { 1556 [ C(OP_READ) ] = { 1557 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1558 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1559 }, 1560 [ C(OP_WRITE) ] = { 1561 [ C(RESULT_ACCESS) ] = -1, 1562 [ C(RESULT_MISS) ] = -1, 1563 }, 1564 [ C(OP_PREFETCH) ] = { 1565 [ C(RESULT_ACCESS) ] = 0, 1566 [ C(RESULT_MISS) ] = 0, 1567 }, 1568 }, 1569 [ C(LL ) ] = { 1570 [ C(OP_READ) ] = { 1571 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1572 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1573 }, 1574 [ C(OP_WRITE) ] = { 1575 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1576 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1577 }, 1578 [ C(OP_PREFETCH) ] = { 1579 [ C(RESULT_ACCESS) ] = 0, 1580 [ C(RESULT_MISS) ] = 0, 1581 }, 1582 }, 1583 [ C(DTLB) ] = { 1584 [ C(OP_READ) ] = { 1585 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1586 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1587 }, 1588 [ C(OP_WRITE) ] = { 1589 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1590 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1591 }, 1592 [ C(OP_PREFETCH) ] = { 1593 [ C(RESULT_ACCESS) ] = 0, 1594 [ C(RESULT_MISS) ] = 0, 1595 }, 1596 }, 1597 [ C(ITLB) ] = { 1598 [ C(OP_READ) ] = { 1599 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1600 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1601 }, 1602 [ C(OP_WRITE) ] = { 1603 [ C(RESULT_ACCESS) ] = -1, 1604 [ C(RESULT_MISS) ] = -1, 1605 }, 1606 [ C(OP_PREFETCH) ] = { 1607 [ C(RESULT_ACCESS) ] = -1, 1608 [ C(RESULT_MISS) ] = -1, 1609 }, 1610 }, 1611 [ C(BPU ) ] = { 1612 [ C(OP_READ) ] = { 1613 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1614 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1615 }, 1616 [ C(OP_WRITE) ] = { 1617 [ C(RESULT_ACCESS) ] = -1, 1618 [ C(RESULT_MISS) ] = -1, 1619 }, 1620 [ C(OP_PREFETCH) ] = { 1621 [ C(RESULT_ACCESS) ] = -1, 1622 [ C(RESULT_MISS) ] = -1, 1623 }, 1624 }, 1625 }; 1626 1627 static __initconst const u64 atom_hw_cache_event_ids 1628 [PERF_COUNT_HW_CACHE_MAX] 1629 [PERF_COUNT_HW_CACHE_OP_MAX] 1630 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1631 { 1632 [ C(L1D) ] = { 1633 [ C(OP_READ) ] = { 1634 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1635 [ C(RESULT_MISS) ] = 0, 1636 }, 1637 [ C(OP_WRITE) ] = { 1638 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1639 [ C(RESULT_MISS) ] = 0, 1640 }, 1641 [ C(OP_PREFETCH) ] = { 1642 [ C(RESULT_ACCESS) ] = 0x0, 1643 [ C(RESULT_MISS) ] = 0, 1644 }, 1645 }, 1646 [ C(L1I ) ] = { 1647 [ C(OP_READ) ] = { 1648 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1649 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1650 }, 1651 [ C(OP_WRITE) ] = { 1652 [ C(RESULT_ACCESS) ] = -1, 1653 [ C(RESULT_MISS) ] = -1, 1654 }, 1655 [ C(OP_PREFETCH) ] = { 1656 [ C(RESULT_ACCESS) ] = 0, 1657 [ C(RESULT_MISS) ] = 0, 1658 }, 1659 }, 1660 [ C(LL ) ] = { 1661 [ C(OP_READ) ] = { 1662 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1663 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1664 }, 1665 [ C(OP_WRITE) ] = { 1666 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1667 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1668 }, 1669 [ C(OP_PREFETCH) ] = { 1670 [ C(RESULT_ACCESS) ] = 0, 1671 [ C(RESULT_MISS) ] = 0, 1672 }, 1673 }, 1674 [ C(DTLB) ] = { 1675 [ C(OP_READ) ] = { 1676 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1677 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1678 }, 1679 [ C(OP_WRITE) ] = { 1680 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1681 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1682 }, 1683 [ C(OP_PREFETCH) ] = { 1684 [ C(RESULT_ACCESS) ] = 0, 1685 [ C(RESULT_MISS) ] = 0, 1686 }, 1687 }, 1688 [ C(ITLB) ] = { 1689 [ C(OP_READ) ] = { 1690 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1691 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1692 }, 1693 [ C(OP_WRITE) ] = { 1694 [ C(RESULT_ACCESS) ] = -1, 1695 [ C(RESULT_MISS) ] = -1, 1696 }, 1697 [ C(OP_PREFETCH) ] = { 1698 [ C(RESULT_ACCESS) ] = -1, 1699 [ C(RESULT_MISS) ] = -1, 1700 }, 1701 }, 1702 [ C(BPU ) ] = { 1703 [ C(OP_READ) ] = { 1704 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1705 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1706 }, 1707 [ C(OP_WRITE) ] = { 1708 [ C(RESULT_ACCESS) ] = -1, 1709 [ C(RESULT_MISS) ] = -1, 1710 }, 1711 [ C(OP_PREFETCH) ] = { 1712 [ C(RESULT_ACCESS) ] = -1, 1713 [ C(RESULT_MISS) ] = -1, 1714 }, 1715 }, 1716 }; 1717 1718 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1719 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1720 /* no_alloc_cycles.not_delivered */ 1721 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1722 "event=0xca,umask=0x50"); 1723 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1724 /* uops_retired.all */ 1725 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1726 "event=0xc2,umask=0x10"); 1727 /* uops_retired.all */ 1728 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1729 "event=0xc2,umask=0x10"); 1730 1731 static struct attribute *slm_events_attrs[] = { 1732 EVENT_PTR(td_total_slots_slm), 1733 EVENT_PTR(td_total_slots_scale_slm), 1734 EVENT_PTR(td_fetch_bubbles_slm), 1735 EVENT_PTR(td_fetch_bubbles_scale_slm), 1736 EVENT_PTR(td_slots_issued_slm), 1737 EVENT_PTR(td_slots_retired_slm), 1738 NULL 1739 }; 1740 1741 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1742 { 1743 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1744 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1745 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1746 EVENT_EXTRA_END 1747 }; 1748 1749 #define SLM_DMND_READ SNB_DMND_DATA_RD 1750 #define SLM_DMND_WRITE SNB_DMND_RFO 1751 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1752 1753 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1754 #define SLM_LLC_ACCESS SNB_RESP_ANY 1755 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1756 1757 static __initconst const u64 slm_hw_cache_extra_regs 1758 [PERF_COUNT_HW_CACHE_MAX] 1759 [PERF_COUNT_HW_CACHE_OP_MAX] 1760 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1761 { 1762 [ C(LL ) ] = { 1763 [ C(OP_READ) ] = { 1764 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1765 [ C(RESULT_MISS) ] = 0, 1766 }, 1767 [ C(OP_WRITE) ] = { 1768 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1769 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1770 }, 1771 [ C(OP_PREFETCH) ] = { 1772 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1773 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1774 }, 1775 }, 1776 }; 1777 1778 static __initconst const u64 slm_hw_cache_event_ids 1779 [PERF_COUNT_HW_CACHE_MAX] 1780 [PERF_COUNT_HW_CACHE_OP_MAX] 1781 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1782 { 1783 [ C(L1D) ] = { 1784 [ C(OP_READ) ] = { 1785 [ C(RESULT_ACCESS) ] = 0, 1786 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1787 }, 1788 [ C(OP_WRITE) ] = { 1789 [ C(RESULT_ACCESS) ] = 0, 1790 [ C(RESULT_MISS) ] = 0, 1791 }, 1792 [ C(OP_PREFETCH) ] = { 1793 [ C(RESULT_ACCESS) ] = 0, 1794 [ C(RESULT_MISS) ] = 0, 1795 }, 1796 }, 1797 [ C(L1I ) ] = { 1798 [ C(OP_READ) ] = { 1799 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1800 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1801 }, 1802 [ C(OP_WRITE) ] = { 1803 [ C(RESULT_ACCESS) ] = -1, 1804 [ C(RESULT_MISS) ] = -1, 1805 }, 1806 [ C(OP_PREFETCH) ] = { 1807 [ C(RESULT_ACCESS) ] = 0, 1808 [ C(RESULT_MISS) ] = 0, 1809 }, 1810 }, 1811 [ C(LL ) ] = { 1812 [ C(OP_READ) ] = { 1813 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1814 [ C(RESULT_ACCESS) ] = 0x01b7, 1815 [ C(RESULT_MISS) ] = 0, 1816 }, 1817 [ C(OP_WRITE) ] = { 1818 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1819 [ C(RESULT_ACCESS) ] = 0x01b7, 1820 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1821 [ C(RESULT_MISS) ] = 0x01b7, 1822 }, 1823 [ C(OP_PREFETCH) ] = { 1824 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1825 [ C(RESULT_ACCESS) ] = 0x01b7, 1826 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1827 [ C(RESULT_MISS) ] = 0x01b7, 1828 }, 1829 }, 1830 [ C(DTLB) ] = { 1831 [ C(OP_READ) ] = { 1832 [ C(RESULT_ACCESS) ] = 0, 1833 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1834 }, 1835 [ C(OP_WRITE) ] = { 1836 [ C(RESULT_ACCESS) ] = 0, 1837 [ C(RESULT_MISS) ] = 0, 1838 }, 1839 [ C(OP_PREFETCH) ] = { 1840 [ C(RESULT_ACCESS) ] = 0, 1841 [ C(RESULT_MISS) ] = 0, 1842 }, 1843 }, 1844 [ C(ITLB) ] = { 1845 [ C(OP_READ) ] = { 1846 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1847 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1848 }, 1849 [ C(OP_WRITE) ] = { 1850 [ C(RESULT_ACCESS) ] = -1, 1851 [ C(RESULT_MISS) ] = -1, 1852 }, 1853 [ C(OP_PREFETCH) ] = { 1854 [ C(RESULT_ACCESS) ] = -1, 1855 [ C(RESULT_MISS) ] = -1, 1856 }, 1857 }, 1858 [ C(BPU ) ] = { 1859 [ C(OP_READ) ] = { 1860 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1861 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1862 }, 1863 [ C(OP_WRITE) ] = { 1864 [ C(RESULT_ACCESS) ] = -1, 1865 [ C(RESULT_MISS) ] = -1, 1866 }, 1867 [ C(OP_PREFETCH) ] = { 1868 [ C(RESULT_ACCESS) ] = -1, 1869 [ C(RESULT_MISS) ] = -1, 1870 }, 1871 }, 1872 }; 1873 1874 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1875 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1876 /* UOPS_NOT_DELIVERED.ANY */ 1877 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1878 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1879 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1880 /* UOPS_RETIRED.ANY */ 1881 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1882 /* UOPS_ISSUED.ANY */ 1883 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1884 1885 static struct attribute *glm_events_attrs[] = { 1886 EVENT_PTR(td_total_slots_glm), 1887 EVENT_PTR(td_total_slots_scale_glm), 1888 EVENT_PTR(td_fetch_bubbles_glm), 1889 EVENT_PTR(td_recovery_bubbles_glm), 1890 EVENT_PTR(td_slots_issued_glm), 1891 EVENT_PTR(td_slots_retired_glm), 1892 NULL 1893 }; 1894 1895 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1896 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1897 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1898 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1899 EVENT_EXTRA_END 1900 }; 1901 1902 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 1903 #define GLM_DEMAND_RFO BIT_ULL(1) 1904 #define GLM_ANY_RESPONSE BIT_ULL(16) 1905 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1906 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1907 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1908 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1909 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1910 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1911 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1912 1913 static __initconst const u64 glm_hw_cache_event_ids 1914 [PERF_COUNT_HW_CACHE_MAX] 1915 [PERF_COUNT_HW_CACHE_OP_MAX] 1916 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1917 [C(L1D)] = { 1918 [C(OP_READ)] = { 1919 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1920 [C(RESULT_MISS)] = 0x0, 1921 }, 1922 [C(OP_WRITE)] = { 1923 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1924 [C(RESULT_MISS)] = 0x0, 1925 }, 1926 [C(OP_PREFETCH)] = { 1927 [C(RESULT_ACCESS)] = 0x0, 1928 [C(RESULT_MISS)] = 0x0, 1929 }, 1930 }, 1931 [C(L1I)] = { 1932 [C(OP_READ)] = { 1933 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1934 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1935 }, 1936 [C(OP_WRITE)] = { 1937 [C(RESULT_ACCESS)] = -1, 1938 [C(RESULT_MISS)] = -1, 1939 }, 1940 [C(OP_PREFETCH)] = { 1941 [C(RESULT_ACCESS)] = 0x0, 1942 [C(RESULT_MISS)] = 0x0, 1943 }, 1944 }, 1945 [C(LL)] = { 1946 [C(OP_READ)] = { 1947 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1948 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1949 }, 1950 [C(OP_WRITE)] = { 1951 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1952 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1953 }, 1954 [C(OP_PREFETCH)] = { 1955 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1956 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1957 }, 1958 }, 1959 [C(DTLB)] = { 1960 [C(OP_READ)] = { 1961 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1962 [C(RESULT_MISS)] = 0x0, 1963 }, 1964 [C(OP_WRITE)] = { 1965 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1966 [C(RESULT_MISS)] = 0x0, 1967 }, 1968 [C(OP_PREFETCH)] = { 1969 [C(RESULT_ACCESS)] = 0x0, 1970 [C(RESULT_MISS)] = 0x0, 1971 }, 1972 }, 1973 [C(ITLB)] = { 1974 [C(OP_READ)] = { 1975 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1976 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1977 }, 1978 [C(OP_WRITE)] = { 1979 [C(RESULT_ACCESS)] = -1, 1980 [C(RESULT_MISS)] = -1, 1981 }, 1982 [C(OP_PREFETCH)] = { 1983 [C(RESULT_ACCESS)] = -1, 1984 [C(RESULT_MISS)] = -1, 1985 }, 1986 }, 1987 [C(BPU)] = { 1988 [C(OP_READ)] = { 1989 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1990 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1991 }, 1992 [C(OP_WRITE)] = { 1993 [C(RESULT_ACCESS)] = -1, 1994 [C(RESULT_MISS)] = -1, 1995 }, 1996 [C(OP_PREFETCH)] = { 1997 [C(RESULT_ACCESS)] = -1, 1998 [C(RESULT_MISS)] = -1, 1999 }, 2000 }, 2001 }; 2002 2003 static __initconst const u64 glm_hw_cache_extra_regs 2004 [PERF_COUNT_HW_CACHE_MAX] 2005 [PERF_COUNT_HW_CACHE_OP_MAX] 2006 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2007 [C(LL)] = { 2008 [C(OP_READ)] = { 2009 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2010 GLM_LLC_ACCESS, 2011 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2012 GLM_LLC_MISS, 2013 }, 2014 [C(OP_WRITE)] = { 2015 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2016 GLM_LLC_ACCESS, 2017 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2018 GLM_LLC_MISS, 2019 }, 2020 [C(OP_PREFETCH)] = { 2021 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 2022 GLM_LLC_ACCESS, 2023 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 2024 GLM_LLC_MISS, 2025 }, 2026 }, 2027 }; 2028 2029 static __initconst const u64 glp_hw_cache_event_ids 2030 [PERF_COUNT_HW_CACHE_MAX] 2031 [PERF_COUNT_HW_CACHE_OP_MAX] 2032 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2033 [C(L1D)] = { 2034 [C(OP_READ)] = { 2035 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2036 [C(RESULT_MISS)] = 0x0, 2037 }, 2038 [C(OP_WRITE)] = { 2039 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2040 [C(RESULT_MISS)] = 0x0, 2041 }, 2042 [C(OP_PREFETCH)] = { 2043 [C(RESULT_ACCESS)] = 0x0, 2044 [C(RESULT_MISS)] = 0x0, 2045 }, 2046 }, 2047 [C(L1I)] = { 2048 [C(OP_READ)] = { 2049 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 2050 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 2051 }, 2052 [C(OP_WRITE)] = { 2053 [C(RESULT_ACCESS)] = -1, 2054 [C(RESULT_MISS)] = -1, 2055 }, 2056 [C(OP_PREFETCH)] = { 2057 [C(RESULT_ACCESS)] = 0x0, 2058 [C(RESULT_MISS)] = 0x0, 2059 }, 2060 }, 2061 [C(LL)] = { 2062 [C(OP_READ)] = { 2063 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2064 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2065 }, 2066 [C(OP_WRITE)] = { 2067 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2068 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2069 }, 2070 [C(OP_PREFETCH)] = { 2071 [C(RESULT_ACCESS)] = 0x0, 2072 [C(RESULT_MISS)] = 0x0, 2073 }, 2074 }, 2075 [C(DTLB)] = { 2076 [C(OP_READ)] = { 2077 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2078 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 2079 }, 2080 [C(OP_WRITE)] = { 2081 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2082 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 2083 }, 2084 [C(OP_PREFETCH)] = { 2085 [C(RESULT_ACCESS)] = 0x0, 2086 [C(RESULT_MISS)] = 0x0, 2087 }, 2088 }, 2089 [C(ITLB)] = { 2090 [C(OP_READ)] = { 2091 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 2092 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 2093 }, 2094 [C(OP_WRITE)] = { 2095 [C(RESULT_ACCESS)] = -1, 2096 [C(RESULT_MISS)] = -1, 2097 }, 2098 [C(OP_PREFETCH)] = { 2099 [C(RESULT_ACCESS)] = -1, 2100 [C(RESULT_MISS)] = -1, 2101 }, 2102 }, 2103 [C(BPU)] = { 2104 [C(OP_READ)] = { 2105 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 2106 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 2107 }, 2108 [C(OP_WRITE)] = { 2109 [C(RESULT_ACCESS)] = -1, 2110 [C(RESULT_MISS)] = -1, 2111 }, 2112 [C(OP_PREFETCH)] = { 2113 [C(RESULT_ACCESS)] = -1, 2114 [C(RESULT_MISS)] = -1, 2115 }, 2116 }, 2117 }; 2118 2119 static __initconst const u64 glp_hw_cache_extra_regs 2120 [PERF_COUNT_HW_CACHE_MAX] 2121 [PERF_COUNT_HW_CACHE_OP_MAX] 2122 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2123 [C(LL)] = { 2124 [C(OP_READ)] = { 2125 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2126 GLM_LLC_ACCESS, 2127 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2128 GLM_LLC_MISS, 2129 }, 2130 [C(OP_WRITE)] = { 2131 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2132 GLM_LLC_ACCESS, 2133 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2134 GLM_LLC_MISS, 2135 }, 2136 [C(OP_PREFETCH)] = { 2137 [C(RESULT_ACCESS)] = 0x0, 2138 [C(RESULT_MISS)] = 0x0, 2139 }, 2140 }, 2141 }; 2142 2143 #define TNT_LOCAL_DRAM BIT_ULL(26) 2144 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 2145 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 2146 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 2147 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 2148 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 2149 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 2150 2151 static __initconst const u64 tnt_hw_cache_extra_regs 2152 [PERF_COUNT_HW_CACHE_MAX] 2153 [PERF_COUNT_HW_CACHE_OP_MAX] 2154 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2155 [C(LL)] = { 2156 [C(OP_READ)] = { 2157 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 2158 TNT_LLC_ACCESS, 2159 [C(RESULT_MISS)] = TNT_DEMAND_READ| 2160 TNT_LLC_MISS, 2161 }, 2162 [C(OP_WRITE)] = { 2163 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 2164 TNT_LLC_ACCESS, 2165 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 2166 TNT_LLC_MISS, 2167 }, 2168 [C(OP_PREFETCH)] = { 2169 [C(RESULT_ACCESS)] = 0x0, 2170 [C(RESULT_MISS)] = 0x0, 2171 }, 2172 }, 2173 }; 2174 2175 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2176 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2177 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2178 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2179 2180 static struct attribute *tnt_events_attrs[] = { 2181 EVENT_PTR(td_fe_bound_tnt), 2182 EVENT_PTR(td_retiring_tnt), 2183 EVENT_PTR(td_bad_spec_tnt), 2184 EVENT_PTR(td_be_bound_tnt), 2185 NULL, 2186 }; 2187 2188 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 2189 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2190 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 2191 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 2192 EVENT_EXTRA_END 2193 }; 2194 2195 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3"); 2196 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6"); 2197 2198 static struct attribute *grt_mem_attrs[] = { 2199 EVENT_PTR(mem_ld_grt), 2200 EVENT_PTR(mem_st_grt), 2201 NULL 2202 }; 2203 2204 static struct extra_reg intel_grt_extra_regs[] __read_mostly = { 2205 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2206 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 2207 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 2208 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2209 EVENT_EXTRA_END 2210 }; 2211 2212 EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0"); 2213 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0"); 2214 2215 static struct attribute *cmt_events_attrs[] = { 2216 EVENT_PTR(td_fe_bound_tnt), 2217 EVENT_PTR(td_retiring_cmt), 2218 EVENT_PTR(td_bad_spec_cmt), 2219 EVENT_PTR(td_be_bound_tnt), 2220 NULL 2221 }; 2222 2223 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = { 2224 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2225 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0), 2226 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1), 2227 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2228 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0), 2229 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1), 2230 EVENT_EXTRA_END 2231 }; 2232 2233 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2234 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2235 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 2236 #define KNL_MCDRAM_FAR BIT_ULL(22) 2237 #define KNL_DDR_LOCAL BIT_ULL(23) 2238 #define KNL_DDR_FAR BIT_ULL(24) 2239 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2240 KNL_DDR_LOCAL | KNL_DDR_FAR) 2241 #define KNL_L2_READ SLM_DMND_READ 2242 #define KNL_L2_WRITE SLM_DMND_WRITE 2243 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2244 #define KNL_L2_ACCESS SLM_LLC_ACCESS 2245 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2246 KNL_DRAM_ANY | SNB_SNP_ANY | \ 2247 SNB_NON_DRAM) 2248 2249 static __initconst const u64 knl_hw_cache_extra_regs 2250 [PERF_COUNT_HW_CACHE_MAX] 2251 [PERF_COUNT_HW_CACHE_OP_MAX] 2252 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2253 [C(LL)] = { 2254 [C(OP_READ)] = { 2255 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2256 [C(RESULT_MISS)] = 0, 2257 }, 2258 [C(OP_WRITE)] = { 2259 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2260 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2261 }, 2262 [C(OP_PREFETCH)] = { 2263 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2264 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2265 }, 2266 }, 2267 }; 2268 2269 /* 2270 * Used from PMIs where the LBRs are already disabled. 2271 * 2272 * This function could be called consecutively. It is required to remain in 2273 * disabled state if called consecutively. 2274 * 2275 * During consecutive calls, the same disable value will be written to related 2276 * registers, so the PMU state remains unchanged. 2277 * 2278 * intel_bts events don't coexist with intel PMU's BTS events because of 2279 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2280 * disabled around intel PMU's event batching etc, only inside the PMI handler. 2281 * 2282 * Avoid PEBS_ENABLE MSR access in PMIs. 2283 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 2284 * It doesn't matter if the PEBS is enabled or not. 2285 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 2286 * access PEBS_ENABLE MSR in disable_all()/enable_all(). 2287 * However, there are some cases which may change PEBS status, e.g. PMI 2288 * throttle. The PEBS_ENABLE should be updated where the status changes. 2289 */ 2290 static __always_inline void __intel_pmu_disable_all(bool bts) 2291 { 2292 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2293 2294 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2295 2296 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2297 intel_pmu_disable_bts(); 2298 } 2299 2300 static __always_inline void intel_pmu_disable_all(void) 2301 { 2302 __intel_pmu_disable_all(true); 2303 intel_pmu_pebs_disable_all(); 2304 intel_pmu_lbr_disable_all(); 2305 } 2306 2307 static void __intel_pmu_enable_all(int added, bool pmi) 2308 { 2309 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2310 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2311 2312 intel_pmu_lbr_enable_all(pmi); 2313 2314 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) { 2315 wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val); 2316 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val; 2317 } 2318 2319 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 2320 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2321 2322 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2323 struct perf_event *event = 2324 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2325 2326 if (WARN_ON_ONCE(!event)) 2327 return; 2328 2329 intel_pmu_enable_bts(event->hw.config); 2330 } 2331 } 2332 2333 static void intel_pmu_enable_all(int added) 2334 { 2335 intel_pmu_pebs_enable_all(); 2336 __intel_pmu_enable_all(added, false); 2337 } 2338 2339 static noinline int 2340 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, 2341 unsigned int cnt, unsigned long flags) 2342 { 2343 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2344 2345 intel_pmu_lbr_read(); 2346 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); 2347 2348 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); 2349 intel_pmu_enable_all(0); 2350 local_irq_restore(flags); 2351 return cnt; 2352 } 2353 2354 static int 2355 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2356 { 2357 unsigned long flags; 2358 2359 /* must not have branches... */ 2360 local_irq_save(flags); 2361 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2362 __intel_pmu_lbr_disable(); 2363 /* ... until here */ 2364 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2365 } 2366 2367 static int 2368 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2369 { 2370 unsigned long flags; 2371 2372 /* must not have branches... */ 2373 local_irq_save(flags); 2374 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2375 __intel_pmu_arch_lbr_disable(); 2376 /* ... until here */ 2377 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2378 } 2379 2380 /* 2381 * Workaround for: 2382 * Intel Errata AAK100 (model 26) 2383 * Intel Errata AAP53 (model 30) 2384 * Intel Errata BD53 (model 44) 2385 * 2386 * The official story: 2387 * These chips need to be 'reset' when adding counters by programming the 2388 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2389 * in sequence on the same PMC or on different PMCs. 2390 * 2391 * In practice it appears some of these events do in fact count, and 2392 * we need to program all 4 events. 2393 */ 2394 static void intel_pmu_nhm_workaround(void) 2395 { 2396 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2397 static const unsigned long nhm_magic[4] = { 2398 0x4300B5, 2399 0x4300D2, 2400 0x4300B1, 2401 0x4300B1 2402 }; 2403 struct perf_event *event; 2404 int i; 2405 2406 /* 2407 * The Errata requires below steps: 2408 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2409 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2410 * the corresponding PMCx; 2411 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2412 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2413 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2414 */ 2415 2416 /* 2417 * The real steps we choose are a little different from above. 2418 * A) To reduce MSR operations, we don't run step 1) as they 2419 * are already cleared before this function is called; 2420 * B) Call x86_perf_event_update to save PMCx before configuring 2421 * PERFEVTSELx with magic number; 2422 * C) With step 5), we do clear only when the PERFEVTSELx is 2423 * not used currently. 2424 * D) Call x86_perf_event_set_period to restore PMCx; 2425 */ 2426 2427 /* We always operate 4 pairs of PERF Counters */ 2428 for (i = 0; i < 4; i++) { 2429 event = cpuc->events[i]; 2430 if (event) 2431 static_call(x86_pmu_update)(event); 2432 } 2433 2434 for (i = 0; i < 4; i++) { 2435 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2436 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2437 } 2438 2439 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2440 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2441 2442 for (i = 0; i < 4; i++) { 2443 event = cpuc->events[i]; 2444 2445 if (event) { 2446 static_call(x86_pmu_set_period)(event); 2447 __x86_pmu_enable_event(&event->hw, 2448 ARCH_PERFMON_EVENTSEL_ENABLE); 2449 } else 2450 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2451 } 2452 } 2453 2454 static void intel_pmu_nhm_enable_all(int added) 2455 { 2456 if (added) 2457 intel_pmu_nhm_workaround(); 2458 intel_pmu_enable_all(added); 2459 } 2460 2461 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2462 { 2463 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2464 2465 if (cpuc->tfa_shadow != val) { 2466 cpuc->tfa_shadow = val; 2467 wrmsrl(MSR_TSX_FORCE_ABORT, val); 2468 } 2469 } 2470 2471 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2472 { 2473 /* 2474 * We're going to use PMC3, make sure TFA is set before we touch it. 2475 */ 2476 if (cntr == 3) 2477 intel_set_tfa(cpuc, true); 2478 } 2479 2480 static void intel_tfa_pmu_enable_all(int added) 2481 { 2482 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2483 2484 /* 2485 * If we find PMC3 is no longer used when we enable the PMU, we can 2486 * clear TFA. 2487 */ 2488 if (!test_bit(3, cpuc->active_mask)) 2489 intel_set_tfa(cpuc, false); 2490 2491 intel_pmu_enable_all(added); 2492 } 2493 2494 static inline u64 intel_pmu_get_status(void) 2495 { 2496 u64 status; 2497 2498 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2499 2500 return status; 2501 } 2502 2503 static inline void intel_pmu_ack_status(u64 ack) 2504 { 2505 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2506 } 2507 2508 static inline bool event_is_checkpointed(struct perf_event *event) 2509 { 2510 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2511 } 2512 2513 static inline void intel_set_masks(struct perf_event *event, int idx) 2514 { 2515 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2516 2517 if (event->attr.exclude_host) 2518 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2519 if (event->attr.exclude_guest) 2520 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2521 if (event_is_checkpointed(event)) 2522 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2523 } 2524 2525 static inline void intel_clear_masks(struct perf_event *event, int idx) 2526 { 2527 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2528 2529 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2530 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2531 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2532 } 2533 2534 static void intel_pmu_disable_fixed(struct perf_event *event) 2535 { 2536 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2537 struct hw_perf_event *hwc = &event->hw; 2538 int idx = hwc->idx; 2539 u64 mask; 2540 2541 if (is_topdown_idx(idx)) { 2542 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2543 2544 /* 2545 * When there are other active TopDown events, 2546 * don't disable the fixed counter 3. 2547 */ 2548 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2549 return; 2550 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2551 } 2552 2553 intel_clear_masks(event, idx); 2554 2555 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK); 2556 cpuc->fixed_ctrl_val &= ~mask; 2557 } 2558 2559 static void intel_pmu_disable_event(struct perf_event *event) 2560 { 2561 struct hw_perf_event *hwc = &event->hw; 2562 int idx = hwc->idx; 2563 2564 switch (idx) { 2565 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2566 intel_clear_masks(event, idx); 2567 x86_pmu_disable_event(event); 2568 break; 2569 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2570 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2571 intel_pmu_disable_fixed(event); 2572 break; 2573 case INTEL_PMC_IDX_FIXED_BTS: 2574 intel_pmu_disable_bts(); 2575 intel_pmu_drain_bts_buffer(); 2576 return; 2577 case INTEL_PMC_IDX_FIXED_VLBR: 2578 intel_clear_masks(event, idx); 2579 break; 2580 default: 2581 intel_clear_masks(event, idx); 2582 pr_warn("Failed to disable the event with invalid index %d\n", 2583 idx); 2584 return; 2585 } 2586 2587 /* 2588 * Needs to be called after x86_pmu_disable_event, 2589 * so we don't trigger the event without PEBS bit set. 2590 */ 2591 if (unlikely(event->attr.precise_ip)) 2592 intel_pmu_pebs_disable(event); 2593 } 2594 2595 static void intel_pmu_assign_event(struct perf_event *event, int idx) 2596 { 2597 if (is_pebs_pt(event)) 2598 perf_report_aux_output_id(event, idx); 2599 } 2600 2601 static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event) 2602 { 2603 return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK; 2604 } 2605 2606 static void intel_pmu_del_event(struct perf_event *event) 2607 { 2608 if (intel_pmu_needs_branch_stack(event)) 2609 intel_pmu_lbr_del(event); 2610 if (event->attr.precise_ip) 2611 intel_pmu_pebs_del(event); 2612 } 2613 2614 static int icl_set_topdown_event_period(struct perf_event *event) 2615 { 2616 struct hw_perf_event *hwc = &event->hw; 2617 s64 left = local64_read(&hwc->period_left); 2618 2619 /* 2620 * The values in PERF_METRICS MSR are derived from fixed counter 3. 2621 * Software should start both registers, PERF_METRICS and fixed 2622 * counter 3, from zero. 2623 * Clear PERF_METRICS and Fixed counter 3 in initialization. 2624 * After that, both MSRs will be cleared for each read. 2625 * Don't need to clear them again. 2626 */ 2627 if (left == x86_pmu.max_period) { 2628 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2629 wrmsrl(MSR_PERF_METRICS, 0); 2630 hwc->saved_slots = 0; 2631 hwc->saved_metric = 0; 2632 } 2633 2634 if ((hwc->saved_slots) && is_slots_event(event)) { 2635 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2636 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric); 2637 } 2638 2639 perf_event_update_userpage(event); 2640 2641 return 0; 2642 } 2643 2644 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period); 2645 2646 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 2647 { 2648 u32 val; 2649 2650 /* 2651 * The metric is reported as an 8bit integer fraction 2652 * summing up to 0xff. 2653 * slots-in-metric = (Metric / 0xff) * slots 2654 */ 2655 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 2656 return mul_u64_u32_div(slots, val, 0xff); 2657 } 2658 2659 static u64 icl_get_topdown_value(struct perf_event *event, 2660 u64 slots, u64 metrics) 2661 { 2662 int idx = event->hw.idx; 2663 u64 delta; 2664 2665 if (is_metric_idx(idx)) 2666 delta = icl_get_metrics_event_value(metrics, slots, idx); 2667 else 2668 delta = slots; 2669 2670 return delta; 2671 } 2672 2673 static void __icl_update_topdown_event(struct perf_event *event, 2674 u64 slots, u64 metrics, 2675 u64 last_slots, u64 last_metrics) 2676 { 2677 u64 delta, last = 0; 2678 2679 delta = icl_get_topdown_value(event, slots, metrics); 2680 if (last_slots) 2681 last = icl_get_topdown_value(event, last_slots, last_metrics); 2682 2683 /* 2684 * The 8bit integer fraction of metric may be not accurate, 2685 * especially when the changes is very small. 2686 * For example, if only a few bad_spec happens, the fraction 2687 * may be reduced from 1 to 0. If so, the bad_spec event value 2688 * will be 0 which is definitely less than the last value. 2689 * Avoid update event->count for this case. 2690 */ 2691 if (delta > last) { 2692 delta -= last; 2693 local64_add(delta, &event->count); 2694 } 2695 } 2696 2697 static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 2698 u64 metrics, int metric_end) 2699 { 2700 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2701 struct perf_event *other; 2702 int idx; 2703 2704 event->hw.saved_slots = slots; 2705 event->hw.saved_metric = metrics; 2706 2707 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2708 if (!is_topdown_idx(idx)) 2709 continue; 2710 other = cpuc->events[idx]; 2711 other->hw.saved_slots = slots; 2712 other->hw.saved_metric = metrics; 2713 } 2714 } 2715 2716 /* 2717 * Update all active Topdown events. 2718 * 2719 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 2720 * modify by a NMI. PMU has to be disabled before calling this function. 2721 */ 2722 2723 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end) 2724 { 2725 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2726 struct perf_event *other; 2727 u64 slots, metrics; 2728 bool reset = true; 2729 int idx; 2730 2731 /* read Fixed counter 3 */ 2732 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); 2733 if (!slots) 2734 return 0; 2735 2736 /* read PERF_METRICS */ 2737 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); 2738 2739 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2740 if (!is_topdown_idx(idx)) 2741 continue; 2742 other = cpuc->events[idx]; 2743 __icl_update_topdown_event(other, slots, metrics, 2744 event ? event->hw.saved_slots : 0, 2745 event ? event->hw.saved_metric : 0); 2746 } 2747 2748 /* 2749 * Check and update this event, which may have been cleared 2750 * in active_mask e.g. x86_pmu_stop() 2751 */ 2752 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 2753 __icl_update_topdown_event(event, slots, metrics, 2754 event->hw.saved_slots, 2755 event->hw.saved_metric); 2756 2757 /* 2758 * In x86_pmu_stop(), the event is cleared in active_mask first, 2759 * then drain the delta, which indicates context switch for 2760 * counting. 2761 * Save metric and slots for context switch. 2762 * Don't need to reset the PERF_METRICS and Fixed counter 3. 2763 * Because the values will be restored in next schedule in. 2764 */ 2765 update_saved_topdown_regs(event, slots, metrics, metric_end); 2766 reset = false; 2767 } 2768 2769 if (reset) { 2770 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 2771 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2772 wrmsrl(MSR_PERF_METRICS, 0); 2773 if (event) 2774 update_saved_topdown_regs(event, 0, 0, metric_end); 2775 } 2776 2777 return slots; 2778 } 2779 2780 static u64 icl_update_topdown_event(struct perf_event *event) 2781 { 2782 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 2783 x86_pmu.num_topdown_events - 1); 2784 } 2785 2786 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, x86_perf_event_update); 2787 2788 static void intel_pmu_read_topdown_event(struct perf_event *event) 2789 { 2790 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2791 2792 /* Only need to call update_topdown_event() once for group read. */ 2793 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) && 2794 !is_slots_event(event)) 2795 return; 2796 2797 perf_pmu_disable(event->pmu); 2798 static_call(intel_pmu_update_topdown_event)(event); 2799 perf_pmu_enable(event->pmu); 2800 } 2801 2802 static void intel_pmu_read_event(struct perf_event *event) 2803 { 2804 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2805 intel_pmu_auto_reload_read(event); 2806 else if (is_topdown_count(event)) 2807 intel_pmu_read_topdown_event(event); 2808 else 2809 x86_perf_event_update(event); 2810 } 2811 2812 static void intel_pmu_enable_fixed(struct perf_event *event) 2813 { 2814 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2815 struct hw_perf_event *hwc = &event->hw; 2816 u64 mask, bits = 0; 2817 int idx = hwc->idx; 2818 2819 if (is_topdown_idx(idx)) { 2820 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2821 /* 2822 * When there are other active TopDown events, 2823 * don't enable the fixed counter 3 again. 2824 */ 2825 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2826 return; 2827 2828 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2829 } 2830 2831 intel_set_masks(event, idx); 2832 2833 /* 2834 * Enable IRQ generation (0x8), if not PEBS, 2835 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2836 * if requested: 2837 */ 2838 if (!event->attr.precise_ip) 2839 bits |= INTEL_FIXED_0_ENABLE_PMI; 2840 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2841 bits |= INTEL_FIXED_0_USER; 2842 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2843 bits |= INTEL_FIXED_0_KERNEL; 2844 2845 /* 2846 * ANY bit is supported in v3 and up 2847 */ 2848 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2849 bits |= INTEL_FIXED_0_ANYTHREAD; 2850 2851 idx -= INTEL_PMC_IDX_FIXED; 2852 bits = intel_fixed_bits_by_idx(idx, bits); 2853 mask = intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK); 2854 2855 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2856 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); 2857 mask |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); 2858 } 2859 2860 cpuc->fixed_ctrl_val &= ~mask; 2861 cpuc->fixed_ctrl_val |= bits; 2862 } 2863 2864 static void intel_pmu_enable_event(struct perf_event *event) 2865 { 2866 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE; 2867 struct hw_perf_event *hwc = &event->hw; 2868 int idx = hwc->idx; 2869 2870 if (unlikely(event->attr.precise_ip)) 2871 intel_pmu_pebs_enable(event); 2872 2873 switch (idx) { 2874 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2875 if (branch_sample_counters(event)) 2876 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR; 2877 intel_set_masks(event, idx); 2878 __x86_pmu_enable_event(hwc, enable_mask); 2879 break; 2880 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2881 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2882 intel_pmu_enable_fixed(event); 2883 break; 2884 case INTEL_PMC_IDX_FIXED_BTS: 2885 if (!__this_cpu_read(cpu_hw_events.enabled)) 2886 return; 2887 intel_pmu_enable_bts(hwc->config); 2888 break; 2889 case INTEL_PMC_IDX_FIXED_VLBR: 2890 intel_set_masks(event, idx); 2891 break; 2892 default: 2893 pr_warn("Failed to enable the event with invalid index %d\n", 2894 idx); 2895 } 2896 } 2897 2898 static void intel_pmu_add_event(struct perf_event *event) 2899 { 2900 if (event->attr.precise_ip) 2901 intel_pmu_pebs_add(event); 2902 if (intel_pmu_needs_branch_stack(event)) 2903 intel_pmu_lbr_add(event); 2904 } 2905 2906 /* 2907 * Save and restart an expired event. Called by NMI contexts, 2908 * so it has to be careful about preempting normal event ops: 2909 */ 2910 int intel_pmu_save_and_restart(struct perf_event *event) 2911 { 2912 static_call(x86_pmu_update)(event); 2913 /* 2914 * For a checkpointed counter always reset back to 0. This 2915 * avoids a situation where the counter overflows, aborts the 2916 * transaction and is then set back to shortly before the 2917 * overflow, and overflows and aborts again. 2918 */ 2919 if (unlikely(event_is_checkpointed(event))) { 2920 /* No race with NMIs because the counter should not be armed */ 2921 wrmsrl(event->hw.event_base, 0); 2922 local64_set(&event->hw.prev_count, 0); 2923 } 2924 return static_call(x86_pmu_set_period)(event); 2925 } 2926 2927 static int intel_pmu_set_period(struct perf_event *event) 2928 { 2929 if (unlikely(is_topdown_count(event))) 2930 return static_call(intel_pmu_set_topdown_event_period)(event); 2931 2932 return x86_perf_event_set_period(event); 2933 } 2934 2935 static u64 intel_pmu_update(struct perf_event *event) 2936 { 2937 if (unlikely(is_topdown_count(event))) 2938 return static_call(intel_pmu_update_topdown_event)(event); 2939 2940 return x86_perf_event_update(event); 2941 } 2942 2943 static void intel_pmu_reset(void) 2944 { 2945 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2946 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2947 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask); 2948 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask); 2949 unsigned long flags; 2950 int idx; 2951 2952 if (!*(u64 *)cntr_mask) 2953 return; 2954 2955 local_irq_save(flags); 2956 2957 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2958 2959 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) { 2960 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2961 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2962 } 2963 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) { 2964 if (fixed_counter_disabled(idx, cpuc->pmu)) 2965 continue; 2966 wrmsrl_safe(x86_pmu_fixed_ctr_addr(idx), 0ull); 2967 } 2968 2969 if (ds) 2970 ds->bts_index = ds->bts_buffer_base; 2971 2972 /* Ack all overflows and disable fixed counters */ 2973 if (x86_pmu.version >= 2) { 2974 intel_pmu_ack_status(intel_pmu_get_status()); 2975 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2976 } 2977 2978 /* Reset LBRs and LBR freezing */ 2979 if (x86_pmu.lbr_nr) { 2980 update_debugctlmsr(get_debugctlmsr() & 2981 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2982 } 2983 2984 local_irq_restore(flags); 2985 } 2986 2987 /* 2988 * We may be running with guest PEBS events created by KVM, and the 2989 * PEBS records are logged into the guest's DS and invisible to host. 2990 * 2991 * In the case of guest PEBS overflow, we only trigger a fake event 2992 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM. 2993 * The guest will then vm-entry and check the guest DS area to read 2994 * the guest PEBS records. 2995 * 2996 * The contents and other behavior of the guest event do not matter. 2997 */ 2998 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs, 2999 struct perf_sample_data *data) 3000 { 3001 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3002 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask; 3003 struct perf_event *event = NULL; 3004 int bit; 3005 3006 if (!unlikely(perf_guest_state())) 3007 return; 3008 3009 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active || 3010 !guest_pebs_idxs) 3011 return; 3012 3013 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) { 3014 event = cpuc->events[bit]; 3015 if (!event->attr.precise_ip) 3016 continue; 3017 3018 perf_sample_data_init(data, 0, event->hw.last_period); 3019 if (perf_event_overflow(event, data, regs)) 3020 x86_pmu_stop(event, 0); 3021 3022 /* Inject one fake event is enough. */ 3023 break; 3024 } 3025 } 3026 3027 static int handle_pmi_common(struct pt_regs *regs, u64 status) 3028 { 3029 struct perf_sample_data data; 3030 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3031 int bit; 3032 int handled = 0; 3033 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 3034 3035 inc_irq_stat(apic_perf_irqs); 3036 3037 /* 3038 * Ignore a range of extra bits in status that do not indicate 3039 * overflow by themselves. 3040 */ 3041 status &= ~(GLOBAL_STATUS_COND_CHG | 3042 GLOBAL_STATUS_ASIF | 3043 GLOBAL_STATUS_LBRS_FROZEN); 3044 if (!status) 3045 return 0; 3046 /* 3047 * In case multiple PEBS events are sampled at the same time, 3048 * it is possible to have GLOBAL_STATUS bit 62 set indicating 3049 * PEBS buffer overflow and also seeing at most 3 PEBS counters 3050 * having their bits set in the status register. This is a sign 3051 * that there was at least one PEBS record pending at the time 3052 * of the PMU interrupt. PEBS counters must only be processed 3053 * via the drain_pebs() calls and not via the regular sample 3054 * processing loop coming after that the function, otherwise 3055 * phony regular samples may be generated in the sampling buffer 3056 * not marked with the EXACT tag. Another possibility is to have 3057 * one PEBS event and at least one non-PEBS event which overflows 3058 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 3059 * not be set, yet the overflow status bit for the PEBS counter will 3060 * be on Skylake. 3061 * 3062 * To avoid this problem, we systematically ignore the PEBS-enabled 3063 * counters from the GLOBAL_STATUS mask and we always process PEBS 3064 * events via drain_pebs(). 3065 */ 3066 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable); 3067 3068 /* 3069 * PEBS overflow sets bit 62 in the global status register 3070 */ 3071 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 3072 u64 pebs_enabled = cpuc->pebs_enabled; 3073 3074 handled++; 3075 x86_pmu_handle_guest_pebs(regs, &data); 3076 x86_pmu.drain_pebs(regs, &data); 3077 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 3078 3079 /* 3080 * PMI throttle may be triggered, which stops the PEBS event. 3081 * Although cpuc->pebs_enabled is updated accordingly, the 3082 * MSR_IA32_PEBS_ENABLE is not updated. Because the 3083 * cpuc->enabled has been forced to 0 in PMI. 3084 * Update the MSR if pebs_enabled is changed. 3085 */ 3086 if (pebs_enabled != cpuc->pebs_enabled) 3087 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 3088 } 3089 3090 /* 3091 * Intel PT 3092 */ 3093 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 3094 handled++; 3095 if (!perf_guest_handle_intel_pt_intr()) 3096 intel_pt_interrupt(); 3097 } 3098 3099 /* 3100 * Intel Perf metrics 3101 */ 3102 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 3103 handled++; 3104 static_call(intel_pmu_update_topdown_event)(NULL); 3105 } 3106 3107 /* 3108 * Checkpointed counters can lead to 'spurious' PMIs because the 3109 * rollback caused by the PMI will have cleared the overflow status 3110 * bit. Therefore always force probe these counters. 3111 */ 3112 status |= cpuc->intel_cp_status; 3113 3114 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 3115 struct perf_event *event = cpuc->events[bit]; 3116 3117 handled++; 3118 3119 if (!test_bit(bit, cpuc->active_mask)) 3120 continue; 3121 3122 if (!intel_pmu_save_and_restart(event)) 3123 continue; 3124 3125 perf_sample_data_init(&data, 0, event->hw.last_period); 3126 3127 if (has_branch_stack(event)) 3128 intel_pmu_lbr_save_brstack(&data, cpuc, event); 3129 3130 if (perf_event_overflow(event, &data, regs)) 3131 x86_pmu_stop(event, 0); 3132 } 3133 3134 return handled; 3135 } 3136 3137 /* 3138 * This handler is triggered by the local APIC, so the APIC IRQ handling 3139 * rules apply: 3140 */ 3141 static int intel_pmu_handle_irq(struct pt_regs *regs) 3142 { 3143 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3144 bool late_ack = hybrid_bit(cpuc->pmu, late_ack); 3145 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); 3146 int loops; 3147 u64 status; 3148 int handled; 3149 int pmu_enabled; 3150 3151 /* 3152 * Save the PMU state. 3153 * It needs to be restored when leaving the handler. 3154 */ 3155 pmu_enabled = cpuc->enabled; 3156 /* 3157 * In general, the early ACK is only applied for old platforms. 3158 * For the big core starts from Haswell, the late ACK should be 3159 * applied. 3160 * For the small core after Tremont, we have to do the ACK right 3161 * before re-enabling counters, which is in the middle of the 3162 * NMI handler. 3163 */ 3164 if (!late_ack && !mid_ack) 3165 apic_write(APIC_LVTPC, APIC_DM_NMI); 3166 intel_bts_disable_local(); 3167 cpuc->enabled = 0; 3168 __intel_pmu_disable_all(true); 3169 handled = intel_pmu_drain_bts_buffer(); 3170 handled += intel_bts_interrupt(); 3171 status = intel_pmu_get_status(); 3172 if (!status) 3173 goto done; 3174 3175 loops = 0; 3176 again: 3177 intel_pmu_lbr_read(); 3178 intel_pmu_ack_status(status); 3179 if (++loops > 100) { 3180 static bool warned; 3181 3182 if (!warned) { 3183 WARN(1, "perfevents: irq loop stuck!\n"); 3184 perf_event_print_debug(); 3185 warned = true; 3186 } 3187 intel_pmu_reset(); 3188 goto done; 3189 } 3190 3191 handled += handle_pmi_common(regs, status); 3192 3193 /* 3194 * Repeat if there is more work to be done: 3195 */ 3196 status = intel_pmu_get_status(); 3197 if (status) 3198 goto again; 3199 3200 done: 3201 if (mid_ack) 3202 apic_write(APIC_LVTPC, APIC_DM_NMI); 3203 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 3204 cpuc->enabled = pmu_enabled; 3205 if (pmu_enabled) 3206 __intel_pmu_enable_all(0, true); 3207 intel_bts_enable_local(); 3208 3209 /* 3210 * Only unmask the NMI after the overflow counters 3211 * have been reset. This avoids spurious NMIs on 3212 * Haswell CPUs. 3213 */ 3214 if (late_ack) 3215 apic_write(APIC_LVTPC, APIC_DM_NMI); 3216 return handled; 3217 } 3218 3219 static struct event_constraint * 3220 intel_bts_constraints(struct perf_event *event) 3221 { 3222 if (unlikely(intel_pmu_has_bts(event))) 3223 return &bts_constraint; 3224 3225 return NULL; 3226 } 3227 3228 /* 3229 * Note: matches a fake event, like Fixed2. 3230 */ 3231 static struct event_constraint * 3232 intel_vlbr_constraints(struct perf_event *event) 3233 { 3234 struct event_constraint *c = &vlbr_constraint; 3235 3236 if (unlikely(constraint_match(c, event->hw.config))) { 3237 event->hw.flags |= c->flags; 3238 return c; 3239 } 3240 3241 return NULL; 3242 } 3243 3244 static int intel_alt_er(struct cpu_hw_events *cpuc, 3245 int idx, u64 config) 3246 { 3247 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); 3248 int alt_idx = idx; 3249 3250 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 3251 return idx; 3252 3253 if (idx == EXTRA_REG_RSP_0) 3254 alt_idx = EXTRA_REG_RSP_1; 3255 3256 if (idx == EXTRA_REG_RSP_1) 3257 alt_idx = EXTRA_REG_RSP_0; 3258 3259 if (config & ~extra_regs[alt_idx].valid_mask) 3260 return idx; 3261 3262 return alt_idx; 3263 } 3264 3265 static void intel_fixup_er(struct perf_event *event, int idx) 3266 { 3267 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); 3268 event->hw.extra_reg.idx = idx; 3269 3270 if (idx == EXTRA_REG_RSP_0) { 3271 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3272 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event; 3273 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 3274 } else if (idx == EXTRA_REG_RSP_1) { 3275 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3276 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event; 3277 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 3278 } 3279 } 3280 3281 /* 3282 * manage allocation of shared extra msr for certain events 3283 * 3284 * sharing can be: 3285 * per-cpu: to be shared between the various events on a single PMU 3286 * per-core: per-cpu + shared by HT threads 3287 */ 3288 static struct event_constraint * 3289 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 3290 struct perf_event *event, 3291 struct hw_perf_event_extra *reg) 3292 { 3293 struct event_constraint *c = &emptyconstraint; 3294 struct er_account *era; 3295 unsigned long flags; 3296 int idx = reg->idx; 3297 3298 /* 3299 * reg->alloc can be set due to existing state, so for fake cpuc we 3300 * need to ignore this, otherwise we might fail to allocate proper fake 3301 * state for this extra reg constraint. Also see the comment below. 3302 */ 3303 if (reg->alloc && !cpuc->is_fake) 3304 return NULL; /* call x86_get_event_constraint() */ 3305 3306 again: 3307 era = &cpuc->shared_regs->regs[idx]; 3308 /* 3309 * we use spin_lock_irqsave() to avoid lockdep issues when 3310 * passing a fake cpuc 3311 */ 3312 raw_spin_lock_irqsave(&era->lock, flags); 3313 3314 if (!atomic_read(&era->ref) || era->config == reg->config) { 3315 3316 /* 3317 * If its a fake cpuc -- as per validate_{group,event}() we 3318 * shouldn't touch event state and we can avoid doing so 3319 * since both will only call get_event_constraints() once 3320 * on each event, this avoids the need for reg->alloc. 3321 * 3322 * Not doing the ER fixup will only result in era->reg being 3323 * wrong, but since we won't actually try and program hardware 3324 * this isn't a problem either. 3325 */ 3326 if (!cpuc->is_fake) { 3327 if (idx != reg->idx) 3328 intel_fixup_er(event, idx); 3329 3330 /* 3331 * x86_schedule_events() can call get_event_constraints() 3332 * multiple times on events in the case of incremental 3333 * scheduling(). reg->alloc ensures we only do the ER 3334 * allocation once. 3335 */ 3336 reg->alloc = 1; 3337 } 3338 3339 /* lock in msr value */ 3340 era->config = reg->config; 3341 era->reg = reg->reg; 3342 3343 /* one more user */ 3344 atomic_inc(&era->ref); 3345 3346 /* 3347 * need to call x86_get_event_constraint() 3348 * to check if associated event has constraints 3349 */ 3350 c = NULL; 3351 } else { 3352 idx = intel_alt_er(cpuc, idx, reg->config); 3353 if (idx != reg->idx) { 3354 raw_spin_unlock_irqrestore(&era->lock, flags); 3355 goto again; 3356 } 3357 } 3358 raw_spin_unlock_irqrestore(&era->lock, flags); 3359 3360 return c; 3361 } 3362 3363 static void 3364 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3365 struct hw_perf_event_extra *reg) 3366 { 3367 struct er_account *era; 3368 3369 /* 3370 * Only put constraint if extra reg was actually allocated. Also takes 3371 * care of event which do not use an extra shared reg. 3372 * 3373 * Also, if this is a fake cpuc we shouldn't touch any event state 3374 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3375 * either since it'll be thrown out. 3376 */ 3377 if (!reg->alloc || cpuc->is_fake) 3378 return; 3379 3380 era = &cpuc->shared_regs->regs[reg->idx]; 3381 3382 /* one fewer user */ 3383 atomic_dec(&era->ref); 3384 3385 /* allocate again next time */ 3386 reg->alloc = 0; 3387 } 3388 3389 static struct event_constraint * 3390 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3391 struct perf_event *event) 3392 { 3393 struct event_constraint *c = NULL, *d; 3394 struct hw_perf_event_extra *xreg, *breg; 3395 3396 xreg = &event->hw.extra_reg; 3397 if (xreg->idx != EXTRA_REG_NONE) { 3398 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3399 if (c == &emptyconstraint) 3400 return c; 3401 } 3402 breg = &event->hw.branch_reg; 3403 if (breg->idx != EXTRA_REG_NONE) { 3404 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3405 if (d == &emptyconstraint) { 3406 __intel_shared_reg_put_constraints(cpuc, xreg); 3407 c = d; 3408 } 3409 } 3410 return c; 3411 } 3412 3413 struct event_constraint * 3414 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3415 struct perf_event *event) 3416 { 3417 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); 3418 struct event_constraint *c; 3419 3420 if (event_constraints) { 3421 for_each_event_constraint(c, event_constraints) { 3422 if (constraint_match(c, event->hw.config)) { 3423 event->hw.flags |= c->flags; 3424 return c; 3425 } 3426 } 3427 } 3428 3429 return &hybrid_var(cpuc->pmu, unconstrained); 3430 } 3431 3432 static struct event_constraint * 3433 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3434 struct perf_event *event) 3435 { 3436 struct event_constraint *c; 3437 3438 c = intel_vlbr_constraints(event); 3439 if (c) 3440 return c; 3441 3442 c = intel_bts_constraints(event); 3443 if (c) 3444 return c; 3445 3446 c = intel_shared_regs_constraints(cpuc, event); 3447 if (c) 3448 return c; 3449 3450 c = intel_pebs_constraints(event); 3451 if (c) 3452 return c; 3453 3454 return x86_get_event_constraints(cpuc, idx, event); 3455 } 3456 3457 static void 3458 intel_start_scheduling(struct cpu_hw_events *cpuc) 3459 { 3460 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3461 struct intel_excl_states *xl; 3462 int tid = cpuc->excl_thread_id; 3463 3464 /* 3465 * nothing needed if in group validation mode 3466 */ 3467 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3468 return; 3469 3470 /* 3471 * no exclusion needed 3472 */ 3473 if (WARN_ON_ONCE(!excl_cntrs)) 3474 return; 3475 3476 xl = &excl_cntrs->states[tid]; 3477 3478 xl->sched_started = true; 3479 /* 3480 * lock shared state until we are done scheduling 3481 * in stop_event_scheduling() 3482 * makes scheduling appear as a transaction 3483 */ 3484 raw_spin_lock(&excl_cntrs->lock); 3485 } 3486 3487 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3488 { 3489 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3490 struct event_constraint *c = cpuc->event_constraint[idx]; 3491 struct intel_excl_states *xl; 3492 int tid = cpuc->excl_thread_id; 3493 3494 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3495 return; 3496 3497 if (WARN_ON_ONCE(!excl_cntrs)) 3498 return; 3499 3500 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3501 return; 3502 3503 xl = &excl_cntrs->states[tid]; 3504 3505 lockdep_assert_held(&excl_cntrs->lock); 3506 3507 if (c->flags & PERF_X86_EVENT_EXCL) 3508 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3509 else 3510 xl->state[cntr] = INTEL_EXCL_SHARED; 3511 } 3512 3513 static void 3514 intel_stop_scheduling(struct cpu_hw_events *cpuc) 3515 { 3516 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3517 struct intel_excl_states *xl; 3518 int tid = cpuc->excl_thread_id; 3519 3520 /* 3521 * nothing needed if in group validation mode 3522 */ 3523 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3524 return; 3525 /* 3526 * no exclusion needed 3527 */ 3528 if (WARN_ON_ONCE(!excl_cntrs)) 3529 return; 3530 3531 xl = &excl_cntrs->states[tid]; 3532 3533 xl->sched_started = false; 3534 /* 3535 * release shared state lock (acquired in intel_start_scheduling()) 3536 */ 3537 raw_spin_unlock(&excl_cntrs->lock); 3538 } 3539 3540 static struct event_constraint * 3541 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 3542 { 3543 WARN_ON_ONCE(!cpuc->constraint_list); 3544 3545 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 3546 struct event_constraint *cx; 3547 3548 /* 3549 * grab pre-allocated constraint entry 3550 */ 3551 cx = &cpuc->constraint_list[idx]; 3552 3553 /* 3554 * initialize dynamic constraint 3555 * with static constraint 3556 */ 3557 *cx = *c; 3558 3559 /* 3560 * mark constraint as dynamic 3561 */ 3562 cx->flags |= PERF_X86_EVENT_DYNAMIC; 3563 c = cx; 3564 } 3565 3566 return c; 3567 } 3568 3569 static struct event_constraint * 3570 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3571 int idx, struct event_constraint *c) 3572 { 3573 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3574 struct intel_excl_states *xlo; 3575 int tid = cpuc->excl_thread_id; 3576 int is_excl, i, w; 3577 3578 /* 3579 * validating a group does not require 3580 * enforcing cross-thread exclusion 3581 */ 3582 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3583 return c; 3584 3585 /* 3586 * no exclusion needed 3587 */ 3588 if (WARN_ON_ONCE(!excl_cntrs)) 3589 return c; 3590 3591 /* 3592 * because we modify the constraint, we need 3593 * to make a copy. Static constraints come 3594 * from static const tables. 3595 * 3596 * only needed when constraint has not yet 3597 * been cloned (marked dynamic) 3598 */ 3599 c = dyn_constraint(cpuc, c, idx); 3600 3601 /* 3602 * From here on, the constraint is dynamic. 3603 * Either it was just allocated above, or it 3604 * was allocated during a earlier invocation 3605 * of this function 3606 */ 3607 3608 /* 3609 * state of sibling HT 3610 */ 3611 xlo = &excl_cntrs->states[tid ^ 1]; 3612 3613 /* 3614 * event requires exclusive counter access 3615 * across HT threads 3616 */ 3617 is_excl = c->flags & PERF_X86_EVENT_EXCL; 3618 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3619 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3620 if (!cpuc->n_excl++) 3621 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3622 } 3623 3624 /* 3625 * Modify static constraint with current dynamic 3626 * state of thread 3627 * 3628 * EXCLUSIVE: sibling counter measuring exclusive event 3629 * SHARED : sibling counter measuring non-exclusive event 3630 * UNUSED : sibling counter unused 3631 */ 3632 w = c->weight; 3633 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3634 /* 3635 * exclusive event in sibling counter 3636 * our corresponding counter cannot be used 3637 * regardless of our event 3638 */ 3639 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3640 __clear_bit(i, c->idxmsk); 3641 w--; 3642 continue; 3643 } 3644 /* 3645 * if measuring an exclusive event, sibling 3646 * measuring non-exclusive, then counter cannot 3647 * be used 3648 */ 3649 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3650 __clear_bit(i, c->idxmsk); 3651 w--; 3652 continue; 3653 } 3654 } 3655 3656 /* 3657 * if we return an empty mask, then switch 3658 * back to static empty constraint to avoid 3659 * the cost of freeing later on 3660 */ 3661 if (!w) 3662 c = &emptyconstraint; 3663 3664 c->weight = w; 3665 3666 return c; 3667 } 3668 3669 static struct event_constraint * 3670 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3671 struct perf_event *event) 3672 { 3673 struct event_constraint *c1, *c2; 3674 3675 c1 = cpuc->event_constraint[idx]; 3676 3677 /* 3678 * first time only 3679 * - static constraint: no change across incremental scheduling calls 3680 * - dynamic constraint: handled by intel_get_excl_constraints() 3681 */ 3682 c2 = __intel_get_event_constraints(cpuc, idx, event); 3683 if (c1) { 3684 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3685 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3686 c1->weight = c2->weight; 3687 c2 = c1; 3688 } 3689 3690 if (cpuc->excl_cntrs) 3691 return intel_get_excl_constraints(cpuc, event, idx, c2); 3692 3693 /* Not all counters support the branch counter feature. */ 3694 if (branch_sample_counters(event)) { 3695 c2 = dyn_constraint(cpuc, c2, idx); 3696 c2->idxmsk64 &= x86_pmu.lbr_counters; 3697 c2->weight = hweight64(c2->idxmsk64); 3698 } 3699 3700 return c2; 3701 } 3702 3703 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3704 struct perf_event *event) 3705 { 3706 struct hw_perf_event *hwc = &event->hw; 3707 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3708 int tid = cpuc->excl_thread_id; 3709 struct intel_excl_states *xl; 3710 3711 /* 3712 * nothing needed if in group validation mode 3713 */ 3714 if (cpuc->is_fake) 3715 return; 3716 3717 if (WARN_ON_ONCE(!excl_cntrs)) 3718 return; 3719 3720 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3721 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3722 if (!--cpuc->n_excl) 3723 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3724 } 3725 3726 /* 3727 * If event was actually assigned, then mark the counter state as 3728 * unused now. 3729 */ 3730 if (hwc->idx >= 0) { 3731 xl = &excl_cntrs->states[tid]; 3732 3733 /* 3734 * put_constraint may be called from x86_schedule_events() 3735 * which already has the lock held so here make locking 3736 * conditional. 3737 */ 3738 if (!xl->sched_started) 3739 raw_spin_lock(&excl_cntrs->lock); 3740 3741 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3742 3743 if (!xl->sched_started) 3744 raw_spin_unlock(&excl_cntrs->lock); 3745 } 3746 } 3747 3748 static void 3749 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3750 struct perf_event *event) 3751 { 3752 struct hw_perf_event_extra *reg; 3753 3754 reg = &event->hw.extra_reg; 3755 if (reg->idx != EXTRA_REG_NONE) 3756 __intel_shared_reg_put_constraints(cpuc, reg); 3757 3758 reg = &event->hw.branch_reg; 3759 if (reg->idx != EXTRA_REG_NONE) 3760 __intel_shared_reg_put_constraints(cpuc, reg); 3761 } 3762 3763 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3764 struct perf_event *event) 3765 { 3766 intel_put_shared_regs_event_constraints(cpuc, event); 3767 3768 /* 3769 * is PMU has exclusive counter restrictions, then 3770 * all events are subject to and must call the 3771 * put_excl_constraints() routine 3772 */ 3773 if (cpuc->excl_cntrs) 3774 intel_put_excl_constraints(cpuc, event); 3775 } 3776 3777 static void intel_pebs_aliases_core2(struct perf_event *event) 3778 { 3779 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3780 /* 3781 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3782 * (0x003c) so that we can use it with PEBS. 3783 * 3784 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3785 * PEBS capable. However we can use INST_RETIRED.ANY_P 3786 * (0x00c0), which is a PEBS capable event, to get the same 3787 * count. 3788 * 3789 * INST_RETIRED.ANY_P counts the number of cycles that retires 3790 * CNTMASK instructions. By setting CNTMASK to a value (16) 3791 * larger than the maximum number of instructions that can be 3792 * retired per cycle (4) and then inverting the condition, we 3793 * count all cycles that retire 16 or less instructions, which 3794 * is every cycle. 3795 * 3796 * Thereby we gain a PEBS capable cycle counter. 3797 */ 3798 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3799 3800 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3801 event->hw.config = alt_config; 3802 } 3803 } 3804 3805 static void intel_pebs_aliases_snb(struct perf_event *event) 3806 { 3807 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3808 /* 3809 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3810 * (0x003c) so that we can use it with PEBS. 3811 * 3812 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3813 * PEBS capable. However we can use UOPS_RETIRED.ALL 3814 * (0x01c2), which is a PEBS capable event, to get the same 3815 * count. 3816 * 3817 * UOPS_RETIRED.ALL counts the number of cycles that retires 3818 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3819 * larger than the maximum number of micro-ops that can be 3820 * retired per cycle (4) and then inverting the condition, we 3821 * count all cycles that retire 16 or less micro-ops, which 3822 * is every cycle. 3823 * 3824 * Thereby we gain a PEBS capable cycle counter. 3825 */ 3826 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3827 3828 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3829 event->hw.config = alt_config; 3830 } 3831 } 3832 3833 static void intel_pebs_aliases_precdist(struct perf_event *event) 3834 { 3835 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3836 /* 3837 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3838 * (0x003c) so that we can use it with PEBS. 3839 * 3840 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3841 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3842 * (0x01c0), which is a PEBS capable event, to get the same 3843 * count. 3844 * 3845 * The PREC_DIST event has special support to minimize sample 3846 * shadowing effects. One drawback is that it can be 3847 * only programmed on counter 1, but that seems like an 3848 * acceptable trade off. 3849 */ 3850 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3851 3852 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3853 event->hw.config = alt_config; 3854 } 3855 } 3856 3857 static void intel_pebs_aliases_ivb(struct perf_event *event) 3858 { 3859 if (event->attr.precise_ip < 3) 3860 return intel_pebs_aliases_snb(event); 3861 return intel_pebs_aliases_precdist(event); 3862 } 3863 3864 static void intel_pebs_aliases_skl(struct perf_event *event) 3865 { 3866 if (event->attr.precise_ip < 3) 3867 return intel_pebs_aliases_core2(event); 3868 return intel_pebs_aliases_precdist(event); 3869 } 3870 3871 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3872 { 3873 unsigned long flags = x86_pmu.large_pebs_flags; 3874 3875 if (event->attr.use_clockid) 3876 flags &= ~PERF_SAMPLE_TIME; 3877 if (!event->attr.exclude_kernel) 3878 flags &= ~PERF_SAMPLE_REGS_USER; 3879 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3880 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3881 return flags; 3882 } 3883 3884 static int intel_pmu_bts_config(struct perf_event *event) 3885 { 3886 struct perf_event_attr *attr = &event->attr; 3887 3888 if (unlikely(intel_pmu_has_bts(event))) { 3889 /* BTS is not supported by this architecture. */ 3890 if (!x86_pmu.bts_active) 3891 return -EOPNOTSUPP; 3892 3893 /* BTS is currently only allowed for user-mode. */ 3894 if (!attr->exclude_kernel) 3895 return -EOPNOTSUPP; 3896 3897 /* BTS is not allowed for precise events. */ 3898 if (attr->precise_ip) 3899 return -EOPNOTSUPP; 3900 3901 /* disallow bts if conflicting events are present */ 3902 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3903 return -EBUSY; 3904 3905 event->destroy = hw_perf_lbr_event_destroy; 3906 } 3907 3908 return 0; 3909 } 3910 3911 static int core_pmu_hw_config(struct perf_event *event) 3912 { 3913 int ret = x86_pmu_hw_config(event); 3914 3915 if (ret) 3916 return ret; 3917 3918 return intel_pmu_bts_config(event); 3919 } 3920 3921 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 3922 ((x86_pmu.num_topdown_events - 1) << 8)) 3923 3924 static bool is_available_metric_event(struct perf_event *event) 3925 { 3926 return is_metric_event(event) && 3927 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 3928 } 3929 3930 static inline bool is_mem_loads_event(struct perf_event *event) 3931 { 3932 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 3933 } 3934 3935 static inline bool is_mem_loads_aux_event(struct perf_event *event) 3936 { 3937 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 3938 } 3939 3940 static inline bool require_mem_loads_aux_event(struct perf_event *event) 3941 { 3942 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) 3943 return false; 3944 3945 if (is_hybrid()) 3946 return hybrid_pmu(event->pmu)->pmu_type == hybrid_big; 3947 3948 return true; 3949 } 3950 3951 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) 3952 { 3953 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); 3954 3955 return test_bit(idx, (unsigned long *)&intel_cap->capabilities); 3956 } 3957 3958 static int intel_pmu_hw_config(struct perf_event *event) 3959 { 3960 int ret = x86_pmu_hw_config(event); 3961 3962 if (ret) 3963 return ret; 3964 3965 ret = intel_pmu_bts_config(event); 3966 if (ret) 3967 return ret; 3968 3969 if (event->attr.precise_ip) { 3970 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) 3971 return -EINVAL; 3972 3973 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 3974 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3975 if (!(event->attr.sample_type & ~intel_pmu_large_pebs_flags(event)) && 3976 !has_aux_action(event)) { 3977 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3978 event->attach_state |= PERF_ATTACH_SCHED_CB; 3979 } 3980 } 3981 if (x86_pmu.pebs_aliases) 3982 x86_pmu.pebs_aliases(event); 3983 } 3984 3985 if (needs_branch_stack(event)) { 3986 /* Avoid branch stack setup for counting events in SAMPLE READ */ 3987 if (is_sampling_event(event) || 3988 !(event->attr.sample_type & PERF_SAMPLE_READ)) 3989 event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK; 3990 } 3991 3992 if (branch_sample_counters(event)) { 3993 struct perf_event *leader, *sibling; 3994 int num = 0; 3995 3996 if (!(x86_pmu.flags & PMU_FL_BR_CNTR) || 3997 (event->attr.config & ~INTEL_ARCH_EVENT_MASK)) 3998 return -EINVAL; 3999 4000 /* 4001 * The branch counter logging is not supported in the call stack 4002 * mode yet, since we cannot simply flush the LBR during e.g., 4003 * multiplexing. Also, there is no obvious usage with the call 4004 * stack mode. Simply forbids it for now. 4005 * 4006 * If any events in the group enable the branch counter logging 4007 * feature, the group is treated as a branch counter logging 4008 * group, which requires the extra space to store the counters. 4009 */ 4010 leader = event->group_leader; 4011 if (branch_sample_call_stack(leader)) 4012 return -EINVAL; 4013 if (branch_sample_counters(leader)) 4014 num++; 4015 leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS; 4016 4017 for_each_sibling_event(sibling, leader) { 4018 if (branch_sample_call_stack(sibling)) 4019 return -EINVAL; 4020 if (branch_sample_counters(sibling)) 4021 num++; 4022 } 4023 4024 if (num > fls(x86_pmu.lbr_counters)) 4025 return -EINVAL; 4026 /* 4027 * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't 4028 * require any branch stack setup. 4029 * Clear the bit to avoid unnecessary branch stack setup. 4030 */ 4031 if (0 == (event->attr.branch_sample_type & 4032 ~(PERF_SAMPLE_BRANCH_PLM_ALL | 4033 PERF_SAMPLE_BRANCH_COUNTERS))) 4034 event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK; 4035 4036 /* 4037 * Force the leader to be a LBR event. So LBRs can be reset 4038 * with the leader event. See intel_pmu_lbr_del() for details. 4039 */ 4040 if (!intel_pmu_needs_branch_stack(leader)) 4041 return -EINVAL; 4042 } 4043 4044 if (intel_pmu_needs_branch_stack(event)) { 4045 ret = intel_pmu_setup_lbr_filter(event); 4046 if (ret) 4047 return ret; 4048 event->attach_state |= PERF_ATTACH_SCHED_CB; 4049 4050 /* 4051 * BTS is set up earlier in this path, so don't account twice 4052 */ 4053 if (!unlikely(intel_pmu_has_bts(event))) { 4054 /* disallow lbr if conflicting events are present */ 4055 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 4056 return -EBUSY; 4057 4058 event->destroy = hw_perf_lbr_event_destroy; 4059 } 4060 } 4061 4062 if (event->attr.aux_output) { 4063 if (!event->attr.precise_ip) 4064 return -EINVAL; 4065 4066 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 4067 } 4068 4069 if ((event->attr.type == PERF_TYPE_HARDWARE) || 4070 (event->attr.type == PERF_TYPE_HW_CACHE)) 4071 return 0; 4072 4073 /* 4074 * Config Topdown slots and metric events 4075 * 4076 * The slots event on Fixed Counter 3 can support sampling, 4077 * which will be handled normally in x86_perf_event_update(). 4078 * 4079 * Metric events don't support sampling and require being paired 4080 * with a slots event as group leader. When the slots event 4081 * is used in a metrics group, it too cannot support sampling. 4082 */ 4083 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { 4084 if (event->attr.config1 || event->attr.config2) 4085 return -EINVAL; 4086 4087 /* 4088 * The TopDown metrics events and slots event don't 4089 * support any filters. 4090 */ 4091 if (event->attr.config & X86_ALL_EVENT_FLAGS) 4092 return -EINVAL; 4093 4094 if (is_available_metric_event(event)) { 4095 struct perf_event *leader = event->group_leader; 4096 4097 /* The metric events don't support sampling. */ 4098 if (is_sampling_event(event)) 4099 return -EINVAL; 4100 4101 /* The metric events require a slots group leader. */ 4102 if (!is_slots_event(leader)) 4103 return -EINVAL; 4104 4105 /* 4106 * The leader/SLOTS must not be a sampling event for 4107 * metric use; hardware requires it starts at 0 when used 4108 * in conjunction with MSR_PERF_METRICS. 4109 */ 4110 if (is_sampling_event(leader)) 4111 return -EINVAL; 4112 4113 event->event_caps |= PERF_EV_CAP_SIBLING; 4114 /* 4115 * Only once we have a METRICs sibling do we 4116 * need TopDown magic. 4117 */ 4118 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 4119 event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 4120 } 4121 } 4122 4123 /* 4124 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 4125 * doesn't function quite right. As a work-around it needs to always be 4126 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 4127 * The actual count of this second event is irrelevant it just needs 4128 * to be active to make the first event function correctly. 4129 * 4130 * In a group, the auxiliary event must be in front of the load latency 4131 * event. The rule is to simplify the implementation of the check. 4132 * That's because perf cannot have a complete group at the moment. 4133 */ 4134 if (require_mem_loads_aux_event(event) && 4135 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 4136 is_mem_loads_event(event)) { 4137 struct perf_event *leader = event->group_leader; 4138 struct perf_event *sibling = NULL; 4139 4140 /* 4141 * When this memload event is also the first event (no group 4142 * exists yet), then there is no aux event before it. 4143 */ 4144 if (leader == event) 4145 return -ENODATA; 4146 4147 if (!is_mem_loads_aux_event(leader)) { 4148 for_each_sibling_event(sibling, leader) { 4149 if (is_mem_loads_aux_event(sibling)) 4150 break; 4151 } 4152 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 4153 return -ENODATA; 4154 } 4155 } 4156 4157 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 4158 return 0; 4159 4160 if (x86_pmu.version < 3) 4161 return -EINVAL; 4162 4163 ret = perf_allow_cpu(&event->attr); 4164 if (ret) 4165 return ret; 4166 4167 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 4168 4169 return 0; 4170 } 4171 4172 /* 4173 * Currently, the only caller of this function is the atomic_switch_perf_msrs(). 4174 * The host perf context helps to prepare the values of the real hardware for 4175 * a set of msrs that need to be switched atomically in a vmx transaction. 4176 * 4177 * For example, the pseudocode needed to add a new msr should look like: 4178 * 4179 * arr[(*nr)++] = (struct perf_guest_switch_msr){ 4180 * .msr = the hardware msr address, 4181 * .host = the value the hardware has when it doesn't run a guest, 4182 * .guest = the value the hardware has when it runs a guest, 4183 * }; 4184 * 4185 * These values have nothing to do with the emulated values the guest sees 4186 * when it uses {RD,WR}MSR, which should be handled by the KVM context, 4187 * specifically in the intel_pmu_{get,set}_msr(). 4188 */ 4189 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) 4190 { 4191 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4192 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4193 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data; 4194 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 4195 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; 4196 int global_ctrl, pebs_enable; 4197 4198 /* 4199 * In addition to obeying exclude_guest/exclude_host, remove bits being 4200 * used for PEBS when running a guest, because PEBS writes to virtual 4201 * addresses (not physical addresses). 4202 */ 4203 *nr = 0; 4204 global_ctrl = (*nr)++; 4205 arr[global_ctrl] = (struct perf_guest_switch_msr){ 4206 .msr = MSR_CORE_PERF_GLOBAL_CTRL, 4207 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask, 4208 .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask, 4209 }; 4210 4211 if (!x86_pmu.pebs) 4212 return arr; 4213 4214 /* 4215 * If PMU counter has PEBS enabled it is not enough to 4216 * disable counter on a guest entry since PEBS memory 4217 * write can overshoot guest entry and corrupt guest 4218 * memory. Disabling PEBS solves the problem. 4219 * 4220 * Don't do this if the CPU already enforces it. 4221 */ 4222 if (x86_pmu.pebs_no_isolation) { 4223 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4224 .msr = MSR_IA32_PEBS_ENABLE, 4225 .host = cpuc->pebs_enabled, 4226 .guest = 0, 4227 }; 4228 return arr; 4229 } 4230 4231 if (!kvm_pmu || !x86_pmu.pebs_ept) 4232 return arr; 4233 4234 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4235 .msr = MSR_IA32_DS_AREA, 4236 .host = (unsigned long)cpuc->ds, 4237 .guest = kvm_pmu->ds_area, 4238 }; 4239 4240 if (x86_pmu.intel_cap.pebs_baseline) { 4241 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4242 .msr = MSR_PEBS_DATA_CFG, 4243 .host = cpuc->active_pebs_data_cfg, 4244 .guest = kvm_pmu->pebs_data_cfg, 4245 }; 4246 } 4247 4248 pebs_enable = (*nr)++; 4249 arr[pebs_enable] = (struct perf_guest_switch_msr){ 4250 .msr = MSR_IA32_PEBS_ENABLE, 4251 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask, 4252 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask, 4253 }; 4254 4255 if (arr[pebs_enable].host) { 4256 /* Disable guest PEBS if host PEBS is enabled. */ 4257 arr[pebs_enable].guest = 0; 4258 } else { 4259 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */ 4260 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask; 4261 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask; 4262 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ 4263 arr[global_ctrl].guest |= arr[pebs_enable].guest; 4264 } 4265 4266 return arr; 4267 } 4268 4269 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data) 4270 { 4271 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4272 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4273 int idx; 4274 4275 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { 4276 struct perf_event *event = cpuc->events[idx]; 4277 4278 arr[idx].msr = x86_pmu_config_addr(idx); 4279 arr[idx].host = arr[idx].guest = 0; 4280 4281 if (!test_bit(idx, cpuc->active_mask)) 4282 continue; 4283 4284 arr[idx].host = arr[idx].guest = 4285 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 4286 4287 if (event->attr.exclude_host) 4288 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4289 else if (event->attr.exclude_guest) 4290 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4291 } 4292 4293 *nr = x86_pmu_max_num_counters(cpuc->pmu); 4294 return arr; 4295 } 4296 4297 static void core_pmu_enable_event(struct perf_event *event) 4298 { 4299 if (!event->attr.exclude_host) 4300 x86_pmu_enable_event(event); 4301 } 4302 4303 static void core_pmu_enable_all(int added) 4304 { 4305 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4306 int idx; 4307 4308 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { 4309 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 4310 4311 if (!test_bit(idx, cpuc->active_mask) || 4312 cpuc->events[idx]->attr.exclude_host) 4313 continue; 4314 4315 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 4316 } 4317 } 4318 4319 static int hsw_hw_config(struct perf_event *event) 4320 { 4321 int ret = intel_pmu_hw_config(event); 4322 4323 if (ret) 4324 return ret; 4325 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 4326 return 0; 4327 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 4328 4329 /* 4330 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 4331 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 4332 * this combination. 4333 */ 4334 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 4335 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 4336 event->attr.precise_ip > 0)) 4337 return -EOPNOTSUPP; 4338 4339 if (event_is_checkpointed(event)) { 4340 /* 4341 * Sampling of checkpointed events can cause situations where 4342 * the CPU constantly aborts because of a overflow, which is 4343 * then checkpointed back and ignored. Forbid checkpointing 4344 * for sampling. 4345 * 4346 * But still allow a long sampling period, so that perf stat 4347 * from KVM works. 4348 */ 4349 if (event->attr.sample_period > 0 && 4350 event->attr.sample_period < 0x7fffffff) 4351 return -EOPNOTSUPP; 4352 } 4353 return 0; 4354 } 4355 4356 static struct event_constraint counter0_constraint = 4357 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 4358 4359 static struct event_constraint counter1_constraint = 4360 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2); 4361 4362 static struct event_constraint counter0_1_constraint = 4363 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3); 4364 4365 static struct event_constraint counter2_constraint = 4366 EVENT_CONSTRAINT(0, 0x4, 0); 4367 4368 static struct event_constraint fixed0_constraint = 4369 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 4370 4371 static struct event_constraint fixed0_counter0_constraint = 4372 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 4373 4374 static struct event_constraint fixed0_counter0_1_constraint = 4375 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL); 4376 4377 static struct event_constraint counters_1_7_constraint = 4378 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL); 4379 4380 static struct event_constraint * 4381 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4382 struct perf_event *event) 4383 { 4384 struct event_constraint *c; 4385 4386 c = intel_get_event_constraints(cpuc, idx, event); 4387 4388 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 4389 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 4390 if (c->idxmsk64 & (1U << 2)) 4391 return &counter2_constraint; 4392 return &emptyconstraint; 4393 } 4394 4395 return c; 4396 } 4397 4398 static struct event_constraint * 4399 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4400 struct perf_event *event) 4401 { 4402 /* 4403 * Fixed counter 0 has less skid. 4404 * Force instruction:ppp in Fixed counter 0 4405 */ 4406 if ((event->attr.precise_ip == 3) && 4407 constraint_match(&fixed0_constraint, event->hw.config)) 4408 return &fixed0_constraint; 4409 4410 return hsw_get_event_constraints(cpuc, idx, event); 4411 } 4412 4413 static struct event_constraint * 4414 glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4415 struct perf_event *event) 4416 { 4417 struct event_constraint *c; 4418 4419 c = icl_get_event_constraints(cpuc, idx, event); 4420 4421 /* 4422 * The :ppp indicates the Precise Distribution (PDist) facility, which 4423 * is only supported on the GP counter 0. If a :ppp event which is not 4424 * available on the GP counter 0, error out. 4425 * Exception: Instruction PDIR is only available on the fixed counter 0. 4426 */ 4427 if ((event->attr.precise_ip == 3) && 4428 !constraint_match(&fixed0_constraint, event->hw.config)) { 4429 if (c->idxmsk64 & BIT_ULL(0)) 4430 return &counter0_constraint; 4431 4432 return &emptyconstraint; 4433 } 4434 4435 return c; 4436 } 4437 4438 static struct event_constraint * 4439 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4440 struct perf_event *event) 4441 { 4442 struct event_constraint *c; 4443 4444 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 4445 if (event->attr.precise_ip == 3) 4446 return &counter0_constraint; 4447 4448 c = intel_get_event_constraints(cpuc, idx, event); 4449 4450 return c; 4451 } 4452 4453 static struct event_constraint * 4454 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4455 struct perf_event *event) 4456 { 4457 struct event_constraint *c; 4458 4459 c = intel_get_event_constraints(cpuc, idx, event); 4460 4461 /* 4462 * :ppp means to do reduced skid PEBS, 4463 * which is available on PMC0 and fixed counter 0. 4464 */ 4465 if (event->attr.precise_ip == 3) { 4466 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 4467 if (constraint_match(&fixed0_constraint, event->hw.config)) 4468 return &fixed0_counter0_constraint; 4469 4470 return &counter0_constraint; 4471 } 4472 4473 return c; 4474 } 4475 4476 static bool allow_tsx_force_abort = true; 4477 4478 static struct event_constraint * 4479 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4480 struct perf_event *event) 4481 { 4482 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 4483 4484 /* 4485 * Without TFA we must not use PMC3. 4486 */ 4487 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 4488 c = dyn_constraint(cpuc, c, idx); 4489 c->idxmsk64 &= ~(1ULL << 3); 4490 c->weight--; 4491 } 4492 4493 return c; 4494 } 4495 4496 static struct event_constraint * 4497 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4498 struct perf_event *event) 4499 { 4500 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4501 4502 if (pmu->pmu_type == hybrid_big) 4503 return glc_get_event_constraints(cpuc, idx, event); 4504 else if (pmu->pmu_type == hybrid_small) 4505 return tnt_get_event_constraints(cpuc, idx, event); 4506 4507 WARN_ON(1); 4508 return &emptyconstraint; 4509 } 4510 4511 static struct event_constraint * 4512 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4513 struct perf_event *event) 4514 { 4515 struct event_constraint *c; 4516 4517 c = intel_get_event_constraints(cpuc, idx, event); 4518 4519 /* 4520 * The :ppp indicates the Precise Distribution (PDist) facility, which 4521 * is only supported on the GP counter 0 & 1 and Fixed counter 0. 4522 * If a :ppp event which is not available on the above eligible counters, 4523 * error out. 4524 */ 4525 if (event->attr.precise_ip == 3) { 4526 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */ 4527 if (constraint_match(&fixed0_constraint, event->hw.config)) { 4528 /* The fixed counter 0 doesn't support LBR event logging. */ 4529 if (branch_sample_counters(event)) 4530 return &counter0_1_constraint; 4531 else 4532 return &fixed0_counter0_1_constraint; 4533 } 4534 4535 switch (c->idxmsk64 & 0x3ull) { 4536 case 0x1: 4537 return &counter0_constraint; 4538 case 0x2: 4539 return &counter1_constraint; 4540 case 0x3: 4541 return &counter0_1_constraint; 4542 } 4543 return &emptyconstraint; 4544 } 4545 4546 return c; 4547 } 4548 4549 static struct event_constraint * 4550 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4551 struct perf_event *event) 4552 { 4553 struct event_constraint *c; 4554 4555 c = glc_get_event_constraints(cpuc, idx, event); 4556 4557 /* The Retire Latency is not supported by the fixed counter 0. */ 4558 if (event->attr.precise_ip && 4559 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) && 4560 constraint_match(&fixed0_constraint, event->hw.config)) { 4561 /* 4562 * The Instruction PDIR is only available 4563 * on the fixed counter 0. Error out for this case. 4564 */ 4565 if (event->attr.precise_ip == 3) 4566 return &emptyconstraint; 4567 return &counters_1_7_constraint; 4568 } 4569 4570 return c; 4571 } 4572 4573 static struct event_constraint * 4574 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4575 struct perf_event *event) 4576 { 4577 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4578 4579 if (pmu->pmu_type == hybrid_big) 4580 return rwc_get_event_constraints(cpuc, idx, event); 4581 if (pmu->pmu_type == hybrid_small) 4582 return cmt_get_event_constraints(cpuc, idx, event); 4583 4584 WARN_ON(1); 4585 return &emptyconstraint; 4586 } 4587 4588 static int adl_hw_config(struct perf_event *event) 4589 { 4590 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4591 4592 if (pmu->pmu_type == hybrid_big) 4593 return hsw_hw_config(event); 4594 else if (pmu->pmu_type == hybrid_small) 4595 return intel_pmu_hw_config(event); 4596 4597 WARN_ON(1); 4598 return -EOPNOTSUPP; 4599 } 4600 4601 static enum hybrid_cpu_type adl_get_hybrid_cpu_type(void) 4602 { 4603 return HYBRID_INTEL_CORE; 4604 } 4605 4606 static inline bool erratum_hsw11(struct perf_event *event) 4607 { 4608 return (event->hw.config & INTEL_ARCH_EVENT_MASK) == 4609 X86_CONFIG(.event=0xc0, .umask=0x01); 4610 } 4611 4612 static struct event_constraint * 4613 arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4614 struct perf_event *event) 4615 { 4616 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4617 4618 if (pmu->pmu_type == hybrid_tiny) 4619 return cmt_get_event_constraints(cpuc, idx, event); 4620 4621 return mtl_get_event_constraints(cpuc, idx, event); 4622 } 4623 4624 static int arl_h_hw_config(struct perf_event *event) 4625 { 4626 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4627 4628 if (pmu->pmu_type == hybrid_tiny) 4629 return intel_pmu_hw_config(event); 4630 4631 return adl_hw_config(event); 4632 } 4633 4634 /* 4635 * The HSW11 requires a period larger than 100 which is the same as the BDM11. 4636 * A minimum period of 128 is enforced as well for the INST_RETIRED.ALL. 4637 * 4638 * The message 'interrupt took too long' can be observed on any counter which 4639 * was armed with a period < 32 and two events expired in the same NMI. 4640 * A minimum period of 32 is enforced for the rest of the events. 4641 */ 4642 static void hsw_limit_period(struct perf_event *event, s64 *left) 4643 { 4644 *left = max(*left, erratum_hsw11(event) ? 128 : 32); 4645 } 4646 4647 /* 4648 * Broadwell: 4649 * 4650 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 4651 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 4652 * the two to enforce a minimum period of 128 (the smallest value that has bits 4653 * 0-5 cleared and >= 100). 4654 * 4655 * Because of how the code in x86_perf_event_set_period() works, the truncation 4656 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 4657 * to make up for the 'lost' events due to carrying the 'error' in period_left. 4658 * 4659 * Therefore the effective (average) period matches the requested period, 4660 * despite coarser hardware granularity. 4661 */ 4662 static void bdw_limit_period(struct perf_event *event, s64 *left) 4663 { 4664 if (erratum_hsw11(event)) { 4665 if (*left < 128) 4666 *left = 128; 4667 *left &= ~0x3fULL; 4668 } 4669 } 4670 4671 static void nhm_limit_period(struct perf_event *event, s64 *left) 4672 { 4673 *left = max(*left, 32LL); 4674 } 4675 4676 static void glc_limit_period(struct perf_event *event, s64 *left) 4677 { 4678 if (event->attr.precise_ip == 3) 4679 *left = max(*left, 128LL); 4680 } 4681 4682 PMU_FORMAT_ATTR(event, "config:0-7" ); 4683 PMU_FORMAT_ATTR(umask, "config:8-15" ); 4684 PMU_FORMAT_ATTR(edge, "config:18" ); 4685 PMU_FORMAT_ATTR(pc, "config:19" ); 4686 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 4687 PMU_FORMAT_ATTR(inv, "config:23" ); 4688 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 4689 PMU_FORMAT_ATTR(in_tx, "config:32" ); 4690 PMU_FORMAT_ATTR(in_tx_cp, "config:33" ); 4691 PMU_FORMAT_ATTR(eq, "config:36" ); /* v6 + */ 4692 4693 static ssize_t umask2_show(struct device *dev, 4694 struct device_attribute *attr, 4695 char *page) 4696 { 4697 u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2; 4698 4699 if (mask == ARCH_PERFMON_EVENTSEL_UMASK2) 4700 return sprintf(page, "config:8-15,40-47\n"); 4701 4702 /* Roll back to the old format if umask2 is not supported. */ 4703 return sprintf(page, "config:8-15\n"); 4704 } 4705 4706 static struct device_attribute format_attr_umask2 = 4707 __ATTR(umask, 0444, umask2_show, NULL); 4708 4709 static struct attribute *format_evtsel_ext_attrs[] = { 4710 &format_attr_umask2.attr, 4711 &format_attr_eq.attr, 4712 NULL 4713 }; 4714 4715 static umode_t 4716 evtsel_ext_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4717 { 4718 struct device *dev = kobj_to_dev(kobj); 4719 u64 mask; 4720 4721 /* 4722 * The umask and umask2 have different formats but share the 4723 * same attr name. In update mode, the previous value of the 4724 * umask is unconditionally removed before is_visible. If 4725 * umask2 format is not enumerated, it's impossible to roll 4726 * back to the old format. 4727 * Does the check in umask2_show rather than is_visible. 4728 */ 4729 if (i == 0) 4730 return attr->mode; 4731 4732 mask = hybrid(dev_get_drvdata(dev), config_mask); 4733 if (i == 1) 4734 return (mask & ARCH_PERFMON_EVENTSEL_EQ) ? attr->mode : 0; 4735 4736 return 0; 4737 } 4738 4739 static struct attribute *intel_arch_formats_attr[] = { 4740 &format_attr_event.attr, 4741 &format_attr_umask.attr, 4742 &format_attr_edge.attr, 4743 &format_attr_pc.attr, 4744 &format_attr_inv.attr, 4745 &format_attr_cmask.attr, 4746 NULL, 4747 }; 4748 4749 ssize_t intel_event_sysfs_show(char *page, u64 config) 4750 { 4751 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 4752 4753 return x86_event_sysfs_show(page, config, event); 4754 } 4755 4756 static struct intel_shared_regs *allocate_shared_regs(int cpu) 4757 { 4758 struct intel_shared_regs *regs; 4759 int i; 4760 4761 regs = kzalloc_node(sizeof(struct intel_shared_regs), 4762 GFP_KERNEL, cpu_to_node(cpu)); 4763 if (regs) { 4764 /* 4765 * initialize the locks to keep lockdep happy 4766 */ 4767 for (i = 0; i < EXTRA_REG_MAX; i++) 4768 raw_spin_lock_init(®s->regs[i].lock); 4769 4770 regs->core_id = -1; 4771 } 4772 return regs; 4773 } 4774 4775 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 4776 { 4777 struct intel_excl_cntrs *c; 4778 4779 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 4780 GFP_KERNEL, cpu_to_node(cpu)); 4781 if (c) { 4782 raw_spin_lock_init(&c->lock); 4783 c->core_id = -1; 4784 } 4785 return c; 4786 } 4787 4788 4789 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 4790 { 4791 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 4792 4793 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 4794 cpuc->shared_regs = allocate_shared_regs(cpu); 4795 if (!cpuc->shared_regs) 4796 goto err; 4797 } 4798 4799 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_BR_CNTR)) { 4800 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 4801 4802 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 4803 if (!cpuc->constraint_list) 4804 goto err_shared_regs; 4805 } 4806 4807 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4808 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 4809 if (!cpuc->excl_cntrs) 4810 goto err_constraint_list; 4811 4812 cpuc->excl_thread_id = 0; 4813 } 4814 4815 return 0; 4816 4817 err_constraint_list: 4818 kfree(cpuc->constraint_list); 4819 cpuc->constraint_list = NULL; 4820 4821 err_shared_regs: 4822 kfree(cpuc->shared_regs); 4823 cpuc->shared_regs = NULL; 4824 4825 err: 4826 return -ENOMEM; 4827 } 4828 4829 static int intel_pmu_cpu_prepare(int cpu) 4830 { 4831 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 4832 } 4833 4834 static void flip_smm_bit(void *data) 4835 { 4836 unsigned long set = *(unsigned long *)data; 4837 4838 if (set > 0) { 4839 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 4840 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4841 } else { 4842 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 4843 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4844 } 4845 } 4846 4847 static void intel_pmu_check_counters_mask(u64 *cntr_mask, 4848 u64 *fixed_cntr_mask, 4849 u64 *intel_ctrl) 4850 { 4851 unsigned int bit; 4852 4853 bit = fls64(*cntr_mask); 4854 if (bit > INTEL_PMC_MAX_GENERIC) { 4855 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 4856 bit, INTEL_PMC_MAX_GENERIC); 4857 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); 4858 } 4859 *intel_ctrl = *cntr_mask; 4860 4861 bit = fls64(*fixed_cntr_mask); 4862 if (bit > INTEL_PMC_MAX_FIXED) { 4863 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 4864 bit, INTEL_PMC_MAX_FIXED); 4865 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0); 4866 } 4867 4868 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED; 4869 } 4870 4871 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 4872 u64 cntr_mask, 4873 u64 fixed_cntr_mask, 4874 u64 intel_ctrl); 4875 4876 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs); 4877 4878 static inline bool intel_pmu_broken_perf_cap(void) 4879 { 4880 /* The Perf Metric (Bit 15) is always cleared */ 4881 if (boot_cpu_data.x86_vfm == INTEL_METEORLAKE || 4882 boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L) 4883 return true; 4884 4885 return false; 4886 } 4887 4888 static void update_pmu_cap(struct x86_hybrid_pmu *pmu) 4889 { 4890 unsigned int sub_bitmaps, eax, ebx, ecx, edx; 4891 4892 cpuid(ARCH_PERFMON_EXT_LEAF, &sub_bitmaps, &ebx, &ecx, &edx); 4893 4894 if (ebx & ARCH_PERFMON_EXT_UMASK2) 4895 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_UMASK2; 4896 if (ebx & ARCH_PERFMON_EXT_EQ) 4897 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_EQ; 4898 4899 if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF_BIT) { 4900 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF, 4901 &eax, &ebx, &ecx, &edx); 4902 pmu->cntr_mask64 = eax; 4903 pmu->fixed_cntr_mask64 = ebx; 4904 } 4905 4906 if (!intel_pmu_broken_perf_cap()) { 4907 /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */ 4908 rdmsrl(MSR_IA32_PERF_CAPABILITIES, pmu->intel_cap.capabilities); 4909 } 4910 } 4911 4912 static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu) 4913 { 4914 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64, 4915 &pmu->intel_ctrl); 4916 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 4917 pmu->unconstrained = (struct event_constraint) 4918 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 4919 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 4920 4921 if (pmu->intel_cap.perf_metrics) 4922 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 4923 else 4924 pmu->intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 4925 4926 if (pmu->intel_cap.pebs_output_pt_available) 4927 pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT; 4928 else 4929 pmu->pmu.capabilities &= ~PERF_PMU_CAP_AUX_OUTPUT; 4930 4931 intel_pmu_check_event_constraints(pmu->event_constraints, 4932 pmu->cntr_mask64, 4933 pmu->fixed_cntr_mask64, 4934 pmu->intel_ctrl); 4935 4936 intel_pmu_check_extra_regs(pmu->extra_regs); 4937 } 4938 4939 static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void) 4940 { 4941 u8 cpu_type = get_this_hybrid_cpu_type(); 4942 int i; 4943 4944 /* 4945 * This is running on a CPU model that is known to have hybrid 4946 * configurations. But the CPU told us it is not hybrid, shame 4947 * on it. There should be a fixup function provided for these 4948 * troublesome CPUs (->get_hybrid_cpu_type). 4949 */ 4950 if (cpu_type == HYBRID_INTEL_NONE) { 4951 if (x86_pmu.get_hybrid_cpu_type) 4952 cpu_type = x86_pmu.get_hybrid_cpu_type(); 4953 else 4954 return NULL; 4955 } 4956 4957 /* 4958 * This essentially just maps between the 'hybrid_cpu_type' 4959 * and 'hybrid_pmu_type' enums except for ARL-H processor 4960 * which needs to compare atom uarch native id since ARL-H 4961 * contains two different atom uarchs. 4962 */ 4963 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 4964 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type; 4965 u32 native_id; 4966 4967 if (cpu_type == HYBRID_INTEL_CORE && pmu_type == hybrid_big) 4968 return &x86_pmu.hybrid_pmu[i]; 4969 if (cpu_type == HYBRID_INTEL_ATOM) { 4970 if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small) 4971 return &x86_pmu.hybrid_pmu[i]; 4972 4973 native_id = get_this_hybrid_cpu_native_id(); 4974 if (native_id == skt_native_id && pmu_type == hybrid_small) 4975 return &x86_pmu.hybrid_pmu[i]; 4976 if (native_id == cmt_native_id && pmu_type == hybrid_tiny) 4977 return &x86_pmu.hybrid_pmu[i]; 4978 } 4979 } 4980 4981 return NULL; 4982 } 4983 4984 static bool init_hybrid_pmu(int cpu) 4985 { 4986 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4987 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu(); 4988 4989 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { 4990 cpuc->pmu = NULL; 4991 return false; 4992 } 4993 4994 /* Only check and dump the PMU information for the first CPU */ 4995 if (!cpumask_empty(&pmu->supported_cpus)) 4996 goto end; 4997 4998 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) 4999 update_pmu_cap(pmu); 5000 5001 intel_pmu_check_hybrid_pmus(pmu); 5002 5003 if (!check_hw_exists(&pmu->pmu, pmu->cntr_mask, pmu->fixed_cntr_mask)) 5004 return false; 5005 5006 pr_info("%s PMU driver: ", pmu->name); 5007 5008 if (pmu->intel_cap.pebs_output_pt_available) 5009 pr_cont("PEBS-via-PT "); 5010 5011 pr_cont("\n"); 5012 5013 x86_pmu_show_pmu_cap(&pmu->pmu); 5014 5015 end: 5016 cpumask_set_cpu(cpu, &pmu->supported_cpus); 5017 cpuc->pmu = &pmu->pmu; 5018 5019 return true; 5020 } 5021 5022 static void intel_pmu_cpu_starting(int cpu) 5023 { 5024 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 5025 int core_id = topology_core_id(cpu); 5026 int i; 5027 5028 if (is_hybrid() && !init_hybrid_pmu(cpu)) 5029 return; 5030 5031 init_debug_store_on_cpu(cpu); 5032 /* 5033 * Deal with CPUs that don't clear their LBRs on power-up. 5034 */ 5035 intel_pmu_lbr_reset(); 5036 5037 cpuc->lbr_sel = NULL; 5038 5039 if (x86_pmu.flags & PMU_FL_TFA) { 5040 WARN_ON_ONCE(cpuc->tfa_shadow); 5041 cpuc->tfa_shadow = ~0ULL; 5042 intel_set_tfa(cpuc, false); 5043 } 5044 5045 if (x86_pmu.version > 1) 5046 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 5047 5048 /* 5049 * Disable perf metrics if any added CPU doesn't support it. 5050 * 5051 * Turn off the check for a hybrid architecture, because the 5052 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate 5053 * the architecture features. The perf metrics is a model-specific 5054 * feature for now. The corresponding bit should always be 0 on 5055 * a hybrid platform, e.g., Alder Lake. 5056 */ 5057 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 5058 union perf_capabilities perf_cap; 5059 5060 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 5061 if (!perf_cap.perf_metrics) { 5062 x86_pmu.intel_cap.perf_metrics = 0; 5063 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 5064 } 5065 } 5066 5067 if (!cpuc->shared_regs) 5068 return; 5069 5070 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 5071 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 5072 struct intel_shared_regs *pc; 5073 5074 pc = per_cpu(cpu_hw_events, i).shared_regs; 5075 if (pc && pc->core_id == core_id) { 5076 cpuc->kfree_on_online[0] = cpuc->shared_regs; 5077 cpuc->shared_regs = pc; 5078 break; 5079 } 5080 } 5081 cpuc->shared_regs->core_id = core_id; 5082 cpuc->shared_regs->refcnt++; 5083 } 5084 5085 if (x86_pmu.lbr_sel_map) 5086 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 5087 5088 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 5089 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 5090 struct cpu_hw_events *sibling; 5091 struct intel_excl_cntrs *c; 5092 5093 sibling = &per_cpu(cpu_hw_events, i); 5094 c = sibling->excl_cntrs; 5095 if (c && c->core_id == core_id) { 5096 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 5097 cpuc->excl_cntrs = c; 5098 if (!sibling->excl_thread_id) 5099 cpuc->excl_thread_id = 1; 5100 break; 5101 } 5102 } 5103 cpuc->excl_cntrs->core_id = core_id; 5104 cpuc->excl_cntrs->refcnt++; 5105 } 5106 } 5107 5108 static void free_excl_cntrs(struct cpu_hw_events *cpuc) 5109 { 5110 struct intel_excl_cntrs *c; 5111 5112 c = cpuc->excl_cntrs; 5113 if (c) { 5114 if (c->core_id == -1 || --c->refcnt == 0) 5115 kfree(c); 5116 cpuc->excl_cntrs = NULL; 5117 } 5118 5119 kfree(cpuc->constraint_list); 5120 cpuc->constraint_list = NULL; 5121 } 5122 5123 static void intel_pmu_cpu_dying(int cpu) 5124 { 5125 fini_debug_store_on_cpu(cpu); 5126 } 5127 5128 void intel_cpuc_finish(struct cpu_hw_events *cpuc) 5129 { 5130 struct intel_shared_regs *pc; 5131 5132 pc = cpuc->shared_regs; 5133 if (pc) { 5134 if (pc->core_id == -1 || --pc->refcnt == 0) 5135 kfree(pc); 5136 cpuc->shared_regs = NULL; 5137 } 5138 5139 free_excl_cntrs(cpuc); 5140 } 5141 5142 static void intel_pmu_cpu_dead(int cpu) 5143 { 5144 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 5145 5146 intel_cpuc_finish(cpuc); 5147 5148 if (is_hybrid() && cpuc->pmu) 5149 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); 5150 } 5151 5152 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, 5153 bool sched_in) 5154 { 5155 intel_pmu_pebs_sched_task(pmu_ctx, sched_in); 5156 intel_pmu_lbr_sched_task(pmu_ctx, sched_in); 5157 } 5158 5159 static void intel_pmu_swap_task_ctx(struct perf_event_pmu_context *prev_epc, 5160 struct perf_event_pmu_context *next_epc) 5161 { 5162 intel_pmu_lbr_swap_task_ctx(prev_epc, next_epc); 5163 } 5164 5165 static int intel_pmu_check_period(struct perf_event *event, u64 value) 5166 { 5167 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 5168 } 5169 5170 static void intel_aux_output_init(void) 5171 { 5172 /* Refer also intel_pmu_aux_output_match() */ 5173 if (x86_pmu.intel_cap.pebs_output_pt_available) 5174 x86_pmu.assign = intel_pmu_assign_event; 5175 } 5176 5177 static int intel_pmu_aux_output_match(struct perf_event *event) 5178 { 5179 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */ 5180 if (!x86_pmu.intel_cap.pebs_output_pt_available) 5181 return 0; 5182 5183 return is_intel_pt_event(event); 5184 } 5185 5186 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret) 5187 { 5188 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu); 5189 5190 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus); 5191 } 5192 5193 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 5194 5195 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 5196 5197 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 5198 5199 PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63"); 5200 5201 static struct attribute *intel_arch3_formats_attr[] = { 5202 &format_attr_event.attr, 5203 &format_attr_umask.attr, 5204 &format_attr_edge.attr, 5205 &format_attr_pc.attr, 5206 &format_attr_any.attr, 5207 &format_attr_inv.attr, 5208 &format_attr_cmask.attr, 5209 NULL, 5210 }; 5211 5212 static struct attribute *hsw_format_attr[] = { 5213 &format_attr_in_tx.attr, 5214 &format_attr_in_tx_cp.attr, 5215 &format_attr_offcore_rsp.attr, 5216 &format_attr_ldlat.attr, 5217 NULL 5218 }; 5219 5220 static struct attribute *nhm_format_attr[] = { 5221 &format_attr_offcore_rsp.attr, 5222 &format_attr_ldlat.attr, 5223 NULL 5224 }; 5225 5226 static struct attribute *slm_format_attr[] = { 5227 &format_attr_offcore_rsp.attr, 5228 NULL 5229 }; 5230 5231 static struct attribute *cmt_format_attr[] = { 5232 &format_attr_offcore_rsp.attr, 5233 &format_attr_ldlat.attr, 5234 &format_attr_snoop_rsp.attr, 5235 NULL 5236 }; 5237 5238 static struct attribute *skl_format_attr[] = { 5239 &format_attr_frontend.attr, 5240 NULL, 5241 }; 5242 5243 static __initconst const struct x86_pmu core_pmu = { 5244 .name = "core", 5245 .handle_irq = x86_pmu_handle_irq, 5246 .disable_all = x86_pmu_disable_all, 5247 .enable_all = core_pmu_enable_all, 5248 .enable = core_pmu_enable_event, 5249 .disable = x86_pmu_disable_event, 5250 .hw_config = core_pmu_hw_config, 5251 .schedule_events = x86_schedule_events, 5252 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 5253 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 5254 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0, 5255 .event_map = intel_pmu_event_map, 5256 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 5257 .apic = 1, 5258 .large_pebs_flags = LARGE_PEBS_FLAGS, 5259 5260 /* 5261 * Intel PMCs cannot be accessed sanely above 32-bit width, 5262 * so we install an artificial 1<<31 period regardless of 5263 * the generic event period: 5264 */ 5265 .max_period = (1ULL<<31) - 1, 5266 .get_event_constraints = intel_get_event_constraints, 5267 .put_event_constraints = intel_put_event_constraints, 5268 .event_constraints = intel_core_event_constraints, 5269 .guest_get_msrs = core_guest_get_msrs, 5270 .format_attrs = intel_arch_formats_attr, 5271 .events_sysfs_show = intel_event_sysfs_show, 5272 5273 /* 5274 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 5275 * together with PMU version 1 and thus be using core_pmu with 5276 * shared_regs. We need following callbacks here to allocate 5277 * it properly. 5278 */ 5279 .cpu_prepare = intel_pmu_cpu_prepare, 5280 .cpu_starting = intel_pmu_cpu_starting, 5281 .cpu_dying = intel_pmu_cpu_dying, 5282 .cpu_dead = intel_pmu_cpu_dead, 5283 5284 .check_period = intel_pmu_check_period, 5285 5286 .lbr_reset = intel_pmu_lbr_reset_64, 5287 .lbr_read = intel_pmu_lbr_read_64, 5288 .lbr_save = intel_pmu_lbr_save, 5289 .lbr_restore = intel_pmu_lbr_restore, 5290 }; 5291 5292 static __initconst const struct x86_pmu intel_pmu = { 5293 .name = "Intel", 5294 .handle_irq = intel_pmu_handle_irq, 5295 .disable_all = intel_pmu_disable_all, 5296 .enable_all = intel_pmu_enable_all, 5297 .enable = intel_pmu_enable_event, 5298 .disable = intel_pmu_disable_event, 5299 .add = intel_pmu_add_event, 5300 .del = intel_pmu_del_event, 5301 .read = intel_pmu_read_event, 5302 .set_period = intel_pmu_set_period, 5303 .update = intel_pmu_update, 5304 .hw_config = intel_pmu_hw_config, 5305 .schedule_events = x86_schedule_events, 5306 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 5307 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 5308 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0, 5309 .event_map = intel_pmu_event_map, 5310 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 5311 .apic = 1, 5312 .large_pebs_flags = LARGE_PEBS_FLAGS, 5313 /* 5314 * Intel PMCs cannot be accessed sanely above 32 bit width, 5315 * so we install an artificial 1<<31 period regardless of 5316 * the generic event period: 5317 */ 5318 .max_period = (1ULL << 31) - 1, 5319 .get_event_constraints = intel_get_event_constraints, 5320 .put_event_constraints = intel_put_event_constraints, 5321 .pebs_aliases = intel_pebs_aliases_core2, 5322 5323 .format_attrs = intel_arch3_formats_attr, 5324 .events_sysfs_show = intel_event_sysfs_show, 5325 5326 .cpu_prepare = intel_pmu_cpu_prepare, 5327 .cpu_starting = intel_pmu_cpu_starting, 5328 .cpu_dying = intel_pmu_cpu_dying, 5329 .cpu_dead = intel_pmu_cpu_dead, 5330 5331 .guest_get_msrs = intel_guest_get_msrs, 5332 .sched_task = intel_pmu_sched_task, 5333 .swap_task_ctx = intel_pmu_swap_task_ctx, 5334 5335 .check_period = intel_pmu_check_period, 5336 5337 .aux_output_match = intel_pmu_aux_output_match, 5338 5339 .lbr_reset = intel_pmu_lbr_reset_64, 5340 .lbr_read = intel_pmu_lbr_read_64, 5341 .lbr_save = intel_pmu_lbr_save, 5342 .lbr_restore = intel_pmu_lbr_restore, 5343 5344 /* 5345 * SMM has access to all 4 rings and while traditionally SMM code only 5346 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM. 5347 * 5348 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction 5349 * between SMM or not, this results in what should be pure userspace 5350 * counters including SMM data. 5351 * 5352 * This is a clear privilege issue, therefore globally disable 5353 * counting SMM by default. 5354 */ 5355 .attr_freeze_on_smi = 1, 5356 }; 5357 5358 static __init void intel_clovertown_quirk(void) 5359 { 5360 /* 5361 * PEBS is unreliable due to: 5362 * 5363 * AJ67 - PEBS may experience CPL leaks 5364 * AJ68 - PEBS PMI may be delayed by one event 5365 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 5366 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 5367 * 5368 * AJ67 could be worked around by restricting the OS/USR flags. 5369 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 5370 * 5371 * AJ106 could possibly be worked around by not allowing LBR 5372 * usage from PEBS, including the fixup. 5373 * AJ68 could possibly be worked around by always programming 5374 * a pebs_event_reset[0] value and coping with the lost events. 5375 * 5376 * But taken together it might just make sense to not enable PEBS on 5377 * these chips. 5378 */ 5379 pr_warn("PEBS disabled due to CPU errata\n"); 5380 x86_pmu.pebs = 0; 5381 x86_pmu.pebs_constraints = NULL; 5382 } 5383 5384 static const struct x86_cpu_desc isolation_ucodes[] = { 5385 INTEL_CPU_DESC(INTEL_HASWELL, 3, 0x0000001f), 5386 INTEL_CPU_DESC(INTEL_HASWELL_L, 1, 0x0000001e), 5387 INTEL_CPU_DESC(INTEL_HASWELL_G, 1, 0x00000015), 5388 INTEL_CPU_DESC(INTEL_HASWELL_X, 2, 0x00000037), 5389 INTEL_CPU_DESC(INTEL_HASWELL_X, 4, 0x0000000a), 5390 INTEL_CPU_DESC(INTEL_BROADWELL, 4, 0x00000023), 5391 INTEL_CPU_DESC(INTEL_BROADWELL_G, 1, 0x00000014), 5392 INTEL_CPU_DESC(INTEL_BROADWELL_D, 2, 0x00000010), 5393 INTEL_CPU_DESC(INTEL_BROADWELL_D, 3, 0x07000009), 5394 INTEL_CPU_DESC(INTEL_BROADWELL_D, 4, 0x0f000009), 5395 INTEL_CPU_DESC(INTEL_BROADWELL_D, 5, 0x0e000002), 5396 INTEL_CPU_DESC(INTEL_BROADWELL_X, 1, 0x0b000014), 5397 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 3, 0x00000021), 5398 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 4, 0x00000000), 5399 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 5, 0x00000000), 5400 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 6, 0x00000000), 5401 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 7, 0x00000000), 5402 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 11, 0x00000000), 5403 INTEL_CPU_DESC(INTEL_SKYLAKE_L, 3, 0x0000007c), 5404 INTEL_CPU_DESC(INTEL_SKYLAKE, 3, 0x0000007c), 5405 INTEL_CPU_DESC(INTEL_KABYLAKE, 9, 0x0000004e), 5406 INTEL_CPU_DESC(INTEL_KABYLAKE_L, 9, 0x0000004e), 5407 INTEL_CPU_DESC(INTEL_KABYLAKE_L, 10, 0x0000004e), 5408 INTEL_CPU_DESC(INTEL_KABYLAKE_L, 11, 0x0000004e), 5409 INTEL_CPU_DESC(INTEL_KABYLAKE_L, 12, 0x0000004e), 5410 INTEL_CPU_DESC(INTEL_KABYLAKE, 10, 0x0000004e), 5411 INTEL_CPU_DESC(INTEL_KABYLAKE, 11, 0x0000004e), 5412 INTEL_CPU_DESC(INTEL_KABYLAKE, 12, 0x0000004e), 5413 INTEL_CPU_DESC(INTEL_KABYLAKE, 13, 0x0000004e), 5414 {} 5415 }; 5416 5417 static void intel_check_pebs_isolation(void) 5418 { 5419 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 5420 } 5421 5422 static __init void intel_pebs_isolation_quirk(void) 5423 { 5424 WARN_ON_ONCE(x86_pmu.check_microcode); 5425 x86_pmu.check_microcode = intel_check_pebs_isolation; 5426 intel_check_pebs_isolation(); 5427 } 5428 5429 static const struct x86_cpu_desc pebs_ucodes[] = { 5430 INTEL_CPU_DESC(INTEL_SANDYBRIDGE, 7, 0x00000028), 5431 INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X, 6, 0x00000618), 5432 INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X, 7, 0x0000070c), 5433 {} 5434 }; 5435 5436 static bool intel_snb_pebs_broken(void) 5437 { 5438 return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 5439 } 5440 5441 static void intel_snb_check_microcode(void) 5442 { 5443 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 5444 return; 5445 5446 /* 5447 * Serialized by the microcode lock.. 5448 */ 5449 if (x86_pmu.pebs_broken) { 5450 pr_info("PEBS enabled due to microcode update\n"); 5451 x86_pmu.pebs_broken = 0; 5452 } else { 5453 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 5454 x86_pmu.pebs_broken = 1; 5455 } 5456 } 5457 5458 static bool is_lbr_from(unsigned long msr) 5459 { 5460 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 5461 5462 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 5463 } 5464 5465 /* 5466 * Under certain circumstances, access certain MSR may cause #GP. 5467 * The function tests if the input MSR can be safely accessed. 5468 */ 5469 static bool check_msr(unsigned long msr, u64 mask) 5470 { 5471 u64 val_old, val_new, val_tmp; 5472 5473 /* 5474 * Disable the check for real HW, so we don't 5475 * mess with potentially enabled registers: 5476 */ 5477 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 5478 return true; 5479 5480 /* 5481 * Read the current value, change it and read it back to see if it 5482 * matches, this is needed to detect certain hardware emulators 5483 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 5484 */ 5485 if (rdmsrl_safe(msr, &val_old)) 5486 return false; 5487 5488 /* 5489 * Only change the bits which can be updated by wrmsrl. 5490 */ 5491 val_tmp = val_old ^ mask; 5492 5493 if (is_lbr_from(msr)) 5494 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 5495 5496 if (wrmsrl_safe(msr, val_tmp) || 5497 rdmsrl_safe(msr, &val_new)) 5498 return false; 5499 5500 /* 5501 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 5502 * should equal rdmsrl()'s even with the quirk. 5503 */ 5504 if (val_new != val_tmp) 5505 return false; 5506 5507 if (is_lbr_from(msr)) 5508 val_old = lbr_from_signext_quirk_wr(val_old); 5509 5510 /* Here it's sure that the MSR can be safely accessed. 5511 * Restore the old value and return. 5512 */ 5513 wrmsrl(msr, val_old); 5514 5515 return true; 5516 } 5517 5518 static __init void intel_sandybridge_quirk(void) 5519 { 5520 x86_pmu.check_microcode = intel_snb_check_microcode; 5521 cpus_read_lock(); 5522 intel_snb_check_microcode(); 5523 cpus_read_unlock(); 5524 } 5525 5526 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 5527 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 5528 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 5529 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 5530 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 5531 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 5532 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 5533 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 5534 }; 5535 5536 static __init void intel_arch_events_quirk(void) 5537 { 5538 int bit; 5539 5540 /* disable event that reported as not present by cpuid */ 5541 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 5542 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 5543 pr_warn("CPUID marked event: \'%s\' unavailable\n", 5544 intel_arch_events_map[bit].name); 5545 } 5546 } 5547 5548 static __init void intel_nehalem_quirk(void) 5549 { 5550 union cpuid10_ebx ebx; 5551 5552 ebx.full = x86_pmu.events_maskl; 5553 if (ebx.split.no_branch_misses_retired) { 5554 /* 5555 * Erratum AAJ80 detected, we work it around by using 5556 * the BR_MISP_EXEC.ANY event. This will over-count 5557 * branch-misses, but it's still much better than the 5558 * architectural event which is often completely bogus: 5559 */ 5560 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 5561 ebx.split.no_branch_misses_retired = 0; 5562 x86_pmu.events_maskl = ebx.full; 5563 pr_info("CPU erratum AAJ80 worked around\n"); 5564 } 5565 } 5566 5567 /* 5568 * enable software workaround for errata: 5569 * SNB: BJ122 5570 * IVB: BV98 5571 * HSW: HSD29 5572 * 5573 * Only needed when HT is enabled. However detecting 5574 * if HT is enabled is difficult (model specific). So instead, 5575 * we enable the workaround in the early boot, and verify if 5576 * it is needed in a later initcall phase once we have valid 5577 * topology information to check if HT is actually enabled 5578 */ 5579 static __init void intel_ht_bug(void) 5580 { 5581 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 5582 5583 x86_pmu.start_scheduling = intel_start_scheduling; 5584 x86_pmu.commit_scheduling = intel_commit_scheduling; 5585 x86_pmu.stop_scheduling = intel_stop_scheduling; 5586 } 5587 5588 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 5589 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 5590 5591 /* Haswell special events */ 5592 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 5593 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 5594 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 5595 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 5596 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 5597 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 5598 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 5599 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 5600 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 5601 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 5602 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 5603 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 5604 5605 static struct attribute *hsw_events_attrs[] = { 5606 EVENT_PTR(td_slots_issued), 5607 EVENT_PTR(td_slots_retired), 5608 EVENT_PTR(td_fetch_bubbles), 5609 EVENT_PTR(td_total_slots), 5610 EVENT_PTR(td_total_slots_scale), 5611 EVENT_PTR(td_recovery_bubbles), 5612 EVENT_PTR(td_recovery_bubbles_scale), 5613 NULL 5614 }; 5615 5616 static struct attribute *hsw_mem_events_attrs[] = { 5617 EVENT_PTR(mem_ld_hsw), 5618 EVENT_PTR(mem_st_hsw), 5619 NULL, 5620 }; 5621 5622 static struct attribute *hsw_tsx_events_attrs[] = { 5623 EVENT_PTR(tx_start), 5624 EVENT_PTR(tx_commit), 5625 EVENT_PTR(tx_abort), 5626 EVENT_PTR(tx_capacity), 5627 EVENT_PTR(tx_conflict), 5628 EVENT_PTR(el_start), 5629 EVENT_PTR(el_commit), 5630 EVENT_PTR(el_abort), 5631 EVENT_PTR(el_capacity), 5632 EVENT_PTR(el_conflict), 5633 EVENT_PTR(cycles_t), 5634 EVENT_PTR(cycles_ct), 5635 NULL 5636 }; 5637 5638 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 5639 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 5640 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 5641 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 5642 5643 static struct attribute *icl_events_attrs[] = { 5644 EVENT_PTR(mem_ld_hsw), 5645 EVENT_PTR(mem_st_hsw), 5646 NULL, 5647 }; 5648 5649 static struct attribute *icl_td_events_attrs[] = { 5650 EVENT_PTR(slots), 5651 EVENT_PTR(td_retiring), 5652 EVENT_PTR(td_bad_spec), 5653 EVENT_PTR(td_fe_bound), 5654 EVENT_PTR(td_be_bound), 5655 NULL, 5656 }; 5657 5658 static struct attribute *icl_tsx_events_attrs[] = { 5659 EVENT_PTR(tx_start), 5660 EVENT_PTR(tx_abort), 5661 EVENT_PTR(tx_commit), 5662 EVENT_PTR(tx_capacity_read), 5663 EVENT_PTR(tx_capacity_write), 5664 EVENT_PTR(tx_conflict), 5665 EVENT_PTR(el_start), 5666 EVENT_PTR(el_abort), 5667 EVENT_PTR(el_commit), 5668 EVENT_PTR(el_capacity_read), 5669 EVENT_PTR(el_capacity_write), 5670 EVENT_PTR(el_conflict), 5671 EVENT_PTR(cycles_t), 5672 EVENT_PTR(cycles_ct), 5673 NULL, 5674 }; 5675 5676 5677 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 5678 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 5679 5680 static struct attribute *glc_events_attrs[] = { 5681 EVENT_PTR(mem_ld_hsw), 5682 EVENT_PTR(mem_st_spr), 5683 EVENT_PTR(mem_ld_aux), 5684 NULL, 5685 }; 5686 5687 static struct attribute *glc_td_events_attrs[] = { 5688 EVENT_PTR(slots), 5689 EVENT_PTR(td_retiring), 5690 EVENT_PTR(td_bad_spec), 5691 EVENT_PTR(td_fe_bound), 5692 EVENT_PTR(td_be_bound), 5693 EVENT_PTR(td_heavy_ops), 5694 EVENT_PTR(td_br_mispredict), 5695 EVENT_PTR(td_fetch_lat), 5696 EVENT_PTR(td_mem_bound), 5697 NULL, 5698 }; 5699 5700 static struct attribute *glc_tsx_events_attrs[] = { 5701 EVENT_PTR(tx_start), 5702 EVENT_PTR(tx_abort), 5703 EVENT_PTR(tx_commit), 5704 EVENT_PTR(tx_capacity_read), 5705 EVENT_PTR(tx_capacity_write), 5706 EVENT_PTR(tx_conflict), 5707 EVENT_PTR(cycles_t), 5708 EVENT_PTR(cycles_ct), 5709 NULL, 5710 }; 5711 5712 static ssize_t freeze_on_smi_show(struct device *cdev, 5713 struct device_attribute *attr, 5714 char *buf) 5715 { 5716 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 5717 } 5718 5719 static DEFINE_MUTEX(freeze_on_smi_mutex); 5720 5721 static ssize_t freeze_on_smi_store(struct device *cdev, 5722 struct device_attribute *attr, 5723 const char *buf, size_t count) 5724 { 5725 unsigned long val; 5726 ssize_t ret; 5727 5728 ret = kstrtoul(buf, 0, &val); 5729 if (ret) 5730 return ret; 5731 5732 if (val > 1) 5733 return -EINVAL; 5734 5735 mutex_lock(&freeze_on_smi_mutex); 5736 5737 if (x86_pmu.attr_freeze_on_smi == val) 5738 goto done; 5739 5740 x86_pmu.attr_freeze_on_smi = val; 5741 5742 cpus_read_lock(); 5743 on_each_cpu(flip_smm_bit, &val, 1); 5744 cpus_read_unlock(); 5745 done: 5746 mutex_unlock(&freeze_on_smi_mutex); 5747 5748 return count; 5749 } 5750 5751 static void update_tfa_sched(void *ignored) 5752 { 5753 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5754 5755 /* 5756 * check if PMC3 is used 5757 * and if so force schedule out for all event types all contexts 5758 */ 5759 if (test_bit(3, cpuc->active_mask)) 5760 perf_pmu_resched(x86_get_pmu(smp_processor_id())); 5761 } 5762 5763 static ssize_t show_sysctl_tfa(struct device *cdev, 5764 struct device_attribute *attr, 5765 char *buf) 5766 { 5767 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 5768 } 5769 5770 static ssize_t set_sysctl_tfa(struct device *cdev, 5771 struct device_attribute *attr, 5772 const char *buf, size_t count) 5773 { 5774 bool val; 5775 ssize_t ret; 5776 5777 ret = kstrtobool(buf, &val); 5778 if (ret) 5779 return ret; 5780 5781 /* no change */ 5782 if (val == allow_tsx_force_abort) 5783 return count; 5784 5785 allow_tsx_force_abort = val; 5786 5787 cpus_read_lock(); 5788 on_each_cpu(update_tfa_sched, NULL, 1); 5789 cpus_read_unlock(); 5790 5791 return count; 5792 } 5793 5794 5795 static DEVICE_ATTR_RW(freeze_on_smi); 5796 5797 static ssize_t branches_show(struct device *cdev, 5798 struct device_attribute *attr, 5799 char *buf) 5800 { 5801 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 5802 } 5803 5804 static DEVICE_ATTR_RO(branches); 5805 5806 static ssize_t branch_counter_nr_show(struct device *cdev, 5807 struct device_attribute *attr, 5808 char *buf) 5809 { 5810 return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_counters)); 5811 } 5812 5813 static DEVICE_ATTR_RO(branch_counter_nr); 5814 5815 static ssize_t branch_counter_width_show(struct device *cdev, 5816 struct device_attribute *attr, 5817 char *buf) 5818 { 5819 return snprintf(buf, PAGE_SIZE, "%d\n", LBR_INFO_BR_CNTR_BITS); 5820 } 5821 5822 static DEVICE_ATTR_RO(branch_counter_width); 5823 5824 static struct attribute *lbr_attrs[] = { 5825 &dev_attr_branches.attr, 5826 &dev_attr_branch_counter_nr.attr, 5827 &dev_attr_branch_counter_width.attr, 5828 NULL 5829 }; 5830 5831 static umode_t 5832 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5833 { 5834 /* branches */ 5835 if (i == 0) 5836 return x86_pmu.lbr_nr ? attr->mode : 0; 5837 5838 return (x86_pmu.flags & PMU_FL_BR_CNTR) ? attr->mode : 0; 5839 } 5840 5841 static char pmu_name_str[30]; 5842 5843 static DEVICE_STRING_ATTR_RO(pmu_name, 0444, pmu_name_str); 5844 5845 static struct attribute *intel_pmu_caps_attrs[] = { 5846 &dev_attr_pmu_name.attr.attr, 5847 NULL 5848 }; 5849 5850 static DEVICE_ATTR(allow_tsx_force_abort, 0644, 5851 show_sysctl_tfa, 5852 set_sysctl_tfa); 5853 5854 static struct attribute *intel_pmu_attrs[] = { 5855 &dev_attr_freeze_on_smi.attr, 5856 &dev_attr_allow_tsx_force_abort.attr, 5857 NULL, 5858 }; 5859 5860 static umode_t 5861 default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5862 { 5863 if (attr == &dev_attr_allow_tsx_force_abort.attr) 5864 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 5865 5866 return attr->mode; 5867 } 5868 5869 static umode_t 5870 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5871 { 5872 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 5873 } 5874 5875 static umode_t 5876 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5877 { 5878 return x86_pmu.pebs ? attr->mode : 0; 5879 } 5880 5881 static umode_t 5882 mem_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5883 { 5884 if (attr == &event_attr_mem_ld_aux.attr.attr) 5885 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0; 5886 5887 return pebs_is_visible(kobj, attr, i); 5888 } 5889 5890 static umode_t 5891 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5892 { 5893 return x86_pmu.version >= 2 ? attr->mode : 0; 5894 } 5895 5896 static umode_t 5897 td_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5898 { 5899 /* 5900 * Hide the perf metrics topdown events 5901 * if the feature is not enumerated. 5902 */ 5903 if (x86_pmu.num_topdown_events) 5904 return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0; 5905 5906 return attr->mode; 5907 } 5908 5909 static struct attribute_group group_events_td = { 5910 .name = "events", 5911 .is_visible = td_is_visible, 5912 }; 5913 5914 static struct attribute_group group_events_mem = { 5915 .name = "events", 5916 .is_visible = mem_is_visible, 5917 }; 5918 5919 static struct attribute_group group_events_tsx = { 5920 .name = "events", 5921 .is_visible = tsx_is_visible, 5922 }; 5923 5924 static struct attribute_group group_caps_gen = { 5925 .name = "caps", 5926 .attrs = intel_pmu_caps_attrs, 5927 }; 5928 5929 static struct attribute_group group_caps_lbr = { 5930 .name = "caps", 5931 .attrs = lbr_attrs, 5932 .is_visible = lbr_is_visible, 5933 }; 5934 5935 static struct attribute_group group_format_extra = { 5936 .name = "format", 5937 .is_visible = exra_is_visible, 5938 }; 5939 5940 static struct attribute_group group_format_extra_skl = { 5941 .name = "format", 5942 .is_visible = exra_is_visible, 5943 }; 5944 5945 static struct attribute_group group_format_evtsel_ext = { 5946 .name = "format", 5947 .attrs = format_evtsel_ext_attrs, 5948 .is_visible = evtsel_ext_is_visible, 5949 }; 5950 5951 static struct attribute_group group_default = { 5952 .attrs = intel_pmu_attrs, 5953 .is_visible = default_is_visible, 5954 }; 5955 5956 static const struct attribute_group *attr_update[] = { 5957 &group_events_td, 5958 &group_events_mem, 5959 &group_events_tsx, 5960 &group_caps_gen, 5961 &group_caps_lbr, 5962 &group_format_extra, 5963 &group_format_extra_skl, 5964 &group_format_evtsel_ext, 5965 &group_default, 5966 NULL, 5967 }; 5968 5969 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); 5970 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); 5971 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); 5972 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); 5973 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); 5974 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); 5975 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); 5976 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); 5977 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); 5978 5979 static struct attribute *adl_hybrid_events_attrs[] = { 5980 EVENT_PTR(slots_adl), 5981 EVENT_PTR(td_retiring_adl), 5982 EVENT_PTR(td_bad_spec_adl), 5983 EVENT_PTR(td_fe_bound_adl), 5984 EVENT_PTR(td_be_bound_adl), 5985 EVENT_PTR(td_heavy_ops_adl), 5986 EVENT_PTR(td_br_mis_adl), 5987 EVENT_PTR(td_fetch_lat_adl), 5988 EVENT_PTR(td_mem_bound_adl), 5989 NULL, 5990 }; 5991 5992 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_lnl, "event=0xc2,umask=0x02;event=0x00,umask=0x80", hybrid_big_small); 5993 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_lnl, "event=0x9c,umask=0x01;event=0x00,umask=0x82", hybrid_big_small); 5994 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_lnl, "event=0xa4,umask=0x02;event=0x00,umask=0x83", hybrid_big_small); 5995 5996 static struct attribute *lnl_hybrid_events_attrs[] = { 5997 EVENT_PTR(slots_adl), 5998 EVENT_PTR(td_retiring_lnl), 5999 EVENT_PTR(td_bad_spec_adl), 6000 EVENT_PTR(td_fe_bound_lnl), 6001 EVENT_PTR(td_be_bound_lnl), 6002 EVENT_PTR(td_heavy_ops_adl), 6003 EVENT_PTR(td_br_mis_adl), 6004 EVENT_PTR(td_fetch_lat_adl), 6005 EVENT_PTR(td_mem_bound_adl), 6006 NULL 6007 }; 6008 6009 /* The event string must be in PMU IDX order. */ 6010 EVENT_ATTR_STR_HYBRID(topdown-retiring, 6011 td_retiring_arl_h, 6012 "event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0", 6013 hybrid_big_small_tiny); 6014 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, 6015 td_bad_spec_arl_h, 6016 "event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0", 6017 hybrid_big_small_tiny); 6018 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, 6019 td_fe_bound_arl_h, 6020 "event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0", 6021 hybrid_big_small_tiny); 6022 EVENT_ATTR_STR_HYBRID(topdown-be-bound, 6023 td_be_bound_arl_h, 6024 "event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0", 6025 hybrid_big_small_tiny); 6026 6027 static struct attribute *arl_h_hybrid_events_attrs[] = { 6028 EVENT_PTR(slots_adl), 6029 EVENT_PTR(td_retiring_arl_h), 6030 EVENT_PTR(td_bad_spec_arl_h), 6031 EVENT_PTR(td_fe_bound_arl_h), 6032 EVENT_PTR(td_be_bound_arl_h), 6033 EVENT_PTR(td_heavy_ops_adl), 6034 EVENT_PTR(td_br_mis_adl), 6035 EVENT_PTR(td_fetch_lat_adl), 6036 EVENT_PTR(td_mem_bound_adl), 6037 NULL, 6038 }; 6039 6040 /* Must be in IDX order */ 6041 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); 6042 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); 6043 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); 6044 6045 static struct attribute *adl_hybrid_mem_attrs[] = { 6046 EVENT_PTR(mem_ld_adl), 6047 EVENT_PTR(mem_st_adl), 6048 EVENT_PTR(mem_ld_aux_adl), 6049 NULL, 6050 }; 6051 6052 static struct attribute *mtl_hybrid_mem_attrs[] = { 6053 EVENT_PTR(mem_ld_adl), 6054 EVENT_PTR(mem_st_adl), 6055 NULL 6056 }; 6057 6058 EVENT_ATTR_STR_HYBRID(mem-loads, 6059 mem_ld_arl_h, 6060 "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3", 6061 hybrid_big_small_tiny); 6062 EVENT_ATTR_STR_HYBRID(mem-stores, 6063 mem_st_arl_h, 6064 "event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6", 6065 hybrid_big_small_tiny); 6066 6067 static struct attribute *arl_h_hybrid_mem_attrs[] = { 6068 EVENT_PTR(mem_ld_arl_h), 6069 EVENT_PTR(mem_st_arl_h), 6070 NULL, 6071 }; 6072 6073 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); 6074 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); 6075 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); 6076 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); 6077 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); 6078 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); 6079 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); 6080 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); 6081 6082 static struct attribute *adl_hybrid_tsx_attrs[] = { 6083 EVENT_PTR(tx_start_adl), 6084 EVENT_PTR(tx_abort_adl), 6085 EVENT_PTR(tx_commit_adl), 6086 EVENT_PTR(tx_capacity_read_adl), 6087 EVENT_PTR(tx_capacity_write_adl), 6088 EVENT_PTR(tx_conflict_adl), 6089 EVENT_PTR(cycles_t_adl), 6090 EVENT_PTR(cycles_ct_adl), 6091 NULL, 6092 }; 6093 6094 FORMAT_ATTR_HYBRID(in_tx, hybrid_big); 6095 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); 6096 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny); 6097 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny); 6098 FORMAT_ATTR_HYBRID(frontend, hybrid_big); 6099 6100 #define ADL_HYBRID_RTM_FORMAT_ATTR \ 6101 FORMAT_HYBRID_PTR(in_tx), \ 6102 FORMAT_HYBRID_PTR(in_tx_cp) 6103 6104 #define ADL_HYBRID_FORMAT_ATTR \ 6105 FORMAT_HYBRID_PTR(offcore_rsp), \ 6106 FORMAT_HYBRID_PTR(ldlat), \ 6107 FORMAT_HYBRID_PTR(frontend) 6108 6109 static struct attribute *adl_hybrid_extra_attr_rtm[] = { 6110 ADL_HYBRID_RTM_FORMAT_ATTR, 6111 ADL_HYBRID_FORMAT_ATTR, 6112 NULL 6113 }; 6114 6115 static struct attribute *adl_hybrid_extra_attr[] = { 6116 ADL_HYBRID_FORMAT_ATTR, 6117 NULL 6118 }; 6119 6120 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_tiny); 6121 6122 static struct attribute *mtl_hybrid_extra_attr_rtm[] = { 6123 ADL_HYBRID_RTM_FORMAT_ATTR, 6124 ADL_HYBRID_FORMAT_ATTR, 6125 FORMAT_HYBRID_PTR(snoop_rsp), 6126 NULL 6127 }; 6128 6129 static struct attribute *mtl_hybrid_extra_attr[] = { 6130 ADL_HYBRID_FORMAT_ATTR, 6131 FORMAT_HYBRID_PTR(snoop_rsp), 6132 NULL 6133 }; 6134 6135 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) 6136 { 6137 struct device *dev = kobj_to_dev(kobj); 6138 struct x86_hybrid_pmu *pmu = 6139 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6140 struct perf_pmu_events_hybrid_attr *pmu_attr = 6141 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); 6142 6143 return pmu->pmu_type & pmu_attr->pmu_type; 6144 } 6145 6146 static umode_t hybrid_events_is_visible(struct kobject *kobj, 6147 struct attribute *attr, int i) 6148 { 6149 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; 6150 } 6151 6152 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) 6153 { 6154 int cpu = cpumask_first(&pmu->supported_cpus); 6155 6156 return (cpu >= nr_cpu_ids) ? -1 : cpu; 6157 } 6158 6159 static umode_t hybrid_tsx_is_visible(struct kobject *kobj, 6160 struct attribute *attr, int i) 6161 { 6162 struct device *dev = kobj_to_dev(kobj); 6163 struct x86_hybrid_pmu *pmu = 6164 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6165 int cpu = hybrid_find_supported_cpu(pmu); 6166 6167 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; 6168 } 6169 6170 static umode_t hybrid_format_is_visible(struct kobject *kobj, 6171 struct attribute *attr, int i) 6172 { 6173 struct device *dev = kobj_to_dev(kobj); 6174 struct x86_hybrid_pmu *pmu = 6175 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6176 struct perf_pmu_format_hybrid_attr *pmu_attr = 6177 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); 6178 int cpu = hybrid_find_supported_cpu(pmu); 6179 6180 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0; 6181 } 6182 6183 static umode_t hybrid_td_is_visible(struct kobject *kobj, 6184 struct attribute *attr, int i) 6185 { 6186 struct device *dev = kobj_to_dev(kobj); 6187 struct x86_hybrid_pmu *pmu = 6188 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6189 6190 if (!is_attr_for_this_pmu(kobj, attr)) 6191 return 0; 6192 6193 6194 /* Only the big core supports perf metrics */ 6195 if (pmu->pmu_type == hybrid_big) 6196 return pmu->intel_cap.perf_metrics ? attr->mode : 0; 6197 6198 return attr->mode; 6199 } 6200 6201 static struct attribute_group hybrid_group_events_td = { 6202 .name = "events", 6203 .is_visible = hybrid_td_is_visible, 6204 }; 6205 6206 static struct attribute_group hybrid_group_events_mem = { 6207 .name = "events", 6208 .is_visible = hybrid_events_is_visible, 6209 }; 6210 6211 static struct attribute_group hybrid_group_events_tsx = { 6212 .name = "events", 6213 .is_visible = hybrid_tsx_is_visible, 6214 }; 6215 6216 static struct attribute_group hybrid_group_format_extra = { 6217 .name = "format", 6218 .is_visible = hybrid_format_is_visible, 6219 }; 6220 6221 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, 6222 struct device_attribute *attr, 6223 char *buf) 6224 { 6225 struct x86_hybrid_pmu *pmu = 6226 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6227 6228 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus); 6229 } 6230 6231 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); 6232 static struct attribute *intel_hybrid_cpus_attrs[] = { 6233 &dev_attr_cpus.attr, 6234 NULL, 6235 }; 6236 6237 static struct attribute_group hybrid_group_cpus = { 6238 .attrs = intel_hybrid_cpus_attrs, 6239 }; 6240 6241 static const struct attribute_group *hybrid_attr_update[] = { 6242 &hybrid_group_events_td, 6243 &hybrid_group_events_mem, 6244 &hybrid_group_events_tsx, 6245 &group_caps_gen, 6246 &group_caps_lbr, 6247 &hybrid_group_format_extra, 6248 &group_format_evtsel_ext, 6249 &group_default, 6250 &hybrid_group_cpus, 6251 NULL, 6252 }; 6253 6254 static struct attribute *empty_attrs; 6255 6256 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 6257 u64 cntr_mask, 6258 u64 fixed_cntr_mask, 6259 u64 intel_ctrl) 6260 { 6261 struct event_constraint *c; 6262 6263 if (!event_constraints) 6264 return; 6265 6266 /* 6267 * event on fixed counter2 (REF_CYCLES) only works on this 6268 * counter, so do not extend mask to generic counters 6269 */ 6270 for_each_event_constraint(c, event_constraints) { 6271 /* 6272 * Don't extend the topdown slots and metrics 6273 * events to the generic counters. 6274 */ 6275 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 6276 /* 6277 * Disable topdown slots and metrics events, 6278 * if slots event is not in CPUID. 6279 */ 6280 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) 6281 c->idxmsk64 = 0; 6282 c->weight = hweight64(c->idxmsk64); 6283 continue; 6284 } 6285 6286 if (c->cmask == FIXED_EVENT_FLAGS) { 6287 /* Disabled fixed counters which are not in CPUID */ 6288 c->idxmsk64 &= intel_ctrl; 6289 6290 /* 6291 * Don't extend the pseudo-encoding to the 6292 * generic counters 6293 */ 6294 if (!use_fixed_pseudo_encoding(c->code)) 6295 c->idxmsk64 |= cntr_mask; 6296 } 6297 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED); 6298 c->weight = hweight64(c->idxmsk64); 6299 } 6300 } 6301 6302 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) 6303 { 6304 struct extra_reg *er; 6305 6306 /* 6307 * Access extra MSR may cause #GP under certain circumstances. 6308 * E.g. KVM doesn't support offcore event 6309 * Check all extra_regs here. 6310 */ 6311 if (!extra_regs) 6312 return; 6313 6314 for (er = extra_regs; er->msr; er++) { 6315 er->extra_msr_access = check_msr(er->msr, 0x11UL); 6316 /* Disable LBR select mapping */ 6317 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 6318 x86_pmu.lbr_sel_map = NULL; 6319 } 6320 } 6321 6322 static inline int intel_pmu_v6_addr_offset(int index, bool eventsel) 6323 { 6324 return MSR_IA32_PMC_V6_STEP * index; 6325 } 6326 6327 static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = { 6328 { hybrid_small, "cpu_atom" }, 6329 { hybrid_big, "cpu_core" }, 6330 { hybrid_tiny, "cpu_lowpower" }, 6331 }; 6332 6333 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus) 6334 { 6335 unsigned long pmus_mask = pmus; 6336 struct x86_hybrid_pmu *pmu; 6337 int idx = 0, bit; 6338 6339 x86_pmu.num_hybrid_pmus = hweight_long(pmus_mask); 6340 x86_pmu.hybrid_pmu = kcalloc(x86_pmu.num_hybrid_pmus, 6341 sizeof(struct x86_hybrid_pmu), 6342 GFP_KERNEL); 6343 if (!x86_pmu.hybrid_pmu) 6344 return -ENOMEM; 6345 6346 static_branch_enable(&perf_is_hybrid); 6347 x86_pmu.filter = intel_pmu_filter; 6348 6349 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) { 6350 pmu = &x86_pmu.hybrid_pmu[idx++]; 6351 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id; 6352 pmu->name = intel_hybrid_pmu_type_map[bit].name; 6353 6354 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 6355 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 6356 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 6357 pmu->config_mask = X86_RAW_EVENT_MASK; 6358 pmu->unconstrained = (struct event_constraint) 6359 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 6360 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 6361 6362 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6363 if (pmu->pmu_type & hybrid_small_tiny) { 6364 pmu->intel_cap.perf_metrics = 0; 6365 pmu->intel_cap.pebs_output_pt_available = 1; 6366 pmu->mid_ack = true; 6367 } else if (pmu->pmu_type & hybrid_big) { 6368 pmu->intel_cap.perf_metrics = 1; 6369 pmu->intel_cap.pebs_output_pt_available = 0; 6370 pmu->late_ack = true; 6371 } 6372 } 6373 6374 return 0; 6375 } 6376 6377 static __always_inline void intel_pmu_ref_cycles_ext(void) 6378 { 6379 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED))) 6380 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c; 6381 } 6382 6383 static __always_inline void intel_pmu_init_glc(struct pmu *pmu) 6384 { 6385 x86_pmu.late_ack = true; 6386 x86_pmu.limit_period = glc_limit_period; 6387 x86_pmu.pebs_aliases = NULL; 6388 x86_pmu.pebs_prec_dist = true; 6389 x86_pmu.pebs_block = true; 6390 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6391 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6392 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6393 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6394 x86_pmu.lbr_pt_coexist = true; 6395 x86_pmu.num_topdown_events = 8; 6396 static_call_update(intel_pmu_update_topdown_event, 6397 &icl_update_topdown_event); 6398 static_call_update(intel_pmu_set_topdown_event_period, 6399 &icl_set_topdown_event_period); 6400 6401 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6402 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6403 hybrid(pmu, event_constraints) = intel_glc_event_constraints; 6404 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints; 6405 6406 intel_pmu_ref_cycles_ext(); 6407 } 6408 6409 static __always_inline void intel_pmu_init_grt(struct pmu *pmu) 6410 { 6411 x86_pmu.mid_ack = true; 6412 x86_pmu.limit_period = glc_limit_period; 6413 x86_pmu.pebs_aliases = NULL; 6414 x86_pmu.pebs_prec_dist = true; 6415 x86_pmu.pebs_block = true; 6416 x86_pmu.lbr_pt_coexist = true; 6417 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6418 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6419 6420 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6421 memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6422 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6423 hybrid(pmu, event_constraints) = intel_grt_event_constraints; 6424 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints; 6425 hybrid(pmu, extra_regs) = intel_grt_extra_regs; 6426 6427 intel_pmu_ref_cycles_ext(); 6428 } 6429 6430 static __always_inline void intel_pmu_init_lnc(struct pmu *pmu) 6431 { 6432 intel_pmu_init_glc(pmu); 6433 hybrid(pmu, event_constraints) = intel_lnc_event_constraints; 6434 hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints; 6435 hybrid(pmu, extra_regs) = intel_lnc_extra_regs; 6436 } 6437 6438 static __always_inline void intel_pmu_init_skt(struct pmu *pmu) 6439 { 6440 intel_pmu_init_grt(pmu); 6441 hybrid(pmu, event_constraints) = intel_skt_event_constraints; 6442 hybrid(pmu, extra_regs) = intel_cmt_extra_regs; 6443 } 6444 6445 __init int intel_pmu_init(void) 6446 { 6447 struct attribute **extra_skl_attr = &empty_attrs; 6448 struct attribute **extra_attr = &empty_attrs; 6449 struct attribute **td_attr = &empty_attrs; 6450 struct attribute **mem_attr = &empty_attrs; 6451 struct attribute **tsx_attr = &empty_attrs; 6452 union cpuid10_edx edx; 6453 union cpuid10_eax eax; 6454 union cpuid10_ebx ebx; 6455 unsigned int fixed_mask; 6456 bool pmem = false; 6457 int version, i; 6458 char *name; 6459 struct x86_hybrid_pmu *pmu; 6460 6461 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 6462 switch (boot_cpu_data.x86) { 6463 case 0x6: 6464 return p6_pmu_init(); 6465 case 0xb: 6466 return knc_pmu_init(); 6467 case 0xf: 6468 return p4_pmu_init(); 6469 } 6470 return -ENODEV; 6471 } 6472 6473 /* 6474 * Check whether the Architectural PerfMon supports 6475 * Branch Misses Retired hw_event or not. 6476 */ 6477 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); 6478 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 6479 return -ENODEV; 6480 6481 version = eax.split.version_id; 6482 if (version < 2) 6483 x86_pmu = core_pmu; 6484 else 6485 x86_pmu = intel_pmu; 6486 6487 x86_pmu.version = version; 6488 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0); 6489 x86_pmu.cntval_bits = eax.split.bit_width; 6490 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 6491 6492 x86_pmu.events_maskl = ebx.full; 6493 x86_pmu.events_mask_len = eax.split.mask_length; 6494 6495 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64); 6496 x86_pmu.pebs_capable = PEBS_COUNTER_MASK; 6497 6498 /* 6499 * Quirk: v2 perfmon does not report fixed-purpose events, so 6500 * assume at least 3 events, when not running in a hypervisor: 6501 */ 6502 if (version > 1 && version < 5) { 6503 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 6504 6505 x86_pmu.fixed_cntr_mask64 = 6506 GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0); 6507 } else if (version >= 5) 6508 x86_pmu.fixed_cntr_mask64 = fixed_mask; 6509 6510 if (boot_cpu_has(X86_FEATURE_PDCM)) { 6511 u64 capabilities; 6512 6513 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 6514 x86_pmu.intel_cap.capabilities = capabilities; 6515 } 6516 6517 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 6518 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 6519 x86_pmu.lbr_read = intel_pmu_lbr_read_32; 6520 } 6521 6522 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 6523 intel_pmu_arch_lbr_init(); 6524 6525 intel_ds_init(); 6526 6527 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 6528 6529 if (version >= 5) { 6530 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 6531 if (x86_pmu.intel_cap.anythread_deprecated) 6532 pr_cont(" AnyThread deprecated, "); 6533 } 6534 6535 /* 6536 * Install the hw-cache-events table: 6537 */ 6538 switch (boot_cpu_data.x86_vfm) { 6539 case INTEL_CORE_YONAH: 6540 pr_cont("Core events, "); 6541 name = "core"; 6542 break; 6543 6544 case INTEL_CORE2_MEROM: 6545 x86_add_quirk(intel_clovertown_quirk); 6546 fallthrough; 6547 6548 case INTEL_CORE2_MEROM_L: 6549 case INTEL_CORE2_PENRYN: 6550 case INTEL_CORE2_DUNNINGTON: 6551 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 6552 sizeof(hw_cache_event_ids)); 6553 6554 intel_pmu_lbr_init_core(); 6555 6556 x86_pmu.event_constraints = intel_core2_event_constraints; 6557 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 6558 pr_cont("Core2 events, "); 6559 name = "core2"; 6560 break; 6561 6562 case INTEL_NEHALEM: 6563 case INTEL_NEHALEM_EP: 6564 case INTEL_NEHALEM_EX: 6565 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 6566 sizeof(hw_cache_event_ids)); 6567 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 6568 sizeof(hw_cache_extra_regs)); 6569 6570 intel_pmu_lbr_init_nhm(); 6571 6572 x86_pmu.event_constraints = intel_nehalem_event_constraints; 6573 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 6574 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 6575 x86_pmu.extra_regs = intel_nehalem_extra_regs; 6576 x86_pmu.limit_period = nhm_limit_period; 6577 6578 mem_attr = nhm_mem_events_attrs; 6579 6580 /* UOPS_ISSUED.STALLED_CYCLES */ 6581 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6582 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6583 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 6584 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6585 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 6586 6587 intel_pmu_pebs_data_source_nhm(); 6588 x86_add_quirk(intel_nehalem_quirk); 6589 x86_pmu.pebs_no_tlb = 1; 6590 extra_attr = nhm_format_attr; 6591 6592 pr_cont("Nehalem events, "); 6593 name = "nehalem"; 6594 break; 6595 6596 case INTEL_ATOM_BONNELL: 6597 case INTEL_ATOM_BONNELL_MID: 6598 case INTEL_ATOM_SALTWELL: 6599 case INTEL_ATOM_SALTWELL_MID: 6600 case INTEL_ATOM_SALTWELL_TABLET: 6601 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 6602 sizeof(hw_cache_event_ids)); 6603 6604 intel_pmu_lbr_init_atom(); 6605 6606 x86_pmu.event_constraints = intel_gen_event_constraints; 6607 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 6608 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 6609 pr_cont("Atom events, "); 6610 name = "bonnell"; 6611 break; 6612 6613 case INTEL_ATOM_SILVERMONT: 6614 case INTEL_ATOM_SILVERMONT_D: 6615 case INTEL_ATOM_SILVERMONT_MID: 6616 case INTEL_ATOM_AIRMONT: 6617 case INTEL_ATOM_AIRMONT_MID: 6618 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 6619 sizeof(hw_cache_event_ids)); 6620 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 6621 sizeof(hw_cache_extra_regs)); 6622 6623 intel_pmu_lbr_init_slm(); 6624 6625 x86_pmu.event_constraints = intel_slm_event_constraints; 6626 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 6627 x86_pmu.extra_regs = intel_slm_extra_regs; 6628 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6629 td_attr = slm_events_attrs; 6630 extra_attr = slm_format_attr; 6631 pr_cont("Silvermont events, "); 6632 name = "silvermont"; 6633 break; 6634 6635 case INTEL_ATOM_GOLDMONT: 6636 case INTEL_ATOM_GOLDMONT_D: 6637 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 6638 sizeof(hw_cache_event_ids)); 6639 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 6640 sizeof(hw_cache_extra_regs)); 6641 6642 intel_pmu_lbr_init_skl(); 6643 6644 x86_pmu.event_constraints = intel_slm_event_constraints; 6645 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 6646 x86_pmu.extra_regs = intel_glm_extra_regs; 6647 /* 6648 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 6649 * for precise cycles. 6650 * :pp is identical to :ppp 6651 */ 6652 x86_pmu.pebs_aliases = NULL; 6653 x86_pmu.pebs_prec_dist = true; 6654 x86_pmu.lbr_pt_coexist = true; 6655 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6656 td_attr = glm_events_attrs; 6657 extra_attr = slm_format_attr; 6658 pr_cont("Goldmont events, "); 6659 name = "goldmont"; 6660 break; 6661 6662 case INTEL_ATOM_GOLDMONT_PLUS: 6663 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 6664 sizeof(hw_cache_event_ids)); 6665 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 6666 sizeof(hw_cache_extra_regs)); 6667 6668 intel_pmu_lbr_init_skl(); 6669 6670 x86_pmu.event_constraints = intel_slm_event_constraints; 6671 x86_pmu.extra_regs = intel_glm_extra_regs; 6672 /* 6673 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 6674 * for precise cycles. 6675 */ 6676 x86_pmu.pebs_aliases = NULL; 6677 x86_pmu.pebs_prec_dist = true; 6678 x86_pmu.lbr_pt_coexist = true; 6679 x86_pmu.pebs_capable = ~0ULL; 6680 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6681 x86_pmu.flags |= PMU_FL_PEBS_ALL; 6682 x86_pmu.get_event_constraints = glp_get_event_constraints; 6683 td_attr = glm_events_attrs; 6684 /* Goldmont Plus has 4-wide pipeline */ 6685 event_attr_td_total_slots_scale_glm.event_str = "4"; 6686 extra_attr = slm_format_attr; 6687 pr_cont("Goldmont plus events, "); 6688 name = "goldmont_plus"; 6689 break; 6690 6691 case INTEL_ATOM_TREMONT_D: 6692 case INTEL_ATOM_TREMONT: 6693 case INTEL_ATOM_TREMONT_L: 6694 x86_pmu.late_ack = true; 6695 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 6696 sizeof(hw_cache_event_ids)); 6697 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 6698 sizeof(hw_cache_extra_regs)); 6699 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6700 6701 intel_pmu_lbr_init_skl(); 6702 6703 x86_pmu.event_constraints = intel_slm_event_constraints; 6704 x86_pmu.extra_regs = intel_tnt_extra_regs; 6705 /* 6706 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 6707 * for precise cycles. 6708 */ 6709 x86_pmu.pebs_aliases = NULL; 6710 x86_pmu.pebs_prec_dist = true; 6711 x86_pmu.lbr_pt_coexist = true; 6712 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6713 x86_pmu.get_event_constraints = tnt_get_event_constraints; 6714 td_attr = tnt_events_attrs; 6715 extra_attr = slm_format_attr; 6716 pr_cont("Tremont events, "); 6717 name = "Tremont"; 6718 break; 6719 6720 case INTEL_ATOM_GRACEMONT: 6721 intel_pmu_init_grt(NULL); 6722 intel_pmu_pebs_data_source_grt(); 6723 x86_pmu.pebs_latency_data = grt_latency_data; 6724 x86_pmu.get_event_constraints = tnt_get_event_constraints; 6725 td_attr = tnt_events_attrs; 6726 mem_attr = grt_mem_attrs; 6727 extra_attr = nhm_format_attr; 6728 pr_cont("Gracemont events, "); 6729 name = "gracemont"; 6730 break; 6731 6732 case INTEL_ATOM_CRESTMONT: 6733 case INTEL_ATOM_CRESTMONT_X: 6734 intel_pmu_init_grt(NULL); 6735 x86_pmu.extra_regs = intel_cmt_extra_regs; 6736 intel_pmu_pebs_data_source_cmt(); 6737 x86_pmu.pebs_latency_data = cmt_latency_data; 6738 x86_pmu.get_event_constraints = cmt_get_event_constraints; 6739 td_attr = cmt_events_attrs; 6740 mem_attr = grt_mem_attrs; 6741 extra_attr = cmt_format_attr; 6742 pr_cont("Crestmont events, "); 6743 name = "crestmont"; 6744 break; 6745 6746 case INTEL_WESTMERE: 6747 case INTEL_WESTMERE_EP: 6748 case INTEL_WESTMERE_EX: 6749 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 6750 sizeof(hw_cache_event_ids)); 6751 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 6752 sizeof(hw_cache_extra_regs)); 6753 6754 intel_pmu_lbr_init_nhm(); 6755 6756 x86_pmu.event_constraints = intel_westmere_event_constraints; 6757 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 6758 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 6759 x86_pmu.extra_regs = intel_westmere_extra_regs; 6760 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6761 6762 mem_attr = nhm_mem_events_attrs; 6763 6764 /* UOPS_ISSUED.STALLED_CYCLES */ 6765 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6766 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6767 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 6768 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6769 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 6770 6771 intel_pmu_pebs_data_source_nhm(); 6772 extra_attr = nhm_format_attr; 6773 pr_cont("Westmere events, "); 6774 name = "westmere"; 6775 break; 6776 6777 case INTEL_SANDYBRIDGE: 6778 case INTEL_SANDYBRIDGE_X: 6779 x86_add_quirk(intel_sandybridge_quirk); 6780 x86_add_quirk(intel_ht_bug); 6781 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 6782 sizeof(hw_cache_event_ids)); 6783 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 6784 sizeof(hw_cache_extra_regs)); 6785 6786 intel_pmu_lbr_init_snb(); 6787 6788 x86_pmu.event_constraints = intel_snb_event_constraints; 6789 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 6790 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 6791 if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X) 6792 x86_pmu.extra_regs = intel_snbep_extra_regs; 6793 else 6794 x86_pmu.extra_regs = intel_snb_extra_regs; 6795 6796 6797 /* all extra regs are per-cpu when HT is on */ 6798 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6799 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6800 6801 td_attr = snb_events_attrs; 6802 mem_attr = snb_mem_events_attrs; 6803 6804 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 6805 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6806 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6807 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 6808 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6809 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 6810 6811 extra_attr = nhm_format_attr; 6812 6813 pr_cont("SandyBridge events, "); 6814 name = "sandybridge"; 6815 break; 6816 6817 case INTEL_IVYBRIDGE: 6818 case INTEL_IVYBRIDGE_X: 6819 x86_add_quirk(intel_ht_bug); 6820 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 6821 sizeof(hw_cache_event_ids)); 6822 /* dTLB-load-misses on IVB is different than SNB */ 6823 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 6824 6825 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 6826 sizeof(hw_cache_extra_regs)); 6827 6828 intel_pmu_lbr_init_snb(); 6829 6830 x86_pmu.event_constraints = intel_ivb_event_constraints; 6831 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 6832 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6833 x86_pmu.pebs_prec_dist = true; 6834 if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X) 6835 x86_pmu.extra_regs = intel_snbep_extra_regs; 6836 else 6837 x86_pmu.extra_regs = intel_snb_extra_regs; 6838 /* all extra regs are per-cpu when HT is on */ 6839 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6840 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6841 6842 td_attr = snb_events_attrs; 6843 mem_attr = snb_mem_events_attrs; 6844 6845 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 6846 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6847 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6848 6849 extra_attr = nhm_format_attr; 6850 6851 pr_cont("IvyBridge events, "); 6852 name = "ivybridge"; 6853 break; 6854 6855 6856 case INTEL_HASWELL: 6857 case INTEL_HASWELL_X: 6858 case INTEL_HASWELL_L: 6859 case INTEL_HASWELL_G: 6860 x86_add_quirk(intel_ht_bug); 6861 x86_add_quirk(intel_pebs_isolation_quirk); 6862 x86_pmu.late_ack = true; 6863 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6864 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6865 6866 intel_pmu_lbr_init_hsw(); 6867 6868 x86_pmu.event_constraints = intel_hsw_event_constraints; 6869 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 6870 x86_pmu.extra_regs = intel_snbep_extra_regs; 6871 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6872 x86_pmu.pebs_prec_dist = true; 6873 /* all extra regs are per-cpu when HT is on */ 6874 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6875 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6876 6877 x86_pmu.hw_config = hsw_hw_config; 6878 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6879 x86_pmu.limit_period = hsw_limit_period; 6880 x86_pmu.lbr_double_abort = true; 6881 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6882 hsw_format_attr : nhm_format_attr; 6883 td_attr = hsw_events_attrs; 6884 mem_attr = hsw_mem_events_attrs; 6885 tsx_attr = hsw_tsx_events_attrs; 6886 pr_cont("Haswell events, "); 6887 name = "haswell"; 6888 break; 6889 6890 case INTEL_BROADWELL: 6891 case INTEL_BROADWELL_D: 6892 case INTEL_BROADWELL_G: 6893 case INTEL_BROADWELL_X: 6894 x86_add_quirk(intel_pebs_isolation_quirk); 6895 x86_pmu.late_ack = true; 6896 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6897 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6898 6899 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 6900 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 6901 BDW_L3_MISS|HSW_SNOOP_DRAM; 6902 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 6903 HSW_SNOOP_DRAM; 6904 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 6905 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6906 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 6907 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6908 6909 intel_pmu_lbr_init_hsw(); 6910 6911 x86_pmu.event_constraints = intel_bdw_event_constraints; 6912 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 6913 x86_pmu.extra_regs = intel_snbep_extra_regs; 6914 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6915 x86_pmu.pebs_prec_dist = true; 6916 /* all extra regs are per-cpu when HT is on */ 6917 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6918 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6919 6920 x86_pmu.hw_config = hsw_hw_config; 6921 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6922 x86_pmu.limit_period = bdw_limit_period; 6923 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6924 hsw_format_attr : nhm_format_attr; 6925 td_attr = hsw_events_attrs; 6926 mem_attr = hsw_mem_events_attrs; 6927 tsx_attr = hsw_tsx_events_attrs; 6928 pr_cont("Broadwell events, "); 6929 name = "broadwell"; 6930 break; 6931 6932 case INTEL_XEON_PHI_KNL: 6933 case INTEL_XEON_PHI_KNM: 6934 memcpy(hw_cache_event_ids, 6935 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6936 memcpy(hw_cache_extra_regs, 6937 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6938 intel_pmu_lbr_init_knl(); 6939 6940 x86_pmu.event_constraints = intel_slm_event_constraints; 6941 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 6942 x86_pmu.extra_regs = intel_knl_extra_regs; 6943 6944 /* all extra regs are per-cpu when HT is on */ 6945 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6946 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6947 extra_attr = slm_format_attr; 6948 pr_cont("Knights Landing/Mill events, "); 6949 name = "knights-landing"; 6950 break; 6951 6952 case INTEL_SKYLAKE_X: 6953 pmem = true; 6954 fallthrough; 6955 case INTEL_SKYLAKE_L: 6956 case INTEL_SKYLAKE: 6957 case INTEL_KABYLAKE_L: 6958 case INTEL_KABYLAKE: 6959 case INTEL_COMETLAKE_L: 6960 case INTEL_COMETLAKE: 6961 x86_add_quirk(intel_pebs_isolation_quirk); 6962 x86_pmu.late_ack = true; 6963 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6964 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6965 intel_pmu_lbr_init_skl(); 6966 6967 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 6968 event_attr_td_recovery_bubbles.event_str_noht = 6969 "event=0xd,umask=0x1,cmask=1"; 6970 event_attr_td_recovery_bubbles.event_str_ht = 6971 "event=0xd,umask=0x1,cmask=1,any=1"; 6972 6973 x86_pmu.event_constraints = intel_skl_event_constraints; 6974 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 6975 x86_pmu.extra_regs = intel_skl_extra_regs; 6976 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 6977 x86_pmu.pebs_prec_dist = true; 6978 /* all extra regs are per-cpu when HT is on */ 6979 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6980 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6981 6982 x86_pmu.hw_config = hsw_hw_config; 6983 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6984 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6985 hsw_format_attr : nhm_format_attr; 6986 extra_skl_attr = skl_format_attr; 6987 td_attr = hsw_events_attrs; 6988 mem_attr = hsw_mem_events_attrs; 6989 tsx_attr = hsw_tsx_events_attrs; 6990 intel_pmu_pebs_data_source_skl(pmem); 6991 6992 /* 6993 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. 6994 * TSX force abort hooks are not required on these systems. Only deploy 6995 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. 6996 */ 6997 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && 6998 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { 6999 x86_pmu.flags |= PMU_FL_TFA; 7000 x86_pmu.get_event_constraints = tfa_get_event_constraints; 7001 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 7002 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 7003 } 7004 7005 pr_cont("Skylake events, "); 7006 name = "skylake"; 7007 break; 7008 7009 case INTEL_ICELAKE_X: 7010 case INTEL_ICELAKE_D: 7011 x86_pmu.pebs_ept = 1; 7012 pmem = true; 7013 fallthrough; 7014 case INTEL_ICELAKE_L: 7015 case INTEL_ICELAKE: 7016 case INTEL_TIGERLAKE_L: 7017 case INTEL_TIGERLAKE: 7018 case INTEL_ROCKETLAKE: 7019 x86_pmu.late_ack = true; 7020 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7021 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7022 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 7023 intel_pmu_lbr_init_skl(); 7024 7025 x86_pmu.event_constraints = intel_icl_event_constraints; 7026 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 7027 x86_pmu.extra_regs = intel_icl_extra_regs; 7028 x86_pmu.pebs_aliases = NULL; 7029 x86_pmu.pebs_prec_dist = true; 7030 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7031 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7032 7033 x86_pmu.hw_config = hsw_hw_config; 7034 x86_pmu.get_event_constraints = icl_get_event_constraints; 7035 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7036 hsw_format_attr : nhm_format_attr; 7037 extra_skl_attr = skl_format_attr; 7038 mem_attr = icl_events_attrs; 7039 td_attr = icl_td_events_attrs; 7040 tsx_attr = icl_tsx_events_attrs; 7041 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 7042 x86_pmu.lbr_pt_coexist = true; 7043 intel_pmu_pebs_data_source_skl(pmem); 7044 x86_pmu.num_topdown_events = 4; 7045 static_call_update(intel_pmu_update_topdown_event, 7046 &icl_update_topdown_event); 7047 static_call_update(intel_pmu_set_topdown_event_period, 7048 &icl_set_topdown_event_period); 7049 pr_cont("Icelake events, "); 7050 name = "icelake"; 7051 break; 7052 7053 case INTEL_SAPPHIRERAPIDS_X: 7054 case INTEL_EMERALDRAPIDS_X: 7055 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 7056 x86_pmu.extra_regs = intel_glc_extra_regs; 7057 pr_cont("Sapphire Rapids events, "); 7058 name = "sapphire_rapids"; 7059 goto glc_common; 7060 7061 case INTEL_GRANITERAPIDS_X: 7062 case INTEL_GRANITERAPIDS_D: 7063 x86_pmu.extra_regs = intel_rwc_extra_regs; 7064 pr_cont("Granite Rapids events, "); 7065 name = "granite_rapids"; 7066 7067 glc_common: 7068 intel_pmu_init_glc(NULL); 7069 x86_pmu.pebs_ept = 1; 7070 x86_pmu.hw_config = hsw_hw_config; 7071 x86_pmu.get_event_constraints = glc_get_event_constraints; 7072 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7073 hsw_format_attr : nhm_format_attr; 7074 extra_skl_attr = skl_format_attr; 7075 mem_attr = glc_events_attrs; 7076 td_attr = glc_td_events_attrs; 7077 tsx_attr = glc_tsx_events_attrs; 7078 intel_pmu_pebs_data_source_skl(true); 7079 break; 7080 7081 case INTEL_ALDERLAKE: 7082 case INTEL_ALDERLAKE_L: 7083 case INTEL_RAPTORLAKE: 7084 case INTEL_RAPTORLAKE_P: 7085 case INTEL_RAPTORLAKE_S: 7086 /* 7087 * Alder Lake has 2 types of CPU, core and atom. 7088 * 7089 * Initialize the common PerfMon capabilities here. 7090 */ 7091 intel_pmu_init_hybrid(hybrid_big_small); 7092 7093 x86_pmu.pebs_latency_data = grt_latency_data; 7094 x86_pmu.get_event_constraints = adl_get_event_constraints; 7095 x86_pmu.hw_config = adl_hw_config; 7096 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; 7097 7098 td_attr = adl_hybrid_events_attrs; 7099 mem_attr = adl_hybrid_mem_attrs; 7100 tsx_attr = adl_hybrid_tsx_attrs; 7101 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7102 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; 7103 7104 /* Initialize big core specific PerfMon capabilities.*/ 7105 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7106 intel_pmu_init_glc(&pmu->pmu); 7107 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 7108 pmu->cntr_mask64 <<= 2; 7109 pmu->cntr_mask64 |= 0x3; 7110 pmu->fixed_cntr_mask64 <<= 1; 7111 pmu->fixed_cntr_mask64 |= 0x1; 7112 } else { 7113 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 7114 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 7115 } 7116 7117 /* 7118 * Quirk: For some Alder Lake machine, when all E-cores are disabled in 7119 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However, 7120 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will 7121 * mistakenly add extra counters for P-cores. Correct the number of 7122 * counters here. 7123 */ 7124 if ((x86_pmu_num_counters(&pmu->pmu) > 8) || (x86_pmu_num_counters_fixed(&pmu->pmu) > 4)) { 7125 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 7126 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 7127 } 7128 7129 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 7130 pmu->unconstrained = (struct event_constraint) 7131 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 7132 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 7133 7134 pmu->extra_regs = intel_glc_extra_regs; 7135 7136 /* Initialize Atom core specific PerfMon capabilities.*/ 7137 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7138 intel_pmu_init_grt(&pmu->pmu); 7139 7140 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 7141 intel_pmu_pebs_data_source_adl(); 7142 pr_cont("Alderlake Hybrid events, "); 7143 name = "alderlake_hybrid"; 7144 break; 7145 7146 case INTEL_METEORLAKE: 7147 case INTEL_METEORLAKE_L: 7148 case INTEL_ARROWLAKE_U: 7149 intel_pmu_init_hybrid(hybrid_big_small); 7150 7151 x86_pmu.pebs_latency_data = cmt_latency_data; 7152 x86_pmu.get_event_constraints = mtl_get_event_constraints; 7153 x86_pmu.hw_config = adl_hw_config; 7154 7155 td_attr = adl_hybrid_events_attrs; 7156 mem_attr = mtl_hybrid_mem_attrs; 7157 tsx_attr = adl_hybrid_tsx_attrs; 7158 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7159 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 7160 7161 /* Initialize big core specific PerfMon capabilities.*/ 7162 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7163 intel_pmu_init_glc(&pmu->pmu); 7164 pmu->extra_regs = intel_rwc_extra_regs; 7165 7166 /* Initialize Atom core specific PerfMon capabilities.*/ 7167 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7168 intel_pmu_init_grt(&pmu->pmu); 7169 pmu->extra_regs = intel_cmt_extra_regs; 7170 7171 intel_pmu_pebs_data_source_mtl(); 7172 pr_cont("Meteorlake Hybrid events, "); 7173 name = "meteorlake_hybrid"; 7174 break; 7175 7176 case INTEL_LUNARLAKE_M: 7177 case INTEL_ARROWLAKE: 7178 intel_pmu_init_hybrid(hybrid_big_small); 7179 7180 x86_pmu.pebs_latency_data = lnl_latency_data; 7181 x86_pmu.get_event_constraints = mtl_get_event_constraints; 7182 x86_pmu.hw_config = adl_hw_config; 7183 7184 td_attr = lnl_hybrid_events_attrs; 7185 mem_attr = mtl_hybrid_mem_attrs; 7186 tsx_attr = adl_hybrid_tsx_attrs; 7187 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7188 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 7189 7190 /* Initialize big core specific PerfMon capabilities.*/ 7191 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7192 intel_pmu_init_lnc(&pmu->pmu); 7193 7194 /* Initialize Atom core specific PerfMon capabilities.*/ 7195 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7196 intel_pmu_init_skt(&pmu->pmu); 7197 7198 intel_pmu_pebs_data_source_lnl(); 7199 pr_cont("Lunarlake Hybrid events, "); 7200 name = "lunarlake_hybrid"; 7201 break; 7202 7203 case INTEL_ARROWLAKE_H: 7204 intel_pmu_init_hybrid(hybrid_big_small_tiny); 7205 7206 x86_pmu.pebs_latency_data = arl_h_latency_data; 7207 x86_pmu.get_event_constraints = arl_h_get_event_constraints; 7208 x86_pmu.hw_config = arl_h_hw_config; 7209 7210 td_attr = arl_h_hybrid_events_attrs; 7211 mem_attr = arl_h_hybrid_mem_attrs; 7212 tsx_attr = adl_hybrid_tsx_attrs; 7213 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7214 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 7215 7216 /* Initialize big core specific PerfMon capabilities. */ 7217 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7218 intel_pmu_init_lnc(&pmu->pmu); 7219 7220 /* Initialize Atom core specific PerfMon capabilities. */ 7221 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7222 intel_pmu_init_skt(&pmu->pmu); 7223 7224 /* Initialize Lower Power Atom specific PerfMon capabilities. */ 7225 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX]; 7226 intel_pmu_init_grt(&pmu->pmu); 7227 pmu->extra_regs = intel_cmt_extra_regs; 7228 7229 intel_pmu_pebs_data_source_arl_h(); 7230 pr_cont("ArrowLake-H Hybrid events, "); 7231 name = "arrowlake_h_hybrid"; 7232 break; 7233 7234 default: 7235 switch (x86_pmu.version) { 7236 case 1: 7237 x86_pmu.event_constraints = intel_v1_event_constraints; 7238 pr_cont("generic architected perfmon v1, "); 7239 name = "generic_arch_v1"; 7240 break; 7241 case 2: 7242 case 3: 7243 case 4: 7244 /* 7245 * default constraints for v2 and up 7246 */ 7247 x86_pmu.event_constraints = intel_gen_event_constraints; 7248 pr_cont("generic architected perfmon, "); 7249 name = "generic_arch_v2+"; 7250 break; 7251 default: 7252 /* 7253 * The default constraints for v5 and up can support up to 7254 * 16 fixed counters. For the fixed counters 4 and later, 7255 * the pseudo-encoding is applied. 7256 * The constraints may be cut according to the CPUID enumeration 7257 * by inserting the EVENT_CONSTRAINT_END. 7258 */ 7259 if (fls64(x86_pmu.fixed_cntr_mask64) > INTEL_PMC_MAX_FIXED) 7260 x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0); 7261 intel_v5_gen_event_constraints[fls64(x86_pmu.fixed_cntr_mask64)].weight = -1; 7262 x86_pmu.event_constraints = intel_v5_gen_event_constraints; 7263 pr_cont("generic architected perfmon, "); 7264 name = "generic_arch_v5+"; 7265 break; 7266 } 7267 } 7268 7269 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 7270 7271 if (!is_hybrid()) { 7272 group_events_td.attrs = td_attr; 7273 group_events_mem.attrs = mem_attr; 7274 group_events_tsx.attrs = tsx_attr; 7275 group_format_extra.attrs = extra_attr; 7276 group_format_extra_skl.attrs = extra_skl_attr; 7277 7278 x86_pmu.attr_update = attr_update; 7279 } else { 7280 hybrid_group_events_td.attrs = td_attr; 7281 hybrid_group_events_mem.attrs = mem_attr; 7282 hybrid_group_events_tsx.attrs = tsx_attr; 7283 hybrid_group_format_extra.attrs = extra_attr; 7284 7285 x86_pmu.attr_update = hybrid_attr_update; 7286 } 7287 7288 intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64, 7289 &x86_pmu.fixed_cntr_mask64, 7290 &x86_pmu.intel_ctrl); 7291 7292 /* AnyThread may be deprecated on arch perfmon v5 or later */ 7293 if (x86_pmu.intel_cap.anythread_deprecated) 7294 x86_pmu.format_attrs = intel_arch_formats_attr; 7295 7296 intel_pmu_check_event_constraints(x86_pmu.event_constraints, 7297 x86_pmu.cntr_mask64, 7298 x86_pmu.fixed_cntr_mask64, 7299 x86_pmu.intel_ctrl); 7300 /* 7301 * Access LBR MSR may cause #GP under certain circumstances. 7302 * Check all LBR MSR here. 7303 * Disable LBR access if any LBR MSRs can not be accessed. 7304 */ 7305 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 7306 x86_pmu.lbr_nr = 0; 7307 for (i = 0; i < x86_pmu.lbr_nr; i++) { 7308 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 7309 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 7310 x86_pmu.lbr_nr = 0; 7311 } 7312 7313 if (x86_pmu.lbr_nr) { 7314 intel_pmu_lbr_init(); 7315 7316 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 7317 7318 /* only support branch_stack snapshot for perfmon >= v2 */ 7319 if (x86_pmu.disable_all == intel_pmu_disable_all) { 7320 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) { 7321 static_call_update(perf_snapshot_branch_stack, 7322 intel_pmu_snapshot_arch_branch_stack); 7323 } else { 7324 static_call_update(perf_snapshot_branch_stack, 7325 intel_pmu_snapshot_branch_stack); 7326 } 7327 } 7328 } 7329 7330 intel_pmu_check_extra_regs(x86_pmu.extra_regs); 7331 7332 /* Support full width counters using alternative MSR range */ 7333 if (x86_pmu.intel_cap.full_width_write) { 7334 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 7335 x86_pmu.perfctr = MSR_IA32_PMC0; 7336 pr_cont("full-width counters, "); 7337 } 7338 7339 /* Support V6+ MSR Aliasing */ 7340 if (x86_pmu.version >= 6) { 7341 x86_pmu.perfctr = MSR_IA32_PMC_V6_GP0_CTR; 7342 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A; 7343 x86_pmu.fixedctr = MSR_IA32_PMC_V6_FX0_CTR; 7344 x86_pmu.addr_offset = intel_pmu_v6_addr_offset; 7345 } 7346 7347 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 7348 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 7349 7350 if (x86_pmu.intel_cap.pebs_timing_info) 7351 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY; 7352 7353 intel_aux_output_init(); 7354 7355 return 0; 7356 } 7357 7358 /* 7359 * HT bug: phase 2 init 7360 * Called once we have valid topology information to check 7361 * whether or not HT is enabled 7362 * If HT is off, then we disable the workaround 7363 */ 7364 static __init int fixup_ht_bug(void) 7365 { 7366 int c; 7367 /* 7368 * problem not present on this CPU model, nothing to do 7369 */ 7370 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 7371 return 0; 7372 7373 if (topology_max_smt_threads() > 1) { 7374 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 7375 return 0; 7376 } 7377 7378 cpus_read_lock(); 7379 7380 hardlockup_detector_perf_stop(); 7381 7382 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 7383 7384 x86_pmu.start_scheduling = NULL; 7385 x86_pmu.commit_scheduling = NULL; 7386 x86_pmu.stop_scheduling = NULL; 7387 7388 hardlockup_detector_perf_restart(); 7389 7390 for_each_online_cpu(c) 7391 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 7392 7393 cpus_read_unlock(); 7394 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 7395 return 0; 7396 } 7397 subsys_initcall(fixup_ht_bug) 7398