1 /* 2 * Performance events x86 architecture code 3 * 4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2009 Jaswinder Singh Rajput 7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 10 * Copyright (C) 2009 Google, Inc., Stephane Eranian 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 15 #include <linux/perf_event.h> 16 #include <linux/capability.h> 17 #include <linux/notifier.h> 18 #include <linux/hardirq.h> 19 #include <linux/kprobes.h> 20 #include <linux/export.h> 21 #include <linux/init.h> 22 #include <linux/kdebug.h> 23 #include <linux/sched/mm.h> 24 #include <linux/sched/clock.h> 25 #include <linux/uaccess.h> 26 #include <linux/slab.h> 27 #include <linux/cpu.h> 28 #include <linux/bitops.h> 29 #include <linux/device.h> 30 #include <linux/nospec.h> 31 32 #include <asm/apic.h> 33 #include <asm/stacktrace.h> 34 #include <asm/nmi.h> 35 #include <asm/smp.h> 36 #include <asm/alternative.h> 37 #include <asm/mmu_context.h> 38 #include <asm/tlbflush.h> 39 #include <asm/timer.h> 40 #include <asm/desc.h> 41 #include <asm/ldt.h> 42 #include <asm/unwind.h> 43 44 #include "perf_event.h" 45 46 struct x86_pmu x86_pmu __read_mostly; 47 48 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { 49 .enabled = 1, 50 }; 51 52 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key); 53 54 u64 __read_mostly hw_cache_event_ids 55 [PERF_COUNT_HW_CACHE_MAX] 56 [PERF_COUNT_HW_CACHE_OP_MAX] 57 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 58 u64 __read_mostly hw_cache_extra_regs 59 [PERF_COUNT_HW_CACHE_MAX] 60 [PERF_COUNT_HW_CACHE_OP_MAX] 61 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 62 63 /* 64 * Propagate event elapsed time into the generic event. 65 * Can only be executed on the CPU where the event is active. 66 * Returns the delta events processed. 67 */ 68 u64 x86_perf_event_update(struct perf_event *event) 69 { 70 struct hw_perf_event *hwc = &event->hw; 71 int shift = 64 - x86_pmu.cntval_bits; 72 u64 prev_raw_count, new_raw_count; 73 int idx = hwc->idx; 74 u64 delta; 75 76 if (idx == INTEL_PMC_IDX_FIXED_BTS) 77 return 0; 78 79 /* 80 * Careful: an NMI might modify the previous event value. 81 * 82 * Our tactic to handle this is to first atomically read and 83 * exchange a new raw count - then add that new-prev delta 84 * count to the generic event atomically: 85 */ 86 again: 87 prev_raw_count = local64_read(&hwc->prev_count); 88 rdpmcl(hwc->event_base_rdpmc, new_raw_count); 89 90 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, 91 new_raw_count) != prev_raw_count) 92 goto again; 93 94 /* 95 * Now we have the new raw value and have updated the prev 96 * timestamp already. We can now calculate the elapsed delta 97 * (event-)time and add that to the generic event. 98 * 99 * Careful, not all hw sign-extends above the physical width 100 * of the count. 101 */ 102 delta = (new_raw_count << shift) - (prev_raw_count << shift); 103 delta >>= shift; 104 105 local64_add(delta, &event->count); 106 local64_sub(delta, &hwc->period_left); 107 108 return new_raw_count; 109 } 110 111 /* 112 * Find and validate any extra registers to set up. 113 */ 114 static int x86_pmu_extra_regs(u64 config, struct perf_event *event) 115 { 116 struct hw_perf_event_extra *reg; 117 struct extra_reg *er; 118 119 reg = &event->hw.extra_reg; 120 121 if (!x86_pmu.extra_regs) 122 return 0; 123 124 for (er = x86_pmu.extra_regs; er->msr; er++) { 125 if (er->event != (config & er->config_mask)) 126 continue; 127 if (event->attr.config1 & ~er->valid_mask) 128 return -EINVAL; 129 /* Check if the extra msrs can be safely accessed*/ 130 if (!er->extra_msr_access) 131 return -ENXIO; 132 133 reg->idx = er->idx; 134 reg->config = event->attr.config1; 135 reg->reg = er->msr; 136 break; 137 } 138 return 0; 139 } 140 141 static atomic_t active_events; 142 static atomic_t pmc_refcount; 143 static DEFINE_MUTEX(pmc_reserve_mutex); 144 145 #ifdef CONFIG_X86_LOCAL_APIC 146 147 static bool reserve_pmc_hardware(void) 148 { 149 int i; 150 151 for (i = 0; i < x86_pmu.num_counters; i++) { 152 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) 153 goto perfctr_fail; 154 } 155 156 for (i = 0; i < x86_pmu.num_counters; i++) { 157 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) 158 goto eventsel_fail; 159 } 160 161 return true; 162 163 eventsel_fail: 164 for (i--; i >= 0; i--) 165 release_evntsel_nmi(x86_pmu_config_addr(i)); 166 167 i = x86_pmu.num_counters; 168 169 perfctr_fail: 170 for (i--; i >= 0; i--) 171 release_perfctr_nmi(x86_pmu_event_addr(i)); 172 173 return false; 174 } 175 176 static void release_pmc_hardware(void) 177 { 178 int i; 179 180 for (i = 0; i < x86_pmu.num_counters; i++) { 181 release_perfctr_nmi(x86_pmu_event_addr(i)); 182 release_evntsel_nmi(x86_pmu_config_addr(i)); 183 } 184 } 185 186 #else 187 188 static bool reserve_pmc_hardware(void) { return true; } 189 static void release_pmc_hardware(void) {} 190 191 #endif 192 193 static bool check_hw_exists(void) 194 { 195 u64 val, val_fail = -1, val_new= ~0; 196 int i, reg, reg_fail = -1, ret = 0; 197 int bios_fail = 0; 198 int reg_safe = -1; 199 200 /* 201 * Check to see if the BIOS enabled any of the counters, if so 202 * complain and bail. 203 */ 204 for (i = 0; i < x86_pmu.num_counters; i++) { 205 reg = x86_pmu_config_addr(i); 206 ret = rdmsrl_safe(reg, &val); 207 if (ret) 208 goto msr_fail; 209 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { 210 bios_fail = 1; 211 val_fail = val; 212 reg_fail = reg; 213 } else { 214 reg_safe = i; 215 } 216 } 217 218 if (x86_pmu.num_counters_fixed) { 219 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; 220 ret = rdmsrl_safe(reg, &val); 221 if (ret) 222 goto msr_fail; 223 for (i = 0; i < x86_pmu.num_counters_fixed; i++) { 224 if (val & (0x03 << i*4)) { 225 bios_fail = 1; 226 val_fail = val; 227 reg_fail = reg; 228 } 229 } 230 } 231 232 /* 233 * If all the counters are enabled, the below test will always 234 * fail. The tools will also become useless in this scenario. 235 * Just fail and disable the hardware counters. 236 */ 237 238 if (reg_safe == -1) { 239 reg = reg_safe; 240 goto msr_fail; 241 } 242 243 /* 244 * Read the current value, change it and read it back to see if it 245 * matches, this is needed to detect certain hardware emulators 246 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 247 */ 248 reg = x86_pmu_event_addr(reg_safe); 249 if (rdmsrl_safe(reg, &val)) 250 goto msr_fail; 251 val ^= 0xffffUL; 252 ret = wrmsrl_safe(reg, val); 253 ret |= rdmsrl_safe(reg, &val_new); 254 if (ret || val != val_new) 255 goto msr_fail; 256 257 /* 258 * We still allow the PMU driver to operate: 259 */ 260 if (bios_fail) { 261 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n"); 262 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", 263 reg_fail, val_fail); 264 } 265 266 return true; 267 268 msr_fail: 269 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 270 pr_cont("PMU not available due to virtualization, using software events only.\n"); 271 } else { 272 pr_cont("Broken PMU hardware detected, using software events only.\n"); 273 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n", 274 reg, val_new); 275 } 276 277 return false; 278 } 279 280 static void hw_perf_event_destroy(struct perf_event *event) 281 { 282 x86_release_hardware(); 283 atomic_dec(&active_events); 284 } 285 286 void hw_perf_lbr_event_destroy(struct perf_event *event) 287 { 288 hw_perf_event_destroy(event); 289 290 /* undo the lbr/bts event accounting */ 291 x86_del_exclusive(x86_lbr_exclusive_lbr); 292 } 293 294 static inline int x86_pmu_initialized(void) 295 { 296 return x86_pmu.handle_irq != NULL; 297 } 298 299 static inline int 300 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) 301 { 302 struct perf_event_attr *attr = &event->attr; 303 unsigned int cache_type, cache_op, cache_result; 304 u64 config, val; 305 306 config = attr->config; 307 308 cache_type = (config >> 0) & 0xff; 309 if (cache_type >= PERF_COUNT_HW_CACHE_MAX) 310 return -EINVAL; 311 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX); 312 313 cache_op = (config >> 8) & 0xff; 314 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) 315 return -EINVAL; 316 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX); 317 318 cache_result = (config >> 16) & 0xff; 319 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 320 return -EINVAL; 321 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX); 322 323 val = hw_cache_event_ids[cache_type][cache_op][cache_result]; 324 325 if (val == 0) 326 return -ENOENT; 327 328 if (val == -1) 329 return -EINVAL; 330 331 hwc->config |= val; 332 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; 333 return x86_pmu_extra_regs(val, event); 334 } 335 336 int x86_reserve_hardware(void) 337 { 338 int err = 0; 339 340 if (!atomic_inc_not_zero(&pmc_refcount)) { 341 mutex_lock(&pmc_reserve_mutex); 342 if (atomic_read(&pmc_refcount) == 0) { 343 if (!reserve_pmc_hardware()) 344 err = -EBUSY; 345 else 346 reserve_ds_buffers(); 347 } 348 if (!err) 349 atomic_inc(&pmc_refcount); 350 mutex_unlock(&pmc_reserve_mutex); 351 } 352 353 return err; 354 } 355 356 void x86_release_hardware(void) 357 { 358 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) { 359 release_pmc_hardware(); 360 release_ds_buffers(); 361 mutex_unlock(&pmc_reserve_mutex); 362 } 363 } 364 365 /* 366 * Check if we can create event of a certain type (that no conflicting events 367 * are present). 368 */ 369 int x86_add_exclusive(unsigned int what) 370 { 371 int i; 372 373 /* 374 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS. 375 * LBR and BTS are still mutually exclusive. 376 */ 377 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) 378 return 0; 379 380 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { 381 mutex_lock(&pmc_reserve_mutex); 382 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) { 383 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i])) 384 goto fail_unlock; 385 } 386 atomic_inc(&x86_pmu.lbr_exclusive[what]); 387 mutex_unlock(&pmc_reserve_mutex); 388 } 389 390 atomic_inc(&active_events); 391 return 0; 392 393 fail_unlock: 394 mutex_unlock(&pmc_reserve_mutex); 395 return -EBUSY; 396 } 397 398 void x86_del_exclusive(unsigned int what) 399 { 400 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) 401 return; 402 403 atomic_dec(&x86_pmu.lbr_exclusive[what]); 404 atomic_dec(&active_events); 405 } 406 407 int x86_setup_perfctr(struct perf_event *event) 408 { 409 struct perf_event_attr *attr = &event->attr; 410 struct hw_perf_event *hwc = &event->hw; 411 u64 config; 412 413 if (!is_sampling_event(event)) { 414 hwc->sample_period = x86_pmu.max_period; 415 hwc->last_period = hwc->sample_period; 416 local64_set(&hwc->period_left, hwc->sample_period); 417 } 418 419 if (attr->type == PERF_TYPE_RAW) 420 return x86_pmu_extra_regs(event->attr.config, event); 421 422 if (attr->type == PERF_TYPE_HW_CACHE) 423 return set_ext_hw_attr(hwc, event); 424 425 if (attr->config >= x86_pmu.max_events) 426 return -EINVAL; 427 428 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events); 429 430 /* 431 * The generic map: 432 */ 433 config = x86_pmu.event_map(attr->config); 434 435 if (config == 0) 436 return -ENOENT; 437 438 if (config == -1LL) 439 return -EINVAL; 440 441 hwc->config |= config; 442 443 return 0; 444 } 445 446 /* 447 * check that branch_sample_type is compatible with 448 * settings needed for precise_ip > 1 which implies 449 * using the LBR to capture ALL taken branches at the 450 * priv levels of the measurement 451 */ 452 static inline int precise_br_compat(struct perf_event *event) 453 { 454 u64 m = event->attr.branch_sample_type; 455 u64 b = 0; 456 457 /* must capture all branches */ 458 if (!(m & PERF_SAMPLE_BRANCH_ANY)) 459 return 0; 460 461 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; 462 463 if (!event->attr.exclude_user) 464 b |= PERF_SAMPLE_BRANCH_USER; 465 466 if (!event->attr.exclude_kernel) 467 b |= PERF_SAMPLE_BRANCH_KERNEL; 468 469 /* 470 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 471 */ 472 473 return m == b; 474 } 475 476 int x86_pmu_max_precise(void) 477 { 478 int precise = 0; 479 480 /* Support for constant skid */ 481 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { 482 precise++; 483 484 /* Support for IP fixup */ 485 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) 486 precise++; 487 488 if (x86_pmu.pebs_prec_dist) 489 precise++; 490 } 491 return precise; 492 } 493 494 int x86_pmu_hw_config(struct perf_event *event) 495 { 496 if (event->attr.precise_ip) { 497 int precise = x86_pmu_max_precise(); 498 499 if (event->attr.precise_ip > precise) 500 return -EOPNOTSUPP; 501 502 /* There's no sense in having PEBS for non sampling events: */ 503 if (!is_sampling_event(event)) 504 return -EINVAL; 505 } 506 /* 507 * check that PEBS LBR correction does not conflict with 508 * whatever the user is asking with attr->branch_sample_type 509 */ 510 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) { 511 u64 *br_type = &event->attr.branch_sample_type; 512 513 if (has_branch_stack(event)) { 514 if (!precise_br_compat(event)) 515 return -EOPNOTSUPP; 516 517 /* branch_sample_type is compatible */ 518 519 } else { 520 /* 521 * user did not specify branch_sample_type 522 * 523 * For PEBS fixups, we capture all 524 * the branches at the priv level of the 525 * event. 526 */ 527 *br_type = PERF_SAMPLE_BRANCH_ANY; 528 529 if (!event->attr.exclude_user) 530 *br_type |= PERF_SAMPLE_BRANCH_USER; 531 532 if (!event->attr.exclude_kernel) 533 *br_type |= PERF_SAMPLE_BRANCH_KERNEL; 534 } 535 } 536 537 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK) 538 event->attach_state |= PERF_ATTACH_TASK_DATA; 539 540 /* 541 * Generate PMC IRQs: 542 * (keep 'enabled' bit clear for now) 543 */ 544 event->hw.config = ARCH_PERFMON_EVENTSEL_INT; 545 546 /* 547 * Count user and OS events unless requested not to 548 */ 549 if (!event->attr.exclude_user) 550 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; 551 if (!event->attr.exclude_kernel) 552 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; 553 554 if (event->attr.type == PERF_TYPE_RAW) 555 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; 556 557 if (event->attr.sample_period && x86_pmu.limit_period) { 558 if (x86_pmu.limit_period(event, event->attr.sample_period) > 559 event->attr.sample_period) 560 return -EINVAL; 561 } 562 563 /* sample_regs_user never support XMM registers */ 564 if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK)) 565 return -EINVAL; 566 /* 567 * Besides the general purpose registers, XMM registers may 568 * be collected in PEBS on some platforms, e.g. Icelake 569 */ 570 if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) { 571 if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS)) 572 return -EINVAL; 573 574 if (!event->attr.precise_ip) 575 return -EINVAL; 576 } 577 578 return x86_setup_perfctr(event); 579 } 580 581 /* 582 * Setup the hardware configuration for a given attr_type 583 */ 584 static int __x86_pmu_event_init(struct perf_event *event) 585 { 586 int err; 587 588 if (!x86_pmu_initialized()) 589 return -ENODEV; 590 591 err = x86_reserve_hardware(); 592 if (err) 593 return err; 594 595 atomic_inc(&active_events); 596 event->destroy = hw_perf_event_destroy; 597 598 event->hw.idx = -1; 599 event->hw.last_cpu = -1; 600 event->hw.last_tag = ~0ULL; 601 602 /* mark unused */ 603 event->hw.extra_reg.idx = EXTRA_REG_NONE; 604 event->hw.branch_reg.idx = EXTRA_REG_NONE; 605 606 return x86_pmu.hw_config(event); 607 } 608 609 void x86_pmu_disable_all(void) 610 { 611 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 612 int idx; 613 614 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 615 u64 val; 616 617 if (!test_bit(idx, cpuc->active_mask)) 618 continue; 619 rdmsrl(x86_pmu_config_addr(idx), val); 620 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) 621 continue; 622 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 623 wrmsrl(x86_pmu_config_addr(idx), val); 624 } 625 } 626 627 /* 628 * There may be PMI landing after enabled=0. The PMI hitting could be before or 629 * after disable_all. 630 * 631 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler. 632 * It will not be re-enabled in the NMI handler again, because enabled=0. After 633 * handling the NMI, disable_all will be called, which will not change the 634 * state either. If PMI hits after disable_all, the PMU is already disabled 635 * before entering NMI handler. The NMI handler will not change the state 636 * either. 637 * 638 * So either situation is harmless. 639 */ 640 static void x86_pmu_disable(struct pmu *pmu) 641 { 642 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 643 644 if (!x86_pmu_initialized()) 645 return; 646 647 if (!cpuc->enabled) 648 return; 649 650 cpuc->n_added = 0; 651 cpuc->enabled = 0; 652 barrier(); 653 654 x86_pmu.disable_all(); 655 } 656 657 void x86_pmu_enable_all(int added) 658 { 659 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 660 int idx; 661 662 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 663 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 664 665 if (!test_bit(idx, cpuc->active_mask)) 666 continue; 667 668 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 669 } 670 } 671 672 static struct pmu pmu; 673 674 static inline int is_x86_event(struct perf_event *event) 675 { 676 return event->pmu == &pmu; 677 } 678 679 struct pmu *x86_get_pmu(void) 680 { 681 return &pmu; 682 } 683 /* 684 * Event scheduler state: 685 * 686 * Assign events iterating over all events and counters, beginning 687 * with events with least weights first. Keep the current iterator 688 * state in struct sched_state. 689 */ 690 struct sched_state { 691 int weight; 692 int event; /* event index */ 693 int counter; /* counter index */ 694 int unassigned; /* number of events to be assigned left */ 695 int nr_gp; /* number of GP counters used */ 696 unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 697 }; 698 699 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ 700 #define SCHED_STATES_MAX 2 701 702 struct perf_sched { 703 int max_weight; 704 int max_events; 705 int max_gp; 706 int saved_states; 707 struct event_constraint **constraints; 708 struct sched_state state; 709 struct sched_state saved[SCHED_STATES_MAX]; 710 }; 711 712 /* 713 * Initialize interator that runs through all events and counters. 714 */ 715 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints, 716 int num, int wmin, int wmax, int gpmax) 717 { 718 int idx; 719 720 memset(sched, 0, sizeof(*sched)); 721 sched->max_events = num; 722 sched->max_weight = wmax; 723 sched->max_gp = gpmax; 724 sched->constraints = constraints; 725 726 for (idx = 0; idx < num; idx++) { 727 if (constraints[idx]->weight == wmin) 728 break; 729 } 730 731 sched->state.event = idx; /* start with min weight */ 732 sched->state.weight = wmin; 733 sched->state.unassigned = num; 734 } 735 736 static void perf_sched_save_state(struct perf_sched *sched) 737 { 738 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) 739 return; 740 741 sched->saved[sched->saved_states] = sched->state; 742 sched->saved_states++; 743 } 744 745 static bool perf_sched_restore_state(struct perf_sched *sched) 746 { 747 if (!sched->saved_states) 748 return false; 749 750 sched->saved_states--; 751 sched->state = sched->saved[sched->saved_states]; 752 753 /* continue with next counter: */ 754 clear_bit(sched->state.counter++, sched->state.used); 755 756 return true; 757 } 758 759 /* 760 * Select a counter for the current event to schedule. Return true on 761 * success. 762 */ 763 static bool __perf_sched_find_counter(struct perf_sched *sched) 764 { 765 struct event_constraint *c; 766 int idx; 767 768 if (!sched->state.unassigned) 769 return false; 770 771 if (sched->state.event >= sched->max_events) 772 return false; 773 774 c = sched->constraints[sched->state.event]; 775 /* Prefer fixed purpose counters */ 776 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { 777 idx = INTEL_PMC_IDX_FIXED; 778 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { 779 if (!__test_and_set_bit(idx, sched->state.used)) 780 goto done; 781 } 782 } 783 784 /* Grab the first unused counter starting with idx */ 785 idx = sched->state.counter; 786 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { 787 if (!__test_and_set_bit(idx, sched->state.used)) { 788 if (sched->state.nr_gp++ >= sched->max_gp) 789 return false; 790 791 goto done; 792 } 793 } 794 795 return false; 796 797 done: 798 sched->state.counter = idx; 799 800 if (c->overlap) 801 perf_sched_save_state(sched); 802 803 return true; 804 } 805 806 static bool perf_sched_find_counter(struct perf_sched *sched) 807 { 808 while (!__perf_sched_find_counter(sched)) { 809 if (!perf_sched_restore_state(sched)) 810 return false; 811 } 812 813 return true; 814 } 815 816 /* 817 * Go through all unassigned events and find the next one to schedule. 818 * Take events with the least weight first. Return true on success. 819 */ 820 static bool perf_sched_next_event(struct perf_sched *sched) 821 { 822 struct event_constraint *c; 823 824 if (!sched->state.unassigned || !--sched->state.unassigned) 825 return false; 826 827 do { 828 /* next event */ 829 sched->state.event++; 830 if (sched->state.event >= sched->max_events) { 831 /* next weight */ 832 sched->state.event = 0; 833 sched->state.weight++; 834 if (sched->state.weight > sched->max_weight) 835 return false; 836 } 837 c = sched->constraints[sched->state.event]; 838 } while (c->weight != sched->state.weight); 839 840 sched->state.counter = 0; /* start with first counter */ 841 842 return true; 843 } 844 845 /* 846 * Assign a counter for each event. 847 */ 848 int perf_assign_events(struct event_constraint **constraints, int n, 849 int wmin, int wmax, int gpmax, int *assign) 850 { 851 struct perf_sched sched; 852 853 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax); 854 855 do { 856 if (!perf_sched_find_counter(&sched)) 857 break; /* failed */ 858 if (assign) 859 assign[sched.state.event] = sched.state.counter; 860 } while (perf_sched_next_event(&sched)); 861 862 return sched.state.unassigned; 863 } 864 EXPORT_SYMBOL_GPL(perf_assign_events); 865 866 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) 867 { 868 struct event_constraint *c; 869 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 870 struct perf_event *e; 871 int n0, i, wmin, wmax, unsched = 0; 872 struct hw_perf_event *hwc; 873 874 bitmap_zero(used_mask, X86_PMC_IDX_MAX); 875 876 /* 877 * Compute the number of events already present; see x86_pmu_add(), 878 * validate_group() and x86_pmu_commit_txn(). For the former two 879 * cpuc->n_events hasn't been updated yet, while for the latter 880 * cpuc->n_txn contains the number of events added in the current 881 * transaction. 882 */ 883 n0 = cpuc->n_events; 884 if (cpuc->txn_flags & PERF_PMU_TXN_ADD) 885 n0 -= cpuc->n_txn; 886 887 if (x86_pmu.start_scheduling) 888 x86_pmu.start_scheduling(cpuc); 889 890 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { 891 c = cpuc->event_constraint[i]; 892 893 /* 894 * Previously scheduled events should have a cached constraint, 895 * while new events should not have one. 896 */ 897 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0)); 898 899 /* 900 * Request constraints for new events; or for those events that 901 * have a dynamic constraint -- for those the constraint can 902 * change due to external factors (sibling state, allow_tfa). 903 */ 904 if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) { 905 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]); 906 cpuc->event_constraint[i] = c; 907 } 908 909 wmin = min(wmin, c->weight); 910 wmax = max(wmax, c->weight); 911 } 912 913 /* 914 * fastpath, try to reuse previous register 915 */ 916 for (i = 0; i < n; i++) { 917 hwc = &cpuc->event_list[i]->hw; 918 c = cpuc->event_constraint[i]; 919 920 /* never assigned */ 921 if (hwc->idx == -1) 922 break; 923 924 /* constraint still honored */ 925 if (!test_bit(hwc->idx, c->idxmsk)) 926 break; 927 928 /* not already used */ 929 if (test_bit(hwc->idx, used_mask)) 930 break; 931 932 __set_bit(hwc->idx, used_mask); 933 if (assign) 934 assign[i] = hwc->idx; 935 } 936 937 /* slow path */ 938 if (i != n) { 939 int gpmax = x86_pmu.num_counters; 940 941 /* 942 * Do not allow scheduling of more than half the available 943 * generic counters. 944 * 945 * This helps avoid counter starvation of sibling thread by 946 * ensuring at most half the counters cannot be in exclusive 947 * mode. There is no designated counters for the limits. Any 948 * N/2 counters can be used. This helps with events with 949 * specific counter constraints. 950 */ 951 if (is_ht_workaround_enabled() && !cpuc->is_fake && 952 READ_ONCE(cpuc->excl_cntrs->exclusive_present)) 953 gpmax /= 2; 954 955 unsched = perf_assign_events(cpuc->event_constraint, n, wmin, 956 wmax, gpmax, assign); 957 } 958 959 /* 960 * In case of success (unsched = 0), mark events as committed, 961 * so we do not put_constraint() in case new events are added 962 * and fail to be scheduled 963 * 964 * We invoke the lower level commit callback to lock the resource 965 * 966 * We do not need to do all of this in case we are called to 967 * validate an event group (assign == NULL) 968 */ 969 if (!unsched && assign) { 970 for (i = 0; i < n; i++) { 971 e = cpuc->event_list[i]; 972 if (x86_pmu.commit_scheduling) 973 x86_pmu.commit_scheduling(cpuc, i, assign[i]); 974 } 975 } else { 976 for (i = n0; i < n; i++) { 977 e = cpuc->event_list[i]; 978 979 /* 980 * release events that failed scheduling 981 */ 982 if (x86_pmu.put_event_constraints) 983 x86_pmu.put_event_constraints(cpuc, e); 984 985 cpuc->event_constraint[i] = NULL; 986 } 987 } 988 989 if (x86_pmu.stop_scheduling) 990 x86_pmu.stop_scheduling(cpuc); 991 992 return unsched ? -EINVAL : 0; 993 } 994 995 /* 996 * dogrp: true if must collect siblings events (group) 997 * returns total number of events and error code 998 */ 999 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) 1000 { 1001 struct perf_event *event; 1002 int n, max_count; 1003 1004 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; 1005 1006 /* current number of events already accepted */ 1007 n = cpuc->n_events; 1008 if (!cpuc->n_events) 1009 cpuc->pebs_output = 0; 1010 1011 if (!cpuc->is_fake && leader->attr.precise_ip) { 1012 /* 1013 * For PEBS->PT, if !aux_event, the group leader (PT) went 1014 * away, the group was broken down and this singleton event 1015 * can't schedule any more. 1016 */ 1017 if (is_pebs_pt(leader) && !leader->aux_event) 1018 return -EINVAL; 1019 1020 /* 1021 * pebs_output: 0: no PEBS so far, 1: PT, 2: DS 1022 */ 1023 if (cpuc->pebs_output && 1024 cpuc->pebs_output != is_pebs_pt(leader) + 1) 1025 return -EINVAL; 1026 1027 cpuc->pebs_output = is_pebs_pt(leader) + 1; 1028 } 1029 1030 if (is_x86_event(leader)) { 1031 if (n >= max_count) 1032 return -EINVAL; 1033 cpuc->event_list[n] = leader; 1034 n++; 1035 } 1036 if (!dogrp) 1037 return n; 1038 1039 for_each_sibling_event(event, leader) { 1040 if (!is_x86_event(event) || 1041 event->state <= PERF_EVENT_STATE_OFF) 1042 continue; 1043 1044 if (n >= max_count) 1045 return -EINVAL; 1046 1047 cpuc->event_list[n] = event; 1048 n++; 1049 } 1050 return n; 1051 } 1052 1053 static inline void x86_assign_hw_event(struct perf_event *event, 1054 struct cpu_hw_events *cpuc, int i) 1055 { 1056 struct hw_perf_event *hwc = &event->hw; 1057 1058 hwc->idx = cpuc->assign[i]; 1059 hwc->last_cpu = smp_processor_id(); 1060 hwc->last_tag = ++cpuc->tags[i]; 1061 1062 if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { 1063 hwc->config_base = 0; 1064 hwc->event_base = 0; 1065 } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { 1066 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; 1067 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); 1068 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; 1069 } else { 1070 hwc->config_base = x86_pmu_config_addr(hwc->idx); 1071 hwc->event_base = x86_pmu_event_addr(hwc->idx); 1072 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); 1073 } 1074 } 1075 1076 /** 1077 * x86_perf_rdpmc_index - Return PMC counter used for event 1078 * @event: the perf_event to which the PMC counter was assigned 1079 * 1080 * The counter assigned to this performance event may change if interrupts 1081 * are enabled. This counter should thus never be used while interrupts are 1082 * enabled. Before this function is used to obtain the assigned counter the 1083 * event should be checked for validity using, for example, 1084 * perf_event_read_local(), within the same interrupt disabled section in 1085 * which this counter is planned to be used. 1086 * 1087 * Return: The index of the performance monitoring counter assigned to 1088 * @perf_event. 1089 */ 1090 int x86_perf_rdpmc_index(struct perf_event *event) 1091 { 1092 lockdep_assert_irqs_disabled(); 1093 1094 return event->hw.event_base_rdpmc; 1095 } 1096 1097 static inline int match_prev_assignment(struct hw_perf_event *hwc, 1098 struct cpu_hw_events *cpuc, 1099 int i) 1100 { 1101 return hwc->idx == cpuc->assign[i] && 1102 hwc->last_cpu == smp_processor_id() && 1103 hwc->last_tag == cpuc->tags[i]; 1104 } 1105 1106 static void x86_pmu_start(struct perf_event *event, int flags); 1107 1108 static void x86_pmu_enable(struct pmu *pmu) 1109 { 1110 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1111 struct perf_event *event; 1112 struct hw_perf_event *hwc; 1113 int i, added = cpuc->n_added; 1114 1115 if (!x86_pmu_initialized()) 1116 return; 1117 1118 if (cpuc->enabled) 1119 return; 1120 1121 if (cpuc->n_added) { 1122 int n_running = cpuc->n_events - cpuc->n_added; 1123 /* 1124 * apply assignment obtained either from 1125 * hw_perf_group_sched_in() or x86_pmu_enable() 1126 * 1127 * step1: save events moving to new counters 1128 */ 1129 for (i = 0; i < n_running; i++) { 1130 event = cpuc->event_list[i]; 1131 hwc = &event->hw; 1132 1133 /* 1134 * we can avoid reprogramming counter if: 1135 * - assigned same counter as last time 1136 * - running on same CPU as last time 1137 * - no other event has used the counter since 1138 */ 1139 if (hwc->idx == -1 || 1140 match_prev_assignment(hwc, cpuc, i)) 1141 continue; 1142 1143 /* 1144 * Ensure we don't accidentally enable a stopped 1145 * counter simply because we rescheduled. 1146 */ 1147 if (hwc->state & PERF_HES_STOPPED) 1148 hwc->state |= PERF_HES_ARCH; 1149 1150 x86_pmu_stop(event, PERF_EF_UPDATE); 1151 } 1152 1153 /* 1154 * step2: reprogram moved events into new counters 1155 */ 1156 for (i = 0; i < cpuc->n_events; i++) { 1157 event = cpuc->event_list[i]; 1158 hwc = &event->hw; 1159 1160 if (!match_prev_assignment(hwc, cpuc, i)) 1161 x86_assign_hw_event(event, cpuc, i); 1162 else if (i < n_running) 1163 continue; 1164 1165 if (hwc->state & PERF_HES_ARCH) 1166 continue; 1167 1168 x86_pmu_start(event, PERF_EF_RELOAD); 1169 } 1170 cpuc->n_added = 0; 1171 perf_events_lapic_init(); 1172 } 1173 1174 cpuc->enabled = 1; 1175 barrier(); 1176 1177 x86_pmu.enable_all(added); 1178 } 1179 1180 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); 1181 1182 /* 1183 * Set the next IRQ period, based on the hwc->period_left value. 1184 * To be called with the event disabled in hw: 1185 */ 1186 int x86_perf_event_set_period(struct perf_event *event) 1187 { 1188 struct hw_perf_event *hwc = &event->hw; 1189 s64 left = local64_read(&hwc->period_left); 1190 s64 period = hwc->sample_period; 1191 int ret = 0, idx = hwc->idx; 1192 1193 if (idx == INTEL_PMC_IDX_FIXED_BTS) 1194 return 0; 1195 1196 /* 1197 * If we are way outside a reasonable range then just skip forward: 1198 */ 1199 if (unlikely(left <= -period)) { 1200 left = period; 1201 local64_set(&hwc->period_left, left); 1202 hwc->last_period = period; 1203 ret = 1; 1204 } 1205 1206 if (unlikely(left <= 0)) { 1207 left += period; 1208 local64_set(&hwc->period_left, left); 1209 hwc->last_period = period; 1210 ret = 1; 1211 } 1212 /* 1213 * Quirk: certain CPUs dont like it if just 1 hw_event is left: 1214 */ 1215 if (unlikely(left < 2)) 1216 left = 2; 1217 1218 if (left > x86_pmu.max_period) 1219 left = x86_pmu.max_period; 1220 1221 if (x86_pmu.limit_period) 1222 left = x86_pmu.limit_period(event, left); 1223 1224 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; 1225 1226 /* 1227 * The hw event starts counting from this event offset, 1228 * mark it to be able to extra future deltas: 1229 */ 1230 local64_set(&hwc->prev_count, (u64)-left); 1231 1232 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); 1233 1234 /* 1235 * Due to erratum on certan cpu we need 1236 * a second write to be sure the register 1237 * is updated properly 1238 */ 1239 if (x86_pmu.perfctr_second_write) { 1240 wrmsrl(hwc->event_base, 1241 (u64)(-left) & x86_pmu.cntval_mask); 1242 } 1243 1244 perf_event_update_userpage(event); 1245 1246 return ret; 1247 } 1248 1249 void x86_pmu_enable_event(struct perf_event *event) 1250 { 1251 if (__this_cpu_read(cpu_hw_events.enabled)) 1252 __x86_pmu_enable_event(&event->hw, 1253 ARCH_PERFMON_EVENTSEL_ENABLE); 1254 } 1255 1256 /* 1257 * Add a single event to the PMU. 1258 * 1259 * The event is added to the group of enabled events 1260 * but only if it can be scheduled with existing events. 1261 */ 1262 static int x86_pmu_add(struct perf_event *event, int flags) 1263 { 1264 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1265 struct hw_perf_event *hwc; 1266 int assign[X86_PMC_IDX_MAX]; 1267 int n, n0, ret; 1268 1269 hwc = &event->hw; 1270 1271 n0 = cpuc->n_events; 1272 ret = n = collect_events(cpuc, event, false); 1273 if (ret < 0) 1274 goto out; 1275 1276 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; 1277 if (!(flags & PERF_EF_START)) 1278 hwc->state |= PERF_HES_ARCH; 1279 1280 /* 1281 * If group events scheduling transaction was started, 1282 * skip the schedulability test here, it will be performed 1283 * at commit time (->commit_txn) as a whole. 1284 * 1285 * If commit fails, we'll call ->del() on all events 1286 * for which ->add() was called. 1287 */ 1288 if (cpuc->txn_flags & PERF_PMU_TXN_ADD) 1289 goto done_collect; 1290 1291 ret = x86_pmu.schedule_events(cpuc, n, assign); 1292 if (ret) 1293 goto out; 1294 /* 1295 * copy new assignment, now we know it is possible 1296 * will be used by hw_perf_enable() 1297 */ 1298 memcpy(cpuc->assign, assign, n*sizeof(int)); 1299 1300 done_collect: 1301 /* 1302 * Commit the collect_events() state. See x86_pmu_del() and 1303 * x86_pmu_*_txn(). 1304 */ 1305 cpuc->n_events = n; 1306 cpuc->n_added += n - n0; 1307 cpuc->n_txn += n - n0; 1308 1309 if (x86_pmu.add) { 1310 /* 1311 * This is before x86_pmu_enable() will call x86_pmu_start(), 1312 * so we enable LBRs before an event needs them etc.. 1313 */ 1314 x86_pmu.add(event); 1315 } 1316 1317 ret = 0; 1318 out: 1319 return ret; 1320 } 1321 1322 static void x86_pmu_start(struct perf_event *event, int flags) 1323 { 1324 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1325 int idx = event->hw.idx; 1326 1327 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) 1328 return; 1329 1330 if (WARN_ON_ONCE(idx == -1)) 1331 return; 1332 1333 if (flags & PERF_EF_RELOAD) { 1334 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1335 x86_perf_event_set_period(event); 1336 } 1337 1338 event->hw.state = 0; 1339 1340 cpuc->events[idx] = event; 1341 __set_bit(idx, cpuc->active_mask); 1342 __set_bit(idx, cpuc->running); 1343 x86_pmu.enable(event); 1344 perf_event_update_userpage(event); 1345 } 1346 1347 void perf_event_print_debug(void) 1348 { 1349 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; 1350 u64 pebs, debugctl; 1351 struct cpu_hw_events *cpuc; 1352 unsigned long flags; 1353 int cpu, idx; 1354 1355 if (!x86_pmu.num_counters) 1356 return; 1357 1358 local_irq_save(flags); 1359 1360 cpu = smp_processor_id(); 1361 cpuc = &per_cpu(cpu_hw_events, cpu); 1362 1363 if (x86_pmu.version >= 2) { 1364 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); 1365 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 1366 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); 1367 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); 1368 1369 pr_info("\n"); 1370 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); 1371 pr_info("CPU#%d: status: %016llx\n", cpu, status); 1372 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); 1373 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); 1374 if (x86_pmu.pebs_constraints) { 1375 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); 1376 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); 1377 } 1378 if (x86_pmu.lbr_nr) { 1379 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1380 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); 1381 } 1382 } 1383 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); 1384 1385 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 1386 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); 1387 rdmsrl(x86_pmu_event_addr(idx), pmc_count); 1388 1389 prev_left = per_cpu(pmc_prev_left[idx], cpu); 1390 1391 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", 1392 cpu, idx, pmc_ctrl); 1393 pr_info("CPU#%d: gen-PMC%d count: %016llx\n", 1394 cpu, idx, pmc_count); 1395 pr_info("CPU#%d: gen-PMC%d left: %016llx\n", 1396 cpu, idx, prev_left); 1397 } 1398 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { 1399 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); 1400 1401 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", 1402 cpu, idx, pmc_count); 1403 } 1404 local_irq_restore(flags); 1405 } 1406 1407 void x86_pmu_stop(struct perf_event *event, int flags) 1408 { 1409 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1410 struct hw_perf_event *hwc = &event->hw; 1411 1412 if (test_bit(hwc->idx, cpuc->active_mask)) { 1413 x86_pmu.disable(event); 1414 __clear_bit(hwc->idx, cpuc->active_mask); 1415 cpuc->events[hwc->idx] = NULL; 1416 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); 1417 hwc->state |= PERF_HES_STOPPED; 1418 } 1419 1420 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { 1421 /* 1422 * Drain the remaining delta count out of a event 1423 * that we are disabling: 1424 */ 1425 x86_perf_event_update(event); 1426 hwc->state |= PERF_HES_UPTODATE; 1427 } 1428 } 1429 1430 static void x86_pmu_del(struct perf_event *event, int flags) 1431 { 1432 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1433 int i; 1434 1435 /* 1436 * If we're called during a txn, we only need to undo x86_pmu.add. 1437 * The events never got scheduled and ->cancel_txn will truncate 1438 * the event_list. 1439 * 1440 * XXX assumes any ->del() called during a TXN will only be on 1441 * an event added during that same TXN. 1442 */ 1443 if (cpuc->txn_flags & PERF_PMU_TXN_ADD) 1444 goto do_del; 1445 1446 /* 1447 * Not a TXN, therefore cleanup properly. 1448 */ 1449 x86_pmu_stop(event, PERF_EF_UPDATE); 1450 1451 for (i = 0; i < cpuc->n_events; i++) { 1452 if (event == cpuc->event_list[i]) 1453 break; 1454 } 1455 1456 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */ 1457 return; 1458 1459 /* If we have a newly added event; make sure to decrease n_added. */ 1460 if (i >= cpuc->n_events - cpuc->n_added) 1461 --cpuc->n_added; 1462 1463 if (x86_pmu.put_event_constraints) 1464 x86_pmu.put_event_constraints(cpuc, event); 1465 1466 /* Delete the array entry. */ 1467 while (++i < cpuc->n_events) { 1468 cpuc->event_list[i-1] = cpuc->event_list[i]; 1469 cpuc->event_constraint[i-1] = cpuc->event_constraint[i]; 1470 } 1471 cpuc->event_constraint[i-1] = NULL; 1472 --cpuc->n_events; 1473 1474 perf_event_update_userpage(event); 1475 1476 do_del: 1477 if (x86_pmu.del) { 1478 /* 1479 * This is after x86_pmu_stop(); so we disable LBRs after any 1480 * event can need them etc.. 1481 */ 1482 x86_pmu.del(event); 1483 } 1484 } 1485 1486 int x86_pmu_handle_irq(struct pt_regs *regs) 1487 { 1488 struct perf_sample_data data; 1489 struct cpu_hw_events *cpuc; 1490 struct perf_event *event; 1491 int idx, handled = 0; 1492 u64 val; 1493 1494 cpuc = this_cpu_ptr(&cpu_hw_events); 1495 1496 /* 1497 * Some chipsets need to unmask the LVTPC in a particular spot 1498 * inside the nmi handler. As a result, the unmasking was pushed 1499 * into all the nmi handlers. 1500 * 1501 * This generic handler doesn't seem to have any issues where the 1502 * unmasking occurs so it was left at the top. 1503 */ 1504 apic_write(APIC_LVTPC, APIC_DM_NMI); 1505 1506 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 1507 if (!test_bit(idx, cpuc->active_mask)) 1508 continue; 1509 1510 event = cpuc->events[idx]; 1511 1512 val = x86_perf_event_update(event); 1513 if (val & (1ULL << (x86_pmu.cntval_bits - 1))) 1514 continue; 1515 1516 /* 1517 * event overflow 1518 */ 1519 handled++; 1520 perf_sample_data_init(&data, 0, event->hw.last_period); 1521 1522 if (!x86_perf_event_set_period(event)) 1523 continue; 1524 1525 if (perf_event_overflow(event, &data, regs)) 1526 x86_pmu_stop(event, 0); 1527 } 1528 1529 if (handled) 1530 inc_irq_stat(apic_perf_irqs); 1531 1532 return handled; 1533 } 1534 1535 void perf_events_lapic_init(void) 1536 { 1537 if (!x86_pmu.apic || !x86_pmu_initialized()) 1538 return; 1539 1540 /* 1541 * Always use NMI for PMU 1542 */ 1543 apic_write(APIC_LVTPC, APIC_DM_NMI); 1544 } 1545 1546 static int 1547 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) 1548 { 1549 u64 start_clock; 1550 u64 finish_clock; 1551 int ret; 1552 1553 /* 1554 * All PMUs/events that share this PMI handler should make sure to 1555 * increment active_events for their events. 1556 */ 1557 if (!atomic_read(&active_events)) 1558 return NMI_DONE; 1559 1560 start_clock = sched_clock(); 1561 ret = x86_pmu.handle_irq(regs); 1562 finish_clock = sched_clock(); 1563 1564 perf_sample_event_took(finish_clock - start_clock); 1565 1566 return ret; 1567 } 1568 NOKPROBE_SYMBOL(perf_event_nmi_handler); 1569 1570 struct event_constraint emptyconstraint; 1571 struct event_constraint unconstrained; 1572 1573 static int x86_pmu_prepare_cpu(unsigned int cpu) 1574 { 1575 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 1576 int i; 1577 1578 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) 1579 cpuc->kfree_on_online[i] = NULL; 1580 if (x86_pmu.cpu_prepare) 1581 return x86_pmu.cpu_prepare(cpu); 1582 return 0; 1583 } 1584 1585 static int x86_pmu_dead_cpu(unsigned int cpu) 1586 { 1587 if (x86_pmu.cpu_dead) 1588 x86_pmu.cpu_dead(cpu); 1589 return 0; 1590 } 1591 1592 static int x86_pmu_online_cpu(unsigned int cpu) 1593 { 1594 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 1595 int i; 1596 1597 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) { 1598 kfree(cpuc->kfree_on_online[i]); 1599 cpuc->kfree_on_online[i] = NULL; 1600 } 1601 return 0; 1602 } 1603 1604 static int x86_pmu_starting_cpu(unsigned int cpu) 1605 { 1606 if (x86_pmu.cpu_starting) 1607 x86_pmu.cpu_starting(cpu); 1608 return 0; 1609 } 1610 1611 static int x86_pmu_dying_cpu(unsigned int cpu) 1612 { 1613 if (x86_pmu.cpu_dying) 1614 x86_pmu.cpu_dying(cpu); 1615 return 0; 1616 } 1617 1618 static void __init pmu_check_apic(void) 1619 { 1620 if (boot_cpu_has(X86_FEATURE_APIC)) 1621 return; 1622 1623 x86_pmu.apic = 0; 1624 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); 1625 pr_info("no hardware sampling interrupt available.\n"); 1626 1627 /* 1628 * If we have a PMU initialized but no APIC 1629 * interrupts, we cannot sample hardware 1630 * events (user-space has to fall back and 1631 * sample via a hrtimer based software event): 1632 */ 1633 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; 1634 1635 } 1636 1637 static struct attribute_group x86_pmu_format_group __ro_after_init = { 1638 .name = "format", 1639 .attrs = NULL, 1640 }; 1641 1642 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page) 1643 { 1644 struct perf_pmu_events_attr *pmu_attr = \ 1645 container_of(attr, struct perf_pmu_events_attr, attr); 1646 u64 config = x86_pmu.event_map(pmu_attr->id); 1647 1648 /* string trumps id */ 1649 if (pmu_attr->event_str) 1650 return sprintf(page, "%s", pmu_attr->event_str); 1651 1652 return x86_pmu.events_sysfs_show(page, config); 1653 } 1654 EXPORT_SYMBOL_GPL(events_sysfs_show); 1655 1656 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 1657 char *page) 1658 { 1659 struct perf_pmu_events_ht_attr *pmu_attr = 1660 container_of(attr, struct perf_pmu_events_ht_attr, attr); 1661 1662 /* 1663 * Report conditional events depending on Hyper-Threading. 1664 * 1665 * This is overly conservative as usually the HT special 1666 * handling is not needed if the other CPU thread is idle. 1667 * 1668 * Note this does not (and cannot) handle the case when thread 1669 * siblings are invisible, for example with virtualization 1670 * if they are owned by some other guest. The user tool 1671 * has to re-read when a thread sibling gets onlined later. 1672 */ 1673 return sprintf(page, "%s", 1674 topology_max_smt_threads() > 1 ? 1675 pmu_attr->event_str_ht : 1676 pmu_attr->event_str_noht); 1677 } 1678 1679 EVENT_ATTR(cpu-cycles, CPU_CYCLES ); 1680 EVENT_ATTR(instructions, INSTRUCTIONS ); 1681 EVENT_ATTR(cache-references, CACHE_REFERENCES ); 1682 EVENT_ATTR(cache-misses, CACHE_MISSES ); 1683 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); 1684 EVENT_ATTR(branch-misses, BRANCH_MISSES ); 1685 EVENT_ATTR(bus-cycles, BUS_CYCLES ); 1686 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); 1687 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); 1688 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); 1689 1690 static struct attribute *empty_attrs; 1691 1692 static struct attribute *events_attr[] = { 1693 EVENT_PTR(CPU_CYCLES), 1694 EVENT_PTR(INSTRUCTIONS), 1695 EVENT_PTR(CACHE_REFERENCES), 1696 EVENT_PTR(CACHE_MISSES), 1697 EVENT_PTR(BRANCH_INSTRUCTIONS), 1698 EVENT_PTR(BRANCH_MISSES), 1699 EVENT_PTR(BUS_CYCLES), 1700 EVENT_PTR(STALLED_CYCLES_FRONTEND), 1701 EVENT_PTR(STALLED_CYCLES_BACKEND), 1702 EVENT_PTR(REF_CPU_CYCLES), 1703 NULL, 1704 }; 1705 1706 /* 1707 * Remove all undefined events (x86_pmu.event_map(id) == 0) 1708 * out of events_attr attributes. 1709 */ 1710 static umode_t 1711 is_visible(struct kobject *kobj, struct attribute *attr, int idx) 1712 { 1713 struct perf_pmu_events_attr *pmu_attr; 1714 1715 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr); 1716 /* str trumps id */ 1717 return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0; 1718 } 1719 1720 static struct attribute_group x86_pmu_events_group __ro_after_init = { 1721 .name = "events", 1722 .attrs = events_attr, 1723 .is_visible = is_visible, 1724 }; 1725 1726 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) 1727 { 1728 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; 1729 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; 1730 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); 1731 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); 1732 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); 1733 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); 1734 ssize_t ret; 1735 1736 /* 1737 * We have whole page size to spend and just little data 1738 * to write, so we can safely use sprintf. 1739 */ 1740 ret = sprintf(page, "event=0x%02llx", event); 1741 1742 if (umask) 1743 ret += sprintf(page + ret, ",umask=0x%02llx", umask); 1744 1745 if (edge) 1746 ret += sprintf(page + ret, ",edge"); 1747 1748 if (pc) 1749 ret += sprintf(page + ret, ",pc"); 1750 1751 if (any) 1752 ret += sprintf(page + ret, ",any"); 1753 1754 if (inv) 1755 ret += sprintf(page + ret, ",inv"); 1756 1757 if (cmask) 1758 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); 1759 1760 ret += sprintf(page + ret, "\n"); 1761 1762 return ret; 1763 } 1764 1765 static struct attribute_group x86_pmu_attr_group; 1766 static struct attribute_group x86_pmu_caps_group; 1767 1768 static int __init init_hw_perf_events(void) 1769 { 1770 struct x86_pmu_quirk *quirk; 1771 int err; 1772 1773 pr_info("Performance Events: "); 1774 1775 switch (boot_cpu_data.x86_vendor) { 1776 case X86_VENDOR_INTEL: 1777 err = intel_pmu_init(); 1778 break; 1779 case X86_VENDOR_AMD: 1780 err = amd_pmu_init(); 1781 break; 1782 case X86_VENDOR_HYGON: 1783 err = amd_pmu_init(); 1784 x86_pmu.name = "HYGON"; 1785 break; 1786 default: 1787 err = -ENOTSUPP; 1788 } 1789 if (err != 0) { 1790 pr_cont("no PMU driver, software events only.\n"); 1791 return 0; 1792 } 1793 1794 pmu_check_apic(); 1795 1796 /* sanity check that the hardware exists or is emulated */ 1797 if (!check_hw_exists()) 1798 return 0; 1799 1800 pr_cont("%s PMU driver.\n", x86_pmu.name); 1801 1802 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ 1803 1804 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) 1805 quirk->func(); 1806 1807 if (!x86_pmu.intel_ctrl) 1808 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; 1809 1810 perf_events_lapic_init(); 1811 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); 1812 1813 unconstrained = (struct event_constraint) 1814 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, 1815 0, x86_pmu.num_counters, 0, 0); 1816 1817 x86_pmu_format_group.attrs = x86_pmu.format_attrs; 1818 1819 if (!x86_pmu.events_sysfs_show) 1820 x86_pmu_events_group.attrs = &empty_attrs; 1821 1822 pmu.attr_update = x86_pmu.attr_update; 1823 1824 pr_info("... version: %d\n", x86_pmu.version); 1825 pr_info("... bit width: %d\n", x86_pmu.cntval_bits); 1826 pr_info("... generic registers: %d\n", x86_pmu.num_counters); 1827 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); 1828 pr_info("... max period: %016Lx\n", x86_pmu.max_period); 1829 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); 1830 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); 1831 1832 /* 1833 * Install callbacks. Core will call them for each online 1834 * cpu. 1835 */ 1836 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare", 1837 x86_pmu_prepare_cpu, x86_pmu_dead_cpu); 1838 if (err) 1839 return err; 1840 1841 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING, 1842 "perf/x86:starting", x86_pmu_starting_cpu, 1843 x86_pmu_dying_cpu); 1844 if (err) 1845 goto out; 1846 1847 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online", 1848 x86_pmu_online_cpu, NULL); 1849 if (err) 1850 goto out1; 1851 1852 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); 1853 if (err) 1854 goto out2; 1855 1856 return 0; 1857 1858 out2: 1859 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE); 1860 out1: 1861 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING); 1862 out: 1863 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE); 1864 return err; 1865 } 1866 early_initcall(init_hw_perf_events); 1867 1868 static inline void x86_pmu_read(struct perf_event *event) 1869 { 1870 if (x86_pmu.read) 1871 return x86_pmu.read(event); 1872 x86_perf_event_update(event); 1873 } 1874 1875 /* 1876 * Start group events scheduling transaction 1877 * Set the flag to make pmu::enable() not perform the 1878 * schedulability test, it will be performed at commit time 1879 * 1880 * We only support PERF_PMU_TXN_ADD transactions. Save the 1881 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD 1882 * transactions. 1883 */ 1884 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) 1885 { 1886 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1887 1888 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */ 1889 1890 cpuc->txn_flags = txn_flags; 1891 if (txn_flags & ~PERF_PMU_TXN_ADD) 1892 return; 1893 1894 perf_pmu_disable(pmu); 1895 __this_cpu_write(cpu_hw_events.n_txn, 0); 1896 } 1897 1898 /* 1899 * Stop group events scheduling transaction 1900 * Clear the flag and pmu::enable() will perform the 1901 * schedulability test. 1902 */ 1903 static void x86_pmu_cancel_txn(struct pmu *pmu) 1904 { 1905 unsigned int txn_flags; 1906 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1907 1908 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ 1909 1910 txn_flags = cpuc->txn_flags; 1911 cpuc->txn_flags = 0; 1912 if (txn_flags & ~PERF_PMU_TXN_ADD) 1913 return; 1914 1915 /* 1916 * Truncate collected array by the number of events added in this 1917 * transaction. See x86_pmu_add() and x86_pmu_*_txn(). 1918 */ 1919 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); 1920 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); 1921 perf_pmu_enable(pmu); 1922 } 1923 1924 /* 1925 * Commit group events scheduling transaction 1926 * Perform the group schedulability test as a whole 1927 * Return 0 if success 1928 * 1929 * Does not cancel the transaction on failure; expects the caller to do this. 1930 */ 1931 static int x86_pmu_commit_txn(struct pmu *pmu) 1932 { 1933 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1934 int assign[X86_PMC_IDX_MAX]; 1935 int n, ret; 1936 1937 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ 1938 1939 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) { 1940 cpuc->txn_flags = 0; 1941 return 0; 1942 } 1943 1944 n = cpuc->n_events; 1945 1946 if (!x86_pmu_initialized()) 1947 return -EAGAIN; 1948 1949 ret = x86_pmu.schedule_events(cpuc, n, assign); 1950 if (ret) 1951 return ret; 1952 1953 /* 1954 * copy new assignment, now we know it is possible 1955 * will be used by hw_perf_enable() 1956 */ 1957 memcpy(cpuc->assign, assign, n*sizeof(int)); 1958 1959 cpuc->txn_flags = 0; 1960 perf_pmu_enable(pmu); 1961 return 0; 1962 } 1963 /* 1964 * a fake_cpuc is used to validate event groups. Due to 1965 * the extra reg logic, we need to also allocate a fake 1966 * per_core and per_cpu structure. Otherwise, group events 1967 * using extra reg may conflict without the kernel being 1968 * able to catch this when the last event gets added to 1969 * the group. 1970 */ 1971 static void free_fake_cpuc(struct cpu_hw_events *cpuc) 1972 { 1973 intel_cpuc_finish(cpuc); 1974 kfree(cpuc); 1975 } 1976 1977 static struct cpu_hw_events *allocate_fake_cpuc(void) 1978 { 1979 struct cpu_hw_events *cpuc; 1980 int cpu = raw_smp_processor_id(); 1981 1982 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); 1983 if (!cpuc) 1984 return ERR_PTR(-ENOMEM); 1985 cpuc->is_fake = 1; 1986 1987 if (intel_cpuc_prepare(cpuc, cpu)) 1988 goto error; 1989 1990 return cpuc; 1991 error: 1992 free_fake_cpuc(cpuc); 1993 return ERR_PTR(-ENOMEM); 1994 } 1995 1996 /* 1997 * validate that we can schedule this event 1998 */ 1999 static int validate_event(struct perf_event *event) 2000 { 2001 struct cpu_hw_events *fake_cpuc; 2002 struct event_constraint *c; 2003 int ret = 0; 2004 2005 fake_cpuc = allocate_fake_cpuc(); 2006 if (IS_ERR(fake_cpuc)) 2007 return PTR_ERR(fake_cpuc); 2008 2009 c = x86_pmu.get_event_constraints(fake_cpuc, 0, event); 2010 2011 if (!c || !c->weight) 2012 ret = -EINVAL; 2013 2014 if (x86_pmu.put_event_constraints) 2015 x86_pmu.put_event_constraints(fake_cpuc, event); 2016 2017 free_fake_cpuc(fake_cpuc); 2018 2019 return ret; 2020 } 2021 2022 /* 2023 * validate a single event group 2024 * 2025 * validation include: 2026 * - check events are compatible which each other 2027 * - events do not compete for the same counter 2028 * - number of events <= number of counters 2029 * 2030 * validation ensures the group can be loaded onto the 2031 * PMU if it was the only group available. 2032 */ 2033 static int validate_group(struct perf_event *event) 2034 { 2035 struct perf_event *leader = event->group_leader; 2036 struct cpu_hw_events *fake_cpuc; 2037 int ret = -EINVAL, n; 2038 2039 fake_cpuc = allocate_fake_cpuc(); 2040 if (IS_ERR(fake_cpuc)) 2041 return PTR_ERR(fake_cpuc); 2042 /* 2043 * the event is not yet connected with its 2044 * siblings therefore we must first collect 2045 * existing siblings, then add the new event 2046 * before we can simulate the scheduling 2047 */ 2048 n = collect_events(fake_cpuc, leader, true); 2049 if (n < 0) 2050 goto out; 2051 2052 fake_cpuc->n_events = n; 2053 n = collect_events(fake_cpuc, event, false); 2054 if (n < 0) 2055 goto out; 2056 2057 fake_cpuc->n_events = 0; 2058 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); 2059 2060 out: 2061 free_fake_cpuc(fake_cpuc); 2062 return ret; 2063 } 2064 2065 static int x86_pmu_event_init(struct perf_event *event) 2066 { 2067 struct pmu *tmp; 2068 int err; 2069 2070 switch (event->attr.type) { 2071 case PERF_TYPE_RAW: 2072 case PERF_TYPE_HARDWARE: 2073 case PERF_TYPE_HW_CACHE: 2074 break; 2075 2076 default: 2077 return -ENOENT; 2078 } 2079 2080 err = __x86_pmu_event_init(event); 2081 if (!err) { 2082 /* 2083 * we temporarily connect event to its pmu 2084 * such that validate_group() can classify 2085 * it as an x86 event using is_x86_event() 2086 */ 2087 tmp = event->pmu; 2088 event->pmu = &pmu; 2089 2090 if (event->group_leader != event) 2091 err = validate_group(event); 2092 else 2093 err = validate_event(event); 2094 2095 event->pmu = tmp; 2096 } 2097 if (err) { 2098 if (event->destroy) 2099 event->destroy(event); 2100 } 2101 2102 if (READ_ONCE(x86_pmu.attr_rdpmc) && 2103 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS)) 2104 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED; 2105 2106 return err; 2107 } 2108 2109 static void refresh_pce(void *ignored) 2110 { 2111 load_mm_cr4_irqsoff(this_cpu_read(cpu_tlbstate.loaded_mm)); 2112 } 2113 2114 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm) 2115 { 2116 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) 2117 return; 2118 2119 /* 2120 * This function relies on not being called concurrently in two 2121 * tasks in the same mm. Otherwise one task could observe 2122 * perf_rdpmc_allowed > 1 and return all the way back to 2123 * userspace with CR4.PCE clear while another task is still 2124 * doing on_each_cpu_mask() to propagate CR4.PCE. 2125 * 2126 * For now, this can't happen because all callers hold mmap_sem 2127 * for write. If this changes, we'll need a different solution. 2128 */ 2129 lockdep_assert_held_write(&mm->mmap_sem); 2130 2131 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1) 2132 on_each_cpu_mask(mm_cpumask(mm), refresh_pce, NULL, 1); 2133 } 2134 2135 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm) 2136 { 2137 2138 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) 2139 return; 2140 2141 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed)) 2142 on_each_cpu_mask(mm_cpumask(mm), refresh_pce, NULL, 1); 2143 } 2144 2145 static int x86_pmu_event_idx(struct perf_event *event) 2146 { 2147 int idx = event->hw.idx; 2148 2149 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) 2150 return 0; 2151 2152 if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { 2153 idx -= INTEL_PMC_IDX_FIXED; 2154 idx |= 1 << 30; 2155 } 2156 2157 return idx + 1; 2158 } 2159 2160 static ssize_t get_attr_rdpmc(struct device *cdev, 2161 struct device_attribute *attr, 2162 char *buf) 2163 { 2164 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); 2165 } 2166 2167 static ssize_t set_attr_rdpmc(struct device *cdev, 2168 struct device_attribute *attr, 2169 const char *buf, size_t count) 2170 { 2171 unsigned long val; 2172 ssize_t ret; 2173 2174 ret = kstrtoul(buf, 0, &val); 2175 if (ret) 2176 return ret; 2177 2178 if (val > 2) 2179 return -EINVAL; 2180 2181 if (x86_pmu.attr_rdpmc_broken) 2182 return -ENOTSUPP; 2183 2184 if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) { 2185 /* 2186 * Changing into or out of always available, aka 2187 * perf-event-bypassing mode. This path is extremely slow, 2188 * but only root can trigger it, so it's okay. 2189 */ 2190 if (val == 2) 2191 static_branch_inc(&rdpmc_always_available_key); 2192 else 2193 static_branch_dec(&rdpmc_always_available_key); 2194 on_each_cpu(refresh_pce, NULL, 1); 2195 } 2196 2197 x86_pmu.attr_rdpmc = val; 2198 2199 return count; 2200 } 2201 2202 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); 2203 2204 static struct attribute *x86_pmu_attrs[] = { 2205 &dev_attr_rdpmc.attr, 2206 NULL, 2207 }; 2208 2209 static struct attribute_group x86_pmu_attr_group __ro_after_init = { 2210 .attrs = x86_pmu_attrs, 2211 }; 2212 2213 static ssize_t max_precise_show(struct device *cdev, 2214 struct device_attribute *attr, 2215 char *buf) 2216 { 2217 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise()); 2218 } 2219 2220 static DEVICE_ATTR_RO(max_precise); 2221 2222 static struct attribute *x86_pmu_caps_attrs[] = { 2223 &dev_attr_max_precise.attr, 2224 NULL 2225 }; 2226 2227 static struct attribute_group x86_pmu_caps_group __ro_after_init = { 2228 .name = "caps", 2229 .attrs = x86_pmu_caps_attrs, 2230 }; 2231 2232 static const struct attribute_group *x86_pmu_attr_groups[] = { 2233 &x86_pmu_attr_group, 2234 &x86_pmu_format_group, 2235 &x86_pmu_events_group, 2236 &x86_pmu_caps_group, 2237 NULL, 2238 }; 2239 2240 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) 2241 { 2242 if (x86_pmu.sched_task) 2243 x86_pmu.sched_task(ctx, sched_in); 2244 } 2245 2246 void perf_check_microcode(void) 2247 { 2248 if (x86_pmu.check_microcode) 2249 x86_pmu.check_microcode(); 2250 } 2251 2252 static int x86_pmu_check_period(struct perf_event *event, u64 value) 2253 { 2254 if (x86_pmu.check_period && x86_pmu.check_period(event, value)) 2255 return -EINVAL; 2256 2257 if (value && x86_pmu.limit_period) { 2258 if (x86_pmu.limit_period(event, value) > value) 2259 return -EINVAL; 2260 } 2261 2262 return 0; 2263 } 2264 2265 static int x86_pmu_aux_output_match(struct perf_event *event) 2266 { 2267 if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT)) 2268 return 0; 2269 2270 if (x86_pmu.aux_output_match) 2271 return x86_pmu.aux_output_match(event); 2272 2273 return 0; 2274 } 2275 2276 static struct pmu pmu = { 2277 .pmu_enable = x86_pmu_enable, 2278 .pmu_disable = x86_pmu_disable, 2279 2280 .attr_groups = x86_pmu_attr_groups, 2281 2282 .event_init = x86_pmu_event_init, 2283 2284 .event_mapped = x86_pmu_event_mapped, 2285 .event_unmapped = x86_pmu_event_unmapped, 2286 2287 .add = x86_pmu_add, 2288 .del = x86_pmu_del, 2289 .start = x86_pmu_start, 2290 .stop = x86_pmu_stop, 2291 .read = x86_pmu_read, 2292 2293 .start_txn = x86_pmu_start_txn, 2294 .cancel_txn = x86_pmu_cancel_txn, 2295 .commit_txn = x86_pmu_commit_txn, 2296 2297 .event_idx = x86_pmu_event_idx, 2298 .sched_task = x86_pmu_sched_task, 2299 .task_ctx_size = sizeof(struct x86_perf_task_context), 2300 .check_period = x86_pmu_check_period, 2301 2302 .aux_output_match = x86_pmu_aux_output_match, 2303 }; 2304 2305 void arch_perf_update_userpage(struct perf_event *event, 2306 struct perf_event_mmap_page *userpg, u64 now) 2307 { 2308 struct cyc2ns_data data; 2309 u64 offset; 2310 2311 userpg->cap_user_time = 0; 2312 userpg->cap_user_time_zero = 0; 2313 userpg->cap_user_rdpmc = 2314 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED); 2315 userpg->pmc_width = x86_pmu.cntval_bits; 2316 2317 if (!using_native_sched_clock() || !sched_clock_stable()) 2318 return; 2319 2320 cyc2ns_read_begin(&data); 2321 2322 offset = data.cyc2ns_offset + __sched_clock_offset; 2323 2324 /* 2325 * Internal timekeeping for enabled/running/stopped times 2326 * is always in the local_clock domain. 2327 */ 2328 userpg->cap_user_time = 1; 2329 userpg->time_mult = data.cyc2ns_mul; 2330 userpg->time_shift = data.cyc2ns_shift; 2331 userpg->time_offset = offset - now; 2332 2333 /* 2334 * cap_user_time_zero doesn't make sense when we're using a different 2335 * time base for the records. 2336 */ 2337 if (!event->attr.use_clockid) { 2338 userpg->cap_user_time_zero = 1; 2339 userpg->time_zero = offset; 2340 } 2341 2342 cyc2ns_read_end(); 2343 } 2344 2345 /* 2346 * Determine whether the regs were taken from an irq/exception handler rather 2347 * than from perf_arch_fetch_caller_regs(). 2348 */ 2349 static bool perf_hw_regs(struct pt_regs *regs) 2350 { 2351 return regs->flags & X86_EFLAGS_FIXED; 2352 } 2353 2354 void 2355 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) 2356 { 2357 struct unwind_state state; 2358 unsigned long addr; 2359 2360 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { 2361 /* TODO: We don't support guest os callchain now */ 2362 return; 2363 } 2364 2365 if (perf_callchain_store(entry, regs->ip)) 2366 return; 2367 2368 if (perf_hw_regs(regs)) 2369 unwind_start(&state, current, regs, NULL); 2370 else 2371 unwind_start(&state, current, NULL, (void *)regs->sp); 2372 2373 for (; !unwind_done(&state); unwind_next_frame(&state)) { 2374 addr = unwind_get_return_address(&state); 2375 if (!addr || perf_callchain_store(entry, addr)) 2376 return; 2377 } 2378 } 2379 2380 static inline int 2381 valid_user_frame(const void __user *fp, unsigned long size) 2382 { 2383 return (__range_not_ok(fp, size, TASK_SIZE) == 0); 2384 } 2385 2386 static unsigned long get_segment_base(unsigned int segment) 2387 { 2388 struct desc_struct *desc; 2389 unsigned int idx = segment >> 3; 2390 2391 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { 2392 #ifdef CONFIG_MODIFY_LDT_SYSCALL 2393 struct ldt_struct *ldt; 2394 2395 /* IRQs are off, so this synchronizes with smp_store_release */ 2396 ldt = READ_ONCE(current->active_mm->context.ldt); 2397 if (!ldt || idx >= ldt->nr_entries) 2398 return 0; 2399 2400 desc = &ldt->entries[idx]; 2401 #else 2402 return 0; 2403 #endif 2404 } else { 2405 if (idx >= GDT_ENTRIES) 2406 return 0; 2407 2408 desc = raw_cpu_ptr(gdt_page.gdt) + idx; 2409 } 2410 2411 return get_desc_base(desc); 2412 } 2413 2414 #ifdef CONFIG_IA32_EMULATION 2415 2416 #include <linux/compat.h> 2417 2418 static inline int 2419 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry) 2420 { 2421 /* 32-bit process in 64-bit kernel. */ 2422 unsigned long ss_base, cs_base; 2423 struct stack_frame_ia32 frame; 2424 const void __user *fp; 2425 2426 if (!test_thread_flag(TIF_IA32)) 2427 return 0; 2428 2429 cs_base = get_segment_base(regs->cs); 2430 ss_base = get_segment_base(regs->ss); 2431 2432 fp = compat_ptr(ss_base + regs->bp); 2433 pagefault_disable(); 2434 while (entry->nr < entry->max_stack) { 2435 unsigned long bytes; 2436 frame.next_frame = 0; 2437 frame.return_address = 0; 2438 2439 if (!valid_user_frame(fp, sizeof(frame))) 2440 break; 2441 2442 bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4); 2443 if (bytes != 0) 2444 break; 2445 bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4); 2446 if (bytes != 0) 2447 break; 2448 2449 perf_callchain_store(entry, cs_base + frame.return_address); 2450 fp = compat_ptr(ss_base + frame.next_frame); 2451 } 2452 pagefault_enable(); 2453 return 1; 2454 } 2455 #else 2456 static inline int 2457 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry) 2458 { 2459 return 0; 2460 } 2461 #endif 2462 2463 void 2464 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) 2465 { 2466 struct stack_frame frame; 2467 const unsigned long __user *fp; 2468 2469 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { 2470 /* TODO: We don't support guest os callchain now */ 2471 return; 2472 } 2473 2474 /* 2475 * We don't know what to do with VM86 stacks.. ignore them for now. 2476 */ 2477 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) 2478 return; 2479 2480 fp = (unsigned long __user *)regs->bp; 2481 2482 perf_callchain_store(entry, regs->ip); 2483 2484 if (!nmi_uaccess_okay()) 2485 return; 2486 2487 if (perf_callchain_user32(regs, entry)) 2488 return; 2489 2490 pagefault_disable(); 2491 while (entry->nr < entry->max_stack) { 2492 unsigned long bytes; 2493 2494 frame.next_frame = NULL; 2495 frame.return_address = 0; 2496 2497 if (!valid_user_frame(fp, sizeof(frame))) 2498 break; 2499 2500 bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp)); 2501 if (bytes != 0) 2502 break; 2503 bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp)); 2504 if (bytes != 0) 2505 break; 2506 2507 perf_callchain_store(entry, frame.return_address); 2508 fp = (void __user *)frame.next_frame; 2509 } 2510 pagefault_enable(); 2511 } 2512 2513 /* 2514 * Deal with code segment offsets for the various execution modes: 2515 * 2516 * VM86 - the good olde 16 bit days, where the linear address is 2517 * 20 bits and we use regs->ip + 0x10 * regs->cs. 2518 * 2519 * IA32 - Where we need to look at GDT/LDT segment descriptor tables 2520 * to figure out what the 32bit base address is. 2521 * 2522 * X32 - has TIF_X32 set, but is running in x86_64 2523 * 2524 * X86_64 - CS,DS,SS,ES are all zero based. 2525 */ 2526 static unsigned long code_segment_base(struct pt_regs *regs) 2527 { 2528 /* 2529 * For IA32 we look at the GDT/LDT segment base to convert the 2530 * effective IP to a linear address. 2531 */ 2532 2533 #ifdef CONFIG_X86_32 2534 /* 2535 * If we are in VM86 mode, add the segment offset to convert to a 2536 * linear address. 2537 */ 2538 if (regs->flags & X86_VM_MASK) 2539 return 0x10 * regs->cs; 2540 2541 if (user_mode(regs) && regs->cs != __USER_CS) 2542 return get_segment_base(regs->cs); 2543 #else 2544 if (user_mode(regs) && !user_64bit_mode(regs) && 2545 regs->cs != __USER32_CS) 2546 return get_segment_base(regs->cs); 2547 #endif 2548 return 0; 2549 } 2550 2551 unsigned long perf_instruction_pointer(struct pt_regs *regs) 2552 { 2553 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) 2554 return perf_guest_cbs->get_guest_ip(); 2555 2556 return regs->ip + code_segment_base(regs); 2557 } 2558 2559 unsigned long perf_misc_flags(struct pt_regs *regs) 2560 { 2561 int misc = 0; 2562 2563 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { 2564 if (perf_guest_cbs->is_user_mode()) 2565 misc |= PERF_RECORD_MISC_GUEST_USER; 2566 else 2567 misc |= PERF_RECORD_MISC_GUEST_KERNEL; 2568 } else { 2569 if (user_mode(regs)) 2570 misc |= PERF_RECORD_MISC_USER; 2571 else 2572 misc |= PERF_RECORD_MISC_KERNEL; 2573 } 2574 2575 if (regs->flags & PERF_EFLAGS_EXACT) 2576 misc |= PERF_RECORD_MISC_EXACT_IP; 2577 2578 return misc; 2579 } 2580 2581 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) 2582 { 2583 cap->version = x86_pmu.version; 2584 cap->num_counters_gp = x86_pmu.num_counters; 2585 cap->num_counters_fixed = x86_pmu.num_counters_fixed; 2586 cap->bit_width_gp = x86_pmu.cntval_bits; 2587 cap->bit_width_fixed = x86_pmu.cntval_bits; 2588 cap->events_mask = (unsigned int)x86_pmu.events_maskl; 2589 cap->events_mask_len = x86_pmu.events_mask_len; 2590 } 2591 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); 2592