1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86_64/entry.S 4 * 5 * Copyright (C) 1991, 1992 Linus Torvalds 6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs 7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 8 * 9 * entry.S contains the system-call and fault low-level handling routines. 10 * 11 * Some of this is documented in Documentation/arch/x86/entry_64.rst 12 * 13 * A note on terminology: 14 * - iret frame: Architecture defined interrupt frame from SS to RIP 15 * at the top of the kernel process stack. 16 * 17 * Some macro usage: 18 * - SYM_FUNC_START/END:Define functions in the symbol table. 19 * - idtentry: Define exception entry points. 20 */ 21#include <linux/linkage.h> 22#include <asm/segment.h> 23#include <asm/cache.h> 24#include <asm/errno.h> 25#include <asm/asm-offsets.h> 26#include <asm/msr.h> 27#include <asm/unistd.h> 28#include <asm/thread_info.h> 29#include <asm/hw_irq.h> 30#include <asm/page_types.h> 31#include <asm/irqflags.h> 32#include <asm/paravirt.h> 33#include <asm/percpu.h> 34#include <asm/asm.h> 35#include <asm/smap.h> 36#include <asm/pgtable_types.h> 37#include <asm/export.h> 38#include <asm/frame.h> 39#include <asm/trapnr.h> 40#include <asm/nospec-branch.h> 41#include <asm/fsgsbase.h> 42#include <linux/err.h> 43 44#include "calling.h" 45 46.code64 47.section .entry.text, "ax" 48 49/* 50 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. 51 * 52 * This is the only entry point used for 64-bit system calls. The 53 * hardware interface is reasonably well designed and the register to 54 * argument mapping Linux uses fits well with the registers that are 55 * available when SYSCALL is used. 56 * 57 * SYSCALL instructions can be found inlined in libc implementations as 58 * well as some other programs and libraries. There are also a handful 59 * of SYSCALL instructions in the vDSO used, for example, as a 60 * clock_gettimeofday fallback. 61 * 62 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, 63 * then loads new ss, cs, and rip from previously programmed MSRs. 64 * rflags gets masked by a value from another MSR (so CLD and CLAC 65 * are not needed). SYSCALL does not save anything on the stack 66 * and does not change rsp. 67 * 68 * Registers on entry: 69 * rax system call number 70 * rcx return address 71 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) 72 * rdi arg0 73 * rsi arg1 74 * rdx arg2 75 * r10 arg3 (needs to be moved to rcx to conform to C ABI) 76 * r8 arg4 77 * r9 arg5 78 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) 79 * 80 * Only called from user space. 81 * 82 * When user can change pt_regs->foo always force IRET. That is because 83 * it deals with uncanonical addresses better. SYSRET has trouble 84 * with them due to bugs in both AMD and Intel CPUs. 85 */ 86 87SYM_CODE_START(entry_SYSCALL_64) 88 UNWIND_HINT_ENTRY 89 ENDBR 90 91 swapgs 92 /* tss.sp2 is scratch space. */ 93 movq %rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2) 94 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp 95 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rsp 96 97SYM_INNER_LABEL(entry_SYSCALL_64_safe_stack, SYM_L_GLOBAL) 98 ANNOTATE_NOENDBR 99 100 /* Construct struct pt_regs on stack */ 101 pushq $__USER_DS /* pt_regs->ss */ 102 pushq PER_CPU_VAR(cpu_tss_rw + TSS_sp2) /* pt_regs->sp */ 103 pushq %r11 /* pt_regs->flags */ 104 pushq $__USER_CS /* pt_regs->cs */ 105 pushq %rcx /* pt_regs->ip */ 106SYM_INNER_LABEL(entry_SYSCALL_64_after_hwframe, SYM_L_GLOBAL) 107 pushq %rax /* pt_regs->orig_ax */ 108 109 PUSH_AND_CLEAR_REGS rax=$-ENOSYS 110 111 /* IRQs are off. */ 112 movq %rsp, %rdi 113 /* Sign extend the lower 32bit as syscall numbers are treated as int */ 114 movslq %eax, %rsi 115 116 /* clobbers %rax, make sure it is after saving the syscall nr */ 117 IBRS_ENTER 118 UNTRAIN_RET 119 120 call do_syscall_64 /* returns with IRQs disabled */ 121 122 /* 123 * Try to use SYSRET instead of IRET if we're returning to 124 * a completely clean 64-bit userspace context. If we're not, 125 * go to the slow exit path. 126 * In the Xen PV case we must use iret anyway. 127 */ 128 129 ALTERNATIVE "", "jmp swapgs_restore_regs_and_return_to_usermode", \ 130 X86_FEATURE_XENPV 131 132 movq RCX(%rsp), %rcx 133 movq RIP(%rsp), %r11 134 135 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ 136 jne swapgs_restore_regs_and_return_to_usermode 137 138 /* 139 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP 140 * in kernel space. This essentially lets the user take over 141 * the kernel, since userspace controls RSP. 142 * 143 * If width of "canonical tail" ever becomes variable, this will need 144 * to be updated to remain correct on both old and new CPUs. 145 * 146 * Change top bits to match most significant bit (47th or 56th bit 147 * depending on paging mode) in the address. 148 */ 149#ifdef CONFIG_X86_5LEVEL 150 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \ 151 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57 152#else 153 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 154 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 155#endif 156 157 /* If this changed %rcx, it was not canonical */ 158 cmpq %rcx, %r11 159 jne swapgs_restore_regs_and_return_to_usermode 160 161 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ 162 jne swapgs_restore_regs_and_return_to_usermode 163 164 movq R11(%rsp), %r11 165 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ 166 jne swapgs_restore_regs_and_return_to_usermode 167 168 /* 169 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot 170 * restore RF properly. If the slowpath sets it for whatever reason, we 171 * need to restore it correctly. 172 * 173 * SYSRET can restore TF, but unlike IRET, restoring TF results in a 174 * trap from userspace immediately after SYSRET. This would cause an 175 * infinite loop whenever #DB happens with register state that satisfies 176 * the opportunistic SYSRET conditions. For example, single-stepping 177 * this user code: 178 * 179 * movq $stuck_here, %rcx 180 * pushfq 181 * popq %r11 182 * stuck_here: 183 * 184 * would never get past 'stuck_here'. 185 */ 186 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 187 jnz swapgs_restore_regs_and_return_to_usermode 188 189 /* nothing to check for RSP */ 190 191 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ 192 jne swapgs_restore_regs_and_return_to_usermode 193 194 /* 195 * We win! This label is here just for ease of understanding 196 * perf profiles. Nothing jumps here. 197 */ 198syscall_return_via_sysret: 199 IBRS_EXIT 200 POP_REGS pop_rdi=0 201 202 /* 203 * Now all regs are restored except RSP and RDI. 204 * Save old stack pointer and switch to trampoline stack. 205 */ 206 movq %rsp, %rdi 207 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 208 UNWIND_HINT_END_OF_STACK 209 210 pushq RSP-RDI(%rdi) /* RSP */ 211 pushq (%rdi) /* RDI */ 212 213 /* 214 * We are on the trampoline stack. All regs except RDI are live. 215 * We can do future final exit work right here. 216 */ 217 STACKLEAK_ERASE_NOCLOBBER 218 219 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 220 221 popq %rdi 222 popq %rsp 223SYM_INNER_LABEL(entry_SYSRETQ_unsafe_stack, SYM_L_GLOBAL) 224 ANNOTATE_NOENDBR 225 swapgs 226 sysretq 227SYM_INNER_LABEL(entry_SYSRETQ_end, SYM_L_GLOBAL) 228 ANNOTATE_NOENDBR 229 int3 230SYM_CODE_END(entry_SYSCALL_64) 231 232/* 233 * %rdi: prev task 234 * %rsi: next task 235 */ 236.pushsection .text, "ax" 237SYM_FUNC_START(__switch_to_asm) 238 /* 239 * Save callee-saved registers 240 * This must match the order in inactive_task_frame 241 */ 242 pushq %rbp 243 pushq %rbx 244 pushq %r12 245 pushq %r13 246 pushq %r14 247 pushq %r15 248 249 /* switch stack */ 250 movq %rsp, TASK_threadsp(%rdi) 251 movq TASK_threadsp(%rsi), %rsp 252 253#ifdef CONFIG_STACKPROTECTOR 254 movq TASK_stack_canary(%rsi), %rbx 255 movq %rbx, PER_CPU_VAR(fixed_percpu_data) + FIXED_stack_canary 256#endif 257 258 /* 259 * When switching from a shallower to a deeper call stack 260 * the RSB may either underflow or use entries populated 261 * with userspace addresses. On CPUs where those concerns 262 * exist, overwrite the RSB with entries which capture 263 * speculative execution to prevent attack. 264 */ 265 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW 266 267 /* restore callee-saved registers */ 268 popq %r15 269 popq %r14 270 popq %r13 271 popq %r12 272 popq %rbx 273 popq %rbp 274 275 jmp __switch_to 276SYM_FUNC_END(__switch_to_asm) 277.popsection 278 279/* 280 * A newly forked process directly context switches into this address. 281 * 282 * rax: prev task we switched from 283 * rbx: kernel thread func (NULL for user thread) 284 * r12: kernel thread arg 285 */ 286.pushsection .text, "ax" 287SYM_CODE_START(ret_from_fork_asm) 288 /* 289 * This is the start of the kernel stack; even through there's a 290 * register set at the top, the regset isn't necessarily coherent 291 * (consider kthreads) and one cannot unwind further. 292 * 293 * This ensures stack unwinds of kernel threads terminate in a known 294 * good state. 295 */ 296 UNWIND_HINT_END_OF_STACK 297 ANNOTATE_NOENDBR // copy_thread 298 CALL_DEPTH_ACCOUNT 299 300 movq %rax, %rdi /* prev */ 301 movq %rsp, %rsi /* regs */ 302 movq %rbx, %rdx /* fn */ 303 movq %r12, %rcx /* fn_arg */ 304 call ret_from_fork 305 306 /* 307 * Set the stack state to what is expected for the target function 308 * -- at this point the register set should be a valid user set 309 * and unwind should work normally. 310 */ 311 UNWIND_HINT_REGS 312 jmp swapgs_restore_regs_and_return_to_usermode 313SYM_CODE_END(ret_from_fork_asm) 314.popsection 315 316.macro DEBUG_ENTRY_ASSERT_IRQS_OFF 317#ifdef CONFIG_DEBUG_ENTRY 318 pushq %rax 319 SAVE_FLAGS 320 testl $X86_EFLAGS_IF, %eax 321 jz .Lokay_\@ 322 ud2 323.Lokay_\@: 324 popq %rax 325#endif 326.endm 327 328SYM_CODE_START(xen_error_entry) 329 ANNOTATE_NOENDBR 330 UNWIND_HINT_FUNC 331 PUSH_AND_CLEAR_REGS save_ret=1 332 ENCODE_FRAME_POINTER 8 333 UNTRAIN_RET_FROM_CALL 334 RET 335SYM_CODE_END(xen_error_entry) 336 337/** 338 * idtentry_body - Macro to emit code calling the C function 339 * @cfunc: C function to be called 340 * @has_error_code: Hardware pushed error code on stack 341 */ 342.macro idtentry_body cfunc has_error_code:req 343 344 /* 345 * Call error_entry() and switch to the task stack if from userspace. 346 * 347 * When in XENPV, it is already in the task stack, and it can't fault 348 * for native_iret() nor native_load_gs_index() since XENPV uses its 349 * own pvops for IRET and load_gs_index(). And it doesn't need to 350 * switch the CR3. So it can skip invoking error_entry(). 351 */ 352 ALTERNATIVE "call error_entry; movq %rax, %rsp", \ 353 "call xen_error_entry", X86_FEATURE_XENPV 354 355 ENCODE_FRAME_POINTER 356 UNWIND_HINT_REGS 357 358 movq %rsp, %rdi /* pt_regs pointer into 1st argument*/ 359 360 .if \has_error_code == 1 361 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/ 362 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 363 .endif 364 365 call \cfunc 366 367 /* For some configurations \cfunc ends up being a noreturn. */ 368 REACHABLE 369 370 jmp error_return 371.endm 372 373/** 374 * idtentry - Macro to generate entry stubs for simple IDT entries 375 * @vector: Vector number 376 * @asmsym: ASM symbol for the entry point 377 * @cfunc: C function to be called 378 * @has_error_code: Hardware pushed error code on stack 379 * 380 * The macro emits code to set up the kernel context for straight forward 381 * and simple IDT entries. No IST stack, no paranoid entry checks. 382 */ 383.macro idtentry vector asmsym cfunc has_error_code:req 384SYM_CODE_START(\asmsym) 385 386 .if \vector == X86_TRAP_BP 387 /* #BP advances %rip to the next instruction */ 388 UNWIND_HINT_IRET_ENTRY offset=\has_error_code*8 signal=0 389 .else 390 UNWIND_HINT_IRET_ENTRY offset=\has_error_code*8 391 .endif 392 393 ENDBR 394 ASM_CLAC 395 cld 396 397 .if \has_error_code == 0 398 pushq $-1 /* ORIG_RAX: no syscall to restart */ 399 .endif 400 401 .if \vector == X86_TRAP_BP 402 /* 403 * If coming from kernel space, create a 6-word gap to allow the 404 * int3 handler to emulate a call instruction. 405 */ 406 testb $3, CS-ORIG_RAX(%rsp) 407 jnz .Lfrom_usermode_no_gap_\@ 408 .rept 6 409 pushq 5*8(%rsp) 410 .endr 411 UNWIND_HINT_IRET_REGS offset=8 412.Lfrom_usermode_no_gap_\@: 413 .endif 414 415 idtentry_body \cfunc \has_error_code 416 417_ASM_NOKPROBE(\asmsym) 418SYM_CODE_END(\asmsym) 419.endm 420 421/* 422 * Interrupt entry/exit. 423 * 424 + The interrupt stubs push (vector) onto the stack, which is the error_code 425 * position of idtentry exceptions, and jump to one of the two idtentry points 426 * (common/spurious). 427 * 428 * common_interrupt is a hotpath, align it to a cache line 429 */ 430.macro idtentry_irq vector cfunc 431 .p2align CONFIG_X86_L1_CACHE_SHIFT 432 idtentry \vector asm_\cfunc \cfunc has_error_code=1 433.endm 434 435/* 436 * System vectors which invoke their handlers directly and are not 437 * going through the regular common device interrupt handling code. 438 */ 439.macro idtentry_sysvec vector cfunc 440 idtentry \vector asm_\cfunc \cfunc has_error_code=0 441.endm 442 443/** 444 * idtentry_mce_db - Macro to generate entry stubs for #MC and #DB 445 * @vector: Vector number 446 * @asmsym: ASM symbol for the entry point 447 * @cfunc: C function to be called 448 * 449 * The macro emits code to set up the kernel context for #MC and #DB 450 * 451 * If the entry comes from user space it uses the normal entry path 452 * including the return to user space work and preemption checks on 453 * exit. 454 * 455 * If hits in kernel mode then it needs to go through the paranoid 456 * entry as the exception can hit any random state. No preemption 457 * check on exit to keep the paranoid path simple. 458 */ 459.macro idtentry_mce_db vector asmsym cfunc 460SYM_CODE_START(\asmsym) 461 UNWIND_HINT_IRET_ENTRY 462 ENDBR 463 ASM_CLAC 464 cld 465 466 pushq $-1 /* ORIG_RAX: no syscall to restart */ 467 468 /* 469 * If the entry is from userspace, switch stacks and treat it as 470 * a normal entry. 471 */ 472 testb $3, CS-ORIG_RAX(%rsp) 473 jnz .Lfrom_usermode_switch_stack_\@ 474 475 /* paranoid_entry returns GS information for paranoid_exit in EBX. */ 476 call paranoid_entry 477 478 UNWIND_HINT_REGS 479 480 movq %rsp, %rdi /* pt_regs pointer */ 481 482 call \cfunc 483 484 jmp paranoid_exit 485 486 /* Switch to the regular task stack and use the noist entry point */ 487.Lfrom_usermode_switch_stack_\@: 488 idtentry_body noist_\cfunc, has_error_code=0 489 490_ASM_NOKPROBE(\asmsym) 491SYM_CODE_END(\asmsym) 492.endm 493 494#ifdef CONFIG_AMD_MEM_ENCRYPT 495/** 496 * idtentry_vc - Macro to generate entry stub for #VC 497 * @vector: Vector number 498 * @asmsym: ASM symbol for the entry point 499 * @cfunc: C function to be called 500 * 501 * The macro emits code to set up the kernel context for #VC. The #VC handler 502 * runs on an IST stack and needs to be able to cause nested #VC exceptions. 503 * 504 * To make this work the #VC entry code tries its best to pretend it doesn't use 505 * an IST stack by switching to the task stack if coming from user-space (which 506 * includes early SYSCALL entry path) or back to the stack in the IRET frame if 507 * entered from kernel-mode. 508 * 509 * If entered from kernel-mode the return stack is validated first, and if it is 510 * not safe to use (e.g. because it points to the entry stack) the #VC handler 511 * will switch to a fall-back stack (VC2) and call a special handler function. 512 * 513 * The macro is only used for one vector, but it is planned to be extended in 514 * the future for the #HV exception. 515 */ 516.macro idtentry_vc vector asmsym cfunc 517SYM_CODE_START(\asmsym) 518 UNWIND_HINT_IRET_ENTRY 519 ENDBR 520 ASM_CLAC 521 cld 522 523 /* 524 * If the entry is from userspace, switch stacks and treat it as 525 * a normal entry. 526 */ 527 testb $3, CS-ORIG_RAX(%rsp) 528 jnz .Lfrom_usermode_switch_stack_\@ 529 530 /* 531 * paranoid_entry returns SWAPGS flag for paranoid_exit in EBX. 532 * EBX == 0 -> SWAPGS, EBX == 1 -> no SWAPGS 533 */ 534 call paranoid_entry 535 536 UNWIND_HINT_REGS 537 538 /* 539 * Switch off the IST stack to make it free for nested exceptions. The 540 * vc_switch_off_ist() function will switch back to the interrupted 541 * stack if it is safe to do so. If not it switches to the VC fall-back 542 * stack. 543 */ 544 movq %rsp, %rdi /* pt_regs pointer */ 545 call vc_switch_off_ist 546 movq %rax, %rsp /* Switch to new stack */ 547 548 ENCODE_FRAME_POINTER 549 UNWIND_HINT_REGS 550 551 /* Update pt_regs */ 552 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/ 553 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 554 555 movq %rsp, %rdi /* pt_regs pointer */ 556 557 call kernel_\cfunc 558 559 /* 560 * No need to switch back to the IST stack. The current stack is either 561 * identical to the stack in the IRET frame or the VC fall-back stack, 562 * so it is definitely mapped even with PTI enabled. 563 */ 564 jmp paranoid_exit 565 566 /* Switch to the regular task stack */ 567.Lfrom_usermode_switch_stack_\@: 568 idtentry_body user_\cfunc, has_error_code=1 569 570_ASM_NOKPROBE(\asmsym) 571SYM_CODE_END(\asmsym) 572.endm 573#endif 574 575/* 576 * Double fault entry. Straight paranoid. No checks from which context 577 * this comes because for the espfix induced #DF this would do the wrong 578 * thing. 579 */ 580.macro idtentry_df vector asmsym cfunc 581SYM_CODE_START(\asmsym) 582 UNWIND_HINT_IRET_ENTRY offset=8 583 ENDBR 584 ASM_CLAC 585 cld 586 587 /* paranoid_entry returns GS information for paranoid_exit in EBX. */ 588 call paranoid_entry 589 UNWIND_HINT_REGS 590 591 movq %rsp, %rdi /* pt_regs pointer into first argument */ 592 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/ 593 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 594 call \cfunc 595 596 /* For some configurations \cfunc ends up being a noreturn. */ 597 REACHABLE 598 599 jmp paranoid_exit 600 601_ASM_NOKPROBE(\asmsym) 602SYM_CODE_END(\asmsym) 603.endm 604 605/* 606 * Include the defines which emit the idt entries which are shared 607 * shared between 32 and 64 bit and emit the __irqentry_text_* markers 608 * so the stacktrace boundary checks work. 609 */ 610 __ALIGN 611 .globl __irqentry_text_start 612__irqentry_text_start: 613 614#include <asm/idtentry.h> 615 616 __ALIGN 617 .globl __irqentry_text_end 618__irqentry_text_end: 619 ANNOTATE_NOENDBR 620 621SYM_CODE_START_LOCAL(common_interrupt_return) 622SYM_INNER_LABEL(swapgs_restore_regs_and_return_to_usermode, SYM_L_GLOBAL) 623 IBRS_EXIT 624#ifdef CONFIG_DEBUG_ENTRY 625 /* Assert that pt_regs indicates user mode. */ 626 testb $3, CS(%rsp) 627 jnz 1f 628 ud2 6291: 630#endif 631#ifdef CONFIG_XEN_PV 632 ALTERNATIVE "", "jmp xenpv_restore_regs_and_return_to_usermode", X86_FEATURE_XENPV 633#endif 634 635 POP_REGS pop_rdi=0 636 637 /* 638 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. 639 * Save old stack pointer and switch to trampoline stack. 640 */ 641 movq %rsp, %rdi 642 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 643 UNWIND_HINT_END_OF_STACK 644 645 /* Copy the IRET frame to the trampoline stack. */ 646 pushq 6*8(%rdi) /* SS */ 647 pushq 5*8(%rdi) /* RSP */ 648 pushq 4*8(%rdi) /* EFLAGS */ 649 pushq 3*8(%rdi) /* CS */ 650 pushq 2*8(%rdi) /* RIP */ 651 652 /* Push user RDI on the trampoline stack. */ 653 pushq (%rdi) 654 655 /* 656 * We are on the trampoline stack. All regs except RDI are live. 657 * We can do future final exit work right here. 658 */ 659 STACKLEAK_ERASE_NOCLOBBER 660 661 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 662 663 /* Restore RDI. */ 664 popq %rdi 665 swapgs 666 jmp .Lnative_iret 667 668 669SYM_INNER_LABEL(restore_regs_and_return_to_kernel, SYM_L_GLOBAL) 670#ifdef CONFIG_DEBUG_ENTRY 671 /* Assert that pt_regs indicates kernel mode. */ 672 testb $3, CS(%rsp) 673 jz 1f 674 ud2 6751: 676#endif 677 POP_REGS 678 addq $8, %rsp /* skip regs->orig_ax */ 679 /* 680 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization 681 * when returning from IPI handler. 682 */ 683#ifdef CONFIG_XEN_PV 684SYM_INNER_LABEL(early_xen_iret_patch, SYM_L_GLOBAL) 685 ANNOTATE_NOENDBR 686 .byte 0xe9 687 .long .Lnative_iret - (. + 4) 688#endif 689 690.Lnative_iret: 691 UNWIND_HINT_IRET_REGS 692 /* 693 * Are we returning to a stack segment from the LDT? Note: in 694 * 64-bit mode SS:RSP on the exception stack is always valid. 695 */ 696#ifdef CONFIG_X86_ESPFIX64 697 testb $4, (SS-RIP)(%rsp) 698 jnz native_irq_return_ldt 699#endif 700 701SYM_INNER_LABEL(native_irq_return_iret, SYM_L_GLOBAL) 702 ANNOTATE_NOENDBR // exc_double_fault 703 /* 704 * This may fault. Non-paranoid faults on return to userspace are 705 * handled by fixup_bad_iret. These include #SS, #GP, and #NP. 706 * Double-faults due to espfix64 are handled in exc_double_fault. 707 * Other faults here are fatal. 708 */ 709 iretq 710 711#ifdef CONFIG_X86_ESPFIX64 712native_irq_return_ldt: 713 /* 714 * We are running with user GSBASE. All GPRs contain their user 715 * values. We have a percpu ESPFIX stack that is eight slots 716 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom 717 * of the ESPFIX stack. 718 * 719 * We clobber RAX and RDI in this code. We stash RDI on the 720 * normal stack and RAX on the ESPFIX stack. 721 * 722 * The ESPFIX stack layout we set up looks like this: 723 * 724 * --- top of ESPFIX stack --- 725 * SS 726 * RSP 727 * RFLAGS 728 * CS 729 * RIP <-- RSP points here when we're done 730 * RAX <-- espfix_waddr points here 731 * --- bottom of ESPFIX stack --- 732 */ 733 734 pushq %rdi /* Stash user RDI */ 735 swapgs /* to kernel GS */ 736 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ 737 738 movq PER_CPU_VAR(espfix_waddr), %rdi 739 movq %rax, (0*8)(%rdi) /* user RAX */ 740 movq (1*8)(%rsp), %rax /* user RIP */ 741 movq %rax, (1*8)(%rdi) 742 movq (2*8)(%rsp), %rax /* user CS */ 743 movq %rax, (2*8)(%rdi) 744 movq (3*8)(%rsp), %rax /* user RFLAGS */ 745 movq %rax, (3*8)(%rdi) 746 movq (5*8)(%rsp), %rax /* user SS */ 747 movq %rax, (5*8)(%rdi) 748 movq (4*8)(%rsp), %rax /* user RSP */ 749 movq %rax, (4*8)(%rdi) 750 /* Now RAX == RSP. */ 751 752 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ 753 754 /* 755 * espfix_stack[31:16] == 0. The page tables are set up such that 756 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of 757 * espfix_waddr for any X. That is, there are 65536 RO aliases of 758 * the same page. Set up RSP so that RSP[31:16] contains the 759 * respective 16 bits of the /userspace/ RSP and RSP nonetheless 760 * still points to an RO alias of the ESPFIX stack. 761 */ 762 orq PER_CPU_VAR(espfix_stack), %rax 763 764 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 765 swapgs /* to user GS */ 766 popq %rdi /* Restore user RDI */ 767 768 movq %rax, %rsp 769 UNWIND_HINT_IRET_REGS offset=8 770 771 /* 772 * At this point, we cannot write to the stack any more, but we can 773 * still read. 774 */ 775 popq %rax /* Restore user RAX */ 776 777 /* 778 * RSP now points to an ordinary IRET frame, except that the page 779 * is read-only and RSP[31:16] are preloaded with the userspace 780 * values. We can now IRET back to userspace. 781 */ 782 jmp native_irq_return_iret 783#endif 784SYM_CODE_END(common_interrupt_return) 785_ASM_NOKPROBE(common_interrupt_return) 786 787/* 788 * Reload gs selector with exception handling 789 * di: new selector 790 * 791 * Is in entry.text as it shouldn't be instrumented. 792 */ 793SYM_FUNC_START(asm_load_gs_index) 794 FRAME_BEGIN 795 swapgs 796.Lgs_change: 797 ANNOTATE_NOENDBR // error_entry 798 movl %edi, %gs 7992: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE 800 swapgs 801 FRAME_END 802 RET 803 804 /* running with kernelgs */ 805.Lbad_gs: 806 swapgs /* switch back to user gs */ 807.macro ZAP_GS 808 /* This can't be a string because the preprocessor needs to see it. */ 809 movl $__USER_DS, %eax 810 movl %eax, %gs 811.endm 812 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG 813 xorl %eax, %eax 814 movl %eax, %gs 815 jmp 2b 816 817 _ASM_EXTABLE(.Lgs_change, .Lbad_gs) 818 819SYM_FUNC_END(asm_load_gs_index) 820EXPORT_SYMBOL(asm_load_gs_index) 821 822#ifdef CONFIG_XEN_PV 823/* 824 * A note on the "critical region" in our callback handler. 825 * We want to avoid stacking callback handlers due to events occurring 826 * during handling of the last event. To do this, we keep events disabled 827 * until we've done all processing. HOWEVER, we must enable events before 828 * popping the stack frame (can't be done atomically) and so it would still 829 * be possible to get enough handler activations to overflow the stack. 830 * Although unlikely, bugs of that kind are hard to track down, so we'd 831 * like to avoid the possibility. 832 * So, on entry to the handler we detect whether we interrupted an 833 * existing activation in its critical region -- if so, we pop the current 834 * activation and restart the handler using the previous one. 835 * 836 * C calling convention: exc_xen_hypervisor_callback(struct *pt_regs) 837 */ 838 __FUNC_ALIGN 839SYM_CODE_START_LOCAL_NOALIGN(exc_xen_hypervisor_callback) 840 841/* 842 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will 843 * see the correct pointer to the pt_regs 844 */ 845 UNWIND_HINT_FUNC 846 movq %rdi, %rsp /* we don't return, adjust the stack frame */ 847 UNWIND_HINT_REGS 848 849 call xen_pv_evtchn_do_upcall 850 851 jmp error_return 852SYM_CODE_END(exc_xen_hypervisor_callback) 853 854/* 855 * Hypervisor uses this for application faults while it executes. 856 * We get here for two reasons: 857 * 1. Fault while reloading DS, ES, FS or GS 858 * 2. Fault while executing IRET 859 * Category 1 we do not need to fix up as Xen has already reloaded all segment 860 * registers that could be reloaded and zeroed the others. 861 * Category 2 we fix up by killing the current process. We cannot use the 862 * normal Linux return path in this case because if we use the IRET hypercall 863 * to pop the stack frame we end up in an infinite loop of failsafe callbacks. 864 * We distinguish between categories by comparing each saved segment register 865 * with its current contents: any discrepancy means we in category 1. 866 */ 867 __FUNC_ALIGN 868SYM_CODE_START_NOALIGN(xen_failsafe_callback) 869 UNWIND_HINT_UNDEFINED 870 ENDBR 871 movl %ds, %ecx 872 cmpw %cx, 0x10(%rsp) 873 jne 1f 874 movl %es, %ecx 875 cmpw %cx, 0x18(%rsp) 876 jne 1f 877 movl %fs, %ecx 878 cmpw %cx, 0x20(%rsp) 879 jne 1f 880 movl %gs, %ecx 881 cmpw %cx, 0x28(%rsp) 882 jne 1f 883 /* All segments match their saved values => Category 2 (Bad IRET). */ 884 movq (%rsp), %rcx 885 movq 8(%rsp), %r11 886 addq $0x30, %rsp 887 pushq $0 /* RIP */ 888 UNWIND_HINT_IRET_REGS offset=8 889 jmp asm_exc_general_protection 8901: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ 891 movq (%rsp), %rcx 892 movq 8(%rsp), %r11 893 addq $0x30, %rsp 894 UNWIND_HINT_IRET_REGS 895 pushq $-1 /* orig_ax = -1 => not a system call */ 896 PUSH_AND_CLEAR_REGS 897 ENCODE_FRAME_POINTER 898 jmp error_return 899SYM_CODE_END(xen_failsafe_callback) 900#endif /* CONFIG_XEN_PV */ 901 902/* 903 * Save all registers in pt_regs. Return GSBASE related information 904 * in EBX depending on the availability of the FSGSBASE instructions: 905 * 906 * FSGSBASE R/EBX 907 * N 0 -> SWAPGS on exit 908 * 1 -> no SWAPGS on exit 909 * 910 * Y GSBASE value at entry, must be restored in paranoid_exit 911 * 912 * R14 - old CR3 913 * R15 - old SPEC_CTRL 914 */ 915SYM_CODE_START(paranoid_entry) 916 ANNOTATE_NOENDBR 917 UNWIND_HINT_FUNC 918 PUSH_AND_CLEAR_REGS save_ret=1 919 ENCODE_FRAME_POINTER 8 920 921 /* 922 * Always stash CR3 in %r14. This value will be restored, 923 * verbatim, at exit. Needed if paranoid_entry interrupted 924 * another entry that already switched to the user CR3 value 925 * but has not yet returned to userspace. 926 * 927 * This is also why CS (stashed in the "iret frame" by the 928 * hardware at entry) can not be used: this may be a return 929 * to kernel code, but with a user CR3 value. 930 * 931 * Switching CR3 does not depend on kernel GSBASE so it can 932 * be done before switching to the kernel GSBASE. This is 933 * required for FSGSBASE because the kernel GSBASE has to 934 * be retrieved from a kernel internal table. 935 */ 936 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 937 938 /* 939 * Handling GSBASE depends on the availability of FSGSBASE. 940 * 941 * Without FSGSBASE the kernel enforces that negative GSBASE 942 * values indicate kernel GSBASE. With FSGSBASE no assumptions 943 * can be made about the GSBASE value when entering from user 944 * space. 945 */ 946 ALTERNATIVE "jmp .Lparanoid_entry_checkgs", "", X86_FEATURE_FSGSBASE 947 948 /* 949 * Read the current GSBASE and store it in %rbx unconditionally, 950 * retrieve and set the current CPUs kernel GSBASE. The stored value 951 * has to be restored in paranoid_exit unconditionally. 952 * 953 * The unconditional write to GS base below ensures that no subsequent 954 * loads based on a mispredicted GS base can happen, therefore no LFENCE 955 * is needed here. 956 */ 957 SAVE_AND_SET_GSBASE scratch_reg=%rax save_reg=%rbx 958 jmp .Lparanoid_gsbase_done 959 960.Lparanoid_entry_checkgs: 961 /* EBX = 1 -> kernel GSBASE active, no restore required */ 962 movl $1, %ebx 963 964 /* 965 * The kernel-enforced convention is a negative GSBASE indicates 966 * a kernel value. No SWAPGS needed on entry and exit. 967 */ 968 movl $MSR_GS_BASE, %ecx 969 rdmsr 970 testl %edx, %edx 971 js .Lparanoid_kernel_gsbase 972 973 /* EBX = 0 -> SWAPGS required on exit */ 974 xorl %ebx, %ebx 975 swapgs 976.Lparanoid_kernel_gsbase: 977 FENCE_SWAPGS_KERNEL_ENTRY 978.Lparanoid_gsbase_done: 979 980 /* 981 * Once we have CR3 and %GS setup save and set SPEC_CTRL. Just like 982 * CR3 above, keep the old value in a callee saved register. 983 */ 984 IBRS_ENTER save_reg=%r15 985 UNTRAIN_RET_FROM_CALL 986 987 RET 988SYM_CODE_END(paranoid_entry) 989 990/* 991 * "Paranoid" exit path from exception stack. This is invoked 992 * only on return from non-NMI IST interrupts that came 993 * from kernel space. 994 * 995 * We may be returning to very strange contexts (e.g. very early 996 * in syscall entry), so checking for preemption here would 997 * be complicated. Fortunately, there's no good reason to try 998 * to handle preemption here. 999 * 1000 * R/EBX contains the GSBASE related information depending on the 1001 * availability of the FSGSBASE instructions: 1002 * 1003 * FSGSBASE R/EBX 1004 * N 0 -> SWAPGS on exit 1005 * 1 -> no SWAPGS on exit 1006 * 1007 * Y User space GSBASE, must be restored unconditionally 1008 * 1009 * R14 - old CR3 1010 * R15 - old SPEC_CTRL 1011 */ 1012SYM_CODE_START_LOCAL(paranoid_exit) 1013 UNWIND_HINT_REGS 1014 1015 /* 1016 * Must restore IBRS state before both CR3 and %GS since we need access 1017 * to the per-CPU x86_spec_ctrl_shadow variable. 1018 */ 1019 IBRS_EXIT save_reg=%r15 1020 1021 /* 1022 * The order of operations is important. RESTORE_CR3 requires 1023 * kernel GSBASE. 1024 * 1025 * NB to anyone to try to optimize this code: this code does 1026 * not execute at all for exceptions from user mode. Those 1027 * exceptions go through error_return instead. 1028 */ 1029 RESTORE_CR3 scratch_reg=%rax save_reg=%r14 1030 1031 /* Handle the three GSBASE cases */ 1032 ALTERNATIVE "jmp .Lparanoid_exit_checkgs", "", X86_FEATURE_FSGSBASE 1033 1034 /* With FSGSBASE enabled, unconditionally restore GSBASE */ 1035 wrgsbase %rbx 1036 jmp restore_regs_and_return_to_kernel 1037 1038.Lparanoid_exit_checkgs: 1039 /* On non-FSGSBASE systems, conditionally do SWAPGS */ 1040 testl %ebx, %ebx 1041 jnz restore_regs_and_return_to_kernel 1042 1043 /* We are returning to a context with user GSBASE */ 1044 swapgs 1045 jmp restore_regs_and_return_to_kernel 1046SYM_CODE_END(paranoid_exit) 1047 1048/* 1049 * Switch GS and CR3 if needed. 1050 */ 1051SYM_CODE_START(error_entry) 1052 ANNOTATE_NOENDBR 1053 UNWIND_HINT_FUNC 1054 1055 PUSH_AND_CLEAR_REGS save_ret=1 1056 ENCODE_FRAME_POINTER 8 1057 1058 testb $3, CS+8(%rsp) 1059 jz .Lerror_kernelspace 1060 1061 /* 1062 * We entered from user mode or we're pretending to have entered 1063 * from user mode due to an IRET fault. 1064 */ 1065 swapgs 1066 FENCE_SWAPGS_USER_ENTRY 1067 /* We have user CR3. Change to kernel CR3. */ 1068 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1069 IBRS_ENTER 1070 UNTRAIN_RET_FROM_CALL 1071 1072 leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */ 1073 /* Put us onto the real thread stack. */ 1074 jmp sync_regs 1075 1076 /* 1077 * There are two places in the kernel that can potentially fault with 1078 * usergs. Handle them here. B stepping K8s sometimes report a 1079 * truncated RIP for IRET exceptions returning to compat mode. Check 1080 * for these here too. 1081 */ 1082.Lerror_kernelspace: 1083 leaq native_irq_return_iret(%rip), %rcx 1084 cmpq %rcx, RIP+8(%rsp) 1085 je .Lerror_bad_iret 1086 movl %ecx, %eax /* zero extend */ 1087 cmpq %rax, RIP+8(%rsp) 1088 je .Lbstep_iret 1089 cmpq $.Lgs_change, RIP+8(%rsp) 1090 jne .Lerror_entry_done_lfence 1091 1092 /* 1093 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up 1094 * gsbase and proceed. We'll fix up the exception and land in 1095 * .Lgs_change's error handler with kernel gsbase. 1096 */ 1097 swapgs 1098 1099 /* 1100 * Issue an LFENCE to prevent GS speculation, regardless of whether it is a 1101 * kernel or user gsbase. 1102 */ 1103.Lerror_entry_done_lfence: 1104 FENCE_SWAPGS_KERNEL_ENTRY 1105 CALL_DEPTH_ACCOUNT 1106 leaq 8(%rsp), %rax /* return pt_regs pointer */ 1107 VALIDATE_UNRET_END 1108 RET 1109 1110.Lbstep_iret: 1111 /* Fix truncated RIP */ 1112 movq %rcx, RIP+8(%rsp) 1113 /* fall through */ 1114 1115.Lerror_bad_iret: 1116 /* 1117 * We came from an IRET to user mode, so we have user 1118 * gsbase and CR3. Switch to kernel gsbase and CR3: 1119 */ 1120 swapgs 1121 FENCE_SWAPGS_USER_ENTRY 1122 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1123 IBRS_ENTER 1124 UNTRAIN_RET_FROM_CALL 1125 1126 /* 1127 * Pretend that the exception came from user mode: set up pt_regs 1128 * as if we faulted immediately after IRET. 1129 */ 1130 leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */ 1131 call fixup_bad_iret 1132 mov %rax, %rdi 1133 jmp sync_regs 1134SYM_CODE_END(error_entry) 1135 1136SYM_CODE_START_LOCAL(error_return) 1137 UNWIND_HINT_REGS 1138 DEBUG_ENTRY_ASSERT_IRQS_OFF 1139 testb $3, CS(%rsp) 1140 jz restore_regs_and_return_to_kernel 1141 jmp swapgs_restore_regs_and_return_to_usermode 1142SYM_CODE_END(error_return) 1143 1144/* 1145 * Runs on exception stack. Xen PV does not go through this path at all, 1146 * so we can use real assembly here. 1147 * 1148 * Registers: 1149 * %r14: Used to save/restore the CR3 of the interrupted context 1150 * when PAGE_TABLE_ISOLATION is in use. Do not clobber. 1151 */ 1152SYM_CODE_START(asm_exc_nmi) 1153 UNWIND_HINT_IRET_ENTRY 1154 ENDBR 1155 1156 /* 1157 * We allow breakpoints in NMIs. If a breakpoint occurs, then 1158 * the iretq it performs will take us out of NMI context. 1159 * This means that we can have nested NMIs where the next 1160 * NMI is using the top of the stack of the previous NMI. We 1161 * can't let it execute because the nested NMI will corrupt the 1162 * stack of the previous NMI. NMI handlers are not re-entrant 1163 * anyway. 1164 * 1165 * To handle this case we do the following: 1166 * Check the a special location on the stack that contains 1167 * a variable that is set when NMIs are executing. 1168 * The interrupted task's stack is also checked to see if it 1169 * is an NMI stack. 1170 * If the variable is not set and the stack is not the NMI 1171 * stack then: 1172 * o Set the special variable on the stack 1173 * o Copy the interrupt frame into an "outermost" location on the 1174 * stack 1175 * o Copy the interrupt frame into an "iret" location on the stack 1176 * o Continue processing the NMI 1177 * If the variable is set or the previous stack is the NMI stack: 1178 * o Modify the "iret" location to jump to the repeat_nmi 1179 * o return back to the first NMI 1180 * 1181 * Now on exit of the first NMI, we first clear the stack variable 1182 * The NMI stack will tell any nested NMIs at that point that it is 1183 * nested. Then we pop the stack normally with iret, and if there was 1184 * a nested NMI that updated the copy interrupt stack frame, a 1185 * jump will be made to the repeat_nmi code that will handle the second 1186 * NMI. 1187 * 1188 * However, espfix prevents us from directly returning to userspace 1189 * with a single IRET instruction. Similarly, IRET to user mode 1190 * can fault. We therefore handle NMIs from user space like 1191 * other IST entries. 1192 */ 1193 1194 ASM_CLAC 1195 cld 1196 1197 /* Use %rdx as our temp variable throughout */ 1198 pushq %rdx 1199 1200 testb $3, CS-RIP+8(%rsp) 1201 jz .Lnmi_from_kernel 1202 1203 /* 1204 * NMI from user mode. We need to run on the thread stack, but we 1205 * can't go through the normal entry paths: NMIs are masked, and 1206 * we don't want to enable interrupts, because then we'll end 1207 * up in an awkward situation in which IRQs are on but NMIs 1208 * are off. 1209 * 1210 * We also must not push anything to the stack before switching 1211 * stacks lest we corrupt the "NMI executing" variable. 1212 */ 1213 1214 swapgs 1215 FENCE_SWAPGS_USER_ENTRY 1216 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx 1217 movq %rsp, %rdx 1218 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rsp 1219 UNWIND_HINT_IRET_REGS base=%rdx offset=8 1220 pushq 5*8(%rdx) /* pt_regs->ss */ 1221 pushq 4*8(%rdx) /* pt_regs->rsp */ 1222 pushq 3*8(%rdx) /* pt_regs->flags */ 1223 pushq 2*8(%rdx) /* pt_regs->cs */ 1224 pushq 1*8(%rdx) /* pt_regs->rip */ 1225 UNWIND_HINT_IRET_REGS 1226 pushq $-1 /* pt_regs->orig_ax */ 1227 PUSH_AND_CLEAR_REGS rdx=(%rdx) 1228 ENCODE_FRAME_POINTER 1229 1230 IBRS_ENTER 1231 UNTRAIN_RET 1232 1233 /* 1234 * At this point we no longer need to worry about stack damage 1235 * due to nesting -- we're on the normal thread stack and we're 1236 * done with the NMI stack. 1237 */ 1238 1239 movq %rsp, %rdi 1240 movq $-1, %rsi 1241 call exc_nmi 1242 1243 /* 1244 * Return back to user mode. We must *not* do the normal exit 1245 * work, because we don't want to enable interrupts. 1246 */ 1247 jmp swapgs_restore_regs_and_return_to_usermode 1248 1249.Lnmi_from_kernel: 1250 /* 1251 * Here's what our stack frame will look like: 1252 * +---------------------------------------------------------+ 1253 * | original SS | 1254 * | original Return RSP | 1255 * | original RFLAGS | 1256 * | original CS | 1257 * | original RIP | 1258 * +---------------------------------------------------------+ 1259 * | temp storage for rdx | 1260 * +---------------------------------------------------------+ 1261 * | "NMI executing" variable | 1262 * +---------------------------------------------------------+ 1263 * | iret SS } Copied from "outermost" frame | 1264 * | iret Return RSP } on each loop iteration; overwritten | 1265 * | iret RFLAGS } by a nested NMI to force another | 1266 * | iret CS } iteration if needed. | 1267 * | iret RIP } | 1268 * +---------------------------------------------------------+ 1269 * | outermost SS } initialized in first_nmi; | 1270 * | outermost Return RSP } will not be changed before | 1271 * | outermost RFLAGS } NMI processing is done. | 1272 * | outermost CS } Copied to "iret" frame on each | 1273 * | outermost RIP } iteration. | 1274 * +---------------------------------------------------------+ 1275 * | pt_regs | 1276 * +---------------------------------------------------------+ 1277 * 1278 * The "original" frame is used by hardware. Before re-enabling 1279 * NMIs, we need to be done with it, and we need to leave enough 1280 * space for the asm code here. 1281 * 1282 * We return by executing IRET while RSP points to the "iret" frame. 1283 * That will either return for real or it will loop back into NMI 1284 * processing. 1285 * 1286 * The "outermost" frame is copied to the "iret" frame on each 1287 * iteration of the loop, so each iteration starts with the "iret" 1288 * frame pointing to the final return target. 1289 */ 1290 1291 /* 1292 * Determine whether we're a nested NMI. 1293 * 1294 * If we interrupted kernel code between repeat_nmi and 1295 * end_repeat_nmi, then we are a nested NMI. We must not 1296 * modify the "iret" frame because it's being written by 1297 * the outer NMI. That's okay; the outer NMI handler is 1298 * about to about to call exc_nmi() anyway, so we can just 1299 * resume the outer NMI. 1300 */ 1301 1302 movq $repeat_nmi, %rdx 1303 cmpq 8(%rsp), %rdx 1304 ja 1f 1305 movq $end_repeat_nmi, %rdx 1306 cmpq 8(%rsp), %rdx 1307 ja nested_nmi_out 13081: 1309 1310 /* 1311 * Now check "NMI executing". If it's set, then we're nested. 1312 * This will not detect if we interrupted an outer NMI just 1313 * before IRET. 1314 */ 1315 cmpl $1, -8(%rsp) 1316 je nested_nmi 1317 1318 /* 1319 * Now test if the previous stack was an NMI stack. This covers 1320 * the case where we interrupt an outer NMI after it clears 1321 * "NMI executing" but before IRET. We need to be careful, though: 1322 * there is one case in which RSP could point to the NMI stack 1323 * despite there being no NMI active: naughty userspace controls 1324 * RSP at the very beginning of the SYSCALL targets. We can 1325 * pull a fast one on naughty userspace, though: we program 1326 * SYSCALL to mask DF, so userspace cannot cause DF to be set 1327 * if it controls the kernel's RSP. We set DF before we clear 1328 * "NMI executing". 1329 */ 1330 lea 6*8(%rsp), %rdx 1331 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ 1332 cmpq %rdx, 4*8(%rsp) 1333 /* If the stack pointer is above the NMI stack, this is a normal NMI */ 1334 ja first_nmi 1335 1336 subq $EXCEPTION_STKSZ, %rdx 1337 cmpq %rdx, 4*8(%rsp) 1338 /* If it is below the NMI stack, it is a normal NMI */ 1339 jb first_nmi 1340 1341 /* Ah, it is within the NMI stack. */ 1342 1343 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) 1344 jz first_nmi /* RSP was user controlled. */ 1345 1346 /* This is a nested NMI. */ 1347 1348nested_nmi: 1349 /* 1350 * Modify the "iret" frame to point to repeat_nmi, forcing another 1351 * iteration of NMI handling. 1352 */ 1353 subq $8, %rsp 1354 leaq -10*8(%rsp), %rdx 1355 pushq $__KERNEL_DS 1356 pushq %rdx 1357 pushfq 1358 pushq $__KERNEL_CS 1359 pushq $repeat_nmi 1360 1361 /* Put stack back */ 1362 addq $(6*8), %rsp 1363 1364nested_nmi_out: 1365 popq %rdx 1366 1367 /* We are returning to kernel mode, so this cannot result in a fault. */ 1368 iretq 1369 1370first_nmi: 1371 /* Restore rdx. */ 1372 movq (%rsp), %rdx 1373 1374 /* Make room for "NMI executing". */ 1375 pushq $0 1376 1377 /* Leave room for the "iret" frame */ 1378 subq $(5*8), %rsp 1379 1380 /* Copy the "original" frame to the "outermost" frame */ 1381 .rept 5 1382 pushq 11*8(%rsp) 1383 .endr 1384 UNWIND_HINT_IRET_REGS 1385 1386 /* Everything up to here is safe from nested NMIs */ 1387 1388#ifdef CONFIG_DEBUG_ENTRY 1389 /* 1390 * For ease of testing, unmask NMIs right away. Disabled by 1391 * default because IRET is very expensive. 1392 */ 1393 pushq $0 /* SS */ 1394 pushq %rsp /* RSP (minus 8 because of the previous push) */ 1395 addq $8, (%rsp) /* Fix up RSP */ 1396 pushfq /* RFLAGS */ 1397 pushq $__KERNEL_CS /* CS */ 1398 pushq $1f /* RIP */ 1399 iretq /* continues at repeat_nmi below */ 1400 UNWIND_HINT_IRET_REGS 14011: 1402#endif 1403 1404repeat_nmi: 1405 ANNOTATE_NOENDBR // this code 1406 /* 1407 * If there was a nested NMI, the first NMI's iret will return 1408 * here. But NMIs are still enabled and we can take another 1409 * nested NMI. The nested NMI checks the interrupted RIP to see 1410 * if it is between repeat_nmi and end_repeat_nmi, and if so 1411 * it will just return, as we are about to repeat an NMI anyway. 1412 * This makes it safe to copy to the stack frame that a nested 1413 * NMI will update. 1414 * 1415 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if 1416 * we're repeating an NMI, gsbase has the same value that it had on 1417 * the first iteration. paranoid_entry will load the kernel 1418 * gsbase if needed before we call exc_nmi(). "NMI executing" 1419 * is zero. 1420 */ 1421 movq $1, 10*8(%rsp) /* Set "NMI executing". */ 1422 1423 /* 1424 * Copy the "outermost" frame to the "iret" frame. NMIs that nest 1425 * here must not modify the "iret" frame while we're writing to 1426 * it or it will end up containing garbage. 1427 */ 1428 addq $(10*8), %rsp 1429 .rept 5 1430 pushq -6*8(%rsp) 1431 .endr 1432 subq $(5*8), %rsp 1433end_repeat_nmi: 1434 ANNOTATE_NOENDBR // this code 1435 1436 /* 1437 * Everything below this point can be preempted by a nested NMI. 1438 * If this happens, then the inner NMI will change the "iret" 1439 * frame to point back to repeat_nmi. 1440 */ 1441 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1442 1443 /* 1444 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit 1445 * as we should not be calling schedule in NMI context. 1446 * Even with normal interrupts enabled. An NMI should not be 1447 * setting NEED_RESCHED or anything that normal interrupts and 1448 * exceptions might do. 1449 */ 1450 call paranoid_entry 1451 UNWIND_HINT_REGS 1452 1453 movq %rsp, %rdi 1454 movq $-1, %rsi 1455 call exc_nmi 1456 1457 /* Always restore stashed SPEC_CTRL value (see paranoid_entry) */ 1458 IBRS_EXIT save_reg=%r15 1459 1460 /* Always restore stashed CR3 value (see paranoid_entry) */ 1461 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 1462 1463 /* 1464 * The above invocation of paranoid_entry stored the GSBASE 1465 * related information in R/EBX depending on the availability 1466 * of FSGSBASE. 1467 * 1468 * If FSGSBASE is enabled, restore the saved GSBASE value 1469 * unconditionally, otherwise take the conditional SWAPGS path. 1470 */ 1471 ALTERNATIVE "jmp nmi_no_fsgsbase", "", X86_FEATURE_FSGSBASE 1472 1473 wrgsbase %rbx 1474 jmp nmi_restore 1475 1476nmi_no_fsgsbase: 1477 /* EBX == 0 -> invoke SWAPGS */ 1478 testl %ebx, %ebx 1479 jnz nmi_restore 1480 1481nmi_swapgs: 1482 swapgs 1483 1484nmi_restore: 1485 POP_REGS 1486 1487 /* 1488 * Skip orig_ax and the "outermost" frame to point RSP at the "iret" 1489 * at the "iret" frame. 1490 */ 1491 addq $6*8, %rsp 1492 1493 /* 1494 * Clear "NMI executing". Set DF first so that we can easily 1495 * distinguish the remaining code between here and IRET from 1496 * the SYSCALL entry and exit paths. 1497 * 1498 * We arguably should just inspect RIP instead, but I (Andy) wrote 1499 * this code when I had the misapprehension that Xen PV supported 1500 * NMIs, and Xen PV would break that approach. 1501 */ 1502 std 1503 movq $0, 5*8(%rsp) /* clear "NMI executing" */ 1504 1505 /* 1506 * iretq reads the "iret" frame and exits the NMI stack in a 1507 * single instruction. We are returning to kernel mode, so this 1508 * cannot result in a fault. Similarly, we don't need to worry 1509 * about espfix64 on the way back to kernel mode. 1510 */ 1511 iretq 1512SYM_CODE_END(asm_exc_nmi) 1513 1514#ifndef CONFIG_IA32_EMULATION 1515/* 1516 * This handles SYSCALL from 32-bit code. There is no way to program 1517 * MSRs to fully disable 32-bit SYSCALL. 1518 */ 1519SYM_CODE_START(ignore_sysret) 1520 UNWIND_HINT_END_OF_STACK 1521 ENDBR 1522 mov $-ENOSYS, %eax 1523 sysretl 1524SYM_CODE_END(ignore_sysret) 1525#endif 1526 1527.pushsection .text, "ax" 1528 __FUNC_ALIGN 1529SYM_CODE_START_NOALIGN(rewind_stack_and_make_dead) 1530 UNWIND_HINT_FUNC 1531 /* Prevent any naive code from trying to unwind to our caller. */ 1532 xorl %ebp, %ebp 1533 1534 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rax 1535 leaq -PTREGS_SIZE(%rax), %rsp 1536 UNWIND_HINT_REGS 1537 1538 call make_task_dead 1539SYM_CODE_END(rewind_stack_and_make_dead) 1540.popsection 1541