xref: /linux/arch/x86/entry/entry_64.S (revision c88fb897c1fb5a590dc6353ac4b01c8f46a347b3)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 *  linux/arch/x86_64/entry.S
4 *
5 *  Copyright (C) 1991, 1992  Linus Torvalds
6 *  Copyright (C) 2000, 2001, 2002  Andi Kleen SuSE Labs
7 *  Copyright (C) 2000  Pavel Machek <pavel@suse.cz>
8 *
9 * entry.S contains the system-call and fault low-level handling routines.
10 *
11 * Some of this is documented in Documentation/x86/entry_64.rst
12 *
13 * A note on terminology:
14 * - iret frame:	Architecture defined interrupt frame from SS to RIP
15 *			at the top of the kernel process stack.
16 *
17 * Some macro usage:
18 * - SYM_FUNC_START/END:Define functions in the symbol table.
19 * - idtentry:		Define exception entry points.
20 */
21#include <linux/linkage.h>
22#include <asm/segment.h>
23#include <asm/cache.h>
24#include <asm/errno.h>
25#include <asm/asm-offsets.h>
26#include <asm/msr.h>
27#include <asm/unistd.h>
28#include <asm/thread_info.h>
29#include <asm/hw_irq.h>
30#include <asm/page_types.h>
31#include <asm/irqflags.h>
32#include <asm/paravirt.h>
33#include <asm/percpu.h>
34#include <asm/asm.h>
35#include <asm/smap.h>
36#include <asm/pgtable_types.h>
37#include <asm/export.h>
38#include <asm/frame.h>
39#include <asm/trapnr.h>
40#include <asm/nospec-branch.h>
41#include <asm/fsgsbase.h>
42#include <linux/err.h>
43
44#include "calling.h"
45
46.code64
47.section .entry.text, "ax"
48
49/*
50 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
51 *
52 * This is the only entry point used for 64-bit system calls.  The
53 * hardware interface is reasonably well designed and the register to
54 * argument mapping Linux uses fits well with the registers that are
55 * available when SYSCALL is used.
56 *
57 * SYSCALL instructions can be found inlined in libc implementations as
58 * well as some other programs and libraries.  There are also a handful
59 * of SYSCALL instructions in the vDSO used, for example, as a
60 * clock_gettimeofday fallback.
61 *
62 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
63 * then loads new ss, cs, and rip from previously programmed MSRs.
64 * rflags gets masked by a value from another MSR (so CLD and CLAC
65 * are not needed). SYSCALL does not save anything on the stack
66 * and does not change rsp.
67 *
68 * Registers on entry:
69 * rax  system call number
70 * rcx  return address
71 * r11  saved rflags (note: r11 is callee-clobbered register in C ABI)
72 * rdi  arg0
73 * rsi  arg1
74 * rdx  arg2
75 * r10  arg3 (needs to be moved to rcx to conform to C ABI)
76 * r8   arg4
77 * r9   arg5
78 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
79 *
80 * Only called from user space.
81 *
82 * When user can change pt_regs->foo always force IRET. That is because
83 * it deals with uncanonical addresses better. SYSRET has trouble
84 * with them due to bugs in both AMD and Intel CPUs.
85 */
86
87SYM_CODE_START(entry_SYSCALL_64)
88	UNWIND_HINT_EMPTY
89
90	swapgs
91	/* tss.sp2 is scratch space. */
92	movq	%rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2)
93	SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
94	movq	PER_CPU_VAR(cpu_current_top_of_stack), %rsp
95
96SYM_INNER_LABEL(entry_SYSCALL_64_safe_stack, SYM_L_GLOBAL)
97
98	/* Construct struct pt_regs on stack */
99	pushq	$__USER_DS				/* pt_regs->ss */
100	pushq	PER_CPU_VAR(cpu_tss_rw + TSS_sp2)	/* pt_regs->sp */
101	pushq	%r11					/* pt_regs->flags */
102	pushq	$__USER_CS				/* pt_regs->cs */
103	pushq	%rcx					/* pt_regs->ip */
104SYM_INNER_LABEL(entry_SYSCALL_64_after_hwframe, SYM_L_GLOBAL)
105	pushq	%rax					/* pt_regs->orig_ax */
106
107	PUSH_AND_CLEAR_REGS rax=$-ENOSYS
108
109	/* IRQs are off. */
110	movq	%rax, %rdi
111	movq	%rsp, %rsi
112	call	do_syscall_64		/* returns with IRQs disabled */
113
114	/*
115	 * Try to use SYSRET instead of IRET if we're returning to
116	 * a completely clean 64-bit userspace context.  If we're not,
117	 * go to the slow exit path.
118	 * In the Xen PV case we must use iret anyway.
119	 */
120
121	ALTERNATIVE "", "jmp	swapgs_restore_regs_and_return_to_usermode", \
122		X86_FEATURE_XENPV
123
124	movq	RCX(%rsp), %rcx
125	movq	RIP(%rsp), %r11
126
127	cmpq	%rcx, %r11	/* SYSRET requires RCX == RIP */
128	jne	swapgs_restore_regs_and_return_to_usermode
129
130	/*
131	 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
132	 * in kernel space.  This essentially lets the user take over
133	 * the kernel, since userspace controls RSP.
134	 *
135	 * If width of "canonical tail" ever becomes variable, this will need
136	 * to be updated to remain correct on both old and new CPUs.
137	 *
138	 * Change top bits to match most significant bit (47th or 56th bit
139	 * depending on paging mode) in the address.
140	 */
141#ifdef CONFIG_X86_5LEVEL
142	ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \
143		"shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57
144#else
145	shl	$(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
146	sar	$(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
147#endif
148
149	/* If this changed %rcx, it was not canonical */
150	cmpq	%rcx, %r11
151	jne	swapgs_restore_regs_and_return_to_usermode
152
153	cmpq	$__USER_CS, CS(%rsp)		/* CS must match SYSRET */
154	jne	swapgs_restore_regs_and_return_to_usermode
155
156	movq	R11(%rsp), %r11
157	cmpq	%r11, EFLAGS(%rsp)		/* R11 == RFLAGS */
158	jne	swapgs_restore_regs_and_return_to_usermode
159
160	/*
161	 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
162	 * restore RF properly. If the slowpath sets it for whatever reason, we
163	 * need to restore it correctly.
164	 *
165	 * SYSRET can restore TF, but unlike IRET, restoring TF results in a
166	 * trap from userspace immediately after SYSRET.  This would cause an
167	 * infinite loop whenever #DB happens with register state that satisfies
168	 * the opportunistic SYSRET conditions.  For example, single-stepping
169	 * this user code:
170	 *
171	 *           movq	$stuck_here, %rcx
172	 *           pushfq
173	 *           popq %r11
174	 *   stuck_here:
175	 *
176	 * would never get past 'stuck_here'.
177	 */
178	testq	$(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
179	jnz	swapgs_restore_regs_and_return_to_usermode
180
181	/* nothing to check for RSP */
182
183	cmpq	$__USER_DS, SS(%rsp)		/* SS must match SYSRET */
184	jne	swapgs_restore_regs_and_return_to_usermode
185
186	/*
187	 * We win! This label is here just for ease of understanding
188	 * perf profiles. Nothing jumps here.
189	 */
190syscall_return_via_sysret:
191	/* rcx and r11 are already restored (see code above) */
192	POP_REGS pop_rdi=0 skip_r11rcx=1
193
194	/*
195	 * Now all regs are restored except RSP and RDI.
196	 * Save old stack pointer and switch to trampoline stack.
197	 */
198	movq	%rsp, %rdi
199	movq	PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
200	UNWIND_HINT_EMPTY
201
202	pushq	RSP-RDI(%rdi)	/* RSP */
203	pushq	(%rdi)		/* RDI */
204
205	/*
206	 * We are on the trampoline stack.  All regs except RDI are live.
207	 * We can do future final exit work right here.
208	 */
209	STACKLEAK_ERASE_NOCLOBBER
210
211	SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
212
213	popq	%rdi
214	popq	%rsp
215	swapgs
216	sysretq
217SYM_CODE_END(entry_SYSCALL_64)
218
219/*
220 * %rdi: prev task
221 * %rsi: next task
222 */
223.pushsection .text, "ax"
224SYM_FUNC_START(__switch_to_asm)
225	/*
226	 * Save callee-saved registers
227	 * This must match the order in inactive_task_frame
228	 */
229	pushq	%rbp
230	pushq	%rbx
231	pushq	%r12
232	pushq	%r13
233	pushq	%r14
234	pushq	%r15
235
236	/* switch stack */
237	movq	%rsp, TASK_threadsp(%rdi)
238	movq	TASK_threadsp(%rsi), %rsp
239
240#ifdef CONFIG_STACKPROTECTOR
241	movq	TASK_stack_canary(%rsi), %rbx
242	movq	%rbx, PER_CPU_VAR(fixed_percpu_data) + stack_canary_offset
243#endif
244
245#ifdef CONFIG_RETPOLINE
246	/*
247	 * When switching from a shallower to a deeper call stack
248	 * the RSB may either underflow or use entries populated
249	 * with userspace addresses. On CPUs where those concerns
250	 * exist, overwrite the RSB with entries which capture
251	 * speculative execution to prevent attack.
252	 */
253	FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
254#endif
255
256	/* restore callee-saved registers */
257	popq	%r15
258	popq	%r14
259	popq	%r13
260	popq	%r12
261	popq	%rbx
262	popq	%rbp
263
264	jmp	__switch_to
265SYM_FUNC_END(__switch_to_asm)
266.popsection
267
268/*
269 * A newly forked process directly context switches into this address.
270 *
271 * rax: prev task we switched from
272 * rbx: kernel thread func (NULL for user thread)
273 * r12: kernel thread arg
274 */
275.pushsection .text, "ax"
276SYM_CODE_START(ret_from_fork)
277	UNWIND_HINT_EMPTY
278	movq	%rax, %rdi
279	call	schedule_tail			/* rdi: 'prev' task parameter */
280
281	testq	%rbx, %rbx			/* from kernel_thread? */
282	jnz	1f				/* kernel threads are uncommon */
283
2842:
285	UNWIND_HINT_REGS
286	movq	%rsp, %rdi
287	call	syscall_exit_to_user_mode	/* returns with IRQs disabled */
288	jmp	swapgs_restore_regs_and_return_to_usermode
289
2901:
291	/* kernel thread */
292	UNWIND_HINT_EMPTY
293	movq	%r12, %rdi
294	CALL_NOSPEC rbx
295	/*
296	 * A kernel thread is allowed to return here after successfully
297	 * calling kernel_execve().  Exit to userspace to complete the execve()
298	 * syscall.
299	 */
300	movq	$0, RAX(%rsp)
301	jmp	2b
302SYM_CODE_END(ret_from_fork)
303.popsection
304
305.macro DEBUG_ENTRY_ASSERT_IRQS_OFF
306#ifdef CONFIG_DEBUG_ENTRY
307	pushq %rax
308	SAVE_FLAGS(CLBR_RAX)
309	testl $X86_EFLAGS_IF, %eax
310	jz .Lokay_\@
311	ud2
312.Lokay_\@:
313	popq %rax
314#endif
315.endm
316
317/**
318 * idtentry_body - Macro to emit code calling the C function
319 * @cfunc:		C function to be called
320 * @has_error_code:	Hardware pushed error code on stack
321 */
322.macro idtentry_body cfunc has_error_code:req
323
324	call	error_entry
325	UNWIND_HINT_REGS
326
327	movq	%rsp, %rdi			/* pt_regs pointer into 1st argument*/
328
329	.if \has_error_code == 1
330		movq	ORIG_RAX(%rsp), %rsi	/* get error code into 2nd argument*/
331		movq	$-1, ORIG_RAX(%rsp)	/* no syscall to restart */
332	.endif
333
334	call	\cfunc
335
336	jmp	error_return
337.endm
338
339/**
340 * idtentry - Macro to generate entry stubs for simple IDT entries
341 * @vector:		Vector number
342 * @asmsym:		ASM symbol for the entry point
343 * @cfunc:		C function to be called
344 * @has_error_code:	Hardware pushed error code on stack
345 *
346 * The macro emits code to set up the kernel context for straight forward
347 * and simple IDT entries. No IST stack, no paranoid entry checks.
348 */
349.macro idtentry vector asmsym cfunc has_error_code:req
350SYM_CODE_START(\asmsym)
351	UNWIND_HINT_IRET_REGS offset=\has_error_code*8
352	ASM_CLAC
353
354	.if \has_error_code == 0
355		pushq	$-1			/* ORIG_RAX: no syscall to restart */
356	.endif
357
358	.if \vector == X86_TRAP_BP
359		/*
360		 * If coming from kernel space, create a 6-word gap to allow the
361		 * int3 handler to emulate a call instruction.
362		 */
363		testb	$3, CS-ORIG_RAX(%rsp)
364		jnz	.Lfrom_usermode_no_gap_\@
365		.rept	6
366		pushq	5*8(%rsp)
367		.endr
368		UNWIND_HINT_IRET_REGS offset=8
369.Lfrom_usermode_no_gap_\@:
370	.endif
371
372	idtentry_body \cfunc \has_error_code
373
374_ASM_NOKPROBE(\asmsym)
375SYM_CODE_END(\asmsym)
376.endm
377
378/*
379 * Interrupt entry/exit.
380 *
381 + The interrupt stubs push (vector) onto the stack, which is the error_code
382 * position of idtentry exceptions, and jump to one of the two idtentry points
383 * (common/spurious).
384 *
385 * common_interrupt is a hotpath, align it to a cache line
386 */
387.macro idtentry_irq vector cfunc
388	.p2align CONFIG_X86_L1_CACHE_SHIFT
389	idtentry \vector asm_\cfunc \cfunc has_error_code=1
390.endm
391
392/*
393 * System vectors which invoke their handlers directly and are not
394 * going through the regular common device interrupt handling code.
395 */
396.macro idtentry_sysvec vector cfunc
397	idtentry \vector asm_\cfunc \cfunc has_error_code=0
398.endm
399
400/**
401 * idtentry_mce_db - Macro to generate entry stubs for #MC and #DB
402 * @vector:		Vector number
403 * @asmsym:		ASM symbol for the entry point
404 * @cfunc:		C function to be called
405 *
406 * The macro emits code to set up the kernel context for #MC and #DB
407 *
408 * If the entry comes from user space it uses the normal entry path
409 * including the return to user space work and preemption checks on
410 * exit.
411 *
412 * If hits in kernel mode then it needs to go through the paranoid
413 * entry as the exception can hit any random state. No preemption
414 * check on exit to keep the paranoid path simple.
415 */
416.macro idtentry_mce_db vector asmsym cfunc
417SYM_CODE_START(\asmsym)
418	UNWIND_HINT_IRET_REGS
419	ASM_CLAC
420
421	pushq	$-1			/* ORIG_RAX: no syscall to restart */
422
423	/*
424	 * If the entry is from userspace, switch stacks and treat it as
425	 * a normal entry.
426	 */
427	testb	$3, CS-ORIG_RAX(%rsp)
428	jnz	.Lfrom_usermode_switch_stack_\@
429
430	/* paranoid_entry returns GS information for paranoid_exit in EBX. */
431	call	paranoid_entry
432
433	UNWIND_HINT_REGS
434
435	movq	%rsp, %rdi		/* pt_regs pointer */
436
437	call	\cfunc
438
439	jmp	paranoid_exit
440
441	/* Switch to the regular task stack and use the noist entry point */
442.Lfrom_usermode_switch_stack_\@:
443	idtentry_body noist_\cfunc, has_error_code=0
444
445_ASM_NOKPROBE(\asmsym)
446SYM_CODE_END(\asmsym)
447.endm
448
449#ifdef CONFIG_AMD_MEM_ENCRYPT
450/**
451 * idtentry_vc - Macro to generate entry stub for #VC
452 * @vector:		Vector number
453 * @asmsym:		ASM symbol for the entry point
454 * @cfunc:		C function to be called
455 *
456 * The macro emits code to set up the kernel context for #VC. The #VC handler
457 * runs on an IST stack and needs to be able to cause nested #VC exceptions.
458 *
459 * To make this work the #VC entry code tries its best to pretend it doesn't use
460 * an IST stack by switching to the task stack if coming from user-space (which
461 * includes early SYSCALL entry path) or back to the stack in the IRET frame if
462 * entered from kernel-mode.
463 *
464 * If entered from kernel-mode the return stack is validated first, and if it is
465 * not safe to use (e.g. because it points to the entry stack) the #VC handler
466 * will switch to a fall-back stack (VC2) and call a special handler function.
467 *
468 * The macro is only used for one vector, but it is planned to be extended in
469 * the future for the #HV exception.
470 */
471.macro idtentry_vc vector asmsym cfunc
472SYM_CODE_START(\asmsym)
473	UNWIND_HINT_IRET_REGS
474	ASM_CLAC
475
476	/*
477	 * If the entry is from userspace, switch stacks and treat it as
478	 * a normal entry.
479	 */
480	testb	$3, CS-ORIG_RAX(%rsp)
481	jnz	.Lfrom_usermode_switch_stack_\@
482
483	/*
484	 * paranoid_entry returns SWAPGS flag for paranoid_exit in EBX.
485	 * EBX == 0 -> SWAPGS, EBX == 1 -> no SWAPGS
486	 */
487	call	paranoid_entry
488
489	UNWIND_HINT_REGS
490
491	/*
492	 * Switch off the IST stack to make it free for nested exceptions. The
493	 * vc_switch_off_ist() function will switch back to the interrupted
494	 * stack if it is safe to do so. If not it switches to the VC fall-back
495	 * stack.
496	 */
497	movq	%rsp, %rdi		/* pt_regs pointer */
498	call	vc_switch_off_ist
499	movq	%rax, %rsp		/* Switch to new stack */
500
501	UNWIND_HINT_REGS
502
503	/* Update pt_regs */
504	movq	ORIG_RAX(%rsp), %rsi	/* get error code into 2nd argument*/
505	movq	$-1, ORIG_RAX(%rsp)	/* no syscall to restart */
506
507	movq	%rsp, %rdi		/* pt_regs pointer */
508
509	call	\cfunc
510
511	/*
512	 * No need to switch back to the IST stack. The current stack is either
513	 * identical to the stack in the IRET frame or the VC fall-back stack,
514	 * so it is definitly mapped even with PTI enabled.
515	 */
516	jmp	paranoid_exit
517
518	/* Switch to the regular task stack */
519.Lfrom_usermode_switch_stack_\@:
520	idtentry_body safe_stack_\cfunc, has_error_code=1
521
522_ASM_NOKPROBE(\asmsym)
523SYM_CODE_END(\asmsym)
524.endm
525#endif
526
527/*
528 * Double fault entry. Straight paranoid. No checks from which context
529 * this comes because for the espfix induced #DF this would do the wrong
530 * thing.
531 */
532.macro idtentry_df vector asmsym cfunc
533SYM_CODE_START(\asmsym)
534	UNWIND_HINT_IRET_REGS offset=8
535	ASM_CLAC
536
537	/* paranoid_entry returns GS information for paranoid_exit in EBX. */
538	call	paranoid_entry
539	UNWIND_HINT_REGS
540
541	movq	%rsp, %rdi		/* pt_regs pointer into first argument */
542	movq	ORIG_RAX(%rsp), %rsi	/* get error code into 2nd argument*/
543	movq	$-1, ORIG_RAX(%rsp)	/* no syscall to restart */
544	call	\cfunc
545
546	jmp	paranoid_exit
547
548_ASM_NOKPROBE(\asmsym)
549SYM_CODE_END(\asmsym)
550.endm
551
552/*
553 * Include the defines which emit the idt entries which are shared
554 * shared between 32 and 64 bit and emit the __irqentry_text_* markers
555 * so the stacktrace boundary checks work.
556 */
557	.align 16
558	.globl __irqentry_text_start
559__irqentry_text_start:
560
561#include <asm/idtentry.h>
562
563	.align 16
564	.globl __irqentry_text_end
565__irqentry_text_end:
566
567SYM_CODE_START_LOCAL(common_interrupt_return)
568SYM_INNER_LABEL(swapgs_restore_regs_and_return_to_usermode, SYM_L_GLOBAL)
569#ifdef CONFIG_DEBUG_ENTRY
570	/* Assert that pt_regs indicates user mode. */
571	testb	$3, CS(%rsp)
572	jnz	1f
573	ud2
5741:
575#endif
576	POP_REGS pop_rdi=0
577
578	/*
579	 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS.
580	 * Save old stack pointer and switch to trampoline stack.
581	 */
582	movq	%rsp, %rdi
583	movq	PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
584	UNWIND_HINT_EMPTY
585
586	/* Copy the IRET frame to the trampoline stack. */
587	pushq	6*8(%rdi)	/* SS */
588	pushq	5*8(%rdi)	/* RSP */
589	pushq	4*8(%rdi)	/* EFLAGS */
590	pushq	3*8(%rdi)	/* CS */
591	pushq	2*8(%rdi)	/* RIP */
592
593	/* Push user RDI on the trampoline stack. */
594	pushq	(%rdi)
595
596	/*
597	 * We are on the trampoline stack.  All regs except RDI are live.
598	 * We can do future final exit work right here.
599	 */
600	STACKLEAK_ERASE_NOCLOBBER
601
602	SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
603
604	/* Restore RDI. */
605	popq	%rdi
606	SWAPGS
607	INTERRUPT_RETURN
608
609
610SYM_INNER_LABEL(restore_regs_and_return_to_kernel, SYM_L_GLOBAL)
611#ifdef CONFIG_DEBUG_ENTRY
612	/* Assert that pt_regs indicates kernel mode. */
613	testb	$3, CS(%rsp)
614	jz	1f
615	ud2
6161:
617#endif
618	POP_REGS
619	addq	$8, %rsp	/* skip regs->orig_ax */
620	/*
621	 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
622	 * when returning from IPI handler.
623	 */
624	INTERRUPT_RETURN
625
626SYM_INNER_LABEL_ALIGN(native_iret, SYM_L_GLOBAL)
627	UNWIND_HINT_IRET_REGS
628	/*
629	 * Are we returning to a stack segment from the LDT?  Note: in
630	 * 64-bit mode SS:RSP on the exception stack is always valid.
631	 */
632#ifdef CONFIG_X86_ESPFIX64
633	testb	$4, (SS-RIP)(%rsp)
634	jnz	native_irq_return_ldt
635#endif
636
637SYM_INNER_LABEL(native_irq_return_iret, SYM_L_GLOBAL)
638	/*
639	 * This may fault.  Non-paranoid faults on return to userspace are
640	 * handled by fixup_bad_iret.  These include #SS, #GP, and #NP.
641	 * Double-faults due to espfix64 are handled in exc_double_fault.
642	 * Other faults here are fatal.
643	 */
644	iretq
645
646#ifdef CONFIG_X86_ESPFIX64
647native_irq_return_ldt:
648	/*
649	 * We are running with user GSBASE.  All GPRs contain their user
650	 * values.  We have a percpu ESPFIX stack that is eight slots
651	 * long (see ESPFIX_STACK_SIZE).  espfix_waddr points to the bottom
652	 * of the ESPFIX stack.
653	 *
654	 * We clobber RAX and RDI in this code.  We stash RDI on the
655	 * normal stack and RAX on the ESPFIX stack.
656	 *
657	 * The ESPFIX stack layout we set up looks like this:
658	 *
659	 * --- top of ESPFIX stack ---
660	 * SS
661	 * RSP
662	 * RFLAGS
663	 * CS
664	 * RIP  <-- RSP points here when we're done
665	 * RAX  <-- espfix_waddr points here
666	 * --- bottom of ESPFIX stack ---
667	 */
668
669	pushq	%rdi				/* Stash user RDI */
670	swapgs					/* to kernel GS */
671	SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi	/* to kernel CR3 */
672
673	movq	PER_CPU_VAR(espfix_waddr), %rdi
674	movq	%rax, (0*8)(%rdi)		/* user RAX */
675	movq	(1*8)(%rsp), %rax		/* user RIP */
676	movq	%rax, (1*8)(%rdi)
677	movq	(2*8)(%rsp), %rax		/* user CS */
678	movq	%rax, (2*8)(%rdi)
679	movq	(3*8)(%rsp), %rax		/* user RFLAGS */
680	movq	%rax, (3*8)(%rdi)
681	movq	(5*8)(%rsp), %rax		/* user SS */
682	movq	%rax, (5*8)(%rdi)
683	movq	(4*8)(%rsp), %rax		/* user RSP */
684	movq	%rax, (4*8)(%rdi)
685	/* Now RAX == RSP. */
686
687	andl	$0xffff0000, %eax		/* RAX = (RSP & 0xffff0000) */
688
689	/*
690	 * espfix_stack[31:16] == 0.  The page tables are set up such that
691	 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
692	 * espfix_waddr for any X.  That is, there are 65536 RO aliases of
693	 * the same page.  Set up RSP so that RSP[31:16] contains the
694	 * respective 16 bits of the /userspace/ RSP and RSP nonetheless
695	 * still points to an RO alias of the ESPFIX stack.
696	 */
697	orq	PER_CPU_VAR(espfix_stack), %rax
698
699	SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
700	swapgs					/* to user GS */
701	popq	%rdi				/* Restore user RDI */
702
703	movq	%rax, %rsp
704	UNWIND_HINT_IRET_REGS offset=8
705
706	/*
707	 * At this point, we cannot write to the stack any more, but we can
708	 * still read.
709	 */
710	popq	%rax				/* Restore user RAX */
711
712	/*
713	 * RSP now points to an ordinary IRET frame, except that the page
714	 * is read-only and RSP[31:16] are preloaded with the userspace
715	 * values.  We can now IRET back to userspace.
716	 */
717	jmp	native_irq_return_iret
718#endif
719SYM_CODE_END(common_interrupt_return)
720_ASM_NOKPROBE(common_interrupt_return)
721
722/*
723 * Reload gs selector with exception handling
724 * edi:  new selector
725 *
726 * Is in entry.text as it shouldn't be instrumented.
727 */
728SYM_FUNC_START(asm_load_gs_index)
729	FRAME_BEGIN
730	swapgs
731.Lgs_change:
732	movl	%edi, %gs
7332:	ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
734	swapgs
735	FRAME_END
736	ret
737SYM_FUNC_END(asm_load_gs_index)
738EXPORT_SYMBOL(asm_load_gs_index)
739
740	_ASM_EXTABLE(.Lgs_change, .Lbad_gs)
741	.section .fixup, "ax"
742	/* running with kernelgs */
743SYM_CODE_START_LOCAL_NOALIGN(.Lbad_gs)
744	swapgs					/* switch back to user gs */
745.macro ZAP_GS
746	/* This can't be a string because the preprocessor needs to see it. */
747	movl $__USER_DS, %eax
748	movl %eax, %gs
749.endm
750	ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
751	xorl	%eax, %eax
752	movl	%eax, %gs
753	jmp	2b
754SYM_CODE_END(.Lbad_gs)
755	.previous
756
757/*
758 * rdi: New stack pointer points to the top word of the stack
759 * rsi: Function pointer
760 * rdx: Function argument (can be NULL if none)
761 */
762SYM_FUNC_START(asm_call_on_stack)
763SYM_INNER_LABEL(asm_call_sysvec_on_stack, SYM_L_GLOBAL)
764SYM_INNER_LABEL(asm_call_irq_on_stack, SYM_L_GLOBAL)
765	/*
766	 * Save the frame pointer unconditionally. This allows the ORC
767	 * unwinder to handle the stack switch.
768	 */
769	pushq		%rbp
770	mov		%rsp, %rbp
771
772	/*
773	 * The unwinder relies on the word at the top of the new stack
774	 * page linking back to the previous RSP.
775	 */
776	mov		%rsp, (%rdi)
777	mov		%rdi, %rsp
778	/* Move the argument to the right place */
779	mov		%rdx, %rdi
780
7811:
782	.pushsection .discard.instr_begin
783	.long 1b - .
784	.popsection
785
786	CALL_NOSPEC	rsi
787
7882:
789	.pushsection .discard.instr_end
790	.long 2b - .
791	.popsection
792
793	/* Restore the previous stack pointer from RBP. */
794	leaveq
795	ret
796SYM_FUNC_END(asm_call_on_stack)
797
798#ifdef CONFIG_XEN_PV
799/*
800 * A note on the "critical region" in our callback handler.
801 * We want to avoid stacking callback handlers due to events occurring
802 * during handling of the last event. To do this, we keep events disabled
803 * until we've done all processing. HOWEVER, we must enable events before
804 * popping the stack frame (can't be done atomically) and so it would still
805 * be possible to get enough handler activations to overflow the stack.
806 * Although unlikely, bugs of that kind are hard to track down, so we'd
807 * like to avoid the possibility.
808 * So, on entry to the handler we detect whether we interrupted an
809 * existing activation in its critical region -- if so, we pop the current
810 * activation and restart the handler using the previous one.
811 *
812 * C calling convention: exc_xen_hypervisor_callback(struct *pt_regs)
813 */
814SYM_CODE_START_LOCAL(exc_xen_hypervisor_callback)
815
816/*
817 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
818 * see the correct pointer to the pt_regs
819 */
820	UNWIND_HINT_FUNC
821	movq	%rdi, %rsp			/* we don't return, adjust the stack frame */
822	UNWIND_HINT_REGS
823
824	call	xen_pv_evtchn_do_upcall
825
826	jmp	error_return
827SYM_CODE_END(exc_xen_hypervisor_callback)
828
829/*
830 * Hypervisor uses this for application faults while it executes.
831 * We get here for two reasons:
832 *  1. Fault while reloading DS, ES, FS or GS
833 *  2. Fault while executing IRET
834 * Category 1 we do not need to fix up as Xen has already reloaded all segment
835 * registers that could be reloaded and zeroed the others.
836 * Category 2 we fix up by killing the current process. We cannot use the
837 * normal Linux return path in this case because if we use the IRET hypercall
838 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
839 * We distinguish between categories by comparing each saved segment register
840 * with its current contents: any discrepancy means we in category 1.
841 */
842SYM_CODE_START(xen_failsafe_callback)
843	UNWIND_HINT_EMPTY
844	movl	%ds, %ecx
845	cmpw	%cx, 0x10(%rsp)
846	jne	1f
847	movl	%es, %ecx
848	cmpw	%cx, 0x18(%rsp)
849	jne	1f
850	movl	%fs, %ecx
851	cmpw	%cx, 0x20(%rsp)
852	jne	1f
853	movl	%gs, %ecx
854	cmpw	%cx, 0x28(%rsp)
855	jne	1f
856	/* All segments match their saved values => Category 2 (Bad IRET). */
857	movq	(%rsp), %rcx
858	movq	8(%rsp), %r11
859	addq	$0x30, %rsp
860	pushq	$0				/* RIP */
861	UNWIND_HINT_IRET_REGS offset=8
862	jmp	asm_exc_general_protection
8631:	/* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
864	movq	(%rsp), %rcx
865	movq	8(%rsp), %r11
866	addq	$0x30, %rsp
867	UNWIND_HINT_IRET_REGS
868	pushq	$-1 /* orig_ax = -1 => not a system call */
869	PUSH_AND_CLEAR_REGS
870	ENCODE_FRAME_POINTER
871	jmp	error_return
872SYM_CODE_END(xen_failsafe_callback)
873#endif /* CONFIG_XEN_PV */
874
875/*
876 * Save all registers in pt_regs. Return GSBASE related information
877 * in EBX depending on the availability of the FSGSBASE instructions:
878 *
879 * FSGSBASE	R/EBX
880 *     N        0 -> SWAPGS on exit
881 *              1 -> no SWAPGS on exit
882 *
883 *     Y        GSBASE value at entry, must be restored in paranoid_exit
884 */
885SYM_CODE_START_LOCAL(paranoid_entry)
886	UNWIND_HINT_FUNC
887	cld
888	PUSH_AND_CLEAR_REGS save_ret=1
889	ENCODE_FRAME_POINTER 8
890
891	/*
892	 * Always stash CR3 in %r14.  This value will be restored,
893	 * verbatim, at exit.  Needed if paranoid_entry interrupted
894	 * another entry that already switched to the user CR3 value
895	 * but has not yet returned to userspace.
896	 *
897	 * This is also why CS (stashed in the "iret frame" by the
898	 * hardware at entry) can not be used: this may be a return
899	 * to kernel code, but with a user CR3 value.
900	 *
901	 * Switching CR3 does not depend on kernel GSBASE so it can
902	 * be done before switching to the kernel GSBASE. This is
903	 * required for FSGSBASE because the kernel GSBASE has to
904	 * be retrieved from a kernel internal table.
905	 */
906	SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
907
908	/*
909	 * Handling GSBASE depends on the availability of FSGSBASE.
910	 *
911	 * Without FSGSBASE the kernel enforces that negative GSBASE
912	 * values indicate kernel GSBASE. With FSGSBASE no assumptions
913	 * can be made about the GSBASE value when entering from user
914	 * space.
915	 */
916	ALTERNATIVE "jmp .Lparanoid_entry_checkgs", "", X86_FEATURE_FSGSBASE
917
918	/*
919	 * Read the current GSBASE and store it in %rbx unconditionally,
920	 * retrieve and set the current CPUs kernel GSBASE. The stored value
921	 * has to be restored in paranoid_exit unconditionally.
922	 *
923	 * The unconditional write to GS base below ensures that no subsequent
924	 * loads based on a mispredicted GS base can happen, therefore no LFENCE
925	 * is needed here.
926	 */
927	SAVE_AND_SET_GSBASE scratch_reg=%rax save_reg=%rbx
928	ret
929
930.Lparanoid_entry_checkgs:
931	/* EBX = 1 -> kernel GSBASE active, no restore required */
932	movl	$1, %ebx
933	/*
934	 * The kernel-enforced convention is a negative GSBASE indicates
935	 * a kernel value. No SWAPGS needed on entry and exit.
936	 */
937	movl	$MSR_GS_BASE, %ecx
938	rdmsr
939	testl	%edx, %edx
940	jns	.Lparanoid_entry_swapgs
941	ret
942
943.Lparanoid_entry_swapgs:
944	swapgs
945
946	/*
947	 * The above SAVE_AND_SWITCH_TO_KERNEL_CR3 macro doesn't do an
948	 * unconditional CR3 write, even in the PTI case.  So do an lfence
949	 * to prevent GS speculation, regardless of whether PTI is enabled.
950	 */
951	FENCE_SWAPGS_KERNEL_ENTRY
952
953	/* EBX = 0 -> SWAPGS required on exit */
954	xorl	%ebx, %ebx
955	ret
956SYM_CODE_END(paranoid_entry)
957
958/*
959 * "Paranoid" exit path from exception stack.  This is invoked
960 * only on return from non-NMI IST interrupts that came
961 * from kernel space.
962 *
963 * We may be returning to very strange contexts (e.g. very early
964 * in syscall entry), so checking for preemption here would
965 * be complicated.  Fortunately, there's no good reason to try
966 * to handle preemption here.
967 *
968 * R/EBX contains the GSBASE related information depending on the
969 * availability of the FSGSBASE instructions:
970 *
971 * FSGSBASE	R/EBX
972 *     N        0 -> SWAPGS on exit
973 *              1 -> no SWAPGS on exit
974 *
975 *     Y        User space GSBASE, must be restored unconditionally
976 */
977SYM_CODE_START_LOCAL(paranoid_exit)
978	UNWIND_HINT_REGS
979	/*
980	 * The order of operations is important. RESTORE_CR3 requires
981	 * kernel GSBASE.
982	 *
983	 * NB to anyone to try to optimize this code: this code does
984	 * not execute at all for exceptions from user mode. Those
985	 * exceptions go through error_exit instead.
986	 */
987	RESTORE_CR3	scratch_reg=%rax save_reg=%r14
988
989	/* Handle the three GSBASE cases */
990	ALTERNATIVE "jmp .Lparanoid_exit_checkgs", "", X86_FEATURE_FSGSBASE
991
992	/* With FSGSBASE enabled, unconditionally restore GSBASE */
993	wrgsbase	%rbx
994	jmp		restore_regs_and_return_to_kernel
995
996.Lparanoid_exit_checkgs:
997	/* On non-FSGSBASE systems, conditionally do SWAPGS */
998	testl		%ebx, %ebx
999	jnz		restore_regs_and_return_to_kernel
1000
1001	/* We are returning to a context with user GSBASE */
1002	swapgs
1003	jmp		restore_regs_and_return_to_kernel
1004SYM_CODE_END(paranoid_exit)
1005
1006/*
1007 * Save all registers in pt_regs, and switch GS if needed.
1008 */
1009SYM_CODE_START_LOCAL(error_entry)
1010	UNWIND_HINT_FUNC
1011	cld
1012	PUSH_AND_CLEAR_REGS save_ret=1
1013	ENCODE_FRAME_POINTER 8
1014	testb	$3, CS+8(%rsp)
1015	jz	.Lerror_kernelspace
1016
1017	/*
1018	 * We entered from user mode or we're pretending to have entered
1019	 * from user mode due to an IRET fault.
1020	 */
1021	SWAPGS
1022	FENCE_SWAPGS_USER_ENTRY
1023	/* We have user CR3.  Change to kernel CR3. */
1024	SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1025
1026.Lerror_entry_from_usermode_after_swapgs:
1027	/* Put us onto the real thread stack. */
1028	popq	%r12				/* save return addr in %12 */
1029	movq	%rsp, %rdi			/* arg0 = pt_regs pointer */
1030	call	sync_regs
1031	movq	%rax, %rsp			/* switch stack */
1032	ENCODE_FRAME_POINTER
1033	pushq	%r12
1034	ret
1035
1036.Lerror_entry_done_lfence:
1037	FENCE_SWAPGS_KERNEL_ENTRY
1038.Lerror_entry_done:
1039	ret
1040
1041	/*
1042	 * There are two places in the kernel that can potentially fault with
1043	 * usergs. Handle them here.  B stepping K8s sometimes report a
1044	 * truncated RIP for IRET exceptions returning to compat mode. Check
1045	 * for these here too.
1046	 */
1047.Lerror_kernelspace:
1048	leaq	native_irq_return_iret(%rip), %rcx
1049	cmpq	%rcx, RIP+8(%rsp)
1050	je	.Lerror_bad_iret
1051	movl	%ecx, %eax			/* zero extend */
1052	cmpq	%rax, RIP+8(%rsp)
1053	je	.Lbstep_iret
1054	cmpq	$.Lgs_change, RIP+8(%rsp)
1055	jne	.Lerror_entry_done_lfence
1056
1057	/*
1058	 * hack: .Lgs_change can fail with user gsbase.  If this happens, fix up
1059	 * gsbase and proceed.  We'll fix up the exception and land in
1060	 * .Lgs_change's error handler with kernel gsbase.
1061	 */
1062	SWAPGS
1063	FENCE_SWAPGS_USER_ENTRY
1064	jmp .Lerror_entry_done
1065
1066.Lbstep_iret:
1067	/* Fix truncated RIP */
1068	movq	%rcx, RIP+8(%rsp)
1069	/* fall through */
1070
1071.Lerror_bad_iret:
1072	/*
1073	 * We came from an IRET to user mode, so we have user
1074	 * gsbase and CR3.  Switch to kernel gsbase and CR3:
1075	 */
1076	SWAPGS
1077	FENCE_SWAPGS_USER_ENTRY
1078	SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1079
1080	/*
1081	 * Pretend that the exception came from user mode: set up pt_regs
1082	 * as if we faulted immediately after IRET.
1083	 */
1084	mov	%rsp, %rdi
1085	call	fixup_bad_iret
1086	mov	%rax, %rsp
1087	jmp	.Lerror_entry_from_usermode_after_swapgs
1088SYM_CODE_END(error_entry)
1089
1090SYM_CODE_START_LOCAL(error_return)
1091	UNWIND_HINT_REGS
1092	DEBUG_ENTRY_ASSERT_IRQS_OFF
1093	testb	$3, CS(%rsp)
1094	jz	restore_regs_and_return_to_kernel
1095	jmp	swapgs_restore_regs_and_return_to_usermode
1096SYM_CODE_END(error_return)
1097
1098/*
1099 * Runs on exception stack.  Xen PV does not go through this path at all,
1100 * so we can use real assembly here.
1101 *
1102 * Registers:
1103 *	%r14: Used to save/restore the CR3 of the interrupted context
1104 *	      when PAGE_TABLE_ISOLATION is in use.  Do not clobber.
1105 */
1106SYM_CODE_START(asm_exc_nmi)
1107	UNWIND_HINT_IRET_REGS
1108
1109	/*
1110	 * We allow breakpoints in NMIs. If a breakpoint occurs, then
1111	 * the iretq it performs will take us out of NMI context.
1112	 * This means that we can have nested NMIs where the next
1113	 * NMI is using the top of the stack of the previous NMI. We
1114	 * can't let it execute because the nested NMI will corrupt the
1115	 * stack of the previous NMI. NMI handlers are not re-entrant
1116	 * anyway.
1117	 *
1118	 * To handle this case we do the following:
1119	 *  Check the a special location on the stack that contains
1120	 *  a variable that is set when NMIs are executing.
1121	 *  The interrupted task's stack is also checked to see if it
1122	 *  is an NMI stack.
1123	 *  If the variable is not set and the stack is not the NMI
1124	 *  stack then:
1125	 *    o Set the special variable on the stack
1126	 *    o Copy the interrupt frame into an "outermost" location on the
1127	 *      stack
1128	 *    o Copy the interrupt frame into an "iret" location on the stack
1129	 *    o Continue processing the NMI
1130	 *  If the variable is set or the previous stack is the NMI stack:
1131	 *    o Modify the "iret" location to jump to the repeat_nmi
1132	 *    o return back to the first NMI
1133	 *
1134	 * Now on exit of the first NMI, we first clear the stack variable
1135	 * The NMI stack will tell any nested NMIs at that point that it is
1136	 * nested. Then we pop the stack normally with iret, and if there was
1137	 * a nested NMI that updated the copy interrupt stack frame, a
1138	 * jump will be made to the repeat_nmi code that will handle the second
1139	 * NMI.
1140	 *
1141	 * However, espfix prevents us from directly returning to userspace
1142	 * with a single IRET instruction.  Similarly, IRET to user mode
1143	 * can fault.  We therefore handle NMIs from user space like
1144	 * other IST entries.
1145	 */
1146
1147	ASM_CLAC
1148
1149	/* Use %rdx as our temp variable throughout */
1150	pushq	%rdx
1151
1152	testb	$3, CS-RIP+8(%rsp)
1153	jz	.Lnmi_from_kernel
1154
1155	/*
1156	 * NMI from user mode.  We need to run on the thread stack, but we
1157	 * can't go through the normal entry paths: NMIs are masked, and
1158	 * we don't want to enable interrupts, because then we'll end
1159	 * up in an awkward situation in which IRQs are on but NMIs
1160	 * are off.
1161	 *
1162	 * We also must not push anything to the stack before switching
1163	 * stacks lest we corrupt the "NMI executing" variable.
1164	 */
1165
1166	swapgs
1167	cld
1168	FENCE_SWAPGS_USER_ENTRY
1169	SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx
1170	movq	%rsp, %rdx
1171	movq	PER_CPU_VAR(cpu_current_top_of_stack), %rsp
1172	UNWIND_HINT_IRET_REGS base=%rdx offset=8
1173	pushq	5*8(%rdx)	/* pt_regs->ss */
1174	pushq	4*8(%rdx)	/* pt_regs->rsp */
1175	pushq	3*8(%rdx)	/* pt_regs->flags */
1176	pushq	2*8(%rdx)	/* pt_regs->cs */
1177	pushq	1*8(%rdx)	/* pt_regs->rip */
1178	UNWIND_HINT_IRET_REGS
1179	pushq   $-1		/* pt_regs->orig_ax */
1180	PUSH_AND_CLEAR_REGS rdx=(%rdx)
1181	ENCODE_FRAME_POINTER
1182
1183	/*
1184	 * At this point we no longer need to worry about stack damage
1185	 * due to nesting -- we're on the normal thread stack and we're
1186	 * done with the NMI stack.
1187	 */
1188
1189	movq	%rsp, %rdi
1190	movq	$-1, %rsi
1191	call	exc_nmi
1192
1193	/*
1194	 * Return back to user mode.  We must *not* do the normal exit
1195	 * work, because we don't want to enable interrupts.
1196	 */
1197	jmp	swapgs_restore_regs_and_return_to_usermode
1198
1199.Lnmi_from_kernel:
1200	/*
1201	 * Here's what our stack frame will look like:
1202	 * +---------------------------------------------------------+
1203	 * | original SS                                             |
1204	 * | original Return RSP                                     |
1205	 * | original RFLAGS                                         |
1206	 * | original CS                                             |
1207	 * | original RIP                                            |
1208	 * +---------------------------------------------------------+
1209	 * | temp storage for rdx                                    |
1210	 * +---------------------------------------------------------+
1211	 * | "NMI executing" variable                                |
1212	 * +---------------------------------------------------------+
1213	 * | iret SS          } Copied from "outermost" frame        |
1214	 * | iret Return RSP  } on each loop iteration; overwritten  |
1215	 * | iret RFLAGS      } by a nested NMI to force another     |
1216	 * | iret CS          } iteration if needed.                 |
1217	 * | iret RIP         }                                      |
1218	 * +---------------------------------------------------------+
1219	 * | outermost SS          } initialized in first_nmi;       |
1220	 * | outermost Return RSP  } will not be changed before      |
1221	 * | outermost RFLAGS      } NMI processing is done.         |
1222	 * | outermost CS          } Copied to "iret" frame on each  |
1223	 * | outermost RIP         } iteration.                      |
1224	 * +---------------------------------------------------------+
1225	 * | pt_regs                                                 |
1226	 * +---------------------------------------------------------+
1227	 *
1228	 * The "original" frame is used by hardware.  Before re-enabling
1229	 * NMIs, we need to be done with it, and we need to leave enough
1230	 * space for the asm code here.
1231	 *
1232	 * We return by executing IRET while RSP points to the "iret" frame.
1233	 * That will either return for real or it will loop back into NMI
1234	 * processing.
1235	 *
1236	 * The "outermost" frame is copied to the "iret" frame on each
1237	 * iteration of the loop, so each iteration starts with the "iret"
1238	 * frame pointing to the final return target.
1239	 */
1240
1241	/*
1242	 * Determine whether we're a nested NMI.
1243	 *
1244	 * If we interrupted kernel code between repeat_nmi and
1245	 * end_repeat_nmi, then we are a nested NMI.  We must not
1246	 * modify the "iret" frame because it's being written by
1247	 * the outer NMI.  That's okay; the outer NMI handler is
1248	 * about to about to call exc_nmi() anyway, so we can just
1249	 * resume the outer NMI.
1250	 */
1251
1252	movq	$repeat_nmi, %rdx
1253	cmpq	8(%rsp), %rdx
1254	ja	1f
1255	movq	$end_repeat_nmi, %rdx
1256	cmpq	8(%rsp), %rdx
1257	ja	nested_nmi_out
12581:
1259
1260	/*
1261	 * Now check "NMI executing".  If it's set, then we're nested.
1262	 * This will not detect if we interrupted an outer NMI just
1263	 * before IRET.
1264	 */
1265	cmpl	$1, -8(%rsp)
1266	je	nested_nmi
1267
1268	/*
1269	 * Now test if the previous stack was an NMI stack.  This covers
1270	 * the case where we interrupt an outer NMI after it clears
1271	 * "NMI executing" but before IRET.  We need to be careful, though:
1272	 * there is one case in which RSP could point to the NMI stack
1273	 * despite there being no NMI active: naughty userspace controls
1274	 * RSP at the very beginning of the SYSCALL targets.  We can
1275	 * pull a fast one on naughty userspace, though: we program
1276	 * SYSCALL to mask DF, so userspace cannot cause DF to be set
1277	 * if it controls the kernel's RSP.  We set DF before we clear
1278	 * "NMI executing".
1279	 */
1280	lea	6*8(%rsp), %rdx
1281	/* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
1282	cmpq	%rdx, 4*8(%rsp)
1283	/* If the stack pointer is above the NMI stack, this is a normal NMI */
1284	ja	first_nmi
1285
1286	subq	$EXCEPTION_STKSZ, %rdx
1287	cmpq	%rdx, 4*8(%rsp)
1288	/* If it is below the NMI stack, it is a normal NMI */
1289	jb	first_nmi
1290
1291	/* Ah, it is within the NMI stack. */
1292
1293	testb	$(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
1294	jz	first_nmi	/* RSP was user controlled. */
1295
1296	/* This is a nested NMI. */
1297
1298nested_nmi:
1299	/*
1300	 * Modify the "iret" frame to point to repeat_nmi, forcing another
1301	 * iteration of NMI handling.
1302	 */
1303	subq	$8, %rsp
1304	leaq	-10*8(%rsp), %rdx
1305	pushq	$__KERNEL_DS
1306	pushq	%rdx
1307	pushfq
1308	pushq	$__KERNEL_CS
1309	pushq	$repeat_nmi
1310
1311	/* Put stack back */
1312	addq	$(6*8), %rsp
1313
1314nested_nmi_out:
1315	popq	%rdx
1316
1317	/* We are returning to kernel mode, so this cannot result in a fault. */
1318	iretq
1319
1320first_nmi:
1321	/* Restore rdx. */
1322	movq	(%rsp), %rdx
1323
1324	/* Make room for "NMI executing". */
1325	pushq	$0
1326
1327	/* Leave room for the "iret" frame */
1328	subq	$(5*8), %rsp
1329
1330	/* Copy the "original" frame to the "outermost" frame */
1331	.rept 5
1332	pushq	11*8(%rsp)
1333	.endr
1334	UNWIND_HINT_IRET_REGS
1335
1336	/* Everything up to here is safe from nested NMIs */
1337
1338#ifdef CONFIG_DEBUG_ENTRY
1339	/*
1340	 * For ease of testing, unmask NMIs right away.  Disabled by
1341	 * default because IRET is very expensive.
1342	 */
1343	pushq	$0		/* SS */
1344	pushq	%rsp		/* RSP (minus 8 because of the previous push) */
1345	addq	$8, (%rsp)	/* Fix up RSP */
1346	pushfq			/* RFLAGS */
1347	pushq	$__KERNEL_CS	/* CS */
1348	pushq	$1f		/* RIP */
1349	iretq			/* continues at repeat_nmi below */
1350	UNWIND_HINT_IRET_REGS
13511:
1352#endif
1353
1354repeat_nmi:
1355	/*
1356	 * If there was a nested NMI, the first NMI's iret will return
1357	 * here. But NMIs are still enabled and we can take another
1358	 * nested NMI. The nested NMI checks the interrupted RIP to see
1359	 * if it is between repeat_nmi and end_repeat_nmi, and if so
1360	 * it will just return, as we are about to repeat an NMI anyway.
1361	 * This makes it safe to copy to the stack frame that a nested
1362	 * NMI will update.
1363	 *
1364	 * RSP is pointing to "outermost RIP".  gsbase is unknown, but, if
1365	 * we're repeating an NMI, gsbase has the same value that it had on
1366	 * the first iteration.  paranoid_entry will load the kernel
1367	 * gsbase if needed before we call exc_nmi().  "NMI executing"
1368	 * is zero.
1369	 */
1370	movq	$1, 10*8(%rsp)		/* Set "NMI executing". */
1371
1372	/*
1373	 * Copy the "outermost" frame to the "iret" frame.  NMIs that nest
1374	 * here must not modify the "iret" frame while we're writing to
1375	 * it or it will end up containing garbage.
1376	 */
1377	addq	$(10*8), %rsp
1378	.rept 5
1379	pushq	-6*8(%rsp)
1380	.endr
1381	subq	$(5*8), %rsp
1382end_repeat_nmi:
1383
1384	/*
1385	 * Everything below this point can be preempted by a nested NMI.
1386	 * If this happens, then the inner NMI will change the "iret"
1387	 * frame to point back to repeat_nmi.
1388	 */
1389	pushq	$-1				/* ORIG_RAX: no syscall to restart */
1390
1391	/*
1392	 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit
1393	 * as we should not be calling schedule in NMI context.
1394	 * Even with normal interrupts enabled. An NMI should not be
1395	 * setting NEED_RESCHED or anything that normal interrupts and
1396	 * exceptions might do.
1397	 */
1398	call	paranoid_entry
1399	UNWIND_HINT_REGS
1400
1401	movq	%rsp, %rdi
1402	movq	$-1, %rsi
1403	call	exc_nmi
1404
1405	/* Always restore stashed CR3 value (see paranoid_entry) */
1406	RESTORE_CR3 scratch_reg=%r15 save_reg=%r14
1407
1408	/*
1409	 * The above invocation of paranoid_entry stored the GSBASE
1410	 * related information in R/EBX depending on the availability
1411	 * of FSGSBASE.
1412	 *
1413	 * If FSGSBASE is enabled, restore the saved GSBASE value
1414	 * unconditionally, otherwise take the conditional SWAPGS path.
1415	 */
1416	ALTERNATIVE "jmp nmi_no_fsgsbase", "", X86_FEATURE_FSGSBASE
1417
1418	wrgsbase	%rbx
1419	jmp	nmi_restore
1420
1421nmi_no_fsgsbase:
1422	/* EBX == 0 -> invoke SWAPGS */
1423	testl	%ebx, %ebx
1424	jnz	nmi_restore
1425
1426nmi_swapgs:
1427	swapgs
1428
1429nmi_restore:
1430	POP_REGS
1431
1432	/*
1433	 * Skip orig_ax and the "outermost" frame to point RSP at the "iret"
1434	 * at the "iret" frame.
1435	 */
1436	addq	$6*8, %rsp
1437
1438	/*
1439	 * Clear "NMI executing".  Set DF first so that we can easily
1440	 * distinguish the remaining code between here and IRET from
1441	 * the SYSCALL entry and exit paths.
1442	 *
1443	 * We arguably should just inspect RIP instead, but I (Andy) wrote
1444	 * this code when I had the misapprehension that Xen PV supported
1445	 * NMIs, and Xen PV would break that approach.
1446	 */
1447	std
1448	movq	$0, 5*8(%rsp)		/* clear "NMI executing" */
1449
1450	/*
1451	 * iretq reads the "iret" frame and exits the NMI stack in a
1452	 * single instruction.  We are returning to kernel mode, so this
1453	 * cannot result in a fault.  Similarly, we don't need to worry
1454	 * about espfix64 on the way back to kernel mode.
1455	 */
1456	iretq
1457SYM_CODE_END(asm_exc_nmi)
1458
1459#ifndef CONFIG_IA32_EMULATION
1460/*
1461 * This handles SYSCALL from 32-bit code.  There is no way to program
1462 * MSRs to fully disable 32-bit SYSCALL.
1463 */
1464SYM_CODE_START(ignore_sysret)
1465	UNWIND_HINT_EMPTY
1466	mov	$-ENOSYS, %eax
1467	sysretl
1468SYM_CODE_END(ignore_sysret)
1469#endif
1470
1471.pushsection .text, "ax"
1472SYM_CODE_START(rewind_stack_do_exit)
1473	UNWIND_HINT_FUNC
1474	/* Prevent any naive code from trying to unwind to our caller. */
1475	xorl	%ebp, %ebp
1476
1477	movq	PER_CPU_VAR(cpu_current_top_of_stack), %rax
1478	leaq	-PTREGS_SIZE(%rax), %rsp
1479	UNWIND_HINT_REGS
1480
1481	call	do_exit
1482SYM_CODE_END(rewind_stack_do_exit)
1483.popsection
1484