1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86_64/entry.S 4 * 5 * Copyright (C) 1991, 1992 Linus Torvalds 6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs 7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 8 * 9 * entry.S contains the system-call and fault low-level handling routines. 10 * 11 * Some of this is documented in Documentation/x86/entry_64.rst 12 * 13 * A note on terminology: 14 * - iret frame: Architecture defined interrupt frame from SS to RIP 15 * at the top of the kernel process stack. 16 * 17 * Some macro usage: 18 * - SYM_FUNC_START/END:Define functions in the symbol table. 19 * - idtentry: Define exception entry points. 20 */ 21#include <linux/linkage.h> 22#include <asm/segment.h> 23#include <asm/cache.h> 24#include <asm/errno.h> 25#include <asm/asm-offsets.h> 26#include <asm/msr.h> 27#include <asm/unistd.h> 28#include <asm/thread_info.h> 29#include <asm/hw_irq.h> 30#include <asm/page_types.h> 31#include <asm/irqflags.h> 32#include <asm/paravirt.h> 33#include <asm/percpu.h> 34#include <asm/asm.h> 35#include <asm/smap.h> 36#include <asm/pgtable_types.h> 37#include <asm/export.h> 38#include <asm/frame.h> 39#include <asm/trapnr.h> 40#include <asm/nospec-branch.h> 41#include <asm/fsgsbase.h> 42#include <linux/err.h> 43 44#include "calling.h" 45 46.code64 47.section .entry.text, "ax" 48 49/* 50 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. 51 * 52 * This is the only entry point used for 64-bit system calls. The 53 * hardware interface is reasonably well designed and the register to 54 * argument mapping Linux uses fits well with the registers that are 55 * available when SYSCALL is used. 56 * 57 * SYSCALL instructions can be found inlined in libc implementations as 58 * well as some other programs and libraries. There are also a handful 59 * of SYSCALL instructions in the vDSO used, for example, as a 60 * clock_gettimeofday fallback. 61 * 62 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, 63 * then loads new ss, cs, and rip from previously programmed MSRs. 64 * rflags gets masked by a value from another MSR (so CLD and CLAC 65 * are not needed). SYSCALL does not save anything on the stack 66 * and does not change rsp. 67 * 68 * Registers on entry: 69 * rax system call number 70 * rcx return address 71 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) 72 * rdi arg0 73 * rsi arg1 74 * rdx arg2 75 * r10 arg3 (needs to be moved to rcx to conform to C ABI) 76 * r8 arg4 77 * r9 arg5 78 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) 79 * 80 * Only called from user space. 81 * 82 * When user can change pt_regs->foo always force IRET. That is because 83 * it deals with uncanonical addresses better. SYSRET has trouble 84 * with them due to bugs in both AMD and Intel CPUs. 85 */ 86 87SYM_CODE_START(entry_SYSCALL_64) 88 UNWIND_HINT_EMPTY 89 90 swapgs 91 /* tss.sp2 is scratch space. */ 92 movq %rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2) 93 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp 94 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 95 96SYM_INNER_LABEL(entry_SYSCALL_64_safe_stack, SYM_L_GLOBAL) 97 98 /* Construct struct pt_regs on stack */ 99 pushq $__USER_DS /* pt_regs->ss */ 100 pushq PER_CPU_VAR(cpu_tss_rw + TSS_sp2) /* pt_regs->sp */ 101 pushq %r11 /* pt_regs->flags */ 102 pushq $__USER_CS /* pt_regs->cs */ 103 pushq %rcx /* pt_regs->ip */ 104SYM_INNER_LABEL(entry_SYSCALL_64_after_hwframe, SYM_L_GLOBAL) 105 pushq %rax /* pt_regs->orig_ax */ 106 107 PUSH_AND_CLEAR_REGS rax=$-ENOSYS 108 109 /* IRQs are off. */ 110 movq %rsp, %rdi 111 /* Sign extend the lower 32bit as syscall numbers are treated as int */ 112 movslq %eax, %rsi 113 call do_syscall_64 /* returns with IRQs disabled */ 114 115 /* 116 * Try to use SYSRET instead of IRET if we're returning to 117 * a completely clean 64-bit userspace context. If we're not, 118 * go to the slow exit path. 119 * In the Xen PV case we must use iret anyway. 120 */ 121 122 ALTERNATIVE "", "jmp swapgs_restore_regs_and_return_to_usermode", \ 123 X86_FEATURE_XENPV 124 125 movq RCX(%rsp), %rcx 126 movq RIP(%rsp), %r11 127 128 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ 129 jne swapgs_restore_regs_and_return_to_usermode 130 131 /* 132 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP 133 * in kernel space. This essentially lets the user take over 134 * the kernel, since userspace controls RSP. 135 * 136 * If width of "canonical tail" ever becomes variable, this will need 137 * to be updated to remain correct on both old and new CPUs. 138 * 139 * Change top bits to match most significant bit (47th or 56th bit 140 * depending on paging mode) in the address. 141 */ 142#ifdef CONFIG_X86_5LEVEL 143 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \ 144 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57 145#else 146 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 147 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 148#endif 149 150 /* If this changed %rcx, it was not canonical */ 151 cmpq %rcx, %r11 152 jne swapgs_restore_regs_and_return_to_usermode 153 154 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ 155 jne swapgs_restore_regs_and_return_to_usermode 156 157 movq R11(%rsp), %r11 158 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ 159 jne swapgs_restore_regs_and_return_to_usermode 160 161 /* 162 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot 163 * restore RF properly. If the slowpath sets it for whatever reason, we 164 * need to restore it correctly. 165 * 166 * SYSRET can restore TF, but unlike IRET, restoring TF results in a 167 * trap from userspace immediately after SYSRET. This would cause an 168 * infinite loop whenever #DB happens with register state that satisfies 169 * the opportunistic SYSRET conditions. For example, single-stepping 170 * this user code: 171 * 172 * movq $stuck_here, %rcx 173 * pushfq 174 * popq %r11 175 * stuck_here: 176 * 177 * would never get past 'stuck_here'. 178 */ 179 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 180 jnz swapgs_restore_regs_and_return_to_usermode 181 182 /* nothing to check for RSP */ 183 184 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ 185 jne swapgs_restore_regs_and_return_to_usermode 186 187 /* 188 * We win! This label is here just for ease of understanding 189 * perf profiles. Nothing jumps here. 190 */ 191syscall_return_via_sysret: 192 /* rcx and r11 are already restored (see code above) */ 193 POP_REGS pop_rdi=0 skip_r11rcx=1 194 195 /* 196 * Now all regs are restored except RSP and RDI. 197 * Save old stack pointer and switch to trampoline stack. 198 */ 199 movq %rsp, %rdi 200 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 201 UNWIND_HINT_EMPTY 202 203 pushq RSP-RDI(%rdi) /* RSP */ 204 pushq (%rdi) /* RDI */ 205 206 /* 207 * We are on the trampoline stack. All regs except RDI are live. 208 * We can do future final exit work right here. 209 */ 210 STACKLEAK_ERASE_NOCLOBBER 211 212 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 213 214 popq %rdi 215 popq %rsp 216 swapgs 217 sysretq 218SYM_CODE_END(entry_SYSCALL_64) 219 220/* 221 * %rdi: prev task 222 * %rsi: next task 223 */ 224.pushsection .text, "ax" 225SYM_FUNC_START(__switch_to_asm) 226 /* 227 * Save callee-saved registers 228 * This must match the order in inactive_task_frame 229 */ 230 pushq %rbp 231 pushq %rbx 232 pushq %r12 233 pushq %r13 234 pushq %r14 235 pushq %r15 236 237 /* switch stack */ 238 movq %rsp, TASK_threadsp(%rdi) 239 movq TASK_threadsp(%rsi), %rsp 240 241#ifdef CONFIG_STACKPROTECTOR 242 movq TASK_stack_canary(%rsi), %rbx 243 movq %rbx, PER_CPU_VAR(fixed_percpu_data) + stack_canary_offset 244#endif 245 246#ifdef CONFIG_RETPOLINE 247 /* 248 * When switching from a shallower to a deeper call stack 249 * the RSB may either underflow or use entries populated 250 * with userspace addresses. On CPUs where those concerns 251 * exist, overwrite the RSB with entries which capture 252 * speculative execution to prevent attack. 253 */ 254 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW 255#endif 256 257 /* restore callee-saved registers */ 258 popq %r15 259 popq %r14 260 popq %r13 261 popq %r12 262 popq %rbx 263 popq %rbp 264 265 jmp __switch_to 266SYM_FUNC_END(__switch_to_asm) 267.popsection 268 269/* 270 * A newly forked process directly context switches into this address. 271 * 272 * rax: prev task we switched from 273 * rbx: kernel thread func (NULL for user thread) 274 * r12: kernel thread arg 275 */ 276.pushsection .text, "ax" 277SYM_CODE_START(ret_from_fork) 278 UNWIND_HINT_EMPTY 279 movq %rax, %rdi 280 call schedule_tail /* rdi: 'prev' task parameter */ 281 282 testq %rbx, %rbx /* from kernel_thread? */ 283 jnz 1f /* kernel threads are uncommon */ 284 2852: 286 UNWIND_HINT_REGS 287 movq %rsp, %rdi 288 call syscall_exit_to_user_mode /* returns with IRQs disabled */ 289 jmp swapgs_restore_regs_and_return_to_usermode 290 2911: 292 /* kernel thread */ 293 UNWIND_HINT_EMPTY 294 movq %r12, %rdi 295 CALL_NOSPEC rbx 296 /* 297 * A kernel thread is allowed to return here after successfully 298 * calling kernel_execve(). Exit to userspace to complete the execve() 299 * syscall. 300 */ 301 movq $0, RAX(%rsp) 302 jmp 2b 303SYM_CODE_END(ret_from_fork) 304.popsection 305 306.macro DEBUG_ENTRY_ASSERT_IRQS_OFF 307#ifdef CONFIG_DEBUG_ENTRY 308 pushq %rax 309 SAVE_FLAGS 310 testl $X86_EFLAGS_IF, %eax 311 jz .Lokay_\@ 312 ud2 313.Lokay_\@: 314 popq %rax 315#endif 316.endm 317 318/** 319 * idtentry_body - Macro to emit code calling the C function 320 * @cfunc: C function to be called 321 * @has_error_code: Hardware pushed error code on stack 322 */ 323.macro idtentry_body cfunc has_error_code:req 324 325 call error_entry 326 UNWIND_HINT_REGS 327 328 movq %rsp, %rdi /* pt_regs pointer into 1st argument*/ 329 330 .if \has_error_code == 1 331 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/ 332 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 333 .endif 334 335 call \cfunc 336 337 jmp error_return 338.endm 339 340/** 341 * idtentry - Macro to generate entry stubs for simple IDT entries 342 * @vector: Vector number 343 * @asmsym: ASM symbol for the entry point 344 * @cfunc: C function to be called 345 * @has_error_code: Hardware pushed error code on stack 346 * 347 * The macro emits code to set up the kernel context for straight forward 348 * and simple IDT entries. No IST stack, no paranoid entry checks. 349 */ 350.macro idtentry vector asmsym cfunc has_error_code:req 351SYM_CODE_START(\asmsym) 352 UNWIND_HINT_IRET_REGS offset=\has_error_code*8 353 ASM_CLAC 354 355 .if \has_error_code == 0 356 pushq $-1 /* ORIG_RAX: no syscall to restart */ 357 .endif 358 359 .if \vector == X86_TRAP_BP 360 /* 361 * If coming from kernel space, create a 6-word gap to allow the 362 * int3 handler to emulate a call instruction. 363 */ 364 testb $3, CS-ORIG_RAX(%rsp) 365 jnz .Lfrom_usermode_no_gap_\@ 366 .rept 6 367 pushq 5*8(%rsp) 368 .endr 369 UNWIND_HINT_IRET_REGS offset=8 370.Lfrom_usermode_no_gap_\@: 371 .endif 372 373 idtentry_body \cfunc \has_error_code 374 375_ASM_NOKPROBE(\asmsym) 376SYM_CODE_END(\asmsym) 377.endm 378 379/* 380 * Interrupt entry/exit. 381 * 382 + The interrupt stubs push (vector) onto the stack, which is the error_code 383 * position of idtentry exceptions, and jump to one of the two idtentry points 384 * (common/spurious). 385 * 386 * common_interrupt is a hotpath, align it to a cache line 387 */ 388.macro idtentry_irq vector cfunc 389 .p2align CONFIG_X86_L1_CACHE_SHIFT 390 idtentry \vector asm_\cfunc \cfunc has_error_code=1 391.endm 392 393/* 394 * System vectors which invoke their handlers directly and are not 395 * going through the regular common device interrupt handling code. 396 */ 397.macro idtentry_sysvec vector cfunc 398 idtentry \vector asm_\cfunc \cfunc has_error_code=0 399.endm 400 401/** 402 * idtentry_mce_db - Macro to generate entry stubs for #MC and #DB 403 * @vector: Vector number 404 * @asmsym: ASM symbol for the entry point 405 * @cfunc: C function to be called 406 * 407 * The macro emits code to set up the kernel context for #MC and #DB 408 * 409 * If the entry comes from user space it uses the normal entry path 410 * including the return to user space work and preemption checks on 411 * exit. 412 * 413 * If hits in kernel mode then it needs to go through the paranoid 414 * entry as the exception can hit any random state. No preemption 415 * check on exit to keep the paranoid path simple. 416 */ 417.macro idtentry_mce_db vector asmsym cfunc 418SYM_CODE_START(\asmsym) 419 UNWIND_HINT_IRET_REGS 420 ASM_CLAC 421 422 pushq $-1 /* ORIG_RAX: no syscall to restart */ 423 424 /* 425 * If the entry is from userspace, switch stacks and treat it as 426 * a normal entry. 427 */ 428 testb $3, CS-ORIG_RAX(%rsp) 429 jnz .Lfrom_usermode_switch_stack_\@ 430 431 /* paranoid_entry returns GS information for paranoid_exit in EBX. */ 432 call paranoid_entry 433 434 UNWIND_HINT_REGS 435 436 movq %rsp, %rdi /* pt_regs pointer */ 437 438 call \cfunc 439 440 jmp paranoid_exit 441 442 /* Switch to the regular task stack and use the noist entry point */ 443.Lfrom_usermode_switch_stack_\@: 444 idtentry_body noist_\cfunc, has_error_code=0 445 446_ASM_NOKPROBE(\asmsym) 447SYM_CODE_END(\asmsym) 448.endm 449 450#ifdef CONFIG_AMD_MEM_ENCRYPT 451/** 452 * idtentry_vc - Macro to generate entry stub for #VC 453 * @vector: Vector number 454 * @asmsym: ASM symbol for the entry point 455 * @cfunc: C function to be called 456 * 457 * The macro emits code to set up the kernel context for #VC. The #VC handler 458 * runs on an IST stack and needs to be able to cause nested #VC exceptions. 459 * 460 * To make this work the #VC entry code tries its best to pretend it doesn't use 461 * an IST stack by switching to the task stack if coming from user-space (which 462 * includes early SYSCALL entry path) or back to the stack in the IRET frame if 463 * entered from kernel-mode. 464 * 465 * If entered from kernel-mode the return stack is validated first, and if it is 466 * not safe to use (e.g. because it points to the entry stack) the #VC handler 467 * will switch to a fall-back stack (VC2) and call a special handler function. 468 * 469 * The macro is only used for one vector, but it is planned to be extended in 470 * the future for the #HV exception. 471 */ 472.macro idtentry_vc vector asmsym cfunc 473SYM_CODE_START(\asmsym) 474 UNWIND_HINT_IRET_REGS 475 ASM_CLAC 476 477 /* 478 * If the entry is from userspace, switch stacks and treat it as 479 * a normal entry. 480 */ 481 testb $3, CS-ORIG_RAX(%rsp) 482 jnz .Lfrom_usermode_switch_stack_\@ 483 484 /* 485 * paranoid_entry returns SWAPGS flag for paranoid_exit in EBX. 486 * EBX == 0 -> SWAPGS, EBX == 1 -> no SWAPGS 487 */ 488 call paranoid_entry 489 490 UNWIND_HINT_REGS 491 492 /* 493 * Switch off the IST stack to make it free for nested exceptions. The 494 * vc_switch_off_ist() function will switch back to the interrupted 495 * stack if it is safe to do so. If not it switches to the VC fall-back 496 * stack. 497 */ 498 movq %rsp, %rdi /* pt_regs pointer */ 499 call vc_switch_off_ist 500 movq %rax, %rsp /* Switch to new stack */ 501 502 UNWIND_HINT_REGS 503 504 /* Update pt_regs */ 505 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/ 506 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 507 508 movq %rsp, %rdi /* pt_regs pointer */ 509 510 call kernel_\cfunc 511 512 /* 513 * No need to switch back to the IST stack. The current stack is either 514 * identical to the stack in the IRET frame or the VC fall-back stack, 515 * so it is definitely mapped even with PTI enabled. 516 */ 517 jmp paranoid_exit 518 519 /* Switch to the regular task stack */ 520.Lfrom_usermode_switch_stack_\@: 521 idtentry_body user_\cfunc, has_error_code=1 522 523_ASM_NOKPROBE(\asmsym) 524SYM_CODE_END(\asmsym) 525.endm 526#endif 527 528/* 529 * Double fault entry. Straight paranoid. No checks from which context 530 * this comes because for the espfix induced #DF this would do the wrong 531 * thing. 532 */ 533.macro idtentry_df vector asmsym cfunc 534SYM_CODE_START(\asmsym) 535 UNWIND_HINT_IRET_REGS offset=8 536 ASM_CLAC 537 538 /* paranoid_entry returns GS information for paranoid_exit in EBX. */ 539 call paranoid_entry 540 UNWIND_HINT_REGS 541 542 movq %rsp, %rdi /* pt_regs pointer into first argument */ 543 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/ 544 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 545 call \cfunc 546 547 jmp paranoid_exit 548 549_ASM_NOKPROBE(\asmsym) 550SYM_CODE_END(\asmsym) 551.endm 552 553/* 554 * Include the defines which emit the idt entries which are shared 555 * shared between 32 and 64 bit and emit the __irqentry_text_* markers 556 * so the stacktrace boundary checks work. 557 */ 558 .align 16 559 .globl __irqentry_text_start 560__irqentry_text_start: 561 562#include <asm/idtentry.h> 563 564 .align 16 565 .globl __irqentry_text_end 566__irqentry_text_end: 567 568SYM_CODE_START_LOCAL(common_interrupt_return) 569SYM_INNER_LABEL(swapgs_restore_regs_and_return_to_usermode, SYM_L_GLOBAL) 570#ifdef CONFIG_DEBUG_ENTRY 571 /* Assert that pt_regs indicates user mode. */ 572 testb $3, CS(%rsp) 573 jnz 1f 574 ud2 5751: 576#endif 577 POP_REGS pop_rdi=0 578 579 /* 580 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. 581 * Save old stack pointer and switch to trampoline stack. 582 */ 583 movq %rsp, %rdi 584 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 585 UNWIND_HINT_EMPTY 586 587 /* Copy the IRET frame to the trampoline stack. */ 588 pushq 6*8(%rdi) /* SS */ 589 pushq 5*8(%rdi) /* RSP */ 590 pushq 4*8(%rdi) /* EFLAGS */ 591 pushq 3*8(%rdi) /* CS */ 592 pushq 2*8(%rdi) /* RIP */ 593 594 /* Push user RDI on the trampoline stack. */ 595 pushq (%rdi) 596 597 /* 598 * We are on the trampoline stack. All regs except RDI are live. 599 * We can do future final exit work right here. 600 */ 601 STACKLEAK_ERASE_NOCLOBBER 602 603 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 604 605 /* Restore RDI. */ 606 popq %rdi 607 SWAPGS 608 INTERRUPT_RETURN 609 610 611SYM_INNER_LABEL(restore_regs_and_return_to_kernel, SYM_L_GLOBAL) 612#ifdef CONFIG_DEBUG_ENTRY 613 /* Assert that pt_regs indicates kernel mode. */ 614 testb $3, CS(%rsp) 615 jz 1f 616 ud2 6171: 618#endif 619 POP_REGS 620 addq $8, %rsp /* skip regs->orig_ax */ 621 /* 622 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization 623 * when returning from IPI handler. 624 */ 625 INTERRUPT_RETURN 626 627SYM_INNER_LABEL_ALIGN(native_iret, SYM_L_GLOBAL) 628 UNWIND_HINT_IRET_REGS 629 /* 630 * Are we returning to a stack segment from the LDT? Note: in 631 * 64-bit mode SS:RSP on the exception stack is always valid. 632 */ 633#ifdef CONFIG_X86_ESPFIX64 634 testb $4, (SS-RIP)(%rsp) 635 jnz native_irq_return_ldt 636#endif 637 638SYM_INNER_LABEL(native_irq_return_iret, SYM_L_GLOBAL) 639 /* 640 * This may fault. Non-paranoid faults on return to userspace are 641 * handled by fixup_bad_iret. These include #SS, #GP, and #NP. 642 * Double-faults due to espfix64 are handled in exc_double_fault. 643 * Other faults here are fatal. 644 */ 645 iretq 646 647#ifdef CONFIG_X86_ESPFIX64 648native_irq_return_ldt: 649 /* 650 * We are running with user GSBASE. All GPRs contain their user 651 * values. We have a percpu ESPFIX stack that is eight slots 652 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom 653 * of the ESPFIX stack. 654 * 655 * We clobber RAX and RDI in this code. We stash RDI on the 656 * normal stack and RAX on the ESPFIX stack. 657 * 658 * The ESPFIX stack layout we set up looks like this: 659 * 660 * --- top of ESPFIX stack --- 661 * SS 662 * RSP 663 * RFLAGS 664 * CS 665 * RIP <-- RSP points here when we're done 666 * RAX <-- espfix_waddr points here 667 * --- bottom of ESPFIX stack --- 668 */ 669 670 pushq %rdi /* Stash user RDI */ 671 swapgs /* to kernel GS */ 672 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ 673 674 movq PER_CPU_VAR(espfix_waddr), %rdi 675 movq %rax, (0*8)(%rdi) /* user RAX */ 676 movq (1*8)(%rsp), %rax /* user RIP */ 677 movq %rax, (1*8)(%rdi) 678 movq (2*8)(%rsp), %rax /* user CS */ 679 movq %rax, (2*8)(%rdi) 680 movq (3*8)(%rsp), %rax /* user RFLAGS */ 681 movq %rax, (3*8)(%rdi) 682 movq (5*8)(%rsp), %rax /* user SS */ 683 movq %rax, (5*8)(%rdi) 684 movq (4*8)(%rsp), %rax /* user RSP */ 685 movq %rax, (4*8)(%rdi) 686 /* Now RAX == RSP. */ 687 688 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ 689 690 /* 691 * espfix_stack[31:16] == 0. The page tables are set up such that 692 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of 693 * espfix_waddr for any X. That is, there are 65536 RO aliases of 694 * the same page. Set up RSP so that RSP[31:16] contains the 695 * respective 16 bits of the /userspace/ RSP and RSP nonetheless 696 * still points to an RO alias of the ESPFIX stack. 697 */ 698 orq PER_CPU_VAR(espfix_stack), %rax 699 700 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 701 swapgs /* to user GS */ 702 popq %rdi /* Restore user RDI */ 703 704 movq %rax, %rsp 705 UNWIND_HINT_IRET_REGS offset=8 706 707 /* 708 * At this point, we cannot write to the stack any more, but we can 709 * still read. 710 */ 711 popq %rax /* Restore user RAX */ 712 713 /* 714 * RSP now points to an ordinary IRET frame, except that the page 715 * is read-only and RSP[31:16] are preloaded with the userspace 716 * values. We can now IRET back to userspace. 717 */ 718 jmp native_irq_return_iret 719#endif 720SYM_CODE_END(common_interrupt_return) 721_ASM_NOKPROBE(common_interrupt_return) 722 723/* 724 * Reload gs selector with exception handling 725 * edi: new selector 726 * 727 * Is in entry.text as it shouldn't be instrumented. 728 */ 729SYM_FUNC_START(asm_load_gs_index) 730 FRAME_BEGIN 731 swapgs 732.Lgs_change: 733 movl %edi, %gs 7342: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE 735 swapgs 736 FRAME_END 737 ret 738SYM_FUNC_END(asm_load_gs_index) 739EXPORT_SYMBOL(asm_load_gs_index) 740 741 _ASM_EXTABLE(.Lgs_change, .Lbad_gs) 742 .section .fixup, "ax" 743 /* running with kernelgs */ 744SYM_CODE_START_LOCAL_NOALIGN(.Lbad_gs) 745 swapgs /* switch back to user gs */ 746.macro ZAP_GS 747 /* This can't be a string because the preprocessor needs to see it. */ 748 movl $__USER_DS, %eax 749 movl %eax, %gs 750.endm 751 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG 752 xorl %eax, %eax 753 movl %eax, %gs 754 jmp 2b 755SYM_CODE_END(.Lbad_gs) 756 .previous 757 758#ifdef CONFIG_XEN_PV 759/* 760 * A note on the "critical region" in our callback handler. 761 * We want to avoid stacking callback handlers due to events occurring 762 * during handling of the last event. To do this, we keep events disabled 763 * until we've done all processing. HOWEVER, we must enable events before 764 * popping the stack frame (can't be done atomically) and so it would still 765 * be possible to get enough handler activations to overflow the stack. 766 * Although unlikely, bugs of that kind are hard to track down, so we'd 767 * like to avoid the possibility. 768 * So, on entry to the handler we detect whether we interrupted an 769 * existing activation in its critical region -- if so, we pop the current 770 * activation and restart the handler using the previous one. 771 * 772 * C calling convention: exc_xen_hypervisor_callback(struct *pt_regs) 773 */ 774SYM_CODE_START_LOCAL(exc_xen_hypervisor_callback) 775 776/* 777 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will 778 * see the correct pointer to the pt_regs 779 */ 780 UNWIND_HINT_FUNC 781 movq %rdi, %rsp /* we don't return, adjust the stack frame */ 782 UNWIND_HINT_REGS 783 784 call xen_pv_evtchn_do_upcall 785 786 jmp error_return 787SYM_CODE_END(exc_xen_hypervisor_callback) 788 789/* 790 * Hypervisor uses this for application faults while it executes. 791 * We get here for two reasons: 792 * 1. Fault while reloading DS, ES, FS or GS 793 * 2. Fault while executing IRET 794 * Category 1 we do not need to fix up as Xen has already reloaded all segment 795 * registers that could be reloaded and zeroed the others. 796 * Category 2 we fix up by killing the current process. We cannot use the 797 * normal Linux return path in this case because if we use the IRET hypercall 798 * to pop the stack frame we end up in an infinite loop of failsafe callbacks. 799 * We distinguish between categories by comparing each saved segment register 800 * with its current contents: any discrepancy means we in category 1. 801 */ 802SYM_CODE_START(xen_failsafe_callback) 803 UNWIND_HINT_EMPTY 804 movl %ds, %ecx 805 cmpw %cx, 0x10(%rsp) 806 jne 1f 807 movl %es, %ecx 808 cmpw %cx, 0x18(%rsp) 809 jne 1f 810 movl %fs, %ecx 811 cmpw %cx, 0x20(%rsp) 812 jne 1f 813 movl %gs, %ecx 814 cmpw %cx, 0x28(%rsp) 815 jne 1f 816 /* All segments match their saved values => Category 2 (Bad IRET). */ 817 movq (%rsp), %rcx 818 movq 8(%rsp), %r11 819 addq $0x30, %rsp 820 pushq $0 /* RIP */ 821 UNWIND_HINT_IRET_REGS offset=8 822 jmp asm_exc_general_protection 8231: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ 824 movq (%rsp), %rcx 825 movq 8(%rsp), %r11 826 addq $0x30, %rsp 827 UNWIND_HINT_IRET_REGS 828 pushq $-1 /* orig_ax = -1 => not a system call */ 829 PUSH_AND_CLEAR_REGS 830 ENCODE_FRAME_POINTER 831 jmp error_return 832SYM_CODE_END(xen_failsafe_callback) 833#endif /* CONFIG_XEN_PV */ 834 835/* 836 * Save all registers in pt_regs. Return GSBASE related information 837 * in EBX depending on the availability of the FSGSBASE instructions: 838 * 839 * FSGSBASE R/EBX 840 * N 0 -> SWAPGS on exit 841 * 1 -> no SWAPGS on exit 842 * 843 * Y GSBASE value at entry, must be restored in paranoid_exit 844 */ 845SYM_CODE_START_LOCAL(paranoid_entry) 846 UNWIND_HINT_FUNC 847 cld 848 PUSH_AND_CLEAR_REGS save_ret=1 849 ENCODE_FRAME_POINTER 8 850 851 /* 852 * Always stash CR3 in %r14. This value will be restored, 853 * verbatim, at exit. Needed if paranoid_entry interrupted 854 * another entry that already switched to the user CR3 value 855 * but has not yet returned to userspace. 856 * 857 * This is also why CS (stashed in the "iret frame" by the 858 * hardware at entry) can not be used: this may be a return 859 * to kernel code, but with a user CR3 value. 860 * 861 * Switching CR3 does not depend on kernel GSBASE so it can 862 * be done before switching to the kernel GSBASE. This is 863 * required for FSGSBASE because the kernel GSBASE has to 864 * be retrieved from a kernel internal table. 865 */ 866 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 867 868 /* 869 * Handling GSBASE depends on the availability of FSGSBASE. 870 * 871 * Without FSGSBASE the kernel enforces that negative GSBASE 872 * values indicate kernel GSBASE. With FSGSBASE no assumptions 873 * can be made about the GSBASE value when entering from user 874 * space. 875 */ 876 ALTERNATIVE "jmp .Lparanoid_entry_checkgs", "", X86_FEATURE_FSGSBASE 877 878 /* 879 * Read the current GSBASE and store it in %rbx unconditionally, 880 * retrieve and set the current CPUs kernel GSBASE. The stored value 881 * has to be restored in paranoid_exit unconditionally. 882 * 883 * The unconditional write to GS base below ensures that no subsequent 884 * loads based on a mispredicted GS base can happen, therefore no LFENCE 885 * is needed here. 886 */ 887 SAVE_AND_SET_GSBASE scratch_reg=%rax save_reg=%rbx 888 ret 889 890.Lparanoid_entry_checkgs: 891 /* EBX = 1 -> kernel GSBASE active, no restore required */ 892 movl $1, %ebx 893 /* 894 * The kernel-enforced convention is a negative GSBASE indicates 895 * a kernel value. No SWAPGS needed on entry and exit. 896 */ 897 movl $MSR_GS_BASE, %ecx 898 rdmsr 899 testl %edx, %edx 900 jns .Lparanoid_entry_swapgs 901 ret 902 903.Lparanoid_entry_swapgs: 904 swapgs 905 906 /* 907 * The above SAVE_AND_SWITCH_TO_KERNEL_CR3 macro doesn't do an 908 * unconditional CR3 write, even in the PTI case. So do an lfence 909 * to prevent GS speculation, regardless of whether PTI is enabled. 910 */ 911 FENCE_SWAPGS_KERNEL_ENTRY 912 913 /* EBX = 0 -> SWAPGS required on exit */ 914 xorl %ebx, %ebx 915 ret 916SYM_CODE_END(paranoid_entry) 917 918/* 919 * "Paranoid" exit path from exception stack. This is invoked 920 * only on return from non-NMI IST interrupts that came 921 * from kernel space. 922 * 923 * We may be returning to very strange contexts (e.g. very early 924 * in syscall entry), so checking for preemption here would 925 * be complicated. Fortunately, there's no good reason to try 926 * to handle preemption here. 927 * 928 * R/EBX contains the GSBASE related information depending on the 929 * availability of the FSGSBASE instructions: 930 * 931 * FSGSBASE R/EBX 932 * N 0 -> SWAPGS on exit 933 * 1 -> no SWAPGS on exit 934 * 935 * Y User space GSBASE, must be restored unconditionally 936 */ 937SYM_CODE_START_LOCAL(paranoid_exit) 938 UNWIND_HINT_REGS 939 /* 940 * The order of operations is important. RESTORE_CR3 requires 941 * kernel GSBASE. 942 * 943 * NB to anyone to try to optimize this code: this code does 944 * not execute at all for exceptions from user mode. Those 945 * exceptions go through error_exit instead. 946 */ 947 RESTORE_CR3 scratch_reg=%rax save_reg=%r14 948 949 /* Handle the three GSBASE cases */ 950 ALTERNATIVE "jmp .Lparanoid_exit_checkgs", "", X86_FEATURE_FSGSBASE 951 952 /* With FSGSBASE enabled, unconditionally restore GSBASE */ 953 wrgsbase %rbx 954 jmp restore_regs_and_return_to_kernel 955 956.Lparanoid_exit_checkgs: 957 /* On non-FSGSBASE systems, conditionally do SWAPGS */ 958 testl %ebx, %ebx 959 jnz restore_regs_and_return_to_kernel 960 961 /* We are returning to a context with user GSBASE */ 962 swapgs 963 jmp restore_regs_and_return_to_kernel 964SYM_CODE_END(paranoid_exit) 965 966/* 967 * Save all registers in pt_regs, and switch GS if needed. 968 */ 969SYM_CODE_START_LOCAL(error_entry) 970 UNWIND_HINT_FUNC 971 cld 972 PUSH_AND_CLEAR_REGS save_ret=1 973 ENCODE_FRAME_POINTER 8 974 testb $3, CS+8(%rsp) 975 jz .Lerror_kernelspace 976 977 /* 978 * We entered from user mode or we're pretending to have entered 979 * from user mode due to an IRET fault. 980 */ 981 SWAPGS 982 FENCE_SWAPGS_USER_ENTRY 983 /* We have user CR3. Change to kernel CR3. */ 984 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 985 986.Lerror_entry_from_usermode_after_swapgs: 987 /* Put us onto the real thread stack. */ 988 popq %r12 /* save return addr in %12 */ 989 movq %rsp, %rdi /* arg0 = pt_regs pointer */ 990 call sync_regs 991 movq %rax, %rsp /* switch stack */ 992 ENCODE_FRAME_POINTER 993 pushq %r12 994 ret 995 996.Lerror_entry_done_lfence: 997 FENCE_SWAPGS_KERNEL_ENTRY 998.Lerror_entry_done: 999 ret 1000 1001 /* 1002 * There are two places in the kernel that can potentially fault with 1003 * usergs. Handle them here. B stepping K8s sometimes report a 1004 * truncated RIP for IRET exceptions returning to compat mode. Check 1005 * for these here too. 1006 */ 1007.Lerror_kernelspace: 1008 leaq native_irq_return_iret(%rip), %rcx 1009 cmpq %rcx, RIP+8(%rsp) 1010 je .Lerror_bad_iret 1011 movl %ecx, %eax /* zero extend */ 1012 cmpq %rax, RIP+8(%rsp) 1013 je .Lbstep_iret 1014 cmpq $.Lgs_change, RIP+8(%rsp) 1015 jne .Lerror_entry_done_lfence 1016 1017 /* 1018 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up 1019 * gsbase and proceed. We'll fix up the exception and land in 1020 * .Lgs_change's error handler with kernel gsbase. 1021 */ 1022 SWAPGS 1023 FENCE_SWAPGS_USER_ENTRY 1024 jmp .Lerror_entry_done 1025 1026.Lbstep_iret: 1027 /* Fix truncated RIP */ 1028 movq %rcx, RIP+8(%rsp) 1029 /* fall through */ 1030 1031.Lerror_bad_iret: 1032 /* 1033 * We came from an IRET to user mode, so we have user 1034 * gsbase and CR3. Switch to kernel gsbase and CR3: 1035 */ 1036 SWAPGS 1037 FENCE_SWAPGS_USER_ENTRY 1038 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1039 1040 /* 1041 * Pretend that the exception came from user mode: set up pt_regs 1042 * as if we faulted immediately after IRET. 1043 */ 1044 mov %rsp, %rdi 1045 call fixup_bad_iret 1046 mov %rax, %rsp 1047 jmp .Lerror_entry_from_usermode_after_swapgs 1048SYM_CODE_END(error_entry) 1049 1050SYM_CODE_START_LOCAL(error_return) 1051 UNWIND_HINT_REGS 1052 DEBUG_ENTRY_ASSERT_IRQS_OFF 1053 testb $3, CS(%rsp) 1054 jz restore_regs_and_return_to_kernel 1055 jmp swapgs_restore_regs_and_return_to_usermode 1056SYM_CODE_END(error_return) 1057 1058/* 1059 * Runs on exception stack. Xen PV does not go through this path at all, 1060 * so we can use real assembly here. 1061 * 1062 * Registers: 1063 * %r14: Used to save/restore the CR3 of the interrupted context 1064 * when PAGE_TABLE_ISOLATION is in use. Do not clobber. 1065 */ 1066SYM_CODE_START(asm_exc_nmi) 1067 UNWIND_HINT_IRET_REGS 1068 1069 /* 1070 * We allow breakpoints in NMIs. If a breakpoint occurs, then 1071 * the iretq it performs will take us out of NMI context. 1072 * This means that we can have nested NMIs where the next 1073 * NMI is using the top of the stack of the previous NMI. We 1074 * can't let it execute because the nested NMI will corrupt the 1075 * stack of the previous NMI. NMI handlers are not re-entrant 1076 * anyway. 1077 * 1078 * To handle this case we do the following: 1079 * Check the a special location on the stack that contains 1080 * a variable that is set when NMIs are executing. 1081 * The interrupted task's stack is also checked to see if it 1082 * is an NMI stack. 1083 * If the variable is not set and the stack is not the NMI 1084 * stack then: 1085 * o Set the special variable on the stack 1086 * o Copy the interrupt frame into an "outermost" location on the 1087 * stack 1088 * o Copy the interrupt frame into an "iret" location on the stack 1089 * o Continue processing the NMI 1090 * If the variable is set or the previous stack is the NMI stack: 1091 * o Modify the "iret" location to jump to the repeat_nmi 1092 * o return back to the first NMI 1093 * 1094 * Now on exit of the first NMI, we first clear the stack variable 1095 * The NMI stack will tell any nested NMIs at that point that it is 1096 * nested. Then we pop the stack normally with iret, and if there was 1097 * a nested NMI that updated the copy interrupt stack frame, a 1098 * jump will be made to the repeat_nmi code that will handle the second 1099 * NMI. 1100 * 1101 * However, espfix prevents us from directly returning to userspace 1102 * with a single IRET instruction. Similarly, IRET to user mode 1103 * can fault. We therefore handle NMIs from user space like 1104 * other IST entries. 1105 */ 1106 1107 ASM_CLAC 1108 1109 /* Use %rdx as our temp variable throughout */ 1110 pushq %rdx 1111 1112 testb $3, CS-RIP+8(%rsp) 1113 jz .Lnmi_from_kernel 1114 1115 /* 1116 * NMI from user mode. We need to run on the thread stack, but we 1117 * can't go through the normal entry paths: NMIs are masked, and 1118 * we don't want to enable interrupts, because then we'll end 1119 * up in an awkward situation in which IRQs are on but NMIs 1120 * are off. 1121 * 1122 * We also must not push anything to the stack before switching 1123 * stacks lest we corrupt the "NMI executing" variable. 1124 */ 1125 1126 swapgs 1127 cld 1128 FENCE_SWAPGS_USER_ENTRY 1129 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx 1130 movq %rsp, %rdx 1131 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 1132 UNWIND_HINT_IRET_REGS base=%rdx offset=8 1133 pushq 5*8(%rdx) /* pt_regs->ss */ 1134 pushq 4*8(%rdx) /* pt_regs->rsp */ 1135 pushq 3*8(%rdx) /* pt_regs->flags */ 1136 pushq 2*8(%rdx) /* pt_regs->cs */ 1137 pushq 1*8(%rdx) /* pt_regs->rip */ 1138 UNWIND_HINT_IRET_REGS 1139 pushq $-1 /* pt_regs->orig_ax */ 1140 PUSH_AND_CLEAR_REGS rdx=(%rdx) 1141 ENCODE_FRAME_POINTER 1142 1143 /* 1144 * At this point we no longer need to worry about stack damage 1145 * due to nesting -- we're on the normal thread stack and we're 1146 * done with the NMI stack. 1147 */ 1148 1149 movq %rsp, %rdi 1150 movq $-1, %rsi 1151 call exc_nmi 1152 1153 /* 1154 * Return back to user mode. We must *not* do the normal exit 1155 * work, because we don't want to enable interrupts. 1156 */ 1157 jmp swapgs_restore_regs_and_return_to_usermode 1158 1159.Lnmi_from_kernel: 1160 /* 1161 * Here's what our stack frame will look like: 1162 * +---------------------------------------------------------+ 1163 * | original SS | 1164 * | original Return RSP | 1165 * | original RFLAGS | 1166 * | original CS | 1167 * | original RIP | 1168 * +---------------------------------------------------------+ 1169 * | temp storage for rdx | 1170 * +---------------------------------------------------------+ 1171 * | "NMI executing" variable | 1172 * +---------------------------------------------------------+ 1173 * | iret SS } Copied from "outermost" frame | 1174 * | iret Return RSP } on each loop iteration; overwritten | 1175 * | iret RFLAGS } by a nested NMI to force another | 1176 * | iret CS } iteration if needed. | 1177 * | iret RIP } | 1178 * +---------------------------------------------------------+ 1179 * | outermost SS } initialized in first_nmi; | 1180 * | outermost Return RSP } will not be changed before | 1181 * | outermost RFLAGS } NMI processing is done. | 1182 * | outermost CS } Copied to "iret" frame on each | 1183 * | outermost RIP } iteration. | 1184 * +---------------------------------------------------------+ 1185 * | pt_regs | 1186 * +---------------------------------------------------------+ 1187 * 1188 * The "original" frame is used by hardware. Before re-enabling 1189 * NMIs, we need to be done with it, and we need to leave enough 1190 * space for the asm code here. 1191 * 1192 * We return by executing IRET while RSP points to the "iret" frame. 1193 * That will either return for real or it will loop back into NMI 1194 * processing. 1195 * 1196 * The "outermost" frame is copied to the "iret" frame on each 1197 * iteration of the loop, so each iteration starts with the "iret" 1198 * frame pointing to the final return target. 1199 */ 1200 1201 /* 1202 * Determine whether we're a nested NMI. 1203 * 1204 * If we interrupted kernel code between repeat_nmi and 1205 * end_repeat_nmi, then we are a nested NMI. We must not 1206 * modify the "iret" frame because it's being written by 1207 * the outer NMI. That's okay; the outer NMI handler is 1208 * about to about to call exc_nmi() anyway, so we can just 1209 * resume the outer NMI. 1210 */ 1211 1212 movq $repeat_nmi, %rdx 1213 cmpq 8(%rsp), %rdx 1214 ja 1f 1215 movq $end_repeat_nmi, %rdx 1216 cmpq 8(%rsp), %rdx 1217 ja nested_nmi_out 12181: 1219 1220 /* 1221 * Now check "NMI executing". If it's set, then we're nested. 1222 * This will not detect if we interrupted an outer NMI just 1223 * before IRET. 1224 */ 1225 cmpl $1, -8(%rsp) 1226 je nested_nmi 1227 1228 /* 1229 * Now test if the previous stack was an NMI stack. This covers 1230 * the case where we interrupt an outer NMI after it clears 1231 * "NMI executing" but before IRET. We need to be careful, though: 1232 * there is one case in which RSP could point to the NMI stack 1233 * despite there being no NMI active: naughty userspace controls 1234 * RSP at the very beginning of the SYSCALL targets. We can 1235 * pull a fast one on naughty userspace, though: we program 1236 * SYSCALL to mask DF, so userspace cannot cause DF to be set 1237 * if it controls the kernel's RSP. We set DF before we clear 1238 * "NMI executing". 1239 */ 1240 lea 6*8(%rsp), %rdx 1241 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ 1242 cmpq %rdx, 4*8(%rsp) 1243 /* If the stack pointer is above the NMI stack, this is a normal NMI */ 1244 ja first_nmi 1245 1246 subq $EXCEPTION_STKSZ, %rdx 1247 cmpq %rdx, 4*8(%rsp) 1248 /* If it is below the NMI stack, it is a normal NMI */ 1249 jb first_nmi 1250 1251 /* Ah, it is within the NMI stack. */ 1252 1253 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) 1254 jz first_nmi /* RSP was user controlled. */ 1255 1256 /* This is a nested NMI. */ 1257 1258nested_nmi: 1259 /* 1260 * Modify the "iret" frame to point to repeat_nmi, forcing another 1261 * iteration of NMI handling. 1262 */ 1263 subq $8, %rsp 1264 leaq -10*8(%rsp), %rdx 1265 pushq $__KERNEL_DS 1266 pushq %rdx 1267 pushfq 1268 pushq $__KERNEL_CS 1269 pushq $repeat_nmi 1270 1271 /* Put stack back */ 1272 addq $(6*8), %rsp 1273 1274nested_nmi_out: 1275 popq %rdx 1276 1277 /* We are returning to kernel mode, so this cannot result in a fault. */ 1278 iretq 1279 1280first_nmi: 1281 /* Restore rdx. */ 1282 movq (%rsp), %rdx 1283 1284 /* Make room for "NMI executing". */ 1285 pushq $0 1286 1287 /* Leave room for the "iret" frame */ 1288 subq $(5*8), %rsp 1289 1290 /* Copy the "original" frame to the "outermost" frame */ 1291 .rept 5 1292 pushq 11*8(%rsp) 1293 .endr 1294 UNWIND_HINT_IRET_REGS 1295 1296 /* Everything up to here is safe from nested NMIs */ 1297 1298#ifdef CONFIG_DEBUG_ENTRY 1299 /* 1300 * For ease of testing, unmask NMIs right away. Disabled by 1301 * default because IRET is very expensive. 1302 */ 1303 pushq $0 /* SS */ 1304 pushq %rsp /* RSP (minus 8 because of the previous push) */ 1305 addq $8, (%rsp) /* Fix up RSP */ 1306 pushfq /* RFLAGS */ 1307 pushq $__KERNEL_CS /* CS */ 1308 pushq $1f /* RIP */ 1309 iretq /* continues at repeat_nmi below */ 1310 UNWIND_HINT_IRET_REGS 13111: 1312#endif 1313 1314repeat_nmi: 1315 /* 1316 * If there was a nested NMI, the first NMI's iret will return 1317 * here. But NMIs are still enabled and we can take another 1318 * nested NMI. The nested NMI checks the interrupted RIP to see 1319 * if it is between repeat_nmi and end_repeat_nmi, and if so 1320 * it will just return, as we are about to repeat an NMI anyway. 1321 * This makes it safe to copy to the stack frame that a nested 1322 * NMI will update. 1323 * 1324 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if 1325 * we're repeating an NMI, gsbase has the same value that it had on 1326 * the first iteration. paranoid_entry will load the kernel 1327 * gsbase if needed before we call exc_nmi(). "NMI executing" 1328 * is zero. 1329 */ 1330 movq $1, 10*8(%rsp) /* Set "NMI executing". */ 1331 1332 /* 1333 * Copy the "outermost" frame to the "iret" frame. NMIs that nest 1334 * here must not modify the "iret" frame while we're writing to 1335 * it or it will end up containing garbage. 1336 */ 1337 addq $(10*8), %rsp 1338 .rept 5 1339 pushq -6*8(%rsp) 1340 .endr 1341 subq $(5*8), %rsp 1342end_repeat_nmi: 1343 1344 /* 1345 * Everything below this point can be preempted by a nested NMI. 1346 * If this happens, then the inner NMI will change the "iret" 1347 * frame to point back to repeat_nmi. 1348 */ 1349 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1350 1351 /* 1352 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit 1353 * as we should not be calling schedule in NMI context. 1354 * Even with normal interrupts enabled. An NMI should not be 1355 * setting NEED_RESCHED or anything that normal interrupts and 1356 * exceptions might do. 1357 */ 1358 call paranoid_entry 1359 UNWIND_HINT_REGS 1360 1361 movq %rsp, %rdi 1362 movq $-1, %rsi 1363 call exc_nmi 1364 1365 /* Always restore stashed CR3 value (see paranoid_entry) */ 1366 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 1367 1368 /* 1369 * The above invocation of paranoid_entry stored the GSBASE 1370 * related information in R/EBX depending on the availability 1371 * of FSGSBASE. 1372 * 1373 * If FSGSBASE is enabled, restore the saved GSBASE value 1374 * unconditionally, otherwise take the conditional SWAPGS path. 1375 */ 1376 ALTERNATIVE "jmp nmi_no_fsgsbase", "", X86_FEATURE_FSGSBASE 1377 1378 wrgsbase %rbx 1379 jmp nmi_restore 1380 1381nmi_no_fsgsbase: 1382 /* EBX == 0 -> invoke SWAPGS */ 1383 testl %ebx, %ebx 1384 jnz nmi_restore 1385 1386nmi_swapgs: 1387 swapgs 1388 1389nmi_restore: 1390 POP_REGS 1391 1392 /* 1393 * Skip orig_ax and the "outermost" frame to point RSP at the "iret" 1394 * at the "iret" frame. 1395 */ 1396 addq $6*8, %rsp 1397 1398 /* 1399 * Clear "NMI executing". Set DF first so that we can easily 1400 * distinguish the remaining code between here and IRET from 1401 * the SYSCALL entry and exit paths. 1402 * 1403 * We arguably should just inspect RIP instead, but I (Andy) wrote 1404 * this code when I had the misapprehension that Xen PV supported 1405 * NMIs, and Xen PV would break that approach. 1406 */ 1407 std 1408 movq $0, 5*8(%rsp) /* clear "NMI executing" */ 1409 1410 /* 1411 * iretq reads the "iret" frame and exits the NMI stack in a 1412 * single instruction. We are returning to kernel mode, so this 1413 * cannot result in a fault. Similarly, we don't need to worry 1414 * about espfix64 on the way back to kernel mode. 1415 */ 1416 iretq 1417SYM_CODE_END(asm_exc_nmi) 1418 1419#ifndef CONFIG_IA32_EMULATION 1420/* 1421 * This handles SYSCALL from 32-bit code. There is no way to program 1422 * MSRs to fully disable 32-bit SYSCALL. 1423 */ 1424SYM_CODE_START(ignore_sysret) 1425 UNWIND_HINT_EMPTY 1426 mov $-ENOSYS, %eax 1427 sysretl 1428SYM_CODE_END(ignore_sysret) 1429#endif 1430 1431.pushsection .text, "ax" 1432SYM_CODE_START(rewind_stack_do_exit) 1433 UNWIND_HINT_FUNC 1434 /* Prevent any naive code from trying to unwind to our caller. */ 1435 xorl %ebp, %ebp 1436 1437 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax 1438 leaq -PTREGS_SIZE(%rax), %rsp 1439 UNWIND_HINT_REGS 1440 1441 call do_exit 1442SYM_CODE_END(rewind_stack_do_exit) 1443.popsection 1444