1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86_64/entry.S 4 * 5 * Copyright (C) 1991, 1992 Linus Torvalds 6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs 7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 8 * 9 * entry.S contains the system-call and fault low-level handling routines. 10 * 11 * Some of this is documented in Documentation/x86/entry_64.txt 12 * 13 * A note on terminology: 14 * - iret frame: Architecture defined interrupt frame from SS to RIP 15 * at the top of the kernel process stack. 16 * 17 * Some macro usage: 18 * - ENTRY/END: Define functions in the symbol table. 19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging. 20 * - idtentry: Define exception entry points. 21 */ 22#include <linux/linkage.h> 23#include <asm/segment.h> 24#include <asm/cache.h> 25#include <asm/errno.h> 26#include <asm/asm-offsets.h> 27#include <asm/msr.h> 28#include <asm/unistd.h> 29#include <asm/thread_info.h> 30#include <asm/hw_irq.h> 31#include <asm/page_types.h> 32#include <asm/irqflags.h> 33#include <asm/paravirt.h> 34#include <asm/percpu.h> 35#include <asm/asm.h> 36#include <asm/smap.h> 37#include <asm/pgtable_types.h> 38#include <asm/export.h> 39#include <asm/frame.h> 40#include <asm/nospec-branch.h> 41#include <linux/err.h> 42 43#include "calling.h" 44 45.code64 46.section .entry.text, "ax" 47 48#ifdef CONFIG_PARAVIRT 49ENTRY(native_usergs_sysret64) 50 UNWIND_HINT_EMPTY 51 swapgs 52 sysretq 53END(native_usergs_sysret64) 54#endif /* CONFIG_PARAVIRT */ 55 56.macro TRACE_IRQS_FLAGS flags:req 57#ifdef CONFIG_TRACE_IRQFLAGS 58 bt $9, \flags /* interrupts off? */ 59 jnc 1f 60 TRACE_IRQS_ON 611: 62#endif 63.endm 64 65.macro TRACE_IRQS_IRETQ 66 TRACE_IRQS_FLAGS EFLAGS(%rsp) 67.endm 68 69/* 70 * When dynamic function tracer is enabled it will add a breakpoint 71 * to all locations that it is about to modify, sync CPUs, update 72 * all the code, sync CPUs, then remove the breakpoints. In this time 73 * if lockdep is enabled, it might jump back into the debug handler 74 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). 75 * 76 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to 77 * make sure the stack pointer does not get reset back to the top 78 * of the debug stack, and instead just reuses the current stack. 79 */ 80#if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) 81 82.macro TRACE_IRQS_OFF_DEBUG 83 call debug_stack_set_zero 84 TRACE_IRQS_OFF 85 call debug_stack_reset 86.endm 87 88.macro TRACE_IRQS_ON_DEBUG 89 call debug_stack_set_zero 90 TRACE_IRQS_ON 91 call debug_stack_reset 92.endm 93 94.macro TRACE_IRQS_IRETQ_DEBUG 95 bt $9, EFLAGS(%rsp) /* interrupts off? */ 96 jnc 1f 97 TRACE_IRQS_ON_DEBUG 981: 99.endm 100 101#else 102# define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF 103# define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON 104# define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ 105#endif 106 107/* 108 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. 109 * 110 * This is the only entry point used for 64-bit system calls. The 111 * hardware interface is reasonably well designed and the register to 112 * argument mapping Linux uses fits well with the registers that are 113 * available when SYSCALL is used. 114 * 115 * SYSCALL instructions can be found inlined in libc implementations as 116 * well as some other programs and libraries. There are also a handful 117 * of SYSCALL instructions in the vDSO used, for example, as a 118 * clock_gettimeofday fallback. 119 * 120 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, 121 * then loads new ss, cs, and rip from previously programmed MSRs. 122 * rflags gets masked by a value from another MSR (so CLD and CLAC 123 * are not needed). SYSCALL does not save anything on the stack 124 * and does not change rsp. 125 * 126 * Registers on entry: 127 * rax system call number 128 * rcx return address 129 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) 130 * rdi arg0 131 * rsi arg1 132 * rdx arg2 133 * r10 arg3 (needs to be moved to rcx to conform to C ABI) 134 * r8 arg4 135 * r9 arg5 136 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) 137 * 138 * Only called from user space. 139 * 140 * When user can change pt_regs->foo always force IRET. That is because 141 * it deals with uncanonical addresses better. SYSRET has trouble 142 * with them due to bugs in both AMD and Intel CPUs. 143 */ 144 145 .pushsection .entry_trampoline, "ax" 146 147/* 148 * The code in here gets remapped into cpu_entry_area's trampoline. This means 149 * that the assembler and linker have the wrong idea as to where this code 150 * lives (and, in fact, it's mapped more than once, so it's not even at a 151 * fixed address). So we can't reference any symbols outside the entry 152 * trampoline and expect it to work. 153 * 154 * Instead, we carefully abuse %rip-relative addressing. 155 * _entry_trampoline(%rip) refers to the start of the remapped) entry 156 * trampoline. We can thus find cpu_entry_area with this macro: 157 */ 158 159#define CPU_ENTRY_AREA \ 160 _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip) 161 162/* The top word of the SYSENTER stack is hot and is usable as scratch space. */ 163#define RSP_SCRATCH CPU_ENTRY_AREA_entry_stack + \ 164 SIZEOF_entry_stack - 8 + CPU_ENTRY_AREA 165 166ENTRY(entry_SYSCALL_64_trampoline) 167 UNWIND_HINT_EMPTY 168 swapgs 169 170 /* Stash the user RSP. */ 171 movq %rsp, RSP_SCRATCH 172 173 /* Note: using %rsp as a scratch reg. */ 174 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp 175 176 /* Load the top of the task stack into RSP */ 177 movq CPU_ENTRY_AREA_tss + TSS_sp1 + CPU_ENTRY_AREA, %rsp 178 179 /* Start building the simulated IRET frame. */ 180 pushq $__USER_DS /* pt_regs->ss */ 181 pushq RSP_SCRATCH /* pt_regs->sp */ 182 pushq %r11 /* pt_regs->flags */ 183 pushq $__USER_CS /* pt_regs->cs */ 184 pushq %rcx /* pt_regs->ip */ 185 186 /* 187 * x86 lacks a near absolute jump, and we can't jump to the real 188 * entry text with a relative jump. We could push the target 189 * address and then use retq, but this destroys the pipeline on 190 * many CPUs (wasting over 20 cycles on Sandy Bridge). Instead, 191 * spill RDI and restore it in a second-stage trampoline. 192 */ 193 pushq %rdi 194 movq $entry_SYSCALL_64_stage2, %rdi 195 JMP_NOSPEC %rdi 196END(entry_SYSCALL_64_trampoline) 197 198 .popsection 199 200ENTRY(entry_SYSCALL_64_stage2) 201 UNWIND_HINT_EMPTY 202 popq %rdi 203 jmp entry_SYSCALL_64_after_hwframe 204END(entry_SYSCALL_64_stage2) 205 206ENTRY(entry_SYSCALL_64) 207 UNWIND_HINT_EMPTY 208 /* 209 * Interrupts are off on entry. 210 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, 211 * it is too small to ever cause noticeable irq latency. 212 */ 213 214 swapgs 215 /* 216 * This path is not taken when PAGE_TABLE_ISOLATION is disabled so it 217 * is not required to switch CR3. 218 */ 219 movq %rsp, PER_CPU_VAR(rsp_scratch) 220 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 221 222 /* Construct struct pt_regs on stack */ 223 pushq $__USER_DS /* pt_regs->ss */ 224 pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */ 225 pushq %r11 /* pt_regs->flags */ 226 pushq $__USER_CS /* pt_regs->cs */ 227 pushq %rcx /* pt_regs->ip */ 228GLOBAL(entry_SYSCALL_64_after_hwframe) 229 pushq %rax /* pt_regs->orig_ax */ 230 pushq %rdi /* pt_regs->di */ 231 pushq %rsi /* pt_regs->si */ 232 pushq %rdx /* pt_regs->dx */ 233 pushq %rcx /* pt_regs->cx */ 234 pushq $-ENOSYS /* pt_regs->ax */ 235 pushq %r8 /* pt_regs->r8 */ 236 pushq %r9 /* pt_regs->r9 */ 237 pushq %r10 /* pt_regs->r10 */ 238 pushq %r11 /* pt_regs->r11 */ 239 sub $(6*8), %rsp /* pt_regs->bp, bx, r12-15 not saved */ 240 UNWIND_HINT_REGS extra=0 241 242 TRACE_IRQS_OFF 243 244 /* 245 * If we need to do entry work or if we guess we'll need to do 246 * exit work, go straight to the slow path. 247 */ 248 movq PER_CPU_VAR(current_task), %r11 249 testl $_TIF_WORK_SYSCALL_ENTRY|_TIF_ALLWORK_MASK, TASK_TI_flags(%r11) 250 jnz entry_SYSCALL64_slow_path 251 252entry_SYSCALL_64_fastpath: 253 /* 254 * Easy case: enable interrupts and issue the syscall. If the syscall 255 * needs pt_regs, we'll call a stub that disables interrupts again 256 * and jumps to the slow path. 257 */ 258 TRACE_IRQS_ON 259 ENABLE_INTERRUPTS(CLBR_NONE) 260#if __SYSCALL_MASK == ~0 261 cmpq $__NR_syscall_max, %rax 262#else 263 andl $__SYSCALL_MASK, %eax 264 cmpl $__NR_syscall_max, %eax 265#endif 266 ja 1f /* return -ENOSYS (already in pt_regs->ax) */ 267 movq %r10, %rcx 268 269 /* 270 * This call instruction is handled specially in stub_ptregs_64. 271 * It might end up jumping to the slow path. If it jumps, RAX 272 * and all argument registers are clobbered. 273 */ 274#ifdef CONFIG_RETPOLINE 275 movq sys_call_table(, %rax, 8), %rax 276 call __x86_indirect_thunk_rax 277#else 278 call *sys_call_table(, %rax, 8) 279#endif 280.Lentry_SYSCALL_64_after_fastpath_call: 281 282 movq %rax, RAX(%rsp) 2831: 284 285 /* 286 * If we get here, then we know that pt_regs is clean for SYSRET64. 287 * If we see that no exit work is required (which we are required 288 * to check with IRQs off), then we can go straight to SYSRET64. 289 */ 290 DISABLE_INTERRUPTS(CLBR_ANY) 291 TRACE_IRQS_OFF 292 movq PER_CPU_VAR(current_task), %r11 293 testl $_TIF_ALLWORK_MASK, TASK_TI_flags(%r11) 294 jnz 1f 295 296 LOCKDEP_SYS_EXIT 297 TRACE_IRQS_ON /* user mode is traced as IRQs on */ 298 movq RIP(%rsp), %rcx 299 movq EFLAGS(%rsp), %r11 300 addq $6*8, %rsp /* skip extra regs -- they were preserved */ 301 UNWIND_HINT_EMPTY 302 jmp .Lpop_c_regs_except_rcx_r11_and_sysret 303 3041: 305 /* 306 * The fast path looked good when we started, but something changed 307 * along the way and we need to switch to the slow path. Calling 308 * raise(3) will trigger this, for example. IRQs are off. 309 */ 310 TRACE_IRQS_ON 311 ENABLE_INTERRUPTS(CLBR_ANY) 312 SAVE_EXTRA_REGS 313 movq %rsp, %rdi 314 call syscall_return_slowpath /* returns with IRQs disabled */ 315 jmp return_from_SYSCALL_64 316 317entry_SYSCALL64_slow_path: 318 /* IRQs are off. */ 319 SAVE_EXTRA_REGS 320 movq %rsp, %rdi 321 call do_syscall_64 /* returns with IRQs disabled */ 322 323return_from_SYSCALL_64: 324 TRACE_IRQS_IRETQ /* we're about to change IF */ 325 326 /* 327 * Try to use SYSRET instead of IRET if we're returning to 328 * a completely clean 64-bit userspace context. If we're not, 329 * go to the slow exit path. 330 */ 331 movq RCX(%rsp), %rcx 332 movq RIP(%rsp), %r11 333 334 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ 335 jne swapgs_restore_regs_and_return_to_usermode 336 337 /* 338 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP 339 * in kernel space. This essentially lets the user take over 340 * the kernel, since userspace controls RSP. 341 * 342 * If width of "canonical tail" ever becomes variable, this will need 343 * to be updated to remain correct on both old and new CPUs. 344 * 345 * Change top bits to match most significant bit (47th or 56th bit 346 * depending on paging mode) in the address. 347 */ 348 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 349 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 350 351 /* If this changed %rcx, it was not canonical */ 352 cmpq %rcx, %r11 353 jne swapgs_restore_regs_and_return_to_usermode 354 355 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ 356 jne swapgs_restore_regs_and_return_to_usermode 357 358 movq R11(%rsp), %r11 359 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ 360 jne swapgs_restore_regs_and_return_to_usermode 361 362 /* 363 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot 364 * restore RF properly. If the slowpath sets it for whatever reason, we 365 * need to restore it correctly. 366 * 367 * SYSRET can restore TF, but unlike IRET, restoring TF results in a 368 * trap from userspace immediately after SYSRET. This would cause an 369 * infinite loop whenever #DB happens with register state that satisfies 370 * the opportunistic SYSRET conditions. For example, single-stepping 371 * this user code: 372 * 373 * movq $stuck_here, %rcx 374 * pushfq 375 * popq %r11 376 * stuck_here: 377 * 378 * would never get past 'stuck_here'. 379 */ 380 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 381 jnz swapgs_restore_regs_and_return_to_usermode 382 383 /* nothing to check for RSP */ 384 385 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ 386 jne swapgs_restore_regs_and_return_to_usermode 387 388 /* 389 * We win! This label is here just for ease of understanding 390 * perf profiles. Nothing jumps here. 391 */ 392syscall_return_via_sysret: 393 /* rcx and r11 are already restored (see code above) */ 394 UNWIND_HINT_EMPTY 395 POP_EXTRA_REGS 396.Lpop_c_regs_except_rcx_r11_and_sysret: 397 popq %rsi /* skip r11 */ 398 popq %r10 399 popq %r9 400 popq %r8 401 popq %rax 402 popq %rsi /* skip rcx */ 403 popq %rdx 404 popq %rsi 405 406 /* 407 * Now all regs are restored except RSP and RDI. 408 * Save old stack pointer and switch to trampoline stack. 409 */ 410 movq %rsp, %rdi 411 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 412 413 pushq RSP-RDI(%rdi) /* RSP */ 414 pushq (%rdi) /* RDI */ 415 416 /* 417 * We are on the trampoline stack. All regs except RDI are live. 418 * We can do future final exit work right here. 419 */ 420 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 421 422 popq %rdi 423 popq %rsp 424 USERGS_SYSRET64 425END(entry_SYSCALL_64) 426 427ENTRY(stub_ptregs_64) 428 /* 429 * Syscalls marked as needing ptregs land here. 430 * If we are on the fast path, we need to save the extra regs, 431 * which we achieve by trying again on the slow path. If we are on 432 * the slow path, the extra regs are already saved. 433 * 434 * RAX stores a pointer to the C function implementing the syscall. 435 * IRQs are on. 436 */ 437 cmpq $.Lentry_SYSCALL_64_after_fastpath_call, (%rsp) 438 jne 1f 439 440 /* 441 * Called from fast path -- disable IRQs again, pop return address 442 * and jump to slow path 443 */ 444 DISABLE_INTERRUPTS(CLBR_ANY) 445 TRACE_IRQS_OFF 446 popq %rax 447 UNWIND_HINT_REGS extra=0 448 jmp entry_SYSCALL64_slow_path 449 4501: 451 JMP_NOSPEC %rax /* Called from C */ 452END(stub_ptregs_64) 453 454.macro ptregs_stub func 455ENTRY(ptregs_\func) 456 UNWIND_HINT_FUNC 457 leaq \func(%rip), %rax 458 jmp stub_ptregs_64 459END(ptregs_\func) 460.endm 461 462/* Instantiate ptregs_stub for each ptregs-using syscall */ 463#define __SYSCALL_64_QUAL_(sym) 464#define __SYSCALL_64_QUAL_ptregs(sym) ptregs_stub sym 465#define __SYSCALL_64(nr, sym, qual) __SYSCALL_64_QUAL_##qual(sym) 466#include <asm/syscalls_64.h> 467 468/* 469 * %rdi: prev task 470 * %rsi: next task 471 */ 472ENTRY(__switch_to_asm) 473 UNWIND_HINT_FUNC 474 /* 475 * Save callee-saved registers 476 * This must match the order in inactive_task_frame 477 */ 478 pushq %rbp 479 pushq %rbx 480 pushq %r12 481 pushq %r13 482 pushq %r14 483 pushq %r15 484 485 /* switch stack */ 486 movq %rsp, TASK_threadsp(%rdi) 487 movq TASK_threadsp(%rsi), %rsp 488 489#ifdef CONFIG_CC_STACKPROTECTOR 490 movq TASK_stack_canary(%rsi), %rbx 491 movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset 492#endif 493 494#ifdef CONFIG_RETPOLINE 495 /* 496 * When switching from a shallower to a deeper call stack 497 * the RSB may either underflow or use entries populated 498 * with userspace addresses. On CPUs where those concerns 499 * exist, overwrite the RSB with entries which capture 500 * speculative execution to prevent attack. 501 */ 502 /* Clobbers %rbx */ 503 FILL_RETURN_BUFFER RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW 504#endif 505 506 /* restore callee-saved registers */ 507 popq %r15 508 popq %r14 509 popq %r13 510 popq %r12 511 popq %rbx 512 popq %rbp 513 514 jmp __switch_to 515END(__switch_to_asm) 516 517/* 518 * A newly forked process directly context switches into this address. 519 * 520 * rax: prev task we switched from 521 * rbx: kernel thread func (NULL for user thread) 522 * r12: kernel thread arg 523 */ 524ENTRY(ret_from_fork) 525 UNWIND_HINT_EMPTY 526 movq %rax, %rdi 527 call schedule_tail /* rdi: 'prev' task parameter */ 528 529 testq %rbx, %rbx /* from kernel_thread? */ 530 jnz 1f /* kernel threads are uncommon */ 531 5322: 533 UNWIND_HINT_REGS 534 movq %rsp, %rdi 535 call syscall_return_slowpath /* returns with IRQs disabled */ 536 TRACE_IRQS_ON /* user mode is traced as IRQS on */ 537 jmp swapgs_restore_regs_and_return_to_usermode 538 5391: 540 /* kernel thread */ 541 movq %r12, %rdi 542 CALL_NOSPEC %rbx 543 /* 544 * A kernel thread is allowed to return here after successfully 545 * calling do_execve(). Exit to userspace to complete the execve() 546 * syscall. 547 */ 548 movq $0, RAX(%rsp) 549 jmp 2b 550END(ret_from_fork) 551 552/* 553 * Build the entry stubs with some assembler magic. 554 * We pack 1 stub into every 8-byte block. 555 */ 556 .align 8 557ENTRY(irq_entries_start) 558 vector=FIRST_EXTERNAL_VECTOR 559 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) 560 UNWIND_HINT_IRET_REGS 561 pushq $(~vector+0x80) /* Note: always in signed byte range */ 562 jmp common_interrupt 563 .align 8 564 vector=vector+1 565 .endr 566END(irq_entries_start) 567 568.macro DEBUG_ENTRY_ASSERT_IRQS_OFF 569#ifdef CONFIG_DEBUG_ENTRY 570 pushq %rax 571 SAVE_FLAGS(CLBR_RAX) 572 testl $X86_EFLAGS_IF, %eax 573 jz .Lokay_\@ 574 ud2 575.Lokay_\@: 576 popq %rax 577#endif 578.endm 579 580/* 581 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers 582 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone. 583 * Requires kernel GSBASE. 584 * 585 * The invariant is that, if irq_count != -1, then the IRQ stack is in use. 586 */ 587.macro ENTER_IRQ_STACK regs=1 old_rsp 588 DEBUG_ENTRY_ASSERT_IRQS_OFF 589 movq %rsp, \old_rsp 590 591 .if \regs 592 UNWIND_HINT_REGS base=\old_rsp 593 .endif 594 595 incl PER_CPU_VAR(irq_count) 596 jnz .Lirq_stack_push_old_rsp_\@ 597 598 /* 599 * Right now, if we just incremented irq_count to zero, we've 600 * claimed the IRQ stack but we haven't switched to it yet. 601 * 602 * If anything is added that can interrupt us here without using IST, 603 * it must be *extremely* careful to limit its stack usage. This 604 * could include kprobes and a hypothetical future IST-less #DB 605 * handler. 606 * 607 * The OOPS unwinder relies on the word at the top of the IRQ 608 * stack linking back to the previous RSP for the entire time we're 609 * on the IRQ stack. For this to work reliably, we need to write 610 * it before we actually move ourselves to the IRQ stack. 611 */ 612 613 movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8) 614 movq PER_CPU_VAR(irq_stack_ptr), %rsp 615 616#ifdef CONFIG_DEBUG_ENTRY 617 /* 618 * If the first movq above becomes wrong due to IRQ stack layout 619 * changes, the only way we'll notice is if we try to unwind right 620 * here. Assert that we set up the stack right to catch this type 621 * of bug quickly. 622 */ 623 cmpq -8(%rsp), \old_rsp 624 je .Lirq_stack_okay\@ 625 ud2 626 .Lirq_stack_okay\@: 627#endif 628 629.Lirq_stack_push_old_rsp_\@: 630 pushq \old_rsp 631 632 .if \regs 633 UNWIND_HINT_REGS indirect=1 634 .endif 635.endm 636 637/* 638 * Undoes ENTER_IRQ_STACK. 639 */ 640.macro LEAVE_IRQ_STACK regs=1 641 DEBUG_ENTRY_ASSERT_IRQS_OFF 642 /* We need to be off the IRQ stack before decrementing irq_count. */ 643 popq %rsp 644 645 .if \regs 646 UNWIND_HINT_REGS 647 .endif 648 649 /* 650 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming 651 * the irq stack but we're not on it. 652 */ 653 654 decl PER_CPU_VAR(irq_count) 655.endm 656 657/* 658 * Interrupt entry/exit. 659 * 660 * Interrupt entry points save only callee clobbered registers in fast path. 661 * 662 * Entry runs with interrupts off. 663 */ 664 665/* 0(%rsp): ~(interrupt number) */ 666 .macro interrupt func 667 cld 668 669 testb $3, CS-ORIG_RAX(%rsp) 670 jz 1f 671 SWAPGS 672 call switch_to_thread_stack 6731: 674 675 ALLOC_PT_GPREGS_ON_STACK 676 SAVE_C_REGS 677 SAVE_EXTRA_REGS 678 ENCODE_FRAME_POINTER 679 680 testb $3, CS(%rsp) 681 jz 1f 682 683 /* 684 * IRQ from user mode. 685 * 686 * We need to tell lockdep that IRQs are off. We can't do this until 687 * we fix gsbase, and we should do it before enter_from_user_mode 688 * (which can take locks). Since TRACE_IRQS_OFF idempotent, 689 * the simplest way to handle it is to just call it twice if 690 * we enter from user mode. There's no reason to optimize this since 691 * TRACE_IRQS_OFF is a no-op if lockdep is off. 692 */ 693 TRACE_IRQS_OFF 694 695 CALL_enter_from_user_mode 696 6971: 698 ENTER_IRQ_STACK old_rsp=%rdi 699 /* We entered an interrupt context - irqs are off: */ 700 TRACE_IRQS_OFF 701 702 call \func /* rdi points to pt_regs */ 703 .endm 704 705 /* 706 * The interrupt stubs push (~vector+0x80) onto the stack and 707 * then jump to common_interrupt. 708 */ 709 .p2align CONFIG_X86_L1_CACHE_SHIFT 710common_interrupt: 711 ASM_CLAC 712 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ 713 interrupt do_IRQ 714 /* 0(%rsp): old RSP */ 715ret_from_intr: 716 DISABLE_INTERRUPTS(CLBR_ANY) 717 TRACE_IRQS_OFF 718 719 LEAVE_IRQ_STACK 720 721 testb $3, CS(%rsp) 722 jz retint_kernel 723 724 /* Interrupt came from user space */ 725GLOBAL(retint_user) 726 mov %rsp,%rdi 727 call prepare_exit_to_usermode 728 TRACE_IRQS_IRETQ 729 730GLOBAL(swapgs_restore_regs_and_return_to_usermode) 731#ifdef CONFIG_DEBUG_ENTRY 732 /* Assert that pt_regs indicates user mode. */ 733 testb $3, CS(%rsp) 734 jnz 1f 735 ud2 7361: 737#endif 738 POP_EXTRA_REGS 739 popq %r11 740 popq %r10 741 popq %r9 742 popq %r8 743 popq %rax 744 popq %rcx 745 popq %rdx 746 popq %rsi 747 748 /* 749 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. 750 * Save old stack pointer and switch to trampoline stack. 751 */ 752 movq %rsp, %rdi 753 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 754 755 /* Copy the IRET frame to the trampoline stack. */ 756 pushq 6*8(%rdi) /* SS */ 757 pushq 5*8(%rdi) /* RSP */ 758 pushq 4*8(%rdi) /* EFLAGS */ 759 pushq 3*8(%rdi) /* CS */ 760 pushq 2*8(%rdi) /* RIP */ 761 762 /* Push user RDI on the trampoline stack. */ 763 pushq (%rdi) 764 765 /* 766 * We are on the trampoline stack. All regs except RDI are live. 767 * We can do future final exit work right here. 768 */ 769 770 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 771 772 /* Restore RDI. */ 773 popq %rdi 774 SWAPGS 775 INTERRUPT_RETURN 776 777 778/* Returning to kernel space */ 779retint_kernel: 780#ifdef CONFIG_PREEMPT 781 /* Interrupts are off */ 782 /* Check if we need preemption */ 783 bt $9, EFLAGS(%rsp) /* were interrupts off? */ 784 jnc 1f 7850: cmpl $0, PER_CPU_VAR(__preempt_count) 786 jnz 1f 787 call preempt_schedule_irq 788 jmp 0b 7891: 790#endif 791 /* 792 * The iretq could re-enable interrupts: 793 */ 794 TRACE_IRQS_IRETQ 795 796GLOBAL(restore_regs_and_return_to_kernel) 797#ifdef CONFIG_DEBUG_ENTRY 798 /* Assert that pt_regs indicates kernel mode. */ 799 testb $3, CS(%rsp) 800 jz 1f 801 ud2 8021: 803#endif 804 POP_EXTRA_REGS 805 POP_C_REGS 806 addq $8, %rsp /* skip regs->orig_ax */ 807 INTERRUPT_RETURN 808 809ENTRY(native_iret) 810 UNWIND_HINT_IRET_REGS 811 /* 812 * Are we returning to a stack segment from the LDT? Note: in 813 * 64-bit mode SS:RSP on the exception stack is always valid. 814 */ 815#ifdef CONFIG_X86_ESPFIX64 816 testb $4, (SS-RIP)(%rsp) 817 jnz native_irq_return_ldt 818#endif 819 820.global native_irq_return_iret 821native_irq_return_iret: 822 /* 823 * This may fault. Non-paranoid faults on return to userspace are 824 * handled by fixup_bad_iret. These include #SS, #GP, and #NP. 825 * Double-faults due to espfix64 are handled in do_double_fault. 826 * Other faults here are fatal. 827 */ 828 iretq 829 830#ifdef CONFIG_X86_ESPFIX64 831native_irq_return_ldt: 832 /* 833 * We are running with user GSBASE. All GPRs contain their user 834 * values. We have a percpu ESPFIX stack that is eight slots 835 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom 836 * of the ESPFIX stack. 837 * 838 * We clobber RAX and RDI in this code. We stash RDI on the 839 * normal stack and RAX on the ESPFIX stack. 840 * 841 * The ESPFIX stack layout we set up looks like this: 842 * 843 * --- top of ESPFIX stack --- 844 * SS 845 * RSP 846 * RFLAGS 847 * CS 848 * RIP <-- RSP points here when we're done 849 * RAX <-- espfix_waddr points here 850 * --- bottom of ESPFIX stack --- 851 */ 852 853 pushq %rdi /* Stash user RDI */ 854 SWAPGS /* to kernel GS */ 855 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ 856 857 movq PER_CPU_VAR(espfix_waddr), %rdi 858 movq %rax, (0*8)(%rdi) /* user RAX */ 859 movq (1*8)(%rsp), %rax /* user RIP */ 860 movq %rax, (1*8)(%rdi) 861 movq (2*8)(%rsp), %rax /* user CS */ 862 movq %rax, (2*8)(%rdi) 863 movq (3*8)(%rsp), %rax /* user RFLAGS */ 864 movq %rax, (3*8)(%rdi) 865 movq (5*8)(%rsp), %rax /* user SS */ 866 movq %rax, (5*8)(%rdi) 867 movq (4*8)(%rsp), %rax /* user RSP */ 868 movq %rax, (4*8)(%rdi) 869 /* Now RAX == RSP. */ 870 871 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ 872 873 /* 874 * espfix_stack[31:16] == 0. The page tables are set up such that 875 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of 876 * espfix_waddr for any X. That is, there are 65536 RO aliases of 877 * the same page. Set up RSP so that RSP[31:16] contains the 878 * respective 16 bits of the /userspace/ RSP and RSP nonetheless 879 * still points to an RO alias of the ESPFIX stack. 880 */ 881 orq PER_CPU_VAR(espfix_stack), %rax 882 883 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 884 SWAPGS /* to user GS */ 885 popq %rdi /* Restore user RDI */ 886 887 movq %rax, %rsp 888 UNWIND_HINT_IRET_REGS offset=8 889 890 /* 891 * At this point, we cannot write to the stack any more, but we can 892 * still read. 893 */ 894 popq %rax /* Restore user RAX */ 895 896 /* 897 * RSP now points to an ordinary IRET frame, except that the page 898 * is read-only and RSP[31:16] are preloaded with the userspace 899 * values. We can now IRET back to userspace. 900 */ 901 jmp native_irq_return_iret 902#endif 903END(common_interrupt) 904 905/* 906 * APIC interrupts. 907 */ 908.macro apicinterrupt3 num sym do_sym 909ENTRY(\sym) 910 UNWIND_HINT_IRET_REGS 911 ASM_CLAC 912 pushq $~(\num) 913.Lcommon_\sym: 914 interrupt \do_sym 915 jmp ret_from_intr 916END(\sym) 917.endm 918 919/* Make sure APIC interrupt handlers end up in the irqentry section: */ 920#define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax" 921#define POP_SECTION_IRQENTRY .popsection 922 923.macro apicinterrupt num sym do_sym 924PUSH_SECTION_IRQENTRY 925apicinterrupt3 \num \sym \do_sym 926POP_SECTION_IRQENTRY 927.endm 928 929#ifdef CONFIG_SMP 930apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt 931apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt 932#endif 933 934#ifdef CONFIG_X86_UV 935apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt 936#endif 937 938apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt 939apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi 940 941#ifdef CONFIG_HAVE_KVM 942apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi 943apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi 944apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi 945#endif 946 947#ifdef CONFIG_X86_MCE_THRESHOLD 948apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt 949#endif 950 951#ifdef CONFIG_X86_MCE_AMD 952apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt 953#endif 954 955#ifdef CONFIG_X86_THERMAL_VECTOR 956apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt 957#endif 958 959#ifdef CONFIG_SMP 960apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt 961apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt 962apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt 963#endif 964 965apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt 966apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt 967 968#ifdef CONFIG_IRQ_WORK 969apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt 970#endif 971 972/* 973 * Exception entry points. 974 */ 975#define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8) 976 977/* 978 * Switch to the thread stack. This is called with the IRET frame and 979 * orig_ax on the stack. (That is, RDI..R12 are not on the stack and 980 * space has not been allocated for them.) 981 */ 982ENTRY(switch_to_thread_stack) 983 UNWIND_HINT_FUNC 984 985 pushq %rdi 986 /* Need to switch before accessing the thread stack. */ 987 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi 988 movq %rsp, %rdi 989 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 990 UNWIND_HINT sp_offset=16 sp_reg=ORC_REG_DI 991 992 pushq 7*8(%rdi) /* regs->ss */ 993 pushq 6*8(%rdi) /* regs->rsp */ 994 pushq 5*8(%rdi) /* regs->eflags */ 995 pushq 4*8(%rdi) /* regs->cs */ 996 pushq 3*8(%rdi) /* regs->ip */ 997 pushq 2*8(%rdi) /* regs->orig_ax */ 998 pushq 8(%rdi) /* return address */ 999 UNWIND_HINT_FUNC 1000 1001 movq (%rdi), %rdi 1002 ret 1003END(switch_to_thread_stack) 1004 1005.macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 1006ENTRY(\sym) 1007 UNWIND_HINT_IRET_REGS offset=\has_error_code*8 1008 1009 /* Sanity check */ 1010 .if \shift_ist != -1 && \paranoid == 0 1011 .error "using shift_ist requires paranoid=1" 1012 .endif 1013 1014 ASM_CLAC 1015 1016 .if \has_error_code == 0 1017 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1018 .endif 1019 1020 ALLOC_PT_GPREGS_ON_STACK 1021 1022 .if \paranoid < 2 1023 testb $3, CS(%rsp) /* If coming from userspace, switch stacks */ 1024 jnz .Lfrom_usermode_switch_stack_\@ 1025 .endif 1026 1027 .if \paranoid 1028 call paranoid_entry 1029 .else 1030 call error_entry 1031 .endif 1032 UNWIND_HINT_REGS 1033 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ 1034 1035 .if \paranoid 1036 .if \shift_ist != -1 1037 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ 1038 .else 1039 TRACE_IRQS_OFF 1040 .endif 1041 .endif 1042 1043 movq %rsp, %rdi /* pt_regs pointer */ 1044 1045 .if \has_error_code 1046 movq ORIG_RAX(%rsp), %rsi /* get error code */ 1047 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 1048 .else 1049 xorl %esi, %esi /* no error code */ 1050 .endif 1051 1052 .if \shift_ist != -1 1053 subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 1054 .endif 1055 1056 call \do_sym 1057 1058 .if \shift_ist != -1 1059 addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 1060 .endif 1061 1062 /* these procedures expect "no swapgs" flag in ebx */ 1063 .if \paranoid 1064 jmp paranoid_exit 1065 .else 1066 jmp error_exit 1067 .endif 1068 1069 .if \paranoid < 2 1070 /* 1071 * Entry from userspace. Switch stacks and treat it 1072 * as a normal entry. This means that paranoid handlers 1073 * run in real process context if user_mode(regs). 1074 */ 1075.Lfrom_usermode_switch_stack_\@: 1076 call error_entry 1077 1078 movq %rsp, %rdi /* pt_regs pointer */ 1079 1080 .if \has_error_code 1081 movq ORIG_RAX(%rsp), %rsi /* get error code */ 1082 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 1083 .else 1084 xorl %esi, %esi /* no error code */ 1085 .endif 1086 1087 call \do_sym 1088 1089 jmp error_exit /* %ebx: no swapgs flag */ 1090 .endif 1091END(\sym) 1092.endm 1093 1094idtentry divide_error do_divide_error has_error_code=0 1095idtentry overflow do_overflow has_error_code=0 1096idtentry bounds do_bounds has_error_code=0 1097idtentry invalid_op do_invalid_op has_error_code=0 1098idtentry device_not_available do_device_not_available has_error_code=0 1099idtentry double_fault do_double_fault has_error_code=1 paranoid=2 1100idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 1101idtentry invalid_TSS do_invalid_TSS has_error_code=1 1102idtentry segment_not_present do_segment_not_present has_error_code=1 1103idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 1104idtentry coprocessor_error do_coprocessor_error has_error_code=0 1105idtentry alignment_check do_alignment_check has_error_code=1 1106idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 1107 1108 1109 /* 1110 * Reload gs selector with exception handling 1111 * edi: new selector 1112 */ 1113ENTRY(native_load_gs_index) 1114 FRAME_BEGIN 1115 pushfq 1116 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) 1117 TRACE_IRQS_OFF 1118 SWAPGS 1119.Lgs_change: 1120 movl %edi, %gs 11212: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE 1122 SWAPGS 1123 TRACE_IRQS_FLAGS (%rsp) 1124 popfq 1125 FRAME_END 1126 ret 1127ENDPROC(native_load_gs_index) 1128EXPORT_SYMBOL(native_load_gs_index) 1129 1130 _ASM_EXTABLE(.Lgs_change, bad_gs) 1131 .section .fixup, "ax" 1132 /* running with kernelgs */ 1133bad_gs: 1134 SWAPGS /* switch back to user gs */ 1135.macro ZAP_GS 1136 /* This can't be a string because the preprocessor needs to see it. */ 1137 movl $__USER_DS, %eax 1138 movl %eax, %gs 1139.endm 1140 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG 1141 xorl %eax, %eax 1142 movl %eax, %gs 1143 jmp 2b 1144 .previous 1145 1146/* Call softirq on interrupt stack. Interrupts are off. */ 1147ENTRY(do_softirq_own_stack) 1148 pushq %rbp 1149 mov %rsp, %rbp 1150 ENTER_IRQ_STACK regs=0 old_rsp=%r11 1151 call __do_softirq 1152 LEAVE_IRQ_STACK regs=0 1153 leaveq 1154 ret 1155ENDPROC(do_softirq_own_stack) 1156 1157#ifdef CONFIG_XEN 1158idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0 1159 1160/* 1161 * A note on the "critical region" in our callback handler. 1162 * We want to avoid stacking callback handlers due to events occurring 1163 * during handling of the last event. To do this, we keep events disabled 1164 * until we've done all processing. HOWEVER, we must enable events before 1165 * popping the stack frame (can't be done atomically) and so it would still 1166 * be possible to get enough handler activations to overflow the stack. 1167 * Although unlikely, bugs of that kind are hard to track down, so we'd 1168 * like to avoid the possibility. 1169 * So, on entry to the handler we detect whether we interrupted an 1170 * existing activation in its critical region -- if so, we pop the current 1171 * activation and restart the handler using the previous one. 1172 */ 1173ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ 1174 1175/* 1176 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will 1177 * see the correct pointer to the pt_regs 1178 */ 1179 UNWIND_HINT_FUNC 1180 movq %rdi, %rsp /* we don't return, adjust the stack frame */ 1181 UNWIND_HINT_REGS 1182 1183 ENTER_IRQ_STACK old_rsp=%r10 1184 call xen_evtchn_do_upcall 1185 LEAVE_IRQ_STACK 1186 1187#ifndef CONFIG_PREEMPT 1188 call xen_maybe_preempt_hcall 1189#endif 1190 jmp error_exit 1191END(xen_do_hypervisor_callback) 1192 1193/* 1194 * Hypervisor uses this for application faults while it executes. 1195 * We get here for two reasons: 1196 * 1. Fault while reloading DS, ES, FS or GS 1197 * 2. Fault while executing IRET 1198 * Category 1 we do not need to fix up as Xen has already reloaded all segment 1199 * registers that could be reloaded and zeroed the others. 1200 * Category 2 we fix up by killing the current process. We cannot use the 1201 * normal Linux return path in this case because if we use the IRET hypercall 1202 * to pop the stack frame we end up in an infinite loop of failsafe callbacks. 1203 * We distinguish between categories by comparing each saved segment register 1204 * with its current contents: any discrepancy means we in category 1. 1205 */ 1206ENTRY(xen_failsafe_callback) 1207 UNWIND_HINT_EMPTY 1208 movl %ds, %ecx 1209 cmpw %cx, 0x10(%rsp) 1210 jne 1f 1211 movl %es, %ecx 1212 cmpw %cx, 0x18(%rsp) 1213 jne 1f 1214 movl %fs, %ecx 1215 cmpw %cx, 0x20(%rsp) 1216 jne 1f 1217 movl %gs, %ecx 1218 cmpw %cx, 0x28(%rsp) 1219 jne 1f 1220 /* All segments match their saved values => Category 2 (Bad IRET). */ 1221 movq (%rsp), %rcx 1222 movq 8(%rsp), %r11 1223 addq $0x30, %rsp 1224 pushq $0 /* RIP */ 1225 UNWIND_HINT_IRET_REGS offset=8 1226 jmp general_protection 12271: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ 1228 movq (%rsp), %rcx 1229 movq 8(%rsp), %r11 1230 addq $0x30, %rsp 1231 UNWIND_HINT_IRET_REGS 1232 pushq $-1 /* orig_ax = -1 => not a system call */ 1233 ALLOC_PT_GPREGS_ON_STACK 1234 SAVE_C_REGS 1235 SAVE_EXTRA_REGS 1236 ENCODE_FRAME_POINTER 1237 jmp error_exit 1238END(xen_failsafe_callback) 1239 1240apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1241 xen_hvm_callback_vector xen_evtchn_do_upcall 1242 1243#endif /* CONFIG_XEN */ 1244 1245#if IS_ENABLED(CONFIG_HYPERV) 1246apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1247 hyperv_callback_vector hyperv_vector_handler 1248#endif /* CONFIG_HYPERV */ 1249 1250idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK 1251idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK 1252idtentry stack_segment do_stack_segment has_error_code=1 1253 1254#ifdef CONFIG_XEN 1255idtentry xennmi do_nmi has_error_code=0 1256idtentry xendebug do_debug has_error_code=0 1257idtentry xenint3 do_int3 has_error_code=0 1258#endif 1259 1260idtentry general_protection do_general_protection has_error_code=1 1261idtentry page_fault do_page_fault has_error_code=1 1262 1263#ifdef CONFIG_KVM_GUEST 1264idtentry async_page_fault do_async_page_fault has_error_code=1 1265#endif 1266 1267#ifdef CONFIG_X86_MCE 1268idtentry machine_check do_mce has_error_code=0 paranoid=1 1269#endif 1270 1271/* 1272 * Save all registers in pt_regs, and switch gs if needed. 1273 * Use slow, but surefire "are we in kernel?" check. 1274 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise 1275 */ 1276ENTRY(paranoid_entry) 1277 UNWIND_HINT_FUNC 1278 cld 1279 SAVE_C_REGS 8 1280 SAVE_EXTRA_REGS 8 1281 ENCODE_FRAME_POINTER 8 1282 movl $1, %ebx 1283 movl $MSR_GS_BASE, %ecx 1284 rdmsr 1285 testl %edx, %edx 1286 js 1f /* negative -> in kernel */ 1287 SWAPGS 1288 xorl %ebx, %ebx 1289 12901: 1291 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 1292 1293 ret 1294END(paranoid_entry) 1295 1296/* 1297 * "Paranoid" exit path from exception stack. This is invoked 1298 * only on return from non-NMI IST interrupts that came 1299 * from kernel space. 1300 * 1301 * We may be returning to very strange contexts (e.g. very early 1302 * in syscall entry), so checking for preemption here would 1303 * be complicated. Fortunately, we there's no good reason 1304 * to try to handle preemption here. 1305 * 1306 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) 1307 */ 1308ENTRY(paranoid_exit) 1309 UNWIND_HINT_REGS 1310 DISABLE_INTERRUPTS(CLBR_ANY) 1311 TRACE_IRQS_OFF_DEBUG 1312 testl %ebx, %ebx /* swapgs needed? */ 1313 jnz .Lparanoid_exit_no_swapgs 1314 TRACE_IRQS_IRETQ 1315 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1316 SWAPGS_UNSAFE_STACK 1317 jmp .Lparanoid_exit_restore 1318.Lparanoid_exit_no_swapgs: 1319 TRACE_IRQS_IRETQ_DEBUG 1320.Lparanoid_exit_restore: 1321 jmp restore_regs_and_return_to_kernel 1322END(paranoid_exit) 1323 1324/* 1325 * Save all registers in pt_regs, and switch gs if needed. 1326 * Return: EBX=0: came from user mode; EBX=1: otherwise 1327 */ 1328ENTRY(error_entry) 1329 UNWIND_HINT_FUNC 1330 cld 1331 SAVE_C_REGS 8 1332 SAVE_EXTRA_REGS 8 1333 ENCODE_FRAME_POINTER 8 1334 xorl %ebx, %ebx 1335 testb $3, CS+8(%rsp) 1336 jz .Lerror_kernelspace 1337 1338 /* 1339 * We entered from user mode or we're pretending to have entered 1340 * from user mode due to an IRET fault. 1341 */ 1342 SWAPGS 1343 /* We have user CR3. Change to kernel CR3. */ 1344 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1345 1346.Lerror_entry_from_usermode_after_swapgs: 1347 /* Put us onto the real thread stack. */ 1348 popq %r12 /* save return addr in %12 */ 1349 movq %rsp, %rdi /* arg0 = pt_regs pointer */ 1350 call sync_regs 1351 movq %rax, %rsp /* switch stack */ 1352 ENCODE_FRAME_POINTER 1353 pushq %r12 1354 1355 /* 1356 * We need to tell lockdep that IRQs are off. We can't do this until 1357 * we fix gsbase, and we should do it before enter_from_user_mode 1358 * (which can take locks). 1359 */ 1360 TRACE_IRQS_OFF 1361 CALL_enter_from_user_mode 1362 ret 1363 1364.Lerror_entry_done: 1365 TRACE_IRQS_OFF 1366 ret 1367 1368 /* 1369 * There are two places in the kernel that can potentially fault with 1370 * usergs. Handle them here. B stepping K8s sometimes report a 1371 * truncated RIP for IRET exceptions returning to compat mode. Check 1372 * for these here too. 1373 */ 1374.Lerror_kernelspace: 1375 incl %ebx 1376 leaq native_irq_return_iret(%rip), %rcx 1377 cmpq %rcx, RIP+8(%rsp) 1378 je .Lerror_bad_iret 1379 movl %ecx, %eax /* zero extend */ 1380 cmpq %rax, RIP+8(%rsp) 1381 je .Lbstep_iret 1382 cmpq $.Lgs_change, RIP+8(%rsp) 1383 jne .Lerror_entry_done 1384 1385 /* 1386 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up 1387 * gsbase and proceed. We'll fix up the exception and land in 1388 * .Lgs_change's error handler with kernel gsbase. 1389 */ 1390 SWAPGS 1391 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1392 jmp .Lerror_entry_done 1393 1394.Lbstep_iret: 1395 /* Fix truncated RIP */ 1396 movq %rcx, RIP+8(%rsp) 1397 /* fall through */ 1398 1399.Lerror_bad_iret: 1400 /* 1401 * We came from an IRET to user mode, so we have user 1402 * gsbase and CR3. Switch to kernel gsbase and CR3: 1403 */ 1404 SWAPGS 1405 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1406 1407 /* 1408 * Pretend that the exception came from user mode: set up pt_regs 1409 * as if we faulted immediately after IRET and clear EBX so that 1410 * error_exit knows that we will be returning to user mode. 1411 */ 1412 mov %rsp, %rdi 1413 call fixup_bad_iret 1414 mov %rax, %rsp 1415 decl %ebx 1416 jmp .Lerror_entry_from_usermode_after_swapgs 1417END(error_entry) 1418 1419 1420/* 1421 * On entry, EBX is a "return to kernel mode" flag: 1422 * 1: already in kernel mode, don't need SWAPGS 1423 * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode 1424 */ 1425ENTRY(error_exit) 1426 UNWIND_HINT_REGS 1427 DISABLE_INTERRUPTS(CLBR_ANY) 1428 TRACE_IRQS_OFF 1429 testl %ebx, %ebx 1430 jnz retint_kernel 1431 jmp retint_user 1432END(error_exit) 1433 1434/* 1435 * Runs on exception stack. Xen PV does not go through this path at all, 1436 * so we can use real assembly here. 1437 * 1438 * Registers: 1439 * %r14: Used to save/restore the CR3 of the interrupted context 1440 * when PAGE_TABLE_ISOLATION is in use. Do not clobber. 1441 */ 1442ENTRY(nmi) 1443 UNWIND_HINT_IRET_REGS 1444 1445 /* 1446 * We allow breakpoints in NMIs. If a breakpoint occurs, then 1447 * the iretq it performs will take us out of NMI context. 1448 * This means that we can have nested NMIs where the next 1449 * NMI is using the top of the stack of the previous NMI. We 1450 * can't let it execute because the nested NMI will corrupt the 1451 * stack of the previous NMI. NMI handlers are not re-entrant 1452 * anyway. 1453 * 1454 * To handle this case we do the following: 1455 * Check the a special location on the stack that contains 1456 * a variable that is set when NMIs are executing. 1457 * The interrupted task's stack is also checked to see if it 1458 * is an NMI stack. 1459 * If the variable is not set and the stack is not the NMI 1460 * stack then: 1461 * o Set the special variable on the stack 1462 * o Copy the interrupt frame into an "outermost" location on the 1463 * stack 1464 * o Copy the interrupt frame into an "iret" location on the stack 1465 * o Continue processing the NMI 1466 * If the variable is set or the previous stack is the NMI stack: 1467 * o Modify the "iret" location to jump to the repeat_nmi 1468 * o return back to the first NMI 1469 * 1470 * Now on exit of the first NMI, we first clear the stack variable 1471 * The NMI stack will tell any nested NMIs at that point that it is 1472 * nested. Then we pop the stack normally with iret, and if there was 1473 * a nested NMI that updated the copy interrupt stack frame, a 1474 * jump will be made to the repeat_nmi code that will handle the second 1475 * NMI. 1476 * 1477 * However, espfix prevents us from directly returning to userspace 1478 * with a single IRET instruction. Similarly, IRET to user mode 1479 * can fault. We therefore handle NMIs from user space like 1480 * other IST entries. 1481 */ 1482 1483 ASM_CLAC 1484 1485 /* Use %rdx as our temp variable throughout */ 1486 pushq %rdx 1487 1488 testb $3, CS-RIP+8(%rsp) 1489 jz .Lnmi_from_kernel 1490 1491 /* 1492 * NMI from user mode. We need to run on the thread stack, but we 1493 * can't go through the normal entry paths: NMIs are masked, and 1494 * we don't want to enable interrupts, because then we'll end 1495 * up in an awkward situation in which IRQs are on but NMIs 1496 * are off. 1497 * 1498 * We also must not push anything to the stack before switching 1499 * stacks lest we corrupt the "NMI executing" variable. 1500 */ 1501 1502 swapgs 1503 cld 1504 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx 1505 movq %rsp, %rdx 1506 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 1507 UNWIND_HINT_IRET_REGS base=%rdx offset=8 1508 pushq 5*8(%rdx) /* pt_regs->ss */ 1509 pushq 4*8(%rdx) /* pt_regs->rsp */ 1510 pushq 3*8(%rdx) /* pt_regs->flags */ 1511 pushq 2*8(%rdx) /* pt_regs->cs */ 1512 pushq 1*8(%rdx) /* pt_regs->rip */ 1513 UNWIND_HINT_IRET_REGS 1514 pushq $-1 /* pt_regs->orig_ax */ 1515 pushq %rdi /* pt_regs->di */ 1516 pushq %rsi /* pt_regs->si */ 1517 pushq (%rdx) /* pt_regs->dx */ 1518 pushq %rcx /* pt_regs->cx */ 1519 pushq %rax /* pt_regs->ax */ 1520 pushq %r8 /* pt_regs->r8 */ 1521 pushq %r9 /* pt_regs->r9 */ 1522 pushq %r10 /* pt_regs->r10 */ 1523 pushq %r11 /* pt_regs->r11 */ 1524 pushq %rbx /* pt_regs->rbx */ 1525 pushq %rbp /* pt_regs->rbp */ 1526 pushq %r12 /* pt_regs->r12 */ 1527 pushq %r13 /* pt_regs->r13 */ 1528 pushq %r14 /* pt_regs->r14 */ 1529 pushq %r15 /* pt_regs->r15 */ 1530 UNWIND_HINT_REGS 1531 ENCODE_FRAME_POINTER 1532 1533 /* 1534 * At this point we no longer need to worry about stack damage 1535 * due to nesting -- we're on the normal thread stack and we're 1536 * done with the NMI stack. 1537 */ 1538 1539 movq %rsp, %rdi 1540 movq $-1, %rsi 1541 call do_nmi 1542 1543 /* 1544 * Return back to user mode. We must *not* do the normal exit 1545 * work, because we don't want to enable interrupts. 1546 */ 1547 jmp swapgs_restore_regs_and_return_to_usermode 1548 1549.Lnmi_from_kernel: 1550 /* 1551 * Here's what our stack frame will look like: 1552 * +---------------------------------------------------------+ 1553 * | original SS | 1554 * | original Return RSP | 1555 * | original RFLAGS | 1556 * | original CS | 1557 * | original RIP | 1558 * +---------------------------------------------------------+ 1559 * | temp storage for rdx | 1560 * +---------------------------------------------------------+ 1561 * | "NMI executing" variable | 1562 * +---------------------------------------------------------+ 1563 * | iret SS } Copied from "outermost" frame | 1564 * | iret Return RSP } on each loop iteration; overwritten | 1565 * | iret RFLAGS } by a nested NMI to force another | 1566 * | iret CS } iteration if needed. | 1567 * | iret RIP } | 1568 * +---------------------------------------------------------+ 1569 * | outermost SS } initialized in first_nmi; | 1570 * | outermost Return RSP } will not be changed before | 1571 * | outermost RFLAGS } NMI processing is done. | 1572 * | outermost CS } Copied to "iret" frame on each | 1573 * | outermost RIP } iteration. | 1574 * +---------------------------------------------------------+ 1575 * | pt_regs | 1576 * +---------------------------------------------------------+ 1577 * 1578 * The "original" frame is used by hardware. Before re-enabling 1579 * NMIs, we need to be done with it, and we need to leave enough 1580 * space for the asm code here. 1581 * 1582 * We return by executing IRET while RSP points to the "iret" frame. 1583 * That will either return for real or it will loop back into NMI 1584 * processing. 1585 * 1586 * The "outermost" frame is copied to the "iret" frame on each 1587 * iteration of the loop, so each iteration starts with the "iret" 1588 * frame pointing to the final return target. 1589 */ 1590 1591 /* 1592 * Determine whether we're a nested NMI. 1593 * 1594 * If we interrupted kernel code between repeat_nmi and 1595 * end_repeat_nmi, then we are a nested NMI. We must not 1596 * modify the "iret" frame because it's being written by 1597 * the outer NMI. That's okay; the outer NMI handler is 1598 * about to about to call do_nmi anyway, so we can just 1599 * resume the outer NMI. 1600 */ 1601 1602 movq $repeat_nmi, %rdx 1603 cmpq 8(%rsp), %rdx 1604 ja 1f 1605 movq $end_repeat_nmi, %rdx 1606 cmpq 8(%rsp), %rdx 1607 ja nested_nmi_out 16081: 1609 1610 /* 1611 * Now check "NMI executing". If it's set, then we're nested. 1612 * This will not detect if we interrupted an outer NMI just 1613 * before IRET. 1614 */ 1615 cmpl $1, -8(%rsp) 1616 je nested_nmi 1617 1618 /* 1619 * Now test if the previous stack was an NMI stack. This covers 1620 * the case where we interrupt an outer NMI after it clears 1621 * "NMI executing" but before IRET. We need to be careful, though: 1622 * there is one case in which RSP could point to the NMI stack 1623 * despite there being no NMI active: naughty userspace controls 1624 * RSP at the very beginning of the SYSCALL targets. We can 1625 * pull a fast one on naughty userspace, though: we program 1626 * SYSCALL to mask DF, so userspace cannot cause DF to be set 1627 * if it controls the kernel's RSP. We set DF before we clear 1628 * "NMI executing". 1629 */ 1630 lea 6*8(%rsp), %rdx 1631 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ 1632 cmpq %rdx, 4*8(%rsp) 1633 /* If the stack pointer is above the NMI stack, this is a normal NMI */ 1634 ja first_nmi 1635 1636 subq $EXCEPTION_STKSZ, %rdx 1637 cmpq %rdx, 4*8(%rsp) 1638 /* If it is below the NMI stack, it is a normal NMI */ 1639 jb first_nmi 1640 1641 /* Ah, it is within the NMI stack. */ 1642 1643 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) 1644 jz first_nmi /* RSP was user controlled. */ 1645 1646 /* This is a nested NMI. */ 1647 1648nested_nmi: 1649 /* 1650 * Modify the "iret" frame to point to repeat_nmi, forcing another 1651 * iteration of NMI handling. 1652 */ 1653 subq $8, %rsp 1654 leaq -10*8(%rsp), %rdx 1655 pushq $__KERNEL_DS 1656 pushq %rdx 1657 pushfq 1658 pushq $__KERNEL_CS 1659 pushq $repeat_nmi 1660 1661 /* Put stack back */ 1662 addq $(6*8), %rsp 1663 1664nested_nmi_out: 1665 popq %rdx 1666 1667 /* We are returning to kernel mode, so this cannot result in a fault. */ 1668 iretq 1669 1670first_nmi: 1671 /* Restore rdx. */ 1672 movq (%rsp), %rdx 1673 1674 /* Make room for "NMI executing". */ 1675 pushq $0 1676 1677 /* Leave room for the "iret" frame */ 1678 subq $(5*8), %rsp 1679 1680 /* Copy the "original" frame to the "outermost" frame */ 1681 .rept 5 1682 pushq 11*8(%rsp) 1683 .endr 1684 UNWIND_HINT_IRET_REGS 1685 1686 /* Everything up to here is safe from nested NMIs */ 1687 1688#ifdef CONFIG_DEBUG_ENTRY 1689 /* 1690 * For ease of testing, unmask NMIs right away. Disabled by 1691 * default because IRET is very expensive. 1692 */ 1693 pushq $0 /* SS */ 1694 pushq %rsp /* RSP (minus 8 because of the previous push) */ 1695 addq $8, (%rsp) /* Fix up RSP */ 1696 pushfq /* RFLAGS */ 1697 pushq $__KERNEL_CS /* CS */ 1698 pushq $1f /* RIP */ 1699 iretq /* continues at repeat_nmi below */ 1700 UNWIND_HINT_IRET_REGS 17011: 1702#endif 1703 1704repeat_nmi: 1705 /* 1706 * If there was a nested NMI, the first NMI's iret will return 1707 * here. But NMIs are still enabled and we can take another 1708 * nested NMI. The nested NMI checks the interrupted RIP to see 1709 * if it is between repeat_nmi and end_repeat_nmi, and if so 1710 * it will just return, as we are about to repeat an NMI anyway. 1711 * This makes it safe to copy to the stack frame that a nested 1712 * NMI will update. 1713 * 1714 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if 1715 * we're repeating an NMI, gsbase has the same value that it had on 1716 * the first iteration. paranoid_entry will load the kernel 1717 * gsbase if needed before we call do_nmi. "NMI executing" 1718 * is zero. 1719 */ 1720 movq $1, 10*8(%rsp) /* Set "NMI executing". */ 1721 1722 /* 1723 * Copy the "outermost" frame to the "iret" frame. NMIs that nest 1724 * here must not modify the "iret" frame while we're writing to 1725 * it or it will end up containing garbage. 1726 */ 1727 addq $(10*8), %rsp 1728 .rept 5 1729 pushq -6*8(%rsp) 1730 .endr 1731 subq $(5*8), %rsp 1732end_repeat_nmi: 1733 1734 /* 1735 * Everything below this point can be preempted by a nested NMI. 1736 * If this happens, then the inner NMI will change the "iret" 1737 * frame to point back to repeat_nmi. 1738 */ 1739 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1740 ALLOC_PT_GPREGS_ON_STACK 1741 1742 /* 1743 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit 1744 * as we should not be calling schedule in NMI context. 1745 * Even with normal interrupts enabled. An NMI should not be 1746 * setting NEED_RESCHED or anything that normal interrupts and 1747 * exceptions might do. 1748 */ 1749 call paranoid_entry 1750 UNWIND_HINT_REGS 1751 1752 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ 1753 movq %rsp, %rdi 1754 movq $-1, %rsi 1755 call do_nmi 1756 1757 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 1758 1759 testl %ebx, %ebx /* swapgs needed? */ 1760 jnz nmi_restore 1761nmi_swapgs: 1762 SWAPGS_UNSAFE_STACK 1763nmi_restore: 1764 POP_EXTRA_REGS 1765 POP_C_REGS 1766 1767 /* 1768 * Skip orig_ax and the "outermost" frame to point RSP at the "iret" 1769 * at the "iret" frame. 1770 */ 1771 addq $6*8, %rsp 1772 1773 /* 1774 * Clear "NMI executing". Set DF first so that we can easily 1775 * distinguish the remaining code between here and IRET from 1776 * the SYSCALL entry and exit paths. 1777 * 1778 * We arguably should just inspect RIP instead, but I (Andy) wrote 1779 * this code when I had the misapprehension that Xen PV supported 1780 * NMIs, and Xen PV would break that approach. 1781 */ 1782 std 1783 movq $0, 5*8(%rsp) /* clear "NMI executing" */ 1784 1785 /* 1786 * iretq reads the "iret" frame and exits the NMI stack in a 1787 * single instruction. We are returning to kernel mode, so this 1788 * cannot result in a fault. Similarly, we don't need to worry 1789 * about espfix64 on the way back to kernel mode. 1790 */ 1791 iretq 1792END(nmi) 1793 1794ENTRY(ignore_sysret) 1795 UNWIND_HINT_EMPTY 1796 mov $-ENOSYS, %eax 1797 sysret 1798END(ignore_sysret) 1799 1800ENTRY(rewind_stack_do_exit) 1801 UNWIND_HINT_FUNC 1802 /* Prevent any naive code from trying to unwind to our caller. */ 1803 xorl %ebp, %ebp 1804 1805 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax 1806 leaq -PTREGS_SIZE(%rax), %rsp 1807 UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE 1808 1809 call do_exit 1810END(rewind_stack_do_exit) 1811