1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86_64/entry.S 4 * 5 * Copyright (C) 1991, 1992 Linus Torvalds 6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs 7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 8 * 9 * entry.S contains the system-call and fault low-level handling routines. 10 * 11 * Some of this is documented in Documentation/x86/entry_64.txt 12 * 13 * A note on terminology: 14 * - iret frame: Architecture defined interrupt frame from SS to RIP 15 * at the top of the kernel process stack. 16 * 17 * Some macro usage: 18 * - ENTRY/END: Define functions in the symbol table. 19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging. 20 * - idtentry: Define exception entry points. 21 */ 22#include <linux/linkage.h> 23#include <asm/segment.h> 24#include <asm/cache.h> 25#include <asm/errno.h> 26#include <asm/asm-offsets.h> 27#include <asm/msr.h> 28#include <asm/unistd.h> 29#include <asm/thread_info.h> 30#include <asm/hw_irq.h> 31#include <asm/page_types.h> 32#include <asm/irqflags.h> 33#include <asm/paravirt.h> 34#include <asm/percpu.h> 35#include <asm/asm.h> 36#include <asm/smap.h> 37#include <asm/pgtable_types.h> 38#include <asm/export.h> 39#include <asm/frame.h> 40#include <asm/nospec-branch.h> 41#include <linux/err.h> 42 43#include "calling.h" 44 45.code64 46.section .entry.text, "ax" 47 48#ifdef CONFIG_PARAVIRT 49ENTRY(native_usergs_sysret64) 50 UNWIND_HINT_EMPTY 51 swapgs 52 sysretq 53END(native_usergs_sysret64) 54#endif /* CONFIG_PARAVIRT */ 55 56.macro TRACE_IRQS_FLAGS flags:req 57#ifdef CONFIG_TRACE_IRQFLAGS 58 btl $9, \flags /* interrupts off? */ 59 jnc 1f 60 TRACE_IRQS_ON 611: 62#endif 63.endm 64 65.macro TRACE_IRQS_IRETQ 66 TRACE_IRQS_FLAGS EFLAGS(%rsp) 67.endm 68 69/* 70 * When dynamic function tracer is enabled it will add a breakpoint 71 * to all locations that it is about to modify, sync CPUs, update 72 * all the code, sync CPUs, then remove the breakpoints. In this time 73 * if lockdep is enabled, it might jump back into the debug handler 74 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). 75 * 76 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to 77 * make sure the stack pointer does not get reset back to the top 78 * of the debug stack, and instead just reuses the current stack. 79 */ 80#if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) 81 82.macro TRACE_IRQS_OFF_DEBUG 83 call debug_stack_set_zero 84 TRACE_IRQS_OFF 85 call debug_stack_reset 86.endm 87 88.macro TRACE_IRQS_ON_DEBUG 89 call debug_stack_set_zero 90 TRACE_IRQS_ON 91 call debug_stack_reset 92.endm 93 94.macro TRACE_IRQS_IRETQ_DEBUG 95 btl $9, EFLAGS(%rsp) /* interrupts off? */ 96 jnc 1f 97 TRACE_IRQS_ON_DEBUG 981: 99.endm 100 101#else 102# define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF 103# define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON 104# define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ 105#endif 106 107/* 108 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. 109 * 110 * This is the only entry point used for 64-bit system calls. The 111 * hardware interface is reasonably well designed and the register to 112 * argument mapping Linux uses fits well with the registers that are 113 * available when SYSCALL is used. 114 * 115 * SYSCALL instructions can be found inlined in libc implementations as 116 * well as some other programs and libraries. There are also a handful 117 * of SYSCALL instructions in the vDSO used, for example, as a 118 * clock_gettimeofday fallback. 119 * 120 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, 121 * then loads new ss, cs, and rip from previously programmed MSRs. 122 * rflags gets masked by a value from another MSR (so CLD and CLAC 123 * are not needed). SYSCALL does not save anything on the stack 124 * and does not change rsp. 125 * 126 * Registers on entry: 127 * rax system call number 128 * rcx return address 129 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) 130 * rdi arg0 131 * rsi arg1 132 * rdx arg2 133 * r10 arg3 (needs to be moved to rcx to conform to C ABI) 134 * r8 arg4 135 * r9 arg5 136 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) 137 * 138 * Only called from user space. 139 * 140 * When user can change pt_regs->foo always force IRET. That is because 141 * it deals with uncanonical addresses better. SYSRET has trouble 142 * with them due to bugs in both AMD and Intel CPUs. 143 */ 144 145ENTRY(entry_SYSCALL_64) 146 UNWIND_HINT_EMPTY 147 /* 148 * Interrupts are off on entry. 149 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, 150 * it is too small to ever cause noticeable irq latency. 151 */ 152 153 swapgs 154 /* tss.sp2 is scratch space. */ 155 movq %rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2) 156 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp 157 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 158 159 /* Construct struct pt_regs on stack */ 160 pushq $__USER_DS /* pt_regs->ss */ 161 pushq PER_CPU_VAR(cpu_tss_rw + TSS_sp2) /* pt_regs->sp */ 162 pushq %r11 /* pt_regs->flags */ 163 pushq $__USER_CS /* pt_regs->cs */ 164 pushq %rcx /* pt_regs->ip */ 165GLOBAL(entry_SYSCALL_64_after_hwframe) 166 pushq %rax /* pt_regs->orig_ax */ 167 168 PUSH_AND_CLEAR_REGS rax=$-ENOSYS 169 170 TRACE_IRQS_OFF 171 172 /* IRQs are off. */ 173 movq %rax, %rdi 174 movq %rsp, %rsi 175 call do_syscall_64 /* returns with IRQs disabled */ 176 177 TRACE_IRQS_IRETQ /* we're about to change IF */ 178 179 /* 180 * Try to use SYSRET instead of IRET if we're returning to 181 * a completely clean 64-bit userspace context. If we're not, 182 * go to the slow exit path. 183 */ 184 movq RCX(%rsp), %rcx 185 movq RIP(%rsp), %r11 186 187 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ 188 jne swapgs_restore_regs_and_return_to_usermode 189 190 /* 191 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP 192 * in kernel space. This essentially lets the user take over 193 * the kernel, since userspace controls RSP. 194 * 195 * If width of "canonical tail" ever becomes variable, this will need 196 * to be updated to remain correct on both old and new CPUs. 197 * 198 * Change top bits to match most significant bit (47th or 56th bit 199 * depending on paging mode) in the address. 200 */ 201#ifdef CONFIG_X86_5LEVEL 202 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \ 203 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57 204#else 205 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 206 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 207#endif 208 209 /* If this changed %rcx, it was not canonical */ 210 cmpq %rcx, %r11 211 jne swapgs_restore_regs_and_return_to_usermode 212 213 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ 214 jne swapgs_restore_regs_and_return_to_usermode 215 216 movq R11(%rsp), %r11 217 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ 218 jne swapgs_restore_regs_and_return_to_usermode 219 220 /* 221 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot 222 * restore RF properly. If the slowpath sets it for whatever reason, we 223 * need to restore it correctly. 224 * 225 * SYSRET can restore TF, but unlike IRET, restoring TF results in a 226 * trap from userspace immediately after SYSRET. This would cause an 227 * infinite loop whenever #DB happens with register state that satisfies 228 * the opportunistic SYSRET conditions. For example, single-stepping 229 * this user code: 230 * 231 * movq $stuck_here, %rcx 232 * pushfq 233 * popq %r11 234 * stuck_here: 235 * 236 * would never get past 'stuck_here'. 237 */ 238 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 239 jnz swapgs_restore_regs_and_return_to_usermode 240 241 /* nothing to check for RSP */ 242 243 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ 244 jne swapgs_restore_regs_and_return_to_usermode 245 246 /* 247 * We win! This label is here just for ease of understanding 248 * perf profiles. Nothing jumps here. 249 */ 250syscall_return_via_sysret: 251 /* rcx and r11 are already restored (see code above) */ 252 UNWIND_HINT_EMPTY 253 POP_REGS pop_rdi=0 skip_r11rcx=1 254 255 /* 256 * Now all regs are restored except RSP and RDI. 257 * Save old stack pointer and switch to trampoline stack. 258 */ 259 movq %rsp, %rdi 260 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 261 262 pushq RSP-RDI(%rdi) /* RSP */ 263 pushq (%rdi) /* RDI */ 264 265 /* 266 * We are on the trampoline stack. All regs except RDI are live. 267 * We can do future final exit work right here. 268 */ 269 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 270 271 popq %rdi 272 popq %rsp 273 USERGS_SYSRET64 274END(entry_SYSCALL_64) 275 276/* 277 * %rdi: prev task 278 * %rsi: next task 279 */ 280ENTRY(__switch_to_asm) 281 UNWIND_HINT_FUNC 282 /* 283 * Save callee-saved registers 284 * This must match the order in inactive_task_frame 285 */ 286 pushq %rbp 287 pushq %rbx 288 pushq %r12 289 pushq %r13 290 pushq %r14 291 pushq %r15 292 293 /* switch stack */ 294 movq %rsp, TASK_threadsp(%rdi) 295 movq TASK_threadsp(%rsi), %rsp 296 297#ifdef CONFIG_STACKPROTECTOR 298 movq TASK_stack_canary(%rsi), %rbx 299 movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset 300#endif 301 302#ifdef CONFIG_RETPOLINE 303 /* 304 * When switching from a shallower to a deeper call stack 305 * the RSB may either underflow or use entries populated 306 * with userspace addresses. On CPUs where those concerns 307 * exist, overwrite the RSB with entries which capture 308 * speculative execution to prevent attack. 309 */ 310 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW 311#endif 312 313 /* restore callee-saved registers */ 314 popq %r15 315 popq %r14 316 popq %r13 317 popq %r12 318 popq %rbx 319 popq %rbp 320 321 jmp __switch_to 322END(__switch_to_asm) 323 324/* 325 * A newly forked process directly context switches into this address. 326 * 327 * rax: prev task we switched from 328 * rbx: kernel thread func (NULL for user thread) 329 * r12: kernel thread arg 330 */ 331ENTRY(ret_from_fork) 332 UNWIND_HINT_EMPTY 333 movq %rax, %rdi 334 call schedule_tail /* rdi: 'prev' task parameter */ 335 336 testq %rbx, %rbx /* from kernel_thread? */ 337 jnz 1f /* kernel threads are uncommon */ 338 3392: 340 UNWIND_HINT_REGS 341 movq %rsp, %rdi 342 call syscall_return_slowpath /* returns with IRQs disabled */ 343 TRACE_IRQS_ON /* user mode is traced as IRQS on */ 344 jmp swapgs_restore_regs_and_return_to_usermode 345 3461: 347 /* kernel thread */ 348 UNWIND_HINT_EMPTY 349 movq %r12, %rdi 350 CALL_NOSPEC %rbx 351 /* 352 * A kernel thread is allowed to return here after successfully 353 * calling do_execve(). Exit to userspace to complete the execve() 354 * syscall. 355 */ 356 movq $0, RAX(%rsp) 357 jmp 2b 358END(ret_from_fork) 359 360/* 361 * Build the entry stubs with some assembler magic. 362 * We pack 1 stub into every 8-byte block. 363 */ 364 .align 8 365ENTRY(irq_entries_start) 366 vector=FIRST_EXTERNAL_VECTOR 367 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) 368 UNWIND_HINT_IRET_REGS 369 pushq $(~vector+0x80) /* Note: always in signed byte range */ 370 jmp common_interrupt 371 .align 8 372 vector=vector+1 373 .endr 374END(irq_entries_start) 375 376.macro DEBUG_ENTRY_ASSERT_IRQS_OFF 377#ifdef CONFIG_DEBUG_ENTRY 378 pushq %rax 379 SAVE_FLAGS(CLBR_RAX) 380 testl $X86_EFLAGS_IF, %eax 381 jz .Lokay_\@ 382 ud2 383.Lokay_\@: 384 popq %rax 385#endif 386.endm 387 388/* 389 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers 390 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone. 391 * Requires kernel GSBASE. 392 * 393 * The invariant is that, if irq_count != -1, then the IRQ stack is in use. 394 */ 395.macro ENTER_IRQ_STACK regs=1 old_rsp save_ret=0 396 DEBUG_ENTRY_ASSERT_IRQS_OFF 397 398 .if \save_ret 399 /* 400 * If save_ret is set, the original stack contains one additional 401 * entry -- the return address. Therefore, move the address one 402 * entry below %rsp to \old_rsp. 403 */ 404 leaq 8(%rsp), \old_rsp 405 .else 406 movq %rsp, \old_rsp 407 .endif 408 409 .if \regs 410 UNWIND_HINT_REGS base=\old_rsp 411 .endif 412 413 incl PER_CPU_VAR(irq_count) 414 jnz .Lirq_stack_push_old_rsp_\@ 415 416 /* 417 * Right now, if we just incremented irq_count to zero, we've 418 * claimed the IRQ stack but we haven't switched to it yet. 419 * 420 * If anything is added that can interrupt us here without using IST, 421 * it must be *extremely* careful to limit its stack usage. This 422 * could include kprobes and a hypothetical future IST-less #DB 423 * handler. 424 * 425 * The OOPS unwinder relies on the word at the top of the IRQ 426 * stack linking back to the previous RSP for the entire time we're 427 * on the IRQ stack. For this to work reliably, we need to write 428 * it before we actually move ourselves to the IRQ stack. 429 */ 430 431 movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8) 432 movq PER_CPU_VAR(irq_stack_ptr), %rsp 433 434#ifdef CONFIG_DEBUG_ENTRY 435 /* 436 * If the first movq above becomes wrong due to IRQ stack layout 437 * changes, the only way we'll notice is if we try to unwind right 438 * here. Assert that we set up the stack right to catch this type 439 * of bug quickly. 440 */ 441 cmpq -8(%rsp), \old_rsp 442 je .Lirq_stack_okay\@ 443 ud2 444 .Lirq_stack_okay\@: 445#endif 446 447.Lirq_stack_push_old_rsp_\@: 448 pushq \old_rsp 449 450 .if \regs 451 UNWIND_HINT_REGS indirect=1 452 .endif 453 454 .if \save_ret 455 /* 456 * Push the return address to the stack. This return address can 457 * be found at the "real" original RSP, which was offset by 8 at 458 * the beginning of this macro. 459 */ 460 pushq -8(\old_rsp) 461 .endif 462.endm 463 464/* 465 * Undoes ENTER_IRQ_STACK. 466 */ 467.macro LEAVE_IRQ_STACK regs=1 468 DEBUG_ENTRY_ASSERT_IRQS_OFF 469 /* We need to be off the IRQ stack before decrementing irq_count. */ 470 popq %rsp 471 472 .if \regs 473 UNWIND_HINT_REGS 474 .endif 475 476 /* 477 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming 478 * the irq stack but we're not on it. 479 */ 480 481 decl PER_CPU_VAR(irq_count) 482.endm 483 484/* 485 * Interrupt entry helper function. 486 * 487 * Entry runs with interrupts off. Stack layout at entry: 488 * +----------------------------------------------------+ 489 * | regs->ss | 490 * | regs->rsp | 491 * | regs->eflags | 492 * | regs->cs | 493 * | regs->ip | 494 * +----------------------------------------------------+ 495 * | regs->orig_ax = ~(interrupt number) | 496 * +----------------------------------------------------+ 497 * | return address | 498 * +----------------------------------------------------+ 499 */ 500ENTRY(interrupt_entry) 501 UNWIND_HINT_FUNC 502 ASM_CLAC 503 cld 504 505 testb $3, CS-ORIG_RAX+8(%rsp) 506 jz 1f 507 SWAPGS 508 509 /* 510 * Switch to the thread stack. The IRET frame and orig_ax are 511 * on the stack, as well as the return address. RDI..R12 are 512 * not (yet) on the stack and space has not (yet) been 513 * allocated for them. 514 */ 515 pushq %rdi 516 517 /* Need to switch before accessing the thread stack. */ 518 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi 519 movq %rsp, %rdi 520 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 521 522 /* 523 * We have RDI, return address, and orig_ax on the stack on 524 * top of the IRET frame. That means offset=24 525 */ 526 UNWIND_HINT_IRET_REGS base=%rdi offset=24 527 528 pushq 7*8(%rdi) /* regs->ss */ 529 pushq 6*8(%rdi) /* regs->rsp */ 530 pushq 5*8(%rdi) /* regs->eflags */ 531 pushq 4*8(%rdi) /* regs->cs */ 532 pushq 3*8(%rdi) /* regs->ip */ 533 pushq 2*8(%rdi) /* regs->orig_ax */ 534 pushq 8(%rdi) /* return address */ 535 UNWIND_HINT_FUNC 536 537 movq (%rdi), %rdi 5381: 539 540 PUSH_AND_CLEAR_REGS save_ret=1 541 ENCODE_FRAME_POINTER 8 542 543 testb $3, CS+8(%rsp) 544 jz 1f 545 546 /* 547 * IRQ from user mode. 548 * 549 * We need to tell lockdep that IRQs are off. We can't do this until 550 * we fix gsbase, and we should do it before enter_from_user_mode 551 * (which can take locks). Since TRACE_IRQS_OFF is idempotent, 552 * the simplest way to handle it is to just call it twice if 553 * we enter from user mode. There's no reason to optimize this since 554 * TRACE_IRQS_OFF is a no-op if lockdep is off. 555 */ 556 TRACE_IRQS_OFF 557 558 CALL_enter_from_user_mode 559 5601: 561 ENTER_IRQ_STACK old_rsp=%rdi save_ret=1 562 /* We entered an interrupt context - irqs are off: */ 563 TRACE_IRQS_OFF 564 565 ret 566END(interrupt_entry) 567 568 569/* Interrupt entry/exit. */ 570 571 /* 572 * The interrupt stubs push (~vector+0x80) onto the stack and 573 * then jump to common_interrupt. 574 */ 575 .p2align CONFIG_X86_L1_CACHE_SHIFT 576common_interrupt: 577 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ 578 call interrupt_entry 579 UNWIND_HINT_REGS indirect=1 580 call do_IRQ /* rdi points to pt_regs */ 581 /* 0(%rsp): old RSP */ 582ret_from_intr: 583 DISABLE_INTERRUPTS(CLBR_ANY) 584 TRACE_IRQS_OFF 585 586 LEAVE_IRQ_STACK 587 588 testb $3, CS(%rsp) 589 jz retint_kernel 590 591 /* Interrupt came from user space */ 592GLOBAL(retint_user) 593 mov %rsp,%rdi 594 call prepare_exit_to_usermode 595 TRACE_IRQS_IRETQ 596 597GLOBAL(swapgs_restore_regs_and_return_to_usermode) 598#ifdef CONFIG_DEBUG_ENTRY 599 /* Assert that pt_regs indicates user mode. */ 600 testb $3, CS(%rsp) 601 jnz 1f 602 ud2 6031: 604#endif 605 POP_REGS pop_rdi=0 606 607 /* 608 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. 609 * Save old stack pointer and switch to trampoline stack. 610 */ 611 movq %rsp, %rdi 612 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 613 614 /* Copy the IRET frame to the trampoline stack. */ 615 pushq 6*8(%rdi) /* SS */ 616 pushq 5*8(%rdi) /* RSP */ 617 pushq 4*8(%rdi) /* EFLAGS */ 618 pushq 3*8(%rdi) /* CS */ 619 pushq 2*8(%rdi) /* RIP */ 620 621 /* Push user RDI on the trampoline stack. */ 622 pushq (%rdi) 623 624 /* 625 * We are on the trampoline stack. All regs except RDI are live. 626 * We can do future final exit work right here. 627 */ 628 629 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 630 631 /* Restore RDI. */ 632 popq %rdi 633 SWAPGS 634 INTERRUPT_RETURN 635 636 637/* Returning to kernel space */ 638retint_kernel: 639#ifdef CONFIG_PREEMPT 640 /* Interrupts are off */ 641 /* Check if we need preemption */ 642 btl $9, EFLAGS(%rsp) /* were interrupts off? */ 643 jnc 1f 6440: cmpl $0, PER_CPU_VAR(__preempt_count) 645 jnz 1f 646 call preempt_schedule_irq 647 jmp 0b 6481: 649#endif 650 /* 651 * The iretq could re-enable interrupts: 652 */ 653 TRACE_IRQS_IRETQ 654 655GLOBAL(restore_regs_and_return_to_kernel) 656#ifdef CONFIG_DEBUG_ENTRY 657 /* Assert that pt_regs indicates kernel mode. */ 658 testb $3, CS(%rsp) 659 jz 1f 660 ud2 6611: 662#endif 663 POP_REGS 664 addq $8, %rsp /* skip regs->orig_ax */ 665 /* 666 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization 667 * when returning from IPI handler. 668 */ 669 INTERRUPT_RETURN 670 671ENTRY(native_iret) 672 UNWIND_HINT_IRET_REGS 673 /* 674 * Are we returning to a stack segment from the LDT? Note: in 675 * 64-bit mode SS:RSP on the exception stack is always valid. 676 */ 677#ifdef CONFIG_X86_ESPFIX64 678 testb $4, (SS-RIP)(%rsp) 679 jnz native_irq_return_ldt 680#endif 681 682.global native_irq_return_iret 683native_irq_return_iret: 684 /* 685 * This may fault. Non-paranoid faults on return to userspace are 686 * handled by fixup_bad_iret. These include #SS, #GP, and #NP. 687 * Double-faults due to espfix64 are handled in do_double_fault. 688 * Other faults here are fatal. 689 */ 690 iretq 691 692#ifdef CONFIG_X86_ESPFIX64 693native_irq_return_ldt: 694 /* 695 * We are running with user GSBASE. All GPRs contain their user 696 * values. We have a percpu ESPFIX stack that is eight slots 697 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom 698 * of the ESPFIX stack. 699 * 700 * We clobber RAX and RDI in this code. We stash RDI on the 701 * normal stack and RAX on the ESPFIX stack. 702 * 703 * The ESPFIX stack layout we set up looks like this: 704 * 705 * --- top of ESPFIX stack --- 706 * SS 707 * RSP 708 * RFLAGS 709 * CS 710 * RIP <-- RSP points here when we're done 711 * RAX <-- espfix_waddr points here 712 * --- bottom of ESPFIX stack --- 713 */ 714 715 pushq %rdi /* Stash user RDI */ 716 SWAPGS /* to kernel GS */ 717 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ 718 719 movq PER_CPU_VAR(espfix_waddr), %rdi 720 movq %rax, (0*8)(%rdi) /* user RAX */ 721 movq (1*8)(%rsp), %rax /* user RIP */ 722 movq %rax, (1*8)(%rdi) 723 movq (2*8)(%rsp), %rax /* user CS */ 724 movq %rax, (2*8)(%rdi) 725 movq (3*8)(%rsp), %rax /* user RFLAGS */ 726 movq %rax, (3*8)(%rdi) 727 movq (5*8)(%rsp), %rax /* user SS */ 728 movq %rax, (5*8)(%rdi) 729 movq (4*8)(%rsp), %rax /* user RSP */ 730 movq %rax, (4*8)(%rdi) 731 /* Now RAX == RSP. */ 732 733 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ 734 735 /* 736 * espfix_stack[31:16] == 0. The page tables are set up such that 737 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of 738 * espfix_waddr for any X. That is, there are 65536 RO aliases of 739 * the same page. Set up RSP so that RSP[31:16] contains the 740 * respective 16 bits of the /userspace/ RSP and RSP nonetheless 741 * still points to an RO alias of the ESPFIX stack. 742 */ 743 orq PER_CPU_VAR(espfix_stack), %rax 744 745 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 746 SWAPGS /* to user GS */ 747 popq %rdi /* Restore user RDI */ 748 749 movq %rax, %rsp 750 UNWIND_HINT_IRET_REGS offset=8 751 752 /* 753 * At this point, we cannot write to the stack any more, but we can 754 * still read. 755 */ 756 popq %rax /* Restore user RAX */ 757 758 /* 759 * RSP now points to an ordinary IRET frame, except that the page 760 * is read-only and RSP[31:16] are preloaded with the userspace 761 * values. We can now IRET back to userspace. 762 */ 763 jmp native_irq_return_iret 764#endif 765END(common_interrupt) 766 767/* 768 * APIC interrupts. 769 */ 770.macro apicinterrupt3 num sym do_sym 771ENTRY(\sym) 772 UNWIND_HINT_IRET_REGS 773 pushq $~(\num) 774.Lcommon_\sym: 775 call interrupt_entry 776 UNWIND_HINT_REGS indirect=1 777 call \do_sym /* rdi points to pt_regs */ 778 jmp ret_from_intr 779END(\sym) 780.endm 781 782/* Make sure APIC interrupt handlers end up in the irqentry section: */ 783#define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax" 784#define POP_SECTION_IRQENTRY .popsection 785 786.macro apicinterrupt num sym do_sym 787PUSH_SECTION_IRQENTRY 788apicinterrupt3 \num \sym \do_sym 789POP_SECTION_IRQENTRY 790.endm 791 792#ifdef CONFIG_SMP 793apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt 794apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt 795#endif 796 797#ifdef CONFIG_X86_UV 798apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt 799#endif 800 801apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt 802apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi 803 804#ifdef CONFIG_HAVE_KVM 805apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi 806apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi 807apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi 808#endif 809 810#ifdef CONFIG_X86_MCE_THRESHOLD 811apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt 812#endif 813 814#ifdef CONFIG_X86_MCE_AMD 815apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt 816#endif 817 818#ifdef CONFIG_X86_THERMAL_VECTOR 819apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt 820#endif 821 822#ifdef CONFIG_SMP 823apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt 824apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt 825apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt 826#endif 827 828apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt 829apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt 830 831#ifdef CONFIG_IRQ_WORK 832apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt 833#endif 834 835/* 836 * Exception entry points. 837 */ 838#define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8) 839 840/** 841 * idtentry - Generate an IDT entry stub 842 * @sym: Name of the generated entry point 843 * @do_sym: C function to be called 844 * @has_error_code: True if this IDT vector has an error code on the stack 845 * @paranoid: non-zero means that this vector may be invoked from 846 * kernel mode with user GSBASE and/or user CR3. 847 * 2 is special -- see below. 848 * @shift_ist: Set to an IST index if entries from kernel mode should 849 * decrement the IST stack so that nested entries get a 850 * fresh stack. (This is for #DB, which has a nasty habit 851 * of recursing.) 852 * 853 * idtentry generates an IDT stub that sets up a usable kernel context, 854 * creates struct pt_regs, and calls @do_sym. The stub has the following 855 * special behaviors: 856 * 857 * On an entry from user mode, the stub switches from the trampoline or 858 * IST stack to the normal thread stack. On an exit to user mode, the 859 * normal exit-to-usermode path is invoked. 860 * 861 * On an exit to kernel mode, if @paranoid == 0, we check for preemption, 862 * whereas we omit the preemption check if @paranoid != 0. This is purely 863 * because the implementation is simpler this way. The kernel only needs 864 * to check for asynchronous kernel preemption when IRQ handlers return. 865 * 866 * If @paranoid == 0, then the stub will handle IRET faults by pretending 867 * that the fault came from user mode. It will handle gs_change faults by 868 * pretending that the fault happened with kernel GSBASE. Since this handling 869 * is omitted for @paranoid != 0, the #GP, #SS, and #NP stubs must have 870 * @paranoid == 0. This special handling will do the wrong thing for 871 * espfix-induced #DF on IRET, so #DF must not use @paranoid == 0. 872 * 873 * @paranoid == 2 is special: the stub will never switch stacks. This is for 874 * #DF: if the thread stack is somehow unusable, we'll still get a useful OOPS. 875 */ 876.macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 877ENTRY(\sym) 878 UNWIND_HINT_IRET_REGS offset=\has_error_code*8 879 880 /* Sanity check */ 881 .if \shift_ist != -1 && \paranoid == 0 882 .error "using shift_ist requires paranoid=1" 883 .endif 884 885 ASM_CLAC 886 887 .if \has_error_code == 0 888 pushq $-1 /* ORIG_RAX: no syscall to restart */ 889 .endif 890 891 .if \paranoid == 1 892 testb $3, CS-ORIG_RAX(%rsp) /* If coming from userspace, switch stacks */ 893 jnz .Lfrom_usermode_switch_stack_\@ 894 .endif 895 896 .if \paranoid 897 call paranoid_entry 898 .else 899 call error_entry 900 .endif 901 UNWIND_HINT_REGS 902 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ 903 904 .if \paranoid 905 .if \shift_ist != -1 906 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ 907 .else 908 TRACE_IRQS_OFF 909 .endif 910 .endif 911 912 movq %rsp, %rdi /* pt_regs pointer */ 913 914 .if \has_error_code 915 movq ORIG_RAX(%rsp), %rsi /* get error code */ 916 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 917 .else 918 xorl %esi, %esi /* no error code */ 919 .endif 920 921 .if \shift_ist != -1 922 subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 923 .endif 924 925 call \do_sym 926 927 .if \shift_ist != -1 928 addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 929 .endif 930 931 /* these procedures expect "no swapgs" flag in ebx */ 932 .if \paranoid 933 jmp paranoid_exit 934 .else 935 jmp error_exit 936 .endif 937 938 .if \paranoid == 1 939 /* 940 * Entry from userspace. Switch stacks and treat it 941 * as a normal entry. This means that paranoid handlers 942 * run in real process context if user_mode(regs). 943 */ 944.Lfrom_usermode_switch_stack_\@: 945 call error_entry 946 947 movq %rsp, %rdi /* pt_regs pointer */ 948 949 .if \has_error_code 950 movq ORIG_RAX(%rsp), %rsi /* get error code */ 951 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 952 .else 953 xorl %esi, %esi /* no error code */ 954 .endif 955 956 call \do_sym 957 958 jmp error_exit 959 .endif 960END(\sym) 961.endm 962 963idtentry divide_error do_divide_error has_error_code=0 964idtentry overflow do_overflow has_error_code=0 965idtentry bounds do_bounds has_error_code=0 966idtentry invalid_op do_invalid_op has_error_code=0 967idtentry device_not_available do_device_not_available has_error_code=0 968idtentry double_fault do_double_fault has_error_code=1 paranoid=2 969idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 970idtentry invalid_TSS do_invalid_TSS has_error_code=1 971idtentry segment_not_present do_segment_not_present has_error_code=1 972idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 973idtentry coprocessor_error do_coprocessor_error has_error_code=0 974idtentry alignment_check do_alignment_check has_error_code=1 975idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 976 977 978 /* 979 * Reload gs selector with exception handling 980 * edi: new selector 981 */ 982ENTRY(native_load_gs_index) 983 FRAME_BEGIN 984 pushfq 985 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) 986 TRACE_IRQS_OFF 987 SWAPGS 988.Lgs_change: 989 movl %edi, %gs 9902: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE 991 SWAPGS 992 TRACE_IRQS_FLAGS (%rsp) 993 popfq 994 FRAME_END 995 ret 996ENDPROC(native_load_gs_index) 997EXPORT_SYMBOL(native_load_gs_index) 998 999 _ASM_EXTABLE(.Lgs_change, bad_gs) 1000 .section .fixup, "ax" 1001 /* running with kernelgs */ 1002bad_gs: 1003 SWAPGS /* switch back to user gs */ 1004.macro ZAP_GS 1005 /* This can't be a string because the preprocessor needs to see it. */ 1006 movl $__USER_DS, %eax 1007 movl %eax, %gs 1008.endm 1009 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG 1010 xorl %eax, %eax 1011 movl %eax, %gs 1012 jmp 2b 1013 .previous 1014 1015/* Call softirq on interrupt stack. Interrupts are off. */ 1016ENTRY(do_softirq_own_stack) 1017 pushq %rbp 1018 mov %rsp, %rbp 1019 ENTER_IRQ_STACK regs=0 old_rsp=%r11 1020 call __do_softirq 1021 LEAVE_IRQ_STACK regs=0 1022 leaveq 1023 ret 1024ENDPROC(do_softirq_own_stack) 1025 1026#ifdef CONFIG_XEN_PV 1027idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0 1028 1029/* 1030 * A note on the "critical region" in our callback handler. 1031 * We want to avoid stacking callback handlers due to events occurring 1032 * during handling of the last event. To do this, we keep events disabled 1033 * until we've done all processing. HOWEVER, we must enable events before 1034 * popping the stack frame (can't be done atomically) and so it would still 1035 * be possible to get enough handler activations to overflow the stack. 1036 * Although unlikely, bugs of that kind are hard to track down, so we'd 1037 * like to avoid the possibility. 1038 * So, on entry to the handler we detect whether we interrupted an 1039 * existing activation in its critical region -- if so, we pop the current 1040 * activation and restart the handler using the previous one. 1041 */ 1042ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ 1043 1044/* 1045 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will 1046 * see the correct pointer to the pt_regs 1047 */ 1048 UNWIND_HINT_FUNC 1049 movq %rdi, %rsp /* we don't return, adjust the stack frame */ 1050 UNWIND_HINT_REGS 1051 1052 ENTER_IRQ_STACK old_rsp=%r10 1053 call xen_evtchn_do_upcall 1054 LEAVE_IRQ_STACK 1055 1056#ifndef CONFIG_PREEMPT 1057 call xen_maybe_preempt_hcall 1058#endif 1059 jmp error_exit 1060END(xen_do_hypervisor_callback) 1061 1062/* 1063 * Hypervisor uses this for application faults while it executes. 1064 * We get here for two reasons: 1065 * 1. Fault while reloading DS, ES, FS or GS 1066 * 2. Fault while executing IRET 1067 * Category 1 we do not need to fix up as Xen has already reloaded all segment 1068 * registers that could be reloaded and zeroed the others. 1069 * Category 2 we fix up by killing the current process. We cannot use the 1070 * normal Linux return path in this case because if we use the IRET hypercall 1071 * to pop the stack frame we end up in an infinite loop of failsafe callbacks. 1072 * We distinguish between categories by comparing each saved segment register 1073 * with its current contents: any discrepancy means we in category 1. 1074 */ 1075ENTRY(xen_failsafe_callback) 1076 UNWIND_HINT_EMPTY 1077 movl %ds, %ecx 1078 cmpw %cx, 0x10(%rsp) 1079 jne 1f 1080 movl %es, %ecx 1081 cmpw %cx, 0x18(%rsp) 1082 jne 1f 1083 movl %fs, %ecx 1084 cmpw %cx, 0x20(%rsp) 1085 jne 1f 1086 movl %gs, %ecx 1087 cmpw %cx, 0x28(%rsp) 1088 jne 1f 1089 /* All segments match their saved values => Category 2 (Bad IRET). */ 1090 movq (%rsp), %rcx 1091 movq 8(%rsp), %r11 1092 addq $0x30, %rsp 1093 pushq $0 /* RIP */ 1094 UNWIND_HINT_IRET_REGS offset=8 1095 jmp general_protection 10961: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ 1097 movq (%rsp), %rcx 1098 movq 8(%rsp), %r11 1099 addq $0x30, %rsp 1100 UNWIND_HINT_IRET_REGS 1101 pushq $-1 /* orig_ax = -1 => not a system call */ 1102 PUSH_AND_CLEAR_REGS 1103 ENCODE_FRAME_POINTER 1104 jmp error_exit 1105END(xen_failsafe_callback) 1106#endif /* CONFIG_XEN_PV */ 1107 1108#ifdef CONFIG_XEN_PVHVM 1109apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1110 xen_hvm_callback_vector xen_evtchn_do_upcall 1111#endif 1112 1113 1114#if IS_ENABLED(CONFIG_HYPERV) 1115apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1116 hyperv_callback_vector hyperv_vector_handler 1117 1118apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \ 1119 hyperv_reenlightenment_vector hyperv_reenlightenment_intr 1120 1121apicinterrupt3 HYPERV_STIMER0_VECTOR \ 1122 hv_stimer0_callback_vector hv_stimer0_vector_handler 1123#endif /* CONFIG_HYPERV */ 1124 1125idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK 1126idtentry int3 do_int3 has_error_code=0 1127idtentry stack_segment do_stack_segment has_error_code=1 1128 1129#ifdef CONFIG_XEN_PV 1130idtentry xennmi do_nmi has_error_code=0 1131idtentry xendebug do_debug has_error_code=0 1132idtentry xenint3 do_int3 has_error_code=0 1133#endif 1134 1135idtentry general_protection do_general_protection has_error_code=1 1136idtentry page_fault do_page_fault has_error_code=1 1137 1138#ifdef CONFIG_KVM_GUEST 1139idtentry async_page_fault do_async_page_fault has_error_code=1 1140#endif 1141 1142#ifdef CONFIG_X86_MCE 1143idtentry machine_check do_mce has_error_code=0 paranoid=1 1144#endif 1145 1146/* 1147 * Save all registers in pt_regs, and switch gs if needed. 1148 * Use slow, but surefire "are we in kernel?" check. 1149 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise 1150 */ 1151ENTRY(paranoid_entry) 1152 UNWIND_HINT_FUNC 1153 cld 1154 PUSH_AND_CLEAR_REGS save_ret=1 1155 ENCODE_FRAME_POINTER 8 1156 movl $1, %ebx 1157 movl $MSR_GS_BASE, %ecx 1158 rdmsr 1159 testl %edx, %edx 1160 js 1f /* negative -> in kernel */ 1161 SWAPGS 1162 xorl %ebx, %ebx 1163 11641: 1165 /* 1166 * Always stash CR3 in %r14. This value will be restored, 1167 * verbatim, at exit. Needed if paranoid_entry interrupted 1168 * another entry that already switched to the user CR3 value 1169 * but has not yet returned to userspace. 1170 * 1171 * This is also why CS (stashed in the "iret frame" by the 1172 * hardware at entry) can not be used: this may be a return 1173 * to kernel code, but with a user CR3 value. 1174 */ 1175 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 1176 1177 ret 1178END(paranoid_entry) 1179 1180/* 1181 * "Paranoid" exit path from exception stack. This is invoked 1182 * only on return from non-NMI IST interrupts that came 1183 * from kernel space. 1184 * 1185 * We may be returning to very strange contexts (e.g. very early 1186 * in syscall entry), so checking for preemption here would 1187 * be complicated. Fortunately, we there's no good reason 1188 * to try to handle preemption here. 1189 * 1190 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) 1191 */ 1192ENTRY(paranoid_exit) 1193 UNWIND_HINT_REGS 1194 DISABLE_INTERRUPTS(CLBR_ANY) 1195 TRACE_IRQS_OFF_DEBUG 1196 testl %ebx, %ebx /* swapgs needed? */ 1197 jnz .Lparanoid_exit_no_swapgs 1198 TRACE_IRQS_IRETQ 1199 /* Always restore stashed CR3 value (see paranoid_entry) */ 1200 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1201 SWAPGS_UNSAFE_STACK 1202 jmp .Lparanoid_exit_restore 1203.Lparanoid_exit_no_swapgs: 1204 TRACE_IRQS_IRETQ_DEBUG 1205 /* Always restore stashed CR3 value (see paranoid_entry) */ 1206 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1207.Lparanoid_exit_restore: 1208 jmp restore_regs_and_return_to_kernel 1209END(paranoid_exit) 1210 1211/* 1212 * Save all registers in pt_regs, and switch GS if needed. 1213 */ 1214ENTRY(error_entry) 1215 UNWIND_HINT_FUNC 1216 cld 1217 PUSH_AND_CLEAR_REGS save_ret=1 1218 ENCODE_FRAME_POINTER 8 1219 testb $3, CS+8(%rsp) 1220 jz .Lerror_kernelspace 1221 1222 /* 1223 * We entered from user mode or we're pretending to have entered 1224 * from user mode due to an IRET fault. 1225 */ 1226 SWAPGS 1227 /* We have user CR3. Change to kernel CR3. */ 1228 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1229 1230.Lerror_entry_from_usermode_after_swapgs: 1231 /* Put us onto the real thread stack. */ 1232 popq %r12 /* save return addr in %12 */ 1233 movq %rsp, %rdi /* arg0 = pt_regs pointer */ 1234 call sync_regs 1235 movq %rax, %rsp /* switch stack */ 1236 ENCODE_FRAME_POINTER 1237 pushq %r12 1238 1239 /* 1240 * We need to tell lockdep that IRQs are off. We can't do this until 1241 * we fix gsbase, and we should do it before enter_from_user_mode 1242 * (which can take locks). 1243 */ 1244 TRACE_IRQS_OFF 1245 CALL_enter_from_user_mode 1246 ret 1247 1248.Lerror_entry_done: 1249 TRACE_IRQS_OFF 1250 ret 1251 1252 /* 1253 * There are two places in the kernel that can potentially fault with 1254 * usergs. Handle them here. B stepping K8s sometimes report a 1255 * truncated RIP for IRET exceptions returning to compat mode. Check 1256 * for these here too. 1257 */ 1258.Lerror_kernelspace: 1259 leaq native_irq_return_iret(%rip), %rcx 1260 cmpq %rcx, RIP+8(%rsp) 1261 je .Lerror_bad_iret 1262 movl %ecx, %eax /* zero extend */ 1263 cmpq %rax, RIP+8(%rsp) 1264 je .Lbstep_iret 1265 cmpq $.Lgs_change, RIP+8(%rsp) 1266 jne .Lerror_entry_done 1267 1268 /* 1269 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up 1270 * gsbase and proceed. We'll fix up the exception and land in 1271 * .Lgs_change's error handler with kernel gsbase. 1272 */ 1273 SWAPGS 1274 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1275 jmp .Lerror_entry_done 1276 1277.Lbstep_iret: 1278 /* Fix truncated RIP */ 1279 movq %rcx, RIP+8(%rsp) 1280 /* fall through */ 1281 1282.Lerror_bad_iret: 1283 /* 1284 * We came from an IRET to user mode, so we have user 1285 * gsbase and CR3. Switch to kernel gsbase and CR3: 1286 */ 1287 SWAPGS 1288 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1289 1290 /* 1291 * Pretend that the exception came from user mode: set up pt_regs 1292 * as if we faulted immediately after IRET. 1293 */ 1294 mov %rsp, %rdi 1295 call fixup_bad_iret 1296 mov %rax, %rsp 1297 jmp .Lerror_entry_from_usermode_after_swapgs 1298END(error_entry) 1299 1300ENTRY(error_exit) 1301 UNWIND_HINT_REGS 1302 DISABLE_INTERRUPTS(CLBR_ANY) 1303 TRACE_IRQS_OFF 1304 testb $3, CS(%rsp) 1305 jz retint_kernel 1306 jmp retint_user 1307END(error_exit) 1308 1309/* 1310 * Runs on exception stack. Xen PV does not go through this path at all, 1311 * so we can use real assembly here. 1312 * 1313 * Registers: 1314 * %r14: Used to save/restore the CR3 of the interrupted context 1315 * when PAGE_TABLE_ISOLATION is in use. Do not clobber. 1316 */ 1317ENTRY(nmi) 1318 UNWIND_HINT_IRET_REGS 1319 1320 /* 1321 * We allow breakpoints in NMIs. If a breakpoint occurs, then 1322 * the iretq it performs will take us out of NMI context. 1323 * This means that we can have nested NMIs where the next 1324 * NMI is using the top of the stack of the previous NMI. We 1325 * can't let it execute because the nested NMI will corrupt the 1326 * stack of the previous NMI. NMI handlers are not re-entrant 1327 * anyway. 1328 * 1329 * To handle this case we do the following: 1330 * Check the a special location on the stack that contains 1331 * a variable that is set when NMIs are executing. 1332 * The interrupted task's stack is also checked to see if it 1333 * is an NMI stack. 1334 * If the variable is not set and the stack is not the NMI 1335 * stack then: 1336 * o Set the special variable on the stack 1337 * o Copy the interrupt frame into an "outermost" location on the 1338 * stack 1339 * o Copy the interrupt frame into an "iret" location on the stack 1340 * o Continue processing the NMI 1341 * If the variable is set or the previous stack is the NMI stack: 1342 * o Modify the "iret" location to jump to the repeat_nmi 1343 * o return back to the first NMI 1344 * 1345 * Now on exit of the first NMI, we first clear the stack variable 1346 * The NMI stack will tell any nested NMIs at that point that it is 1347 * nested. Then we pop the stack normally with iret, and if there was 1348 * a nested NMI that updated the copy interrupt stack frame, a 1349 * jump will be made to the repeat_nmi code that will handle the second 1350 * NMI. 1351 * 1352 * However, espfix prevents us from directly returning to userspace 1353 * with a single IRET instruction. Similarly, IRET to user mode 1354 * can fault. We therefore handle NMIs from user space like 1355 * other IST entries. 1356 */ 1357 1358 ASM_CLAC 1359 1360 /* Use %rdx as our temp variable throughout */ 1361 pushq %rdx 1362 1363 testb $3, CS-RIP+8(%rsp) 1364 jz .Lnmi_from_kernel 1365 1366 /* 1367 * NMI from user mode. We need to run on the thread stack, but we 1368 * can't go through the normal entry paths: NMIs are masked, and 1369 * we don't want to enable interrupts, because then we'll end 1370 * up in an awkward situation in which IRQs are on but NMIs 1371 * are off. 1372 * 1373 * We also must not push anything to the stack before switching 1374 * stacks lest we corrupt the "NMI executing" variable. 1375 */ 1376 1377 swapgs 1378 cld 1379 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx 1380 movq %rsp, %rdx 1381 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 1382 UNWIND_HINT_IRET_REGS base=%rdx offset=8 1383 pushq 5*8(%rdx) /* pt_regs->ss */ 1384 pushq 4*8(%rdx) /* pt_regs->rsp */ 1385 pushq 3*8(%rdx) /* pt_regs->flags */ 1386 pushq 2*8(%rdx) /* pt_regs->cs */ 1387 pushq 1*8(%rdx) /* pt_regs->rip */ 1388 UNWIND_HINT_IRET_REGS 1389 pushq $-1 /* pt_regs->orig_ax */ 1390 PUSH_AND_CLEAR_REGS rdx=(%rdx) 1391 ENCODE_FRAME_POINTER 1392 1393 /* 1394 * At this point we no longer need to worry about stack damage 1395 * due to nesting -- we're on the normal thread stack and we're 1396 * done with the NMI stack. 1397 */ 1398 1399 movq %rsp, %rdi 1400 movq $-1, %rsi 1401 call do_nmi 1402 1403 /* 1404 * Return back to user mode. We must *not* do the normal exit 1405 * work, because we don't want to enable interrupts. 1406 */ 1407 jmp swapgs_restore_regs_and_return_to_usermode 1408 1409.Lnmi_from_kernel: 1410 /* 1411 * Here's what our stack frame will look like: 1412 * +---------------------------------------------------------+ 1413 * | original SS | 1414 * | original Return RSP | 1415 * | original RFLAGS | 1416 * | original CS | 1417 * | original RIP | 1418 * +---------------------------------------------------------+ 1419 * | temp storage for rdx | 1420 * +---------------------------------------------------------+ 1421 * | "NMI executing" variable | 1422 * +---------------------------------------------------------+ 1423 * | iret SS } Copied from "outermost" frame | 1424 * | iret Return RSP } on each loop iteration; overwritten | 1425 * | iret RFLAGS } by a nested NMI to force another | 1426 * | iret CS } iteration if needed. | 1427 * | iret RIP } | 1428 * +---------------------------------------------------------+ 1429 * | outermost SS } initialized in first_nmi; | 1430 * | outermost Return RSP } will not be changed before | 1431 * | outermost RFLAGS } NMI processing is done. | 1432 * | outermost CS } Copied to "iret" frame on each | 1433 * | outermost RIP } iteration. | 1434 * +---------------------------------------------------------+ 1435 * | pt_regs | 1436 * +---------------------------------------------------------+ 1437 * 1438 * The "original" frame is used by hardware. Before re-enabling 1439 * NMIs, we need to be done with it, and we need to leave enough 1440 * space for the asm code here. 1441 * 1442 * We return by executing IRET while RSP points to the "iret" frame. 1443 * That will either return for real or it will loop back into NMI 1444 * processing. 1445 * 1446 * The "outermost" frame is copied to the "iret" frame on each 1447 * iteration of the loop, so each iteration starts with the "iret" 1448 * frame pointing to the final return target. 1449 */ 1450 1451 /* 1452 * Determine whether we're a nested NMI. 1453 * 1454 * If we interrupted kernel code between repeat_nmi and 1455 * end_repeat_nmi, then we are a nested NMI. We must not 1456 * modify the "iret" frame because it's being written by 1457 * the outer NMI. That's okay; the outer NMI handler is 1458 * about to about to call do_nmi anyway, so we can just 1459 * resume the outer NMI. 1460 */ 1461 1462 movq $repeat_nmi, %rdx 1463 cmpq 8(%rsp), %rdx 1464 ja 1f 1465 movq $end_repeat_nmi, %rdx 1466 cmpq 8(%rsp), %rdx 1467 ja nested_nmi_out 14681: 1469 1470 /* 1471 * Now check "NMI executing". If it's set, then we're nested. 1472 * This will not detect if we interrupted an outer NMI just 1473 * before IRET. 1474 */ 1475 cmpl $1, -8(%rsp) 1476 je nested_nmi 1477 1478 /* 1479 * Now test if the previous stack was an NMI stack. This covers 1480 * the case where we interrupt an outer NMI after it clears 1481 * "NMI executing" but before IRET. We need to be careful, though: 1482 * there is one case in which RSP could point to the NMI stack 1483 * despite there being no NMI active: naughty userspace controls 1484 * RSP at the very beginning of the SYSCALL targets. We can 1485 * pull a fast one on naughty userspace, though: we program 1486 * SYSCALL to mask DF, so userspace cannot cause DF to be set 1487 * if it controls the kernel's RSP. We set DF before we clear 1488 * "NMI executing". 1489 */ 1490 lea 6*8(%rsp), %rdx 1491 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ 1492 cmpq %rdx, 4*8(%rsp) 1493 /* If the stack pointer is above the NMI stack, this is a normal NMI */ 1494 ja first_nmi 1495 1496 subq $EXCEPTION_STKSZ, %rdx 1497 cmpq %rdx, 4*8(%rsp) 1498 /* If it is below the NMI stack, it is a normal NMI */ 1499 jb first_nmi 1500 1501 /* Ah, it is within the NMI stack. */ 1502 1503 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) 1504 jz first_nmi /* RSP was user controlled. */ 1505 1506 /* This is a nested NMI. */ 1507 1508nested_nmi: 1509 /* 1510 * Modify the "iret" frame to point to repeat_nmi, forcing another 1511 * iteration of NMI handling. 1512 */ 1513 subq $8, %rsp 1514 leaq -10*8(%rsp), %rdx 1515 pushq $__KERNEL_DS 1516 pushq %rdx 1517 pushfq 1518 pushq $__KERNEL_CS 1519 pushq $repeat_nmi 1520 1521 /* Put stack back */ 1522 addq $(6*8), %rsp 1523 1524nested_nmi_out: 1525 popq %rdx 1526 1527 /* We are returning to kernel mode, so this cannot result in a fault. */ 1528 iretq 1529 1530first_nmi: 1531 /* Restore rdx. */ 1532 movq (%rsp), %rdx 1533 1534 /* Make room for "NMI executing". */ 1535 pushq $0 1536 1537 /* Leave room for the "iret" frame */ 1538 subq $(5*8), %rsp 1539 1540 /* Copy the "original" frame to the "outermost" frame */ 1541 .rept 5 1542 pushq 11*8(%rsp) 1543 .endr 1544 UNWIND_HINT_IRET_REGS 1545 1546 /* Everything up to here is safe from nested NMIs */ 1547 1548#ifdef CONFIG_DEBUG_ENTRY 1549 /* 1550 * For ease of testing, unmask NMIs right away. Disabled by 1551 * default because IRET is very expensive. 1552 */ 1553 pushq $0 /* SS */ 1554 pushq %rsp /* RSP (minus 8 because of the previous push) */ 1555 addq $8, (%rsp) /* Fix up RSP */ 1556 pushfq /* RFLAGS */ 1557 pushq $__KERNEL_CS /* CS */ 1558 pushq $1f /* RIP */ 1559 iretq /* continues at repeat_nmi below */ 1560 UNWIND_HINT_IRET_REGS 15611: 1562#endif 1563 1564repeat_nmi: 1565 /* 1566 * If there was a nested NMI, the first NMI's iret will return 1567 * here. But NMIs are still enabled and we can take another 1568 * nested NMI. The nested NMI checks the interrupted RIP to see 1569 * if it is between repeat_nmi and end_repeat_nmi, and if so 1570 * it will just return, as we are about to repeat an NMI anyway. 1571 * This makes it safe to copy to the stack frame that a nested 1572 * NMI will update. 1573 * 1574 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if 1575 * we're repeating an NMI, gsbase has the same value that it had on 1576 * the first iteration. paranoid_entry will load the kernel 1577 * gsbase if needed before we call do_nmi. "NMI executing" 1578 * is zero. 1579 */ 1580 movq $1, 10*8(%rsp) /* Set "NMI executing". */ 1581 1582 /* 1583 * Copy the "outermost" frame to the "iret" frame. NMIs that nest 1584 * here must not modify the "iret" frame while we're writing to 1585 * it or it will end up containing garbage. 1586 */ 1587 addq $(10*8), %rsp 1588 .rept 5 1589 pushq -6*8(%rsp) 1590 .endr 1591 subq $(5*8), %rsp 1592end_repeat_nmi: 1593 1594 /* 1595 * Everything below this point can be preempted by a nested NMI. 1596 * If this happens, then the inner NMI will change the "iret" 1597 * frame to point back to repeat_nmi. 1598 */ 1599 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1600 1601 /* 1602 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit 1603 * as we should not be calling schedule in NMI context. 1604 * Even with normal interrupts enabled. An NMI should not be 1605 * setting NEED_RESCHED or anything that normal interrupts and 1606 * exceptions might do. 1607 */ 1608 call paranoid_entry 1609 UNWIND_HINT_REGS 1610 1611 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ 1612 movq %rsp, %rdi 1613 movq $-1, %rsi 1614 call do_nmi 1615 1616 /* Always restore stashed CR3 value (see paranoid_entry) */ 1617 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 1618 1619 testl %ebx, %ebx /* swapgs needed? */ 1620 jnz nmi_restore 1621nmi_swapgs: 1622 SWAPGS_UNSAFE_STACK 1623nmi_restore: 1624 POP_REGS 1625 1626 /* 1627 * Skip orig_ax and the "outermost" frame to point RSP at the "iret" 1628 * at the "iret" frame. 1629 */ 1630 addq $6*8, %rsp 1631 1632 /* 1633 * Clear "NMI executing". Set DF first so that we can easily 1634 * distinguish the remaining code between here and IRET from 1635 * the SYSCALL entry and exit paths. 1636 * 1637 * We arguably should just inspect RIP instead, but I (Andy) wrote 1638 * this code when I had the misapprehension that Xen PV supported 1639 * NMIs, and Xen PV would break that approach. 1640 */ 1641 std 1642 movq $0, 5*8(%rsp) /* clear "NMI executing" */ 1643 1644 /* 1645 * iretq reads the "iret" frame and exits the NMI stack in a 1646 * single instruction. We are returning to kernel mode, so this 1647 * cannot result in a fault. Similarly, we don't need to worry 1648 * about espfix64 on the way back to kernel mode. 1649 */ 1650 iretq 1651END(nmi) 1652 1653ENTRY(ignore_sysret) 1654 UNWIND_HINT_EMPTY 1655 mov $-ENOSYS, %eax 1656 sysret 1657END(ignore_sysret) 1658 1659ENTRY(rewind_stack_do_exit) 1660 UNWIND_HINT_FUNC 1661 /* Prevent any naive code from trying to unwind to our caller. */ 1662 xorl %ebp, %ebp 1663 1664 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax 1665 leaq -PTREGS_SIZE(%rax), %rsp 1666 UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE 1667 1668 call do_exit 1669END(rewind_stack_do_exit) 1670