1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86_64/entry.S 4 * 5 * Copyright (C) 1991, 1992 Linus Torvalds 6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs 7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 8 * 9 * entry.S contains the system-call and fault low-level handling routines. 10 * 11 * Some of this is documented in Documentation/x86/entry_64.txt 12 * 13 * A note on terminology: 14 * - iret frame: Architecture defined interrupt frame from SS to RIP 15 * at the top of the kernel process stack. 16 * 17 * Some macro usage: 18 * - ENTRY/END: Define functions in the symbol table. 19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging. 20 * - idtentry: Define exception entry points. 21 */ 22#include <linux/linkage.h> 23#include <asm/segment.h> 24#include <asm/cache.h> 25#include <asm/errno.h> 26#include <asm/asm-offsets.h> 27#include <asm/msr.h> 28#include <asm/unistd.h> 29#include <asm/thread_info.h> 30#include <asm/hw_irq.h> 31#include <asm/page_types.h> 32#include <asm/irqflags.h> 33#include <asm/paravirt.h> 34#include <asm/percpu.h> 35#include <asm/asm.h> 36#include <asm/smap.h> 37#include <asm/pgtable_types.h> 38#include <asm/export.h> 39#include <asm/frame.h> 40#include <asm/nospec-branch.h> 41#include <linux/err.h> 42 43#include "calling.h" 44 45.code64 46.section .entry.text, "ax" 47 48#ifdef CONFIG_PARAVIRT 49ENTRY(native_usergs_sysret64) 50 UNWIND_HINT_EMPTY 51 swapgs 52 sysretq 53END(native_usergs_sysret64) 54#endif /* CONFIG_PARAVIRT */ 55 56.macro TRACE_IRQS_FLAGS flags:req 57#ifdef CONFIG_TRACE_IRQFLAGS 58 bt $9, \flags /* interrupts off? */ 59 jnc 1f 60 TRACE_IRQS_ON 611: 62#endif 63.endm 64 65.macro TRACE_IRQS_IRETQ 66 TRACE_IRQS_FLAGS EFLAGS(%rsp) 67.endm 68 69/* 70 * When dynamic function tracer is enabled it will add a breakpoint 71 * to all locations that it is about to modify, sync CPUs, update 72 * all the code, sync CPUs, then remove the breakpoints. In this time 73 * if lockdep is enabled, it might jump back into the debug handler 74 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). 75 * 76 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to 77 * make sure the stack pointer does not get reset back to the top 78 * of the debug stack, and instead just reuses the current stack. 79 */ 80#if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) 81 82.macro TRACE_IRQS_OFF_DEBUG 83 call debug_stack_set_zero 84 TRACE_IRQS_OFF 85 call debug_stack_reset 86.endm 87 88.macro TRACE_IRQS_ON_DEBUG 89 call debug_stack_set_zero 90 TRACE_IRQS_ON 91 call debug_stack_reset 92.endm 93 94.macro TRACE_IRQS_IRETQ_DEBUG 95 bt $9, EFLAGS(%rsp) /* interrupts off? */ 96 jnc 1f 97 TRACE_IRQS_ON_DEBUG 981: 99.endm 100 101#else 102# define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF 103# define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON 104# define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ 105#endif 106 107/* 108 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. 109 * 110 * This is the only entry point used for 64-bit system calls. The 111 * hardware interface is reasonably well designed and the register to 112 * argument mapping Linux uses fits well with the registers that are 113 * available when SYSCALL is used. 114 * 115 * SYSCALL instructions can be found inlined in libc implementations as 116 * well as some other programs and libraries. There are also a handful 117 * of SYSCALL instructions in the vDSO used, for example, as a 118 * clock_gettimeofday fallback. 119 * 120 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, 121 * then loads new ss, cs, and rip from previously programmed MSRs. 122 * rflags gets masked by a value from another MSR (so CLD and CLAC 123 * are not needed). SYSCALL does not save anything on the stack 124 * and does not change rsp. 125 * 126 * Registers on entry: 127 * rax system call number 128 * rcx return address 129 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) 130 * rdi arg0 131 * rsi arg1 132 * rdx arg2 133 * r10 arg3 (needs to be moved to rcx to conform to C ABI) 134 * r8 arg4 135 * r9 arg5 136 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) 137 * 138 * Only called from user space. 139 * 140 * When user can change pt_regs->foo always force IRET. That is because 141 * it deals with uncanonical addresses better. SYSRET has trouble 142 * with them due to bugs in both AMD and Intel CPUs. 143 */ 144 145 .pushsection .entry_trampoline, "ax" 146 147/* 148 * The code in here gets remapped into cpu_entry_area's trampoline. This means 149 * that the assembler and linker have the wrong idea as to where this code 150 * lives (and, in fact, it's mapped more than once, so it's not even at a 151 * fixed address). So we can't reference any symbols outside the entry 152 * trampoline and expect it to work. 153 * 154 * Instead, we carefully abuse %rip-relative addressing. 155 * _entry_trampoline(%rip) refers to the start of the remapped) entry 156 * trampoline. We can thus find cpu_entry_area with this macro: 157 */ 158 159#define CPU_ENTRY_AREA \ 160 _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip) 161 162/* The top word of the SYSENTER stack is hot and is usable as scratch space. */ 163#define RSP_SCRATCH CPU_ENTRY_AREA_entry_stack + \ 164 SIZEOF_entry_stack - 8 + CPU_ENTRY_AREA 165 166ENTRY(entry_SYSCALL_64_trampoline) 167 UNWIND_HINT_EMPTY 168 swapgs 169 170 /* Stash the user RSP. */ 171 movq %rsp, RSP_SCRATCH 172 173 /* Note: using %rsp as a scratch reg. */ 174 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp 175 176 /* Load the top of the task stack into RSP */ 177 movq CPU_ENTRY_AREA_tss + TSS_sp1 + CPU_ENTRY_AREA, %rsp 178 179 /* Start building the simulated IRET frame. */ 180 pushq $__USER_DS /* pt_regs->ss */ 181 pushq RSP_SCRATCH /* pt_regs->sp */ 182 pushq %r11 /* pt_regs->flags */ 183 pushq $__USER_CS /* pt_regs->cs */ 184 pushq %rcx /* pt_regs->ip */ 185 186 /* 187 * x86 lacks a near absolute jump, and we can't jump to the real 188 * entry text with a relative jump. We could push the target 189 * address and then use retq, but this destroys the pipeline on 190 * many CPUs (wasting over 20 cycles on Sandy Bridge). Instead, 191 * spill RDI and restore it in a second-stage trampoline. 192 */ 193 pushq %rdi 194 movq $entry_SYSCALL_64_stage2, %rdi 195 JMP_NOSPEC %rdi 196END(entry_SYSCALL_64_trampoline) 197 198 .popsection 199 200ENTRY(entry_SYSCALL_64_stage2) 201 UNWIND_HINT_EMPTY 202 popq %rdi 203 jmp entry_SYSCALL_64_after_hwframe 204END(entry_SYSCALL_64_stage2) 205 206ENTRY(entry_SYSCALL_64) 207 UNWIND_HINT_EMPTY 208 /* 209 * Interrupts are off on entry. 210 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, 211 * it is too small to ever cause noticeable irq latency. 212 */ 213 214 swapgs 215 /* 216 * This path is not taken when PAGE_TABLE_ISOLATION is disabled so it 217 * is not required to switch CR3. 218 */ 219 movq %rsp, PER_CPU_VAR(rsp_scratch) 220 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 221 222 /* Construct struct pt_regs on stack */ 223 pushq $__USER_DS /* pt_regs->ss */ 224 pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */ 225 pushq %r11 /* pt_regs->flags */ 226 pushq $__USER_CS /* pt_regs->cs */ 227 pushq %rcx /* pt_regs->ip */ 228GLOBAL(entry_SYSCALL_64_after_hwframe) 229 pushq %rax /* pt_regs->orig_ax */ 230 pushq %rdi /* pt_regs->di */ 231 pushq %rsi /* pt_regs->si */ 232 pushq %rdx /* pt_regs->dx */ 233 pushq %rcx /* pt_regs->cx */ 234 pushq $-ENOSYS /* pt_regs->ax */ 235 pushq %r8 /* pt_regs->r8 */ 236 pushq %r9 /* pt_regs->r9 */ 237 pushq %r10 /* pt_regs->r10 */ 238 pushq %r11 /* pt_regs->r11 */ 239 sub $(6*8), %rsp /* pt_regs->bp, bx, r12-15 not saved */ 240 UNWIND_HINT_REGS extra=0 241 242 TRACE_IRQS_OFF 243 244 /* 245 * If we need to do entry work or if we guess we'll need to do 246 * exit work, go straight to the slow path. 247 */ 248 movq PER_CPU_VAR(current_task), %r11 249 testl $_TIF_WORK_SYSCALL_ENTRY|_TIF_ALLWORK_MASK, TASK_TI_flags(%r11) 250 jnz entry_SYSCALL64_slow_path 251 252entry_SYSCALL_64_fastpath: 253 /* 254 * Easy case: enable interrupts and issue the syscall. If the syscall 255 * needs pt_regs, we'll call a stub that disables interrupts again 256 * and jumps to the slow path. 257 */ 258 TRACE_IRQS_ON 259 ENABLE_INTERRUPTS(CLBR_NONE) 260#if __SYSCALL_MASK == ~0 261 cmpq $__NR_syscall_max, %rax 262#else 263 andl $__SYSCALL_MASK, %eax 264 cmpl $__NR_syscall_max, %eax 265#endif 266 ja 1f /* return -ENOSYS (already in pt_regs->ax) */ 267 movq %r10, %rcx 268 269 /* 270 * This call instruction is handled specially in stub_ptregs_64. 271 * It might end up jumping to the slow path. If it jumps, RAX 272 * and all argument registers are clobbered. 273 */ 274#ifdef CONFIG_RETPOLINE 275 movq sys_call_table(, %rax, 8), %rax 276 call __x86_indirect_thunk_rax 277#else 278 call *sys_call_table(, %rax, 8) 279#endif 280.Lentry_SYSCALL_64_after_fastpath_call: 281 282 movq %rax, RAX(%rsp) 2831: 284 285 /* 286 * If we get here, then we know that pt_regs is clean for SYSRET64. 287 * If we see that no exit work is required (which we are required 288 * to check with IRQs off), then we can go straight to SYSRET64. 289 */ 290 DISABLE_INTERRUPTS(CLBR_ANY) 291 TRACE_IRQS_OFF 292 movq PER_CPU_VAR(current_task), %r11 293 testl $_TIF_ALLWORK_MASK, TASK_TI_flags(%r11) 294 jnz 1f 295 296 LOCKDEP_SYS_EXIT 297 TRACE_IRQS_ON /* user mode is traced as IRQs on */ 298 movq RIP(%rsp), %rcx 299 movq EFLAGS(%rsp), %r11 300 addq $6*8, %rsp /* skip extra regs -- they were preserved */ 301 UNWIND_HINT_EMPTY 302 jmp .Lpop_c_regs_except_rcx_r11_and_sysret 303 3041: 305 /* 306 * The fast path looked good when we started, but something changed 307 * along the way and we need to switch to the slow path. Calling 308 * raise(3) will trigger this, for example. IRQs are off. 309 */ 310 TRACE_IRQS_ON 311 ENABLE_INTERRUPTS(CLBR_ANY) 312 SAVE_EXTRA_REGS 313 movq %rsp, %rdi 314 call syscall_return_slowpath /* returns with IRQs disabled */ 315 jmp return_from_SYSCALL_64 316 317entry_SYSCALL64_slow_path: 318 /* IRQs are off. */ 319 SAVE_EXTRA_REGS 320 movq %rsp, %rdi 321 call do_syscall_64 /* returns with IRQs disabled */ 322 323return_from_SYSCALL_64: 324 TRACE_IRQS_IRETQ /* we're about to change IF */ 325 326 /* 327 * Try to use SYSRET instead of IRET if we're returning to 328 * a completely clean 64-bit userspace context. If we're not, 329 * go to the slow exit path. 330 */ 331 movq RCX(%rsp), %rcx 332 movq RIP(%rsp), %r11 333 334 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ 335 jne swapgs_restore_regs_and_return_to_usermode 336 337 /* 338 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP 339 * in kernel space. This essentially lets the user take over 340 * the kernel, since userspace controls RSP. 341 * 342 * If width of "canonical tail" ever becomes variable, this will need 343 * to be updated to remain correct on both old and new CPUs. 344 * 345 * Change top bits to match most significant bit (47th or 56th bit 346 * depending on paging mode) in the address. 347 */ 348 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 349 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 350 351 /* If this changed %rcx, it was not canonical */ 352 cmpq %rcx, %r11 353 jne swapgs_restore_regs_and_return_to_usermode 354 355 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ 356 jne swapgs_restore_regs_and_return_to_usermode 357 358 movq R11(%rsp), %r11 359 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ 360 jne swapgs_restore_regs_and_return_to_usermode 361 362 /* 363 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot 364 * restore RF properly. If the slowpath sets it for whatever reason, we 365 * need to restore it correctly. 366 * 367 * SYSRET can restore TF, but unlike IRET, restoring TF results in a 368 * trap from userspace immediately after SYSRET. This would cause an 369 * infinite loop whenever #DB happens with register state that satisfies 370 * the opportunistic SYSRET conditions. For example, single-stepping 371 * this user code: 372 * 373 * movq $stuck_here, %rcx 374 * pushfq 375 * popq %r11 376 * stuck_here: 377 * 378 * would never get past 'stuck_here'. 379 */ 380 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 381 jnz swapgs_restore_regs_and_return_to_usermode 382 383 /* nothing to check for RSP */ 384 385 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ 386 jne swapgs_restore_regs_and_return_to_usermode 387 388 /* 389 * We win! This label is here just for ease of understanding 390 * perf profiles. Nothing jumps here. 391 */ 392syscall_return_via_sysret: 393 /* rcx and r11 are already restored (see code above) */ 394 UNWIND_HINT_EMPTY 395 POP_EXTRA_REGS 396.Lpop_c_regs_except_rcx_r11_and_sysret: 397 popq %rsi /* skip r11 */ 398 popq %r10 399 popq %r9 400 popq %r8 401 popq %rax 402 popq %rsi /* skip rcx */ 403 popq %rdx 404 popq %rsi 405 406 /* 407 * Now all regs are restored except RSP and RDI. 408 * Save old stack pointer and switch to trampoline stack. 409 */ 410 movq %rsp, %rdi 411 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 412 413 pushq RSP-RDI(%rdi) /* RSP */ 414 pushq (%rdi) /* RDI */ 415 416 /* 417 * We are on the trampoline stack. All regs except RDI are live. 418 * We can do future final exit work right here. 419 */ 420 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 421 422 popq %rdi 423 popq %rsp 424 USERGS_SYSRET64 425END(entry_SYSCALL_64) 426 427ENTRY(stub_ptregs_64) 428 /* 429 * Syscalls marked as needing ptregs land here. 430 * If we are on the fast path, we need to save the extra regs, 431 * which we achieve by trying again on the slow path. If we are on 432 * the slow path, the extra regs are already saved. 433 * 434 * RAX stores a pointer to the C function implementing the syscall. 435 * IRQs are on. 436 */ 437 cmpq $.Lentry_SYSCALL_64_after_fastpath_call, (%rsp) 438 jne 1f 439 440 /* 441 * Called from fast path -- disable IRQs again, pop return address 442 * and jump to slow path 443 */ 444 DISABLE_INTERRUPTS(CLBR_ANY) 445 TRACE_IRQS_OFF 446 popq %rax 447 UNWIND_HINT_REGS extra=0 448 jmp entry_SYSCALL64_slow_path 449 4501: 451 JMP_NOSPEC %rax /* Called from C */ 452END(stub_ptregs_64) 453 454.macro ptregs_stub func 455ENTRY(ptregs_\func) 456 UNWIND_HINT_FUNC 457 leaq \func(%rip), %rax 458 jmp stub_ptregs_64 459END(ptregs_\func) 460.endm 461 462/* Instantiate ptregs_stub for each ptregs-using syscall */ 463#define __SYSCALL_64_QUAL_(sym) 464#define __SYSCALL_64_QUAL_ptregs(sym) ptregs_stub sym 465#define __SYSCALL_64(nr, sym, qual) __SYSCALL_64_QUAL_##qual(sym) 466#include <asm/syscalls_64.h> 467 468/* 469 * %rdi: prev task 470 * %rsi: next task 471 */ 472ENTRY(__switch_to_asm) 473 UNWIND_HINT_FUNC 474 /* 475 * Save callee-saved registers 476 * This must match the order in inactive_task_frame 477 */ 478 pushq %rbp 479 pushq %rbx 480 pushq %r12 481 pushq %r13 482 pushq %r14 483 pushq %r15 484 485 /* switch stack */ 486 movq %rsp, TASK_threadsp(%rdi) 487 movq TASK_threadsp(%rsi), %rsp 488 489#ifdef CONFIG_CC_STACKPROTECTOR 490 movq TASK_stack_canary(%rsi), %rbx 491 movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset 492#endif 493 494#ifdef CONFIG_RETPOLINE 495 /* 496 * When switching from a shallower to a deeper call stack 497 * the RSB may either underflow or use entries populated 498 * with userspace addresses. On CPUs where those concerns 499 * exist, overwrite the RSB with entries which capture 500 * speculative execution to prevent attack. 501 */ 502 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW 503#endif 504 505 /* restore callee-saved registers */ 506 popq %r15 507 popq %r14 508 popq %r13 509 popq %r12 510 popq %rbx 511 popq %rbp 512 513 jmp __switch_to 514END(__switch_to_asm) 515 516/* 517 * A newly forked process directly context switches into this address. 518 * 519 * rax: prev task we switched from 520 * rbx: kernel thread func (NULL for user thread) 521 * r12: kernel thread arg 522 */ 523ENTRY(ret_from_fork) 524 UNWIND_HINT_EMPTY 525 movq %rax, %rdi 526 call schedule_tail /* rdi: 'prev' task parameter */ 527 528 testq %rbx, %rbx /* from kernel_thread? */ 529 jnz 1f /* kernel threads are uncommon */ 530 5312: 532 UNWIND_HINT_REGS 533 movq %rsp, %rdi 534 call syscall_return_slowpath /* returns with IRQs disabled */ 535 TRACE_IRQS_ON /* user mode is traced as IRQS on */ 536 jmp swapgs_restore_regs_and_return_to_usermode 537 5381: 539 /* kernel thread */ 540 movq %r12, %rdi 541 CALL_NOSPEC %rbx 542 /* 543 * A kernel thread is allowed to return here after successfully 544 * calling do_execve(). Exit to userspace to complete the execve() 545 * syscall. 546 */ 547 movq $0, RAX(%rsp) 548 jmp 2b 549END(ret_from_fork) 550 551/* 552 * Build the entry stubs with some assembler magic. 553 * We pack 1 stub into every 8-byte block. 554 */ 555 .align 8 556ENTRY(irq_entries_start) 557 vector=FIRST_EXTERNAL_VECTOR 558 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) 559 UNWIND_HINT_IRET_REGS 560 pushq $(~vector+0x80) /* Note: always in signed byte range */ 561 jmp common_interrupt 562 .align 8 563 vector=vector+1 564 .endr 565END(irq_entries_start) 566 567.macro DEBUG_ENTRY_ASSERT_IRQS_OFF 568#ifdef CONFIG_DEBUG_ENTRY 569 pushq %rax 570 SAVE_FLAGS(CLBR_RAX) 571 testl $X86_EFLAGS_IF, %eax 572 jz .Lokay_\@ 573 ud2 574.Lokay_\@: 575 popq %rax 576#endif 577.endm 578 579/* 580 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers 581 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone. 582 * Requires kernel GSBASE. 583 * 584 * The invariant is that, if irq_count != -1, then the IRQ stack is in use. 585 */ 586.macro ENTER_IRQ_STACK regs=1 old_rsp 587 DEBUG_ENTRY_ASSERT_IRQS_OFF 588 movq %rsp, \old_rsp 589 590 .if \regs 591 UNWIND_HINT_REGS base=\old_rsp 592 .endif 593 594 incl PER_CPU_VAR(irq_count) 595 jnz .Lirq_stack_push_old_rsp_\@ 596 597 /* 598 * Right now, if we just incremented irq_count to zero, we've 599 * claimed the IRQ stack but we haven't switched to it yet. 600 * 601 * If anything is added that can interrupt us here without using IST, 602 * it must be *extremely* careful to limit its stack usage. This 603 * could include kprobes and a hypothetical future IST-less #DB 604 * handler. 605 * 606 * The OOPS unwinder relies on the word at the top of the IRQ 607 * stack linking back to the previous RSP for the entire time we're 608 * on the IRQ stack. For this to work reliably, we need to write 609 * it before we actually move ourselves to the IRQ stack. 610 */ 611 612 movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8) 613 movq PER_CPU_VAR(irq_stack_ptr), %rsp 614 615#ifdef CONFIG_DEBUG_ENTRY 616 /* 617 * If the first movq above becomes wrong due to IRQ stack layout 618 * changes, the only way we'll notice is if we try to unwind right 619 * here. Assert that we set up the stack right to catch this type 620 * of bug quickly. 621 */ 622 cmpq -8(%rsp), \old_rsp 623 je .Lirq_stack_okay\@ 624 ud2 625 .Lirq_stack_okay\@: 626#endif 627 628.Lirq_stack_push_old_rsp_\@: 629 pushq \old_rsp 630 631 .if \regs 632 UNWIND_HINT_REGS indirect=1 633 .endif 634.endm 635 636/* 637 * Undoes ENTER_IRQ_STACK. 638 */ 639.macro LEAVE_IRQ_STACK regs=1 640 DEBUG_ENTRY_ASSERT_IRQS_OFF 641 /* We need to be off the IRQ stack before decrementing irq_count. */ 642 popq %rsp 643 644 .if \regs 645 UNWIND_HINT_REGS 646 .endif 647 648 /* 649 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming 650 * the irq stack but we're not on it. 651 */ 652 653 decl PER_CPU_VAR(irq_count) 654.endm 655 656/* 657 * Interrupt entry/exit. 658 * 659 * Interrupt entry points save only callee clobbered registers in fast path. 660 * 661 * Entry runs with interrupts off. 662 */ 663 664/* 0(%rsp): ~(interrupt number) */ 665 .macro interrupt func 666 cld 667 668 testb $3, CS-ORIG_RAX(%rsp) 669 jz 1f 670 SWAPGS 671 call switch_to_thread_stack 6721: 673 674 ALLOC_PT_GPREGS_ON_STACK 675 SAVE_C_REGS 676 SAVE_EXTRA_REGS 677 ENCODE_FRAME_POINTER 678 679 testb $3, CS(%rsp) 680 jz 1f 681 682 /* 683 * IRQ from user mode. 684 * 685 * We need to tell lockdep that IRQs are off. We can't do this until 686 * we fix gsbase, and we should do it before enter_from_user_mode 687 * (which can take locks). Since TRACE_IRQS_OFF idempotent, 688 * the simplest way to handle it is to just call it twice if 689 * we enter from user mode. There's no reason to optimize this since 690 * TRACE_IRQS_OFF is a no-op if lockdep is off. 691 */ 692 TRACE_IRQS_OFF 693 694 CALL_enter_from_user_mode 695 6961: 697 ENTER_IRQ_STACK old_rsp=%rdi 698 /* We entered an interrupt context - irqs are off: */ 699 TRACE_IRQS_OFF 700 701 call \func /* rdi points to pt_regs */ 702 .endm 703 704 /* 705 * The interrupt stubs push (~vector+0x80) onto the stack and 706 * then jump to common_interrupt. 707 */ 708 .p2align CONFIG_X86_L1_CACHE_SHIFT 709common_interrupt: 710 ASM_CLAC 711 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ 712 interrupt do_IRQ 713 /* 0(%rsp): old RSP */ 714ret_from_intr: 715 DISABLE_INTERRUPTS(CLBR_ANY) 716 TRACE_IRQS_OFF 717 718 LEAVE_IRQ_STACK 719 720 testb $3, CS(%rsp) 721 jz retint_kernel 722 723 /* Interrupt came from user space */ 724GLOBAL(retint_user) 725 mov %rsp,%rdi 726 call prepare_exit_to_usermode 727 TRACE_IRQS_IRETQ 728 729GLOBAL(swapgs_restore_regs_and_return_to_usermode) 730#ifdef CONFIG_DEBUG_ENTRY 731 /* Assert that pt_regs indicates user mode. */ 732 testb $3, CS(%rsp) 733 jnz 1f 734 ud2 7351: 736#endif 737 POP_EXTRA_REGS 738 popq %r11 739 popq %r10 740 popq %r9 741 popq %r8 742 popq %rax 743 popq %rcx 744 popq %rdx 745 popq %rsi 746 747 /* 748 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. 749 * Save old stack pointer and switch to trampoline stack. 750 */ 751 movq %rsp, %rdi 752 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 753 754 /* Copy the IRET frame to the trampoline stack. */ 755 pushq 6*8(%rdi) /* SS */ 756 pushq 5*8(%rdi) /* RSP */ 757 pushq 4*8(%rdi) /* EFLAGS */ 758 pushq 3*8(%rdi) /* CS */ 759 pushq 2*8(%rdi) /* RIP */ 760 761 /* Push user RDI on the trampoline stack. */ 762 pushq (%rdi) 763 764 /* 765 * We are on the trampoline stack. All regs except RDI are live. 766 * We can do future final exit work right here. 767 */ 768 769 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 770 771 /* Restore RDI. */ 772 popq %rdi 773 SWAPGS 774 INTERRUPT_RETURN 775 776 777/* Returning to kernel space */ 778retint_kernel: 779#ifdef CONFIG_PREEMPT 780 /* Interrupts are off */ 781 /* Check if we need preemption */ 782 bt $9, EFLAGS(%rsp) /* were interrupts off? */ 783 jnc 1f 7840: cmpl $0, PER_CPU_VAR(__preempt_count) 785 jnz 1f 786 call preempt_schedule_irq 787 jmp 0b 7881: 789#endif 790 /* 791 * The iretq could re-enable interrupts: 792 */ 793 TRACE_IRQS_IRETQ 794 795GLOBAL(restore_regs_and_return_to_kernel) 796#ifdef CONFIG_DEBUG_ENTRY 797 /* Assert that pt_regs indicates kernel mode. */ 798 testb $3, CS(%rsp) 799 jz 1f 800 ud2 8011: 802#endif 803 POP_EXTRA_REGS 804 POP_C_REGS 805 addq $8, %rsp /* skip regs->orig_ax */ 806 INTERRUPT_RETURN 807 808ENTRY(native_iret) 809 UNWIND_HINT_IRET_REGS 810 /* 811 * Are we returning to a stack segment from the LDT? Note: in 812 * 64-bit mode SS:RSP on the exception stack is always valid. 813 */ 814#ifdef CONFIG_X86_ESPFIX64 815 testb $4, (SS-RIP)(%rsp) 816 jnz native_irq_return_ldt 817#endif 818 819.global native_irq_return_iret 820native_irq_return_iret: 821 /* 822 * This may fault. Non-paranoid faults on return to userspace are 823 * handled by fixup_bad_iret. These include #SS, #GP, and #NP. 824 * Double-faults due to espfix64 are handled in do_double_fault. 825 * Other faults here are fatal. 826 */ 827 iretq 828 829#ifdef CONFIG_X86_ESPFIX64 830native_irq_return_ldt: 831 /* 832 * We are running with user GSBASE. All GPRs contain their user 833 * values. We have a percpu ESPFIX stack that is eight slots 834 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom 835 * of the ESPFIX stack. 836 * 837 * We clobber RAX and RDI in this code. We stash RDI on the 838 * normal stack and RAX on the ESPFIX stack. 839 * 840 * The ESPFIX stack layout we set up looks like this: 841 * 842 * --- top of ESPFIX stack --- 843 * SS 844 * RSP 845 * RFLAGS 846 * CS 847 * RIP <-- RSP points here when we're done 848 * RAX <-- espfix_waddr points here 849 * --- bottom of ESPFIX stack --- 850 */ 851 852 pushq %rdi /* Stash user RDI */ 853 SWAPGS /* to kernel GS */ 854 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ 855 856 movq PER_CPU_VAR(espfix_waddr), %rdi 857 movq %rax, (0*8)(%rdi) /* user RAX */ 858 movq (1*8)(%rsp), %rax /* user RIP */ 859 movq %rax, (1*8)(%rdi) 860 movq (2*8)(%rsp), %rax /* user CS */ 861 movq %rax, (2*8)(%rdi) 862 movq (3*8)(%rsp), %rax /* user RFLAGS */ 863 movq %rax, (3*8)(%rdi) 864 movq (5*8)(%rsp), %rax /* user SS */ 865 movq %rax, (5*8)(%rdi) 866 movq (4*8)(%rsp), %rax /* user RSP */ 867 movq %rax, (4*8)(%rdi) 868 /* Now RAX == RSP. */ 869 870 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ 871 872 /* 873 * espfix_stack[31:16] == 0. The page tables are set up such that 874 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of 875 * espfix_waddr for any X. That is, there are 65536 RO aliases of 876 * the same page. Set up RSP so that RSP[31:16] contains the 877 * respective 16 bits of the /userspace/ RSP and RSP nonetheless 878 * still points to an RO alias of the ESPFIX stack. 879 */ 880 orq PER_CPU_VAR(espfix_stack), %rax 881 882 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 883 SWAPGS /* to user GS */ 884 popq %rdi /* Restore user RDI */ 885 886 movq %rax, %rsp 887 UNWIND_HINT_IRET_REGS offset=8 888 889 /* 890 * At this point, we cannot write to the stack any more, but we can 891 * still read. 892 */ 893 popq %rax /* Restore user RAX */ 894 895 /* 896 * RSP now points to an ordinary IRET frame, except that the page 897 * is read-only and RSP[31:16] are preloaded with the userspace 898 * values. We can now IRET back to userspace. 899 */ 900 jmp native_irq_return_iret 901#endif 902END(common_interrupt) 903 904/* 905 * APIC interrupts. 906 */ 907.macro apicinterrupt3 num sym do_sym 908ENTRY(\sym) 909 UNWIND_HINT_IRET_REGS 910 ASM_CLAC 911 pushq $~(\num) 912.Lcommon_\sym: 913 interrupt \do_sym 914 jmp ret_from_intr 915END(\sym) 916.endm 917 918/* Make sure APIC interrupt handlers end up in the irqentry section: */ 919#define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax" 920#define POP_SECTION_IRQENTRY .popsection 921 922.macro apicinterrupt num sym do_sym 923PUSH_SECTION_IRQENTRY 924apicinterrupt3 \num \sym \do_sym 925POP_SECTION_IRQENTRY 926.endm 927 928#ifdef CONFIG_SMP 929apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt 930apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt 931#endif 932 933#ifdef CONFIG_X86_UV 934apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt 935#endif 936 937apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt 938apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi 939 940#ifdef CONFIG_HAVE_KVM 941apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi 942apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi 943apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi 944#endif 945 946#ifdef CONFIG_X86_MCE_THRESHOLD 947apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt 948#endif 949 950#ifdef CONFIG_X86_MCE_AMD 951apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt 952#endif 953 954#ifdef CONFIG_X86_THERMAL_VECTOR 955apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt 956#endif 957 958#ifdef CONFIG_SMP 959apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt 960apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt 961apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt 962#endif 963 964apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt 965apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt 966 967#ifdef CONFIG_IRQ_WORK 968apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt 969#endif 970 971/* 972 * Exception entry points. 973 */ 974#define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8) 975 976/* 977 * Switch to the thread stack. This is called with the IRET frame and 978 * orig_ax on the stack. (That is, RDI..R12 are not on the stack and 979 * space has not been allocated for them.) 980 */ 981ENTRY(switch_to_thread_stack) 982 UNWIND_HINT_FUNC 983 984 pushq %rdi 985 /* Need to switch before accessing the thread stack. */ 986 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi 987 movq %rsp, %rdi 988 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 989 UNWIND_HINT sp_offset=16 sp_reg=ORC_REG_DI 990 991 pushq 7*8(%rdi) /* regs->ss */ 992 pushq 6*8(%rdi) /* regs->rsp */ 993 pushq 5*8(%rdi) /* regs->eflags */ 994 pushq 4*8(%rdi) /* regs->cs */ 995 pushq 3*8(%rdi) /* regs->ip */ 996 pushq 2*8(%rdi) /* regs->orig_ax */ 997 pushq 8(%rdi) /* return address */ 998 UNWIND_HINT_FUNC 999 1000 movq (%rdi), %rdi 1001 ret 1002END(switch_to_thread_stack) 1003 1004.macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 1005ENTRY(\sym) 1006 UNWIND_HINT_IRET_REGS offset=\has_error_code*8 1007 1008 /* Sanity check */ 1009 .if \shift_ist != -1 && \paranoid == 0 1010 .error "using shift_ist requires paranoid=1" 1011 .endif 1012 1013 ASM_CLAC 1014 1015 .if \has_error_code == 0 1016 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1017 .endif 1018 1019 ALLOC_PT_GPREGS_ON_STACK 1020 1021 .if \paranoid < 2 1022 testb $3, CS(%rsp) /* If coming from userspace, switch stacks */ 1023 jnz .Lfrom_usermode_switch_stack_\@ 1024 .endif 1025 1026 .if \paranoid 1027 call paranoid_entry 1028 .else 1029 call error_entry 1030 .endif 1031 UNWIND_HINT_REGS 1032 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ 1033 1034 .if \paranoid 1035 .if \shift_ist != -1 1036 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ 1037 .else 1038 TRACE_IRQS_OFF 1039 .endif 1040 .endif 1041 1042 movq %rsp, %rdi /* pt_regs pointer */ 1043 1044 .if \has_error_code 1045 movq ORIG_RAX(%rsp), %rsi /* get error code */ 1046 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 1047 .else 1048 xorl %esi, %esi /* no error code */ 1049 .endif 1050 1051 .if \shift_ist != -1 1052 subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 1053 .endif 1054 1055 call \do_sym 1056 1057 .if \shift_ist != -1 1058 addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 1059 .endif 1060 1061 /* these procedures expect "no swapgs" flag in ebx */ 1062 .if \paranoid 1063 jmp paranoid_exit 1064 .else 1065 jmp error_exit 1066 .endif 1067 1068 .if \paranoid < 2 1069 /* 1070 * Entry from userspace. Switch stacks and treat it 1071 * as a normal entry. This means that paranoid handlers 1072 * run in real process context if user_mode(regs). 1073 */ 1074.Lfrom_usermode_switch_stack_\@: 1075 call error_entry 1076 1077 movq %rsp, %rdi /* pt_regs pointer */ 1078 1079 .if \has_error_code 1080 movq ORIG_RAX(%rsp), %rsi /* get error code */ 1081 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 1082 .else 1083 xorl %esi, %esi /* no error code */ 1084 .endif 1085 1086 call \do_sym 1087 1088 jmp error_exit /* %ebx: no swapgs flag */ 1089 .endif 1090END(\sym) 1091.endm 1092 1093idtentry divide_error do_divide_error has_error_code=0 1094idtentry overflow do_overflow has_error_code=0 1095idtentry bounds do_bounds has_error_code=0 1096idtentry invalid_op do_invalid_op has_error_code=0 1097idtentry device_not_available do_device_not_available has_error_code=0 1098idtentry double_fault do_double_fault has_error_code=1 paranoid=2 1099idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 1100idtentry invalid_TSS do_invalid_TSS has_error_code=1 1101idtentry segment_not_present do_segment_not_present has_error_code=1 1102idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 1103idtentry coprocessor_error do_coprocessor_error has_error_code=0 1104idtentry alignment_check do_alignment_check has_error_code=1 1105idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 1106 1107 1108 /* 1109 * Reload gs selector with exception handling 1110 * edi: new selector 1111 */ 1112ENTRY(native_load_gs_index) 1113 FRAME_BEGIN 1114 pushfq 1115 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) 1116 TRACE_IRQS_OFF 1117 SWAPGS 1118.Lgs_change: 1119 movl %edi, %gs 11202: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE 1121 SWAPGS 1122 TRACE_IRQS_FLAGS (%rsp) 1123 popfq 1124 FRAME_END 1125 ret 1126ENDPROC(native_load_gs_index) 1127EXPORT_SYMBOL(native_load_gs_index) 1128 1129 _ASM_EXTABLE(.Lgs_change, bad_gs) 1130 .section .fixup, "ax" 1131 /* running with kernelgs */ 1132bad_gs: 1133 SWAPGS /* switch back to user gs */ 1134.macro ZAP_GS 1135 /* This can't be a string because the preprocessor needs to see it. */ 1136 movl $__USER_DS, %eax 1137 movl %eax, %gs 1138.endm 1139 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG 1140 xorl %eax, %eax 1141 movl %eax, %gs 1142 jmp 2b 1143 .previous 1144 1145/* Call softirq on interrupt stack. Interrupts are off. */ 1146ENTRY(do_softirq_own_stack) 1147 pushq %rbp 1148 mov %rsp, %rbp 1149 ENTER_IRQ_STACK regs=0 old_rsp=%r11 1150 call __do_softirq 1151 LEAVE_IRQ_STACK regs=0 1152 leaveq 1153 ret 1154ENDPROC(do_softirq_own_stack) 1155 1156#ifdef CONFIG_XEN 1157idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0 1158 1159/* 1160 * A note on the "critical region" in our callback handler. 1161 * We want to avoid stacking callback handlers due to events occurring 1162 * during handling of the last event. To do this, we keep events disabled 1163 * until we've done all processing. HOWEVER, we must enable events before 1164 * popping the stack frame (can't be done atomically) and so it would still 1165 * be possible to get enough handler activations to overflow the stack. 1166 * Although unlikely, bugs of that kind are hard to track down, so we'd 1167 * like to avoid the possibility. 1168 * So, on entry to the handler we detect whether we interrupted an 1169 * existing activation in its critical region -- if so, we pop the current 1170 * activation and restart the handler using the previous one. 1171 */ 1172ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ 1173 1174/* 1175 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will 1176 * see the correct pointer to the pt_regs 1177 */ 1178 UNWIND_HINT_FUNC 1179 movq %rdi, %rsp /* we don't return, adjust the stack frame */ 1180 UNWIND_HINT_REGS 1181 1182 ENTER_IRQ_STACK old_rsp=%r10 1183 call xen_evtchn_do_upcall 1184 LEAVE_IRQ_STACK 1185 1186#ifndef CONFIG_PREEMPT 1187 call xen_maybe_preempt_hcall 1188#endif 1189 jmp error_exit 1190END(xen_do_hypervisor_callback) 1191 1192/* 1193 * Hypervisor uses this for application faults while it executes. 1194 * We get here for two reasons: 1195 * 1. Fault while reloading DS, ES, FS or GS 1196 * 2. Fault while executing IRET 1197 * Category 1 we do not need to fix up as Xen has already reloaded all segment 1198 * registers that could be reloaded and zeroed the others. 1199 * Category 2 we fix up by killing the current process. We cannot use the 1200 * normal Linux return path in this case because if we use the IRET hypercall 1201 * to pop the stack frame we end up in an infinite loop of failsafe callbacks. 1202 * We distinguish between categories by comparing each saved segment register 1203 * with its current contents: any discrepancy means we in category 1. 1204 */ 1205ENTRY(xen_failsafe_callback) 1206 UNWIND_HINT_EMPTY 1207 movl %ds, %ecx 1208 cmpw %cx, 0x10(%rsp) 1209 jne 1f 1210 movl %es, %ecx 1211 cmpw %cx, 0x18(%rsp) 1212 jne 1f 1213 movl %fs, %ecx 1214 cmpw %cx, 0x20(%rsp) 1215 jne 1f 1216 movl %gs, %ecx 1217 cmpw %cx, 0x28(%rsp) 1218 jne 1f 1219 /* All segments match their saved values => Category 2 (Bad IRET). */ 1220 movq (%rsp), %rcx 1221 movq 8(%rsp), %r11 1222 addq $0x30, %rsp 1223 pushq $0 /* RIP */ 1224 UNWIND_HINT_IRET_REGS offset=8 1225 jmp general_protection 12261: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ 1227 movq (%rsp), %rcx 1228 movq 8(%rsp), %r11 1229 addq $0x30, %rsp 1230 UNWIND_HINT_IRET_REGS 1231 pushq $-1 /* orig_ax = -1 => not a system call */ 1232 ALLOC_PT_GPREGS_ON_STACK 1233 SAVE_C_REGS 1234 SAVE_EXTRA_REGS 1235 ENCODE_FRAME_POINTER 1236 jmp error_exit 1237END(xen_failsafe_callback) 1238 1239apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1240 xen_hvm_callback_vector xen_evtchn_do_upcall 1241 1242#endif /* CONFIG_XEN */ 1243 1244#if IS_ENABLED(CONFIG_HYPERV) 1245apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1246 hyperv_callback_vector hyperv_vector_handler 1247#endif /* CONFIG_HYPERV */ 1248 1249idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK 1250idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK 1251idtentry stack_segment do_stack_segment has_error_code=1 1252 1253#ifdef CONFIG_XEN 1254idtentry xennmi do_nmi has_error_code=0 1255idtentry xendebug do_debug has_error_code=0 1256idtentry xenint3 do_int3 has_error_code=0 1257#endif 1258 1259idtentry general_protection do_general_protection has_error_code=1 1260idtentry page_fault do_page_fault has_error_code=1 1261 1262#ifdef CONFIG_KVM_GUEST 1263idtentry async_page_fault do_async_page_fault has_error_code=1 1264#endif 1265 1266#ifdef CONFIG_X86_MCE 1267idtentry machine_check do_mce has_error_code=0 paranoid=1 1268#endif 1269 1270/* 1271 * Save all registers in pt_regs, and switch gs if needed. 1272 * Use slow, but surefire "are we in kernel?" check. 1273 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise 1274 */ 1275ENTRY(paranoid_entry) 1276 UNWIND_HINT_FUNC 1277 cld 1278 SAVE_C_REGS 8 1279 SAVE_EXTRA_REGS 8 1280 ENCODE_FRAME_POINTER 8 1281 movl $1, %ebx 1282 movl $MSR_GS_BASE, %ecx 1283 rdmsr 1284 testl %edx, %edx 1285 js 1f /* negative -> in kernel */ 1286 SWAPGS 1287 xorl %ebx, %ebx 1288 12891: 1290 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 1291 1292 ret 1293END(paranoid_entry) 1294 1295/* 1296 * "Paranoid" exit path from exception stack. This is invoked 1297 * only on return from non-NMI IST interrupts that came 1298 * from kernel space. 1299 * 1300 * We may be returning to very strange contexts (e.g. very early 1301 * in syscall entry), so checking for preemption here would 1302 * be complicated. Fortunately, we there's no good reason 1303 * to try to handle preemption here. 1304 * 1305 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) 1306 */ 1307ENTRY(paranoid_exit) 1308 UNWIND_HINT_REGS 1309 DISABLE_INTERRUPTS(CLBR_ANY) 1310 TRACE_IRQS_OFF_DEBUG 1311 testl %ebx, %ebx /* swapgs needed? */ 1312 jnz .Lparanoid_exit_no_swapgs 1313 TRACE_IRQS_IRETQ 1314 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1315 SWAPGS_UNSAFE_STACK 1316 jmp .Lparanoid_exit_restore 1317.Lparanoid_exit_no_swapgs: 1318 TRACE_IRQS_IRETQ_DEBUG 1319.Lparanoid_exit_restore: 1320 jmp restore_regs_and_return_to_kernel 1321END(paranoid_exit) 1322 1323/* 1324 * Save all registers in pt_regs, and switch gs if needed. 1325 * Return: EBX=0: came from user mode; EBX=1: otherwise 1326 */ 1327ENTRY(error_entry) 1328 UNWIND_HINT_FUNC 1329 cld 1330 SAVE_C_REGS 8 1331 SAVE_EXTRA_REGS 8 1332 ENCODE_FRAME_POINTER 8 1333 xorl %ebx, %ebx 1334 testb $3, CS+8(%rsp) 1335 jz .Lerror_kernelspace 1336 1337 /* 1338 * We entered from user mode or we're pretending to have entered 1339 * from user mode due to an IRET fault. 1340 */ 1341 SWAPGS 1342 /* We have user CR3. Change to kernel CR3. */ 1343 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1344 1345.Lerror_entry_from_usermode_after_swapgs: 1346 /* Put us onto the real thread stack. */ 1347 popq %r12 /* save return addr in %12 */ 1348 movq %rsp, %rdi /* arg0 = pt_regs pointer */ 1349 call sync_regs 1350 movq %rax, %rsp /* switch stack */ 1351 ENCODE_FRAME_POINTER 1352 pushq %r12 1353 1354 /* 1355 * We need to tell lockdep that IRQs are off. We can't do this until 1356 * we fix gsbase, and we should do it before enter_from_user_mode 1357 * (which can take locks). 1358 */ 1359 TRACE_IRQS_OFF 1360 CALL_enter_from_user_mode 1361 ret 1362 1363.Lerror_entry_done: 1364 TRACE_IRQS_OFF 1365 ret 1366 1367 /* 1368 * There are two places in the kernel that can potentially fault with 1369 * usergs. Handle them here. B stepping K8s sometimes report a 1370 * truncated RIP for IRET exceptions returning to compat mode. Check 1371 * for these here too. 1372 */ 1373.Lerror_kernelspace: 1374 incl %ebx 1375 leaq native_irq_return_iret(%rip), %rcx 1376 cmpq %rcx, RIP+8(%rsp) 1377 je .Lerror_bad_iret 1378 movl %ecx, %eax /* zero extend */ 1379 cmpq %rax, RIP+8(%rsp) 1380 je .Lbstep_iret 1381 cmpq $.Lgs_change, RIP+8(%rsp) 1382 jne .Lerror_entry_done 1383 1384 /* 1385 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up 1386 * gsbase and proceed. We'll fix up the exception and land in 1387 * .Lgs_change's error handler with kernel gsbase. 1388 */ 1389 SWAPGS 1390 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1391 jmp .Lerror_entry_done 1392 1393.Lbstep_iret: 1394 /* Fix truncated RIP */ 1395 movq %rcx, RIP+8(%rsp) 1396 /* fall through */ 1397 1398.Lerror_bad_iret: 1399 /* 1400 * We came from an IRET to user mode, so we have user 1401 * gsbase and CR3. Switch to kernel gsbase and CR3: 1402 */ 1403 SWAPGS 1404 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1405 1406 /* 1407 * Pretend that the exception came from user mode: set up pt_regs 1408 * as if we faulted immediately after IRET and clear EBX so that 1409 * error_exit knows that we will be returning to user mode. 1410 */ 1411 mov %rsp, %rdi 1412 call fixup_bad_iret 1413 mov %rax, %rsp 1414 decl %ebx 1415 jmp .Lerror_entry_from_usermode_after_swapgs 1416END(error_entry) 1417 1418 1419/* 1420 * On entry, EBX is a "return to kernel mode" flag: 1421 * 1: already in kernel mode, don't need SWAPGS 1422 * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode 1423 */ 1424ENTRY(error_exit) 1425 UNWIND_HINT_REGS 1426 DISABLE_INTERRUPTS(CLBR_ANY) 1427 TRACE_IRQS_OFF 1428 testl %ebx, %ebx 1429 jnz retint_kernel 1430 jmp retint_user 1431END(error_exit) 1432 1433/* 1434 * Runs on exception stack. Xen PV does not go through this path at all, 1435 * so we can use real assembly here. 1436 * 1437 * Registers: 1438 * %r14: Used to save/restore the CR3 of the interrupted context 1439 * when PAGE_TABLE_ISOLATION is in use. Do not clobber. 1440 */ 1441ENTRY(nmi) 1442 UNWIND_HINT_IRET_REGS 1443 1444 /* 1445 * We allow breakpoints in NMIs. If a breakpoint occurs, then 1446 * the iretq it performs will take us out of NMI context. 1447 * This means that we can have nested NMIs where the next 1448 * NMI is using the top of the stack of the previous NMI. We 1449 * can't let it execute because the nested NMI will corrupt the 1450 * stack of the previous NMI. NMI handlers are not re-entrant 1451 * anyway. 1452 * 1453 * To handle this case we do the following: 1454 * Check the a special location on the stack that contains 1455 * a variable that is set when NMIs are executing. 1456 * The interrupted task's stack is also checked to see if it 1457 * is an NMI stack. 1458 * If the variable is not set and the stack is not the NMI 1459 * stack then: 1460 * o Set the special variable on the stack 1461 * o Copy the interrupt frame into an "outermost" location on the 1462 * stack 1463 * o Copy the interrupt frame into an "iret" location on the stack 1464 * o Continue processing the NMI 1465 * If the variable is set or the previous stack is the NMI stack: 1466 * o Modify the "iret" location to jump to the repeat_nmi 1467 * o return back to the first NMI 1468 * 1469 * Now on exit of the first NMI, we first clear the stack variable 1470 * The NMI stack will tell any nested NMIs at that point that it is 1471 * nested. Then we pop the stack normally with iret, and if there was 1472 * a nested NMI that updated the copy interrupt stack frame, a 1473 * jump will be made to the repeat_nmi code that will handle the second 1474 * NMI. 1475 * 1476 * However, espfix prevents us from directly returning to userspace 1477 * with a single IRET instruction. Similarly, IRET to user mode 1478 * can fault. We therefore handle NMIs from user space like 1479 * other IST entries. 1480 */ 1481 1482 ASM_CLAC 1483 1484 /* Use %rdx as our temp variable throughout */ 1485 pushq %rdx 1486 1487 testb $3, CS-RIP+8(%rsp) 1488 jz .Lnmi_from_kernel 1489 1490 /* 1491 * NMI from user mode. We need to run on the thread stack, but we 1492 * can't go through the normal entry paths: NMIs are masked, and 1493 * we don't want to enable interrupts, because then we'll end 1494 * up in an awkward situation in which IRQs are on but NMIs 1495 * are off. 1496 * 1497 * We also must not push anything to the stack before switching 1498 * stacks lest we corrupt the "NMI executing" variable. 1499 */ 1500 1501 swapgs 1502 cld 1503 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx 1504 movq %rsp, %rdx 1505 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 1506 UNWIND_HINT_IRET_REGS base=%rdx offset=8 1507 pushq 5*8(%rdx) /* pt_regs->ss */ 1508 pushq 4*8(%rdx) /* pt_regs->rsp */ 1509 pushq 3*8(%rdx) /* pt_regs->flags */ 1510 pushq 2*8(%rdx) /* pt_regs->cs */ 1511 pushq 1*8(%rdx) /* pt_regs->rip */ 1512 UNWIND_HINT_IRET_REGS 1513 pushq $-1 /* pt_regs->orig_ax */ 1514 pushq %rdi /* pt_regs->di */ 1515 pushq %rsi /* pt_regs->si */ 1516 pushq (%rdx) /* pt_regs->dx */ 1517 pushq %rcx /* pt_regs->cx */ 1518 pushq %rax /* pt_regs->ax */ 1519 pushq %r8 /* pt_regs->r8 */ 1520 pushq %r9 /* pt_regs->r9 */ 1521 pushq %r10 /* pt_regs->r10 */ 1522 pushq %r11 /* pt_regs->r11 */ 1523 pushq %rbx /* pt_regs->rbx */ 1524 pushq %rbp /* pt_regs->rbp */ 1525 pushq %r12 /* pt_regs->r12 */ 1526 pushq %r13 /* pt_regs->r13 */ 1527 pushq %r14 /* pt_regs->r14 */ 1528 pushq %r15 /* pt_regs->r15 */ 1529 UNWIND_HINT_REGS 1530 ENCODE_FRAME_POINTER 1531 1532 /* 1533 * At this point we no longer need to worry about stack damage 1534 * due to nesting -- we're on the normal thread stack and we're 1535 * done with the NMI stack. 1536 */ 1537 1538 movq %rsp, %rdi 1539 movq $-1, %rsi 1540 call do_nmi 1541 1542 /* 1543 * Return back to user mode. We must *not* do the normal exit 1544 * work, because we don't want to enable interrupts. 1545 */ 1546 jmp swapgs_restore_regs_and_return_to_usermode 1547 1548.Lnmi_from_kernel: 1549 /* 1550 * Here's what our stack frame will look like: 1551 * +---------------------------------------------------------+ 1552 * | original SS | 1553 * | original Return RSP | 1554 * | original RFLAGS | 1555 * | original CS | 1556 * | original RIP | 1557 * +---------------------------------------------------------+ 1558 * | temp storage for rdx | 1559 * +---------------------------------------------------------+ 1560 * | "NMI executing" variable | 1561 * +---------------------------------------------------------+ 1562 * | iret SS } Copied from "outermost" frame | 1563 * | iret Return RSP } on each loop iteration; overwritten | 1564 * | iret RFLAGS } by a nested NMI to force another | 1565 * | iret CS } iteration if needed. | 1566 * | iret RIP } | 1567 * +---------------------------------------------------------+ 1568 * | outermost SS } initialized in first_nmi; | 1569 * | outermost Return RSP } will not be changed before | 1570 * | outermost RFLAGS } NMI processing is done. | 1571 * | outermost CS } Copied to "iret" frame on each | 1572 * | outermost RIP } iteration. | 1573 * +---------------------------------------------------------+ 1574 * | pt_regs | 1575 * +---------------------------------------------------------+ 1576 * 1577 * The "original" frame is used by hardware. Before re-enabling 1578 * NMIs, we need to be done with it, and we need to leave enough 1579 * space for the asm code here. 1580 * 1581 * We return by executing IRET while RSP points to the "iret" frame. 1582 * That will either return for real or it will loop back into NMI 1583 * processing. 1584 * 1585 * The "outermost" frame is copied to the "iret" frame on each 1586 * iteration of the loop, so each iteration starts with the "iret" 1587 * frame pointing to the final return target. 1588 */ 1589 1590 /* 1591 * Determine whether we're a nested NMI. 1592 * 1593 * If we interrupted kernel code between repeat_nmi and 1594 * end_repeat_nmi, then we are a nested NMI. We must not 1595 * modify the "iret" frame because it's being written by 1596 * the outer NMI. That's okay; the outer NMI handler is 1597 * about to about to call do_nmi anyway, so we can just 1598 * resume the outer NMI. 1599 */ 1600 1601 movq $repeat_nmi, %rdx 1602 cmpq 8(%rsp), %rdx 1603 ja 1f 1604 movq $end_repeat_nmi, %rdx 1605 cmpq 8(%rsp), %rdx 1606 ja nested_nmi_out 16071: 1608 1609 /* 1610 * Now check "NMI executing". If it's set, then we're nested. 1611 * This will not detect if we interrupted an outer NMI just 1612 * before IRET. 1613 */ 1614 cmpl $1, -8(%rsp) 1615 je nested_nmi 1616 1617 /* 1618 * Now test if the previous stack was an NMI stack. This covers 1619 * the case where we interrupt an outer NMI after it clears 1620 * "NMI executing" but before IRET. We need to be careful, though: 1621 * there is one case in which RSP could point to the NMI stack 1622 * despite there being no NMI active: naughty userspace controls 1623 * RSP at the very beginning of the SYSCALL targets. We can 1624 * pull a fast one on naughty userspace, though: we program 1625 * SYSCALL to mask DF, so userspace cannot cause DF to be set 1626 * if it controls the kernel's RSP. We set DF before we clear 1627 * "NMI executing". 1628 */ 1629 lea 6*8(%rsp), %rdx 1630 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ 1631 cmpq %rdx, 4*8(%rsp) 1632 /* If the stack pointer is above the NMI stack, this is a normal NMI */ 1633 ja first_nmi 1634 1635 subq $EXCEPTION_STKSZ, %rdx 1636 cmpq %rdx, 4*8(%rsp) 1637 /* If it is below the NMI stack, it is a normal NMI */ 1638 jb first_nmi 1639 1640 /* Ah, it is within the NMI stack. */ 1641 1642 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) 1643 jz first_nmi /* RSP was user controlled. */ 1644 1645 /* This is a nested NMI. */ 1646 1647nested_nmi: 1648 /* 1649 * Modify the "iret" frame to point to repeat_nmi, forcing another 1650 * iteration of NMI handling. 1651 */ 1652 subq $8, %rsp 1653 leaq -10*8(%rsp), %rdx 1654 pushq $__KERNEL_DS 1655 pushq %rdx 1656 pushfq 1657 pushq $__KERNEL_CS 1658 pushq $repeat_nmi 1659 1660 /* Put stack back */ 1661 addq $(6*8), %rsp 1662 1663nested_nmi_out: 1664 popq %rdx 1665 1666 /* We are returning to kernel mode, so this cannot result in a fault. */ 1667 iretq 1668 1669first_nmi: 1670 /* Restore rdx. */ 1671 movq (%rsp), %rdx 1672 1673 /* Make room for "NMI executing". */ 1674 pushq $0 1675 1676 /* Leave room for the "iret" frame */ 1677 subq $(5*8), %rsp 1678 1679 /* Copy the "original" frame to the "outermost" frame */ 1680 .rept 5 1681 pushq 11*8(%rsp) 1682 .endr 1683 UNWIND_HINT_IRET_REGS 1684 1685 /* Everything up to here is safe from nested NMIs */ 1686 1687#ifdef CONFIG_DEBUG_ENTRY 1688 /* 1689 * For ease of testing, unmask NMIs right away. Disabled by 1690 * default because IRET is very expensive. 1691 */ 1692 pushq $0 /* SS */ 1693 pushq %rsp /* RSP (minus 8 because of the previous push) */ 1694 addq $8, (%rsp) /* Fix up RSP */ 1695 pushfq /* RFLAGS */ 1696 pushq $__KERNEL_CS /* CS */ 1697 pushq $1f /* RIP */ 1698 iretq /* continues at repeat_nmi below */ 1699 UNWIND_HINT_IRET_REGS 17001: 1701#endif 1702 1703repeat_nmi: 1704 /* 1705 * If there was a nested NMI, the first NMI's iret will return 1706 * here. But NMIs are still enabled and we can take another 1707 * nested NMI. The nested NMI checks the interrupted RIP to see 1708 * if it is between repeat_nmi and end_repeat_nmi, and if so 1709 * it will just return, as we are about to repeat an NMI anyway. 1710 * This makes it safe to copy to the stack frame that a nested 1711 * NMI will update. 1712 * 1713 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if 1714 * we're repeating an NMI, gsbase has the same value that it had on 1715 * the first iteration. paranoid_entry will load the kernel 1716 * gsbase if needed before we call do_nmi. "NMI executing" 1717 * is zero. 1718 */ 1719 movq $1, 10*8(%rsp) /* Set "NMI executing". */ 1720 1721 /* 1722 * Copy the "outermost" frame to the "iret" frame. NMIs that nest 1723 * here must not modify the "iret" frame while we're writing to 1724 * it or it will end up containing garbage. 1725 */ 1726 addq $(10*8), %rsp 1727 .rept 5 1728 pushq -6*8(%rsp) 1729 .endr 1730 subq $(5*8), %rsp 1731end_repeat_nmi: 1732 1733 /* 1734 * Everything below this point can be preempted by a nested NMI. 1735 * If this happens, then the inner NMI will change the "iret" 1736 * frame to point back to repeat_nmi. 1737 */ 1738 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1739 ALLOC_PT_GPREGS_ON_STACK 1740 1741 /* 1742 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit 1743 * as we should not be calling schedule in NMI context. 1744 * Even with normal interrupts enabled. An NMI should not be 1745 * setting NEED_RESCHED or anything that normal interrupts and 1746 * exceptions might do. 1747 */ 1748 call paranoid_entry 1749 UNWIND_HINT_REGS 1750 1751 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ 1752 movq %rsp, %rdi 1753 movq $-1, %rsi 1754 call do_nmi 1755 1756 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 1757 1758 testl %ebx, %ebx /* swapgs needed? */ 1759 jnz nmi_restore 1760nmi_swapgs: 1761 SWAPGS_UNSAFE_STACK 1762nmi_restore: 1763 POP_EXTRA_REGS 1764 POP_C_REGS 1765 1766 /* 1767 * Skip orig_ax and the "outermost" frame to point RSP at the "iret" 1768 * at the "iret" frame. 1769 */ 1770 addq $6*8, %rsp 1771 1772 /* 1773 * Clear "NMI executing". Set DF first so that we can easily 1774 * distinguish the remaining code between here and IRET from 1775 * the SYSCALL entry and exit paths. 1776 * 1777 * We arguably should just inspect RIP instead, but I (Andy) wrote 1778 * this code when I had the misapprehension that Xen PV supported 1779 * NMIs, and Xen PV would break that approach. 1780 */ 1781 std 1782 movq $0, 5*8(%rsp) /* clear "NMI executing" */ 1783 1784 /* 1785 * iretq reads the "iret" frame and exits the NMI stack in a 1786 * single instruction. We are returning to kernel mode, so this 1787 * cannot result in a fault. Similarly, we don't need to worry 1788 * about espfix64 on the way back to kernel mode. 1789 */ 1790 iretq 1791END(nmi) 1792 1793ENTRY(ignore_sysret) 1794 UNWIND_HINT_EMPTY 1795 mov $-ENOSYS, %eax 1796 sysret 1797END(ignore_sysret) 1798 1799ENTRY(rewind_stack_do_exit) 1800 UNWIND_HINT_FUNC 1801 /* Prevent any naive code from trying to unwind to our caller. */ 1802 xorl %ebp, %ebp 1803 1804 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax 1805 leaq -PTREGS_SIZE(%rax), %rsp 1806 UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE 1807 1808 call do_exit 1809END(rewind_stack_do_exit) 1810