1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #include <linux/jump_label.h> 3 #include <asm/unwind_hints.h> 4 #include <asm/cpufeatures.h> 5 #include <asm/page_types.h> 6 #include <asm/percpu.h> 7 #include <asm/asm-offsets.h> 8 #include <asm/processor-flags.h> 9 #include <asm/ptrace-abi.h> 10 #include <asm/msr.h> 11 #include <asm/nospec-branch.h> 12 13 /* 14 15 x86 function call convention, 64-bit: 16 ------------------------------------- 17 arguments | callee-saved | extra caller-saved | return 18 [callee-clobbered] | | [callee-clobbered] | 19 --------------------------------------------------------------------------- 20 rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**] 21 22 ( rsp is obviously invariant across normal function calls. (gcc can 'merge' 23 functions when it sees tail-call optimization possibilities) rflags is 24 clobbered. Leftover arguments are passed over the stack frame.) 25 26 [*] In the frame-pointers case rbp is fixed to the stack frame. 27 28 [**] for struct return values wider than 64 bits the return convention is a 29 bit more complex: up to 128 bits width we return small structures 30 straight in rax, rdx. For structures larger than that (3 words or 31 larger) the caller puts a pointer to an on-stack return struct 32 [allocated in the caller's stack frame] into the first argument - i.e. 33 into rdi. All other arguments shift up by one in this case. 34 Fortunately this case is rare in the kernel. 35 36 For 32-bit we have the following conventions - kernel is built with 37 -mregparm=3 and -freg-struct-return: 38 39 x86 function calling convention, 32-bit: 40 ---------------------------------------- 41 arguments | callee-saved | extra caller-saved | return 42 [callee-clobbered] | | [callee-clobbered] | 43 ------------------------------------------------------------------------- 44 eax edx ecx | ebx edi esi ebp [*] | <none> | eax, edx [**] 45 46 ( here too esp is obviously invariant across normal function calls. eflags 47 is clobbered. Leftover arguments are passed over the stack frame. ) 48 49 [*] In the frame-pointers case ebp is fixed to the stack frame. 50 51 [**] We build with -freg-struct-return, which on 32-bit means similar 52 semantics as on 64-bit: edx can be used for a second return value 53 (i.e. covering integer and structure sizes up to 64 bits) - after that 54 it gets more complex and more expensive: 3-word or larger struct returns 55 get done in the caller's frame and the pointer to the return struct goes 56 into regparm0, i.e. eax - the other arguments shift up and the 57 function's register parameters degenerate to regparm=2 in essence. 58 59 */ 60 61 #ifdef CONFIG_X86_64 62 63 /* 64 * 64-bit system call stack frame layout defines and helpers, 65 * for assembly code: 66 */ 67 68 .macro PUSH_REGS rdx=%rdx rcx=%rcx rax=%rax save_ret=0 unwind_hint=1 69 .if \save_ret 70 pushq %rsi /* pt_regs->si */ 71 movq 8(%rsp), %rsi /* temporarily store the return address in %rsi */ 72 movq %rdi, 8(%rsp) /* pt_regs->di (overwriting original return address) */ 73 .else 74 pushq %rdi /* pt_regs->di */ 75 pushq %rsi /* pt_regs->si */ 76 .endif 77 pushq \rdx /* pt_regs->dx */ 78 pushq \rcx /* pt_regs->cx */ 79 pushq \rax /* pt_regs->ax */ 80 pushq %r8 /* pt_regs->r8 */ 81 pushq %r9 /* pt_regs->r9 */ 82 pushq %r10 /* pt_regs->r10 */ 83 pushq %r11 /* pt_regs->r11 */ 84 pushq %rbx /* pt_regs->rbx */ 85 pushq %rbp /* pt_regs->rbp */ 86 pushq %r12 /* pt_regs->r12 */ 87 pushq %r13 /* pt_regs->r13 */ 88 pushq %r14 /* pt_regs->r14 */ 89 pushq %r15 /* pt_regs->r15 */ 90 91 .if \unwind_hint 92 UNWIND_HINT_REGS 93 .endif 94 95 .if \save_ret 96 pushq %rsi /* return address on top of stack */ 97 .endif 98 .endm 99 100 .macro CLEAR_REGS clear_bp=1 101 /* 102 * Sanitize registers of values that a speculation attack might 103 * otherwise want to exploit. The lower registers are likely clobbered 104 * well before they could be put to use in a speculative execution 105 * gadget. 106 */ 107 xorl %esi, %esi /* nospec si */ 108 xorl %edx, %edx /* nospec dx */ 109 xorl %ecx, %ecx /* nospec cx */ 110 xorl %r8d, %r8d /* nospec r8 */ 111 xorl %r9d, %r9d /* nospec r9 */ 112 xorl %r10d, %r10d /* nospec r10 */ 113 xorl %r11d, %r11d /* nospec r11 */ 114 xorl %ebx, %ebx /* nospec rbx */ 115 .if \clear_bp 116 xorl %ebp, %ebp /* nospec rbp */ 117 .endif 118 xorl %r12d, %r12d /* nospec r12 */ 119 xorl %r13d, %r13d /* nospec r13 */ 120 xorl %r14d, %r14d /* nospec r14 */ 121 xorl %r15d, %r15d /* nospec r15 */ 122 123 .endm 124 125 .macro PUSH_AND_CLEAR_REGS rdx=%rdx rcx=%rcx rax=%rax save_ret=0 clear_bp=1 unwind_hint=1 126 PUSH_REGS rdx=\rdx, rcx=\rcx, rax=\rax, save_ret=\save_ret unwind_hint=\unwind_hint 127 CLEAR_REGS clear_bp=\clear_bp 128 .endm 129 130 .macro POP_REGS pop_rdi=1 131 popq %r15 132 popq %r14 133 popq %r13 134 popq %r12 135 popq %rbp 136 popq %rbx 137 popq %r11 138 popq %r10 139 popq %r9 140 popq %r8 141 popq %rax 142 popq %rcx 143 popq %rdx 144 popq %rsi 145 .if \pop_rdi 146 popq %rdi 147 .endif 148 .endm 149 150 #ifdef CONFIG_PAGE_TABLE_ISOLATION 151 152 /* 153 * PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two 154 * halves: 155 */ 156 #define PTI_USER_PGTABLE_BIT PAGE_SHIFT 157 #define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT) 158 #define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT 159 #define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT) 160 #define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK) 161 162 .macro SET_NOFLUSH_BIT reg:req 163 bts $X86_CR3_PCID_NOFLUSH_BIT, \reg 164 .endm 165 166 .macro ADJUST_KERNEL_CR3 reg:req 167 ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID 168 /* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */ 169 andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg 170 .endm 171 172 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req 173 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 174 mov %cr3, \scratch_reg 175 ADJUST_KERNEL_CR3 \scratch_reg 176 mov \scratch_reg, %cr3 177 .Lend_\@: 178 .endm 179 180 #define THIS_CPU_user_pcid_flush_mask \ 181 PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask 182 183 .macro SWITCH_TO_USER_CR3 scratch_reg:req scratch_reg2:req 184 mov %cr3, \scratch_reg 185 186 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID 187 188 /* 189 * Test if the ASID needs a flush. 190 */ 191 movq \scratch_reg, \scratch_reg2 192 andq $(0x7FF), \scratch_reg /* mask ASID */ 193 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask 194 jnc .Lnoflush_\@ 195 196 /* Flush needed, clear the bit */ 197 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask 198 movq \scratch_reg2, \scratch_reg 199 jmp .Lwrcr3_pcid_\@ 200 201 .Lnoflush_\@: 202 movq \scratch_reg2, \scratch_reg 203 SET_NOFLUSH_BIT \scratch_reg 204 205 .Lwrcr3_pcid_\@: 206 /* Flip the ASID to the user version */ 207 orq $(PTI_USER_PCID_MASK), \scratch_reg 208 209 .Lwrcr3_\@: 210 /* Flip the PGD to the user version */ 211 orq $(PTI_USER_PGTABLE_MASK), \scratch_reg 212 mov \scratch_reg, %cr3 213 .endm 214 215 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req 216 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 217 SWITCH_TO_USER_CR3 \scratch_reg \scratch_reg2 218 .Lend_\@: 219 .endm 220 221 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req 222 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 223 pushq %rax 224 SWITCH_TO_USER_CR3 scratch_reg=\scratch_reg scratch_reg2=%rax 225 popq %rax 226 .Lend_\@: 227 .endm 228 229 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req 230 ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI 231 movq %cr3, \scratch_reg 232 movq \scratch_reg, \save_reg 233 /* 234 * Test the user pagetable bit. If set, then the user page tables 235 * are active. If clear CR3 already has the kernel page table 236 * active. 237 */ 238 bt $PTI_USER_PGTABLE_BIT, \scratch_reg 239 jnc .Ldone_\@ 240 241 ADJUST_KERNEL_CR3 \scratch_reg 242 movq \scratch_reg, %cr3 243 244 .Ldone_\@: 245 .endm 246 247 .macro RESTORE_CR3 scratch_reg:req save_reg:req 248 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 249 250 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID 251 252 /* 253 * KERNEL pages can always resume with NOFLUSH as we do 254 * explicit flushes. 255 */ 256 bt $PTI_USER_PGTABLE_BIT, \save_reg 257 jnc .Lnoflush_\@ 258 259 /* 260 * Check if there's a pending flush for the user ASID we're 261 * about to set. 262 */ 263 movq \save_reg, \scratch_reg 264 andq $(0x7FF), \scratch_reg 265 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask 266 jnc .Lnoflush_\@ 267 268 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask 269 jmp .Lwrcr3_\@ 270 271 .Lnoflush_\@: 272 SET_NOFLUSH_BIT \save_reg 273 274 .Lwrcr3_\@: 275 /* 276 * The CR3 write could be avoided when not changing its value, 277 * but would require a CR3 read *and* a scratch register. 278 */ 279 movq \save_reg, %cr3 280 .Lend_\@: 281 .endm 282 283 #else /* CONFIG_PAGE_TABLE_ISOLATION=n: */ 284 285 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req 286 .endm 287 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req 288 .endm 289 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req 290 .endm 291 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req 292 .endm 293 .macro RESTORE_CR3 scratch_reg:req save_reg:req 294 .endm 295 296 #endif 297 298 /* 299 * IBRS kernel mitigation for Spectre_v2. 300 * 301 * Assumes full context is established (PUSH_REGS, CR3 and GS) and it clobbers 302 * the regs it uses (AX, CX, DX). Must be called before the first RET 303 * instruction (NOTE! UNTRAIN_RET includes a RET instruction) 304 * 305 * The optional argument is used to save/restore the current value, 306 * which is used on the paranoid paths. 307 * 308 * Assumes x86_spec_ctrl_{base,current} to have SPEC_CTRL_IBRS set. 309 */ 310 .macro IBRS_ENTER save_reg 311 #ifdef CONFIG_CPU_IBRS_ENTRY 312 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS 313 movl $MSR_IA32_SPEC_CTRL, %ecx 314 315 .ifnb \save_reg 316 rdmsr 317 shl $32, %rdx 318 or %rdx, %rax 319 mov %rax, \save_reg 320 test $SPEC_CTRL_IBRS, %eax 321 jz .Ldo_wrmsr_\@ 322 lfence 323 jmp .Lend_\@ 324 .Ldo_wrmsr_\@: 325 .endif 326 327 movq PER_CPU_VAR(x86_spec_ctrl_current), %rdx 328 movl %edx, %eax 329 shr $32, %rdx 330 wrmsr 331 .Lend_\@: 332 #endif 333 .endm 334 335 /* 336 * Similar to IBRS_ENTER, requires KERNEL GS,CR3 and clobbers (AX, CX, DX) 337 * regs. Must be called after the last RET. 338 */ 339 .macro IBRS_EXIT save_reg 340 #ifdef CONFIG_CPU_IBRS_ENTRY 341 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS 342 movl $MSR_IA32_SPEC_CTRL, %ecx 343 344 .ifnb \save_reg 345 mov \save_reg, %rdx 346 .else 347 movq PER_CPU_VAR(x86_spec_ctrl_current), %rdx 348 andl $(~SPEC_CTRL_IBRS), %edx 349 .endif 350 351 movl %edx, %eax 352 shr $32, %rdx 353 wrmsr 354 .Lend_\@: 355 #endif 356 .endm 357 358 /* 359 * Mitigate Spectre v1 for conditional swapgs code paths. 360 * 361 * FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to 362 * prevent a speculative swapgs when coming from kernel space. 363 * 364 * FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path, 365 * to prevent the swapgs from getting speculatively skipped when coming from 366 * user space. 367 */ 368 .macro FENCE_SWAPGS_USER_ENTRY 369 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER 370 .endm 371 .macro FENCE_SWAPGS_KERNEL_ENTRY 372 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL 373 .endm 374 375 .macro STACKLEAK_ERASE_NOCLOBBER 376 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK 377 PUSH_AND_CLEAR_REGS 378 call stackleak_erase 379 POP_REGS 380 #endif 381 .endm 382 383 .macro SAVE_AND_SET_GSBASE scratch_reg:req save_reg:req 384 rdgsbase \save_reg 385 GET_PERCPU_BASE \scratch_reg 386 wrgsbase \scratch_reg 387 .endm 388 389 #else /* CONFIG_X86_64 */ 390 # undef UNWIND_HINT_IRET_REGS 391 # define UNWIND_HINT_IRET_REGS 392 #endif /* !CONFIG_X86_64 */ 393 394 .macro STACKLEAK_ERASE 395 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK 396 call stackleak_erase 397 #endif 398 .endm 399 400 #ifdef CONFIG_SMP 401 402 /* 403 * CPU/node NR is loaded from the limit (size) field of a special segment 404 * descriptor entry in GDT. 405 */ 406 .macro LOAD_CPU_AND_NODE_SEG_LIMIT reg:req 407 movq $__CPUNODE_SEG, \reg 408 lsl \reg, \reg 409 .endm 410 411 /* 412 * Fetch the per-CPU GSBASE value for this processor and put it in @reg. 413 * We normally use %gs for accessing per-CPU data, but we are setting up 414 * %gs here and obviously can not use %gs itself to access per-CPU data. 415 * 416 * Do not use RDPID, because KVM loads guest's TSC_AUX on vm-entry and 417 * may not restore the host's value until the CPU returns to userspace. 418 * Thus the kernel would consume a guest's TSC_AUX if an NMI arrives 419 * while running KVM's run loop. 420 */ 421 .macro GET_PERCPU_BASE reg:req 422 LOAD_CPU_AND_NODE_SEG_LIMIT \reg 423 andq $VDSO_CPUNODE_MASK, \reg 424 movq __per_cpu_offset(, \reg, 8), \reg 425 .endm 426 427 #else 428 429 .macro GET_PERCPU_BASE reg:req 430 movq pcpu_unit_offsets(%rip), \reg 431 .endm 432 433 #endif /* CONFIG_SMP */ 434