1######################################################################## 2# Implement fast SHA-512 with SSSE3 instructions. (x86_64) 3# 4# Copyright (C) 2013 Intel Corporation. 5# 6# Authors: 7# James Guilford <james.guilford@intel.com> 8# Kirk Yap <kirk.s.yap@intel.com> 9# David Cote <david.m.cote@intel.com> 10# Tim Chen <tim.c.chen@linux.intel.com> 11# 12# This software is available to you under a choice of one of two 13# licenses. You may choose to be licensed under the terms of the GNU 14# General Public License (GPL) Version 2, available from the file 15# COPYING in the main directory of this source tree, or the 16# OpenIB.org BSD license below: 17# 18# Redistribution and use in source and binary forms, with or 19# without modification, are permitted provided that the following 20# conditions are met: 21# 22# - Redistributions of source code must retain the above 23# copyright notice, this list of conditions and the following 24# disclaimer. 25# 26# - Redistributions in binary form must reproduce the above 27# copyright notice, this list of conditions and the following 28# disclaimer in the documentation and/or other materials 29# provided with the distribution. 30# 31# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 32# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 33# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 34# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 35# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 36# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 37# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 38# SOFTWARE. 39# 40######################################################################## 41# 42# This code is described in an Intel White-Paper: 43# "Fast SHA-512 Implementations on Intel Architecture Processors" 44# 45# To find it, surf to http://www.intel.com/p/en_US/embedded 46# and search for that title. 47# 48######################################################################## 49 50#include <linux/linkage.h> 51 52.text 53 54# Virtual Registers 55# ARG1 56digest = %rdi 57# ARG2 58msg = %rsi 59# ARG3 60msglen = %rdx 61T1 = %rcx 62T2 = %r8 63a_64 = %r9 64b_64 = %r10 65c_64 = %r11 66d_64 = %r12 67e_64 = %r13 68f_64 = %r14 69g_64 = %r15 70h_64 = %rbx 71tmp0 = %rax 72 73# Local variables (stack frame) 74 75W_SIZE = 80*8 76WK_SIZE = 2*8 77RSPSAVE_SIZE = 1*8 78GPRSAVE_SIZE = 5*8 79 80frame_W = 0 81frame_WK = frame_W + W_SIZE 82frame_RSPSAVE = frame_WK + WK_SIZE 83frame_GPRSAVE = frame_RSPSAVE + RSPSAVE_SIZE 84frame_size = frame_GPRSAVE + GPRSAVE_SIZE 85 86# Useful QWORD "arrays" for simpler memory references 87# MSG, DIGEST, K_t, W_t are arrays 88# WK_2(t) points to 1 of 2 qwords at frame.WK depdending on t being odd/even 89 90# Input message (arg1) 91#define MSG(i) 8*i(msg) 92 93# Output Digest (arg2) 94#define DIGEST(i) 8*i(digest) 95 96# SHA Constants (static mem) 97#define K_t(i) 8*i+K512(%rip) 98 99# Message Schedule (stack frame) 100#define W_t(i) 8*i+frame_W(%rsp) 101 102# W[t]+K[t] (stack frame) 103#define WK_2(i) 8*((i%2))+frame_WK(%rsp) 104 105.macro RotateState 106 # Rotate symbols a..h right 107 TMP = h_64 108 h_64 = g_64 109 g_64 = f_64 110 f_64 = e_64 111 e_64 = d_64 112 d_64 = c_64 113 c_64 = b_64 114 b_64 = a_64 115 a_64 = TMP 116.endm 117 118.macro SHA512_Round rnd 119 120 # Compute Round %%t 121 mov f_64, T1 # T1 = f 122 mov e_64, tmp0 # tmp = e 123 xor g_64, T1 # T1 = f ^ g 124 ror $23, tmp0 # 41 # tmp = e ror 23 125 and e_64, T1 # T1 = (f ^ g) & e 126 xor e_64, tmp0 # tmp = (e ror 23) ^ e 127 xor g_64, T1 # T1 = ((f ^ g) & e) ^ g = CH(e,f,g) 128 idx = \rnd 129 add WK_2(idx), T1 # W[t] + K[t] from message scheduler 130 ror $4, tmp0 # 18 # tmp = ((e ror 23) ^ e) ror 4 131 xor e_64, tmp0 # tmp = (((e ror 23) ^ e) ror 4) ^ e 132 mov a_64, T2 # T2 = a 133 add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h 134 ror $14, tmp0 # 14 # tmp = ((((e ror23)^e)ror4)^e)ror14 = S1(e) 135 add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e) 136 mov a_64, tmp0 # tmp = a 137 xor c_64, T2 # T2 = a ^ c 138 and c_64, tmp0 # tmp = a & c 139 and b_64, T2 # T2 = (a ^ c) & b 140 xor tmp0, T2 # T2 = ((a ^ c) & b) ^ (a & c) = Maj(a,b,c) 141 mov a_64, tmp0 # tmp = a 142 ror $5, tmp0 # 39 # tmp = a ror 5 143 xor a_64, tmp0 # tmp = (a ror 5) ^ a 144 add T1, d_64 # e(next_state) = d + T1 145 ror $6, tmp0 # 34 # tmp = ((a ror 5) ^ a) ror 6 146 xor a_64, tmp0 # tmp = (((a ror 5) ^ a) ror 6) ^ a 147 lea (T1, T2), h_64 # a(next_state) = T1 + Maj(a,b,c) 148 ror $28, tmp0 # 28 # tmp = ((((a ror5)^a)ror6)^a)ror28 = S0(a) 149 add tmp0, h_64 # a(next_state) = T1 + Maj(a,b,c) S0(a) 150 RotateState 151.endm 152 153.macro SHA512_2Sched_2Round_sse rnd 154 155 # Compute rounds t-2 and t-1 156 # Compute message schedule QWORDS t and t+1 157 158 # Two rounds are computed based on the values for K[t-2]+W[t-2] and 159 # K[t-1]+W[t-1] which were previously stored at WK_2 by the message 160 # scheduler. 161 # The two new schedule QWORDS are stored at [W_t(%%t)] and [W_t(%%t+1)]. 162 # They are then added to their respective SHA512 constants at 163 # [K_t(%%t)] and [K_t(%%t+1)] and stored at dqword [WK_2(%%t)] 164 # For brievity, the comments following vectored instructions only refer to 165 # the first of a pair of QWORDS. 166 # Eg. XMM2=W[t-2] really means XMM2={W[t-2]|W[t-1]} 167 # The computation of the message schedule and the rounds are tightly 168 # stitched to take advantage of instruction-level parallelism. 169 # For clarity, integer instructions (for the rounds calculation) are indented 170 # by one tab. Vectored instructions (for the message scheduler) are indented 171 # by two tabs. 172 173 mov f_64, T1 174 idx = \rnd -2 175 movdqa W_t(idx), %xmm2 # XMM2 = W[t-2] 176 xor g_64, T1 177 and e_64, T1 178 movdqa %xmm2, %xmm0 # XMM0 = W[t-2] 179 xor g_64, T1 180 idx = \rnd 181 add WK_2(idx), T1 182 idx = \rnd - 15 183 movdqu W_t(idx), %xmm5 # XMM5 = W[t-15] 184 mov e_64, tmp0 185 ror $23, tmp0 # 41 186 movdqa %xmm5, %xmm3 # XMM3 = W[t-15] 187 xor e_64, tmp0 188 ror $4, tmp0 # 18 189 psrlq $61-19, %xmm0 # XMM0 = W[t-2] >> 42 190 xor e_64, tmp0 191 ror $14, tmp0 # 14 192 psrlq $(8-7), %xmm3 # XMM3 = W[t-15] >> 1 193 add tmp0, T1 194 add h_64, T1 195 pxor %xmm2, %xmm0 # XMM0 = (W[t-2] >> 42) ^ W[t-2] 196 mov a_64, T2 197 xor c_64, T2 198 pxor %xmm5, %xmm3 # XMM3 = (W[t-15] >> 1) ^ W[t-15] 199 and b_64, T2 200 mov a_64, tmp0 201 psrlq $(19-6), %xmm0 # XMM0 = ((W[t-2]>>42)^W[t-2])>>13 202 and c_64, tmp0 203 xor tmp0, T2 204 psrlq $(7-1), %xmm3 # XMM3 = ((W[t-15]>>1)^W[t-15])>>6 205 mov a_64, tmp0 206 ror $5, tmp0 # 39 207 pxor %xmm2, %xmm0 # XMM0 = (((W[t-2]>>42)^W[t-2])>>13)^W[t-2] 208 xor a_64, tmp0 209 ror $6, tmp0 # 34 210 pxor %xmm5, %xmm3 # XMM3 = (((W[t-15]>>1)^W[t-15])>>6)^W[t-15] 211 xor a_64, tmp0 212 ror $28, tmp0 # 28 213 psrlq $6, %xmm0 # XMM0 = ((((W[t-2]>>42)^W[t-2])>>13)^W[t-2])>>6 214 add tmp0, T2 215 add T1, d_64 216 psrlq $1, %xmm3 # XMM3 = (((W[t-15]>>1)^W[t-15])>>6)^W[t-15]>>1 217 lea (T1, T2), h_64 218 RotateState 219 movdqa %xmm2, %xmm1 # XMM1 = W[t-2] 220 mov f_64, T1 221 xor g_64, T1 222 movdqa %xmm5, %xmm4 # XMM4 = W[t-15] 223 and e_64, T1 224 xor g_64, T1 225 psllq $(64-19)-(64-61) , %xmm1 # XMM1 = W[t-2] << 42 226 idx = \rnd + 1 227 add WK_2(idx), T1 228 mov e_64, tmp0 229 psllq $(64-1)-(64-8), %xmm4 # XMM4 = W[t-15] << 7 230 ror $23, tmp0 # 41 231 xor e_64, tmp0 232 pxor %xmm2, %xmm1 # XMM1 = (W[t-2] << 42)^W[t-2] 233 ror $4, tmp0 # 18 234 xor e_64, tmp0 235 pxor %xmm5, %xmm4 # XMM4 = (W[t-15]<<7)^W[t-15] 236 ror $14, tmp0 # 14 237 add tmp0, T1 238 psllq $(64-61), %xmm1 # XMM1 = ((W[t-2] << 42)^W[t-2])<<3 239 add h_64, T1 240 mov a_64, T2 241 psllq $(64-8), %xmm4 # XMM4 = ((W[t-15]<<7)^W[t-15])<<56 242 xor c_64, T2 243 and b_64, T2 244 pxor %xmm1, %xmm0 # XMM0 = s1(W[t-2]) 245 mov a_64, tmp0 246 and c_64, tmp0 247 idx = \rnd - 7 248 movdqu W_t(idx), %xmm1 # XMM1 = W[t-7] 249 xor tmp0, T2 250 pxor %xmm4, %xmm3 # XMM3 = s0(W[t-15]) 251 mov a_64, tmp0 252 paddq %xmm3, %xmm0 # XMM0 = s1(W[t-2]) + s0(W[t-15]) 253 ror $5, tmp0 # 39 254 idx =\rnd-16 255 paddq W_t(idx), %xmm0 # XMM0 = s1(W[t-2]) + s0(W[t-15]) + W[t-16] 256 xor a_64, tmp0 257 paddq %xmm1, %xmm0 # XMM0 = s1(W[t-2]) + W[t-7] + s0(W[t-15]) + W[t-16] 258 ror $6, tmp0 # 34 259 movdqa %xmm0, W_t(\rnd) # Store scheduled qwords 260 xor a_64, tmp0 261 paddq K_t(\rnd), %xmm0 # Compute W[t]+K[t] 262 ror $28, tmp0 # 28 263 idx = \rnd 264 movdqa %xmm0, WK_2(idx) # Store W[t]+K[t] for next rounds 265 add tmp0, T2 266 add T1, d_64 267 lea (T1, T2), h_64 268 RotateState 269.endm 270 271######################################################################## 272## void sha512_transform_ssse3(struct sha512_state *state, const u8 *data, 273## int blocks); 274# (struct sha512_state is assumed to begin with u64 state[8]) 275# Purpose: Updates the SHA512 digest stored at "state" with the message 276# stored in "data". 277# The size of the message pointed to by "data" must be an integer multiple 278# of SHA512 message blocks. 279# "blocks" is the message length in SHA512 blocks. 280######################################################################## 281SYM_FUNC_START(sha512_transform_ssse3) 282 283 test msglen, msglen 284 je nowork 285 286 # Allocate Stack Space 287 mov %rsp, %rax 288 sub $frame_size, %rsp 289 and $~(0x20 - 1), %rsp 290 mov %rax, frame_RSPSAVE(%rsp) 291 292 # Save GPRs 293 mov %rbx, frame_GPRSAVE(%rsp) 294 mov %r12, frame_GPRSAVE +8*1(%rsp) 295 mov %r13, frame_GPRSAVE +8*2(%rsp) 296 mov %r14, frame_GPRSAVE +8*3(%rsp) 297 mov %r15, frame_GPRSAVE +8*4(%rsp) 298 299updateblock: 300 301# Load state variables 302 mov DIGEST(0), a_64 303 mov DIGEST(1), b_64 304 mov DIGEST(2), c_64 305 mov DIGEST(3), d_64 306 mov DIGEST(4), e_64 307 mov DIGEST(5), f_64 308 mov DIGEST(6), g_64 309 mov DIGEST(7), h_64 310 311 t = 0 312 .rept 80/2 + 1 313 # (80 rounds) / (2 rounds/iteration) + (1 iteration) 314 # +1 iteration because the scheduler leads hashing by 1 iteration 315 .if t < 2 316 # BSWAP 2 QWORDS 317 movdqa XMM_QWORD_BSWAP(%rip), %xmm1 318 movdqu MSG(t), %xmm0 319 pshufb %xmm1, %xmm0 # BSWAP 320 movdqa %xmm0, W_t(t) # Store Scheduled Pair 321 paddq K_t(t), %xmm0 # Compute W[t]+K[t] 322 movdqa %xmm0, WK_2(t) # Store into WK for rounds 323 .elseif t < 16 324 # BSWAP 2 QWORDS# Compute 2 Rounds 325 movdqu MSG(t), %xmm0 326 pshufb %xmm1, %xmm0 # BSWAP 327 SHA512_Round t-2 # Round t-2 328 movdqa %xmm0, W_t(t) # Store Scheduled Pair 329 paddq K_t(t), %xmm0 # Compute W[t]+K[t] 330 SHA512_Round t-1 # Round t-1 331 movdqa %xmm0, WK_2(t) # Store W[t]+K[t] into WK 332 .elseif t < 79 333 # Schedule 2 QWORDS# Compute 2 Rounds 334 SHA512_2Sched_2Round_sse t 335 .else 336 # Compute 2 Rounds 337 SHA512_Round t-2 338 SHA512_Round t-1 339 .endif 340 t = t+2 341 .endr 342 343 # Update digest 344 add a_64, DIGEST(0) 345 add b_64, DIGEST(1) 346 add c_64, DIGEST(2) 347 add d_64, DIGEST(3) 348 add e_64, DIGEST(4) 349 add f_64, DIGEST(5) 350 add g_64, DIGEST(6) 351 add h_64, DIGEST(7) 352 353 # Advance to next message block 354 add $16*8, msg 355 dec msglen 356 jnz updateblock 357 358 # Restore GPRs 359 mov frame_GPRSAVE(%rsp), %rbx 360 mov frame_GPRSAVE +8*1(%rsp), %r12 361 mov frame_GPRSAVE +8*2(%rsp), %r13 362 mov frame_GPRSAVE +8*3(%rsp), %r14 363 mov frame_GPRSAVE +8*4(%rsp), %r15 364 365 # Restore Stack Pointer 366 mov frame_RSPSAVE(%rsp), %rsp 367 368nowork: 369 ret 370SYM_FUNC_END(sha512_transform_ssse3) 371 372######################################################################## 373### Binary Data 374 375.section .rodata.cst16.XMM_QWORD_BSWAP, "aM", @progbits, 16 376.align 16 377# Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb. 378XMM_QWORD_BSWAP: 379 .octa 0x08090a0b0c0d0e0f0001020304050607 380 381# Mergeable 640-byte rodata section. This allows linker to merge the table 382# with other, exactly the same 640-byte fragment of another rodata section 383# (if such section exists). 384.section .rodata.cst640.K512, "aM", @progbits, 640 385.align 64 386# K[t] used in SHA512 hashing 387K512: 388 .quad 0x428a2f98d728ae22,0x7137449123ef65cd 389 .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc 390 .quad 0x3956c25bf348b538,0x59f111f1b605d019 391 .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118 392 .quad 0xd807aa98a3030242,0x12835b0145706fbe 393 .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2 394 .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1 395 .quad 0x9bdc06a725c71235,0xc19bf174cf692694 396 .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3 397 .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65 398 .quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483 399 .quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5 400 .quad 0x983e5152ee66dfab,0xa831c66d2db43210 401 .quad 0xb00327c898fb213f,0xbf597fc7beef0ee4 402 .quad 0xc6e00bf33da88fc2,0xd5a79147930aa725 403 .quad 0x06ca6351e003826f,0x142929670a0e6e70 404 .quad 0x27b70a8546d22ffc,0x2e1b21385c26c926 405 .quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df 406 .quad 0x650a73548baf63de,0x766a0abb3c77b2a8 407 .quad 0x81c2c92e47edaee6,0x92722c851482353b 408 .quad 0xa2bfe8a14cf10364,0xa81a664bbc423001 409 .quad 0xc24b8b70d0f89791,0xc76c51a30654be30 410 .quad 0xd192e819d6ef5218,0xd69906245565a910 411 .quad 0xf40e35855771202a,0x106aa07032bbd1b8 412 .quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53 413 .quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8 414 .quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb 415 .quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3 416 .quad 0x748f82ee5defb2fc,0x78a5636f43172f60 417 .quad 0x84c87814a1f0ab72,0x8cc702081a6439ec 418 .quad 0x90befffa23631e28,0xa4506cebde82bde9 419 .quad 0xbef9a3f7b2c67915,0xc67178f2e372532b 420 .quad 0xca273eceea26619c,0xd186b8c721c0c207 421 .quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178 422 .quad 0x06f067aa72176fba,0x0a637dc5a2c898a6 423 .quad 0x113f9804bef90dae,0x1b710b35131c471b 424 .quad 0x28db77f523047d84,0x32caab7b40c72493 425 .quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c 426 .quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a 427 .quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817 428