1######################################################################## 2# Implement fast SHA-512 with AVX instructions. (x86_64) 3# 4# Copyright (C) 2013 Intel Corporation. 5# 6# Authors: 7# James Guilford <james.guilford@intel.com> 8# Kirk Yap <kirk.s.yap@intel.com> 9# David Cote <david.m.cote@intel.com> 10# Tim Chen <tim.c.chen@linux.intel.com> 11# 12# This software is available to you under a choice of one of two 13# licenses. You may choose to be licensed under the terms of the GNU 14# General Public License (GPL) Version 2, available from the file 15# COPYING in the main directory of this source tree, or the 16# OpenIB.org BSD license below: 17# 18# Redistribution and use in source and binary forms, with or 19# without modification, are permitted provided that the following 20# conditions are met: 21# 22# - Redistributions of source code must retain the above 23# copyright notice, this list of conditions and the following 24# disclaimer. 25# 26# - Redistributions in binary form must reproduce the above 27# copyright notice, this list of conditions and the following 28# disclaimer in the documentation and/or other materials 29# provided with the distribution. 30# 31# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 32# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 33# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 34# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 35# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 36# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 37# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 38# SOFTWARE. 39# 40######################################################################## 41# 42# This code is described in an Intel White-Paper: 43# "Fast SHA-512 Implementations on Intel Architecture Processors" 44# 45# To find it, surf to http://www.intel.com/p/en_US/embedded 46# and search for that title. 47# 48######################################################################## 49 50#include <linux/linkage.h> 51#include <linux/cfi_types.h> 52 53.text 54 55# Virtual Registers 56# ARG1 57digest = %rdi 58# ARG2 59msg = %rsi 60# ARG3 61msglen = %rdx 62T1 = %rcx 63T2 = %r8 64a_64 = %r9 65b_64 = %r10 66c_64 = %r11 67d_64 = %r12 68e_64 = %r13 69f_64 = %r14 70g_64 = %r15 71h_64 = %rbx 72tmp0 = %rax 73 74# Local variables (stack frame) 75 76# Message Schedule 77W_SIZE = 80*8 78# W[t] + K[t] | W[t+1] + K[t+1] 79WK_SIZE = 2*8 80 81frame_W = 0 82frame_WK = frame_W + W_SIZE 83frame_size = frame_WK + WK_SIZE 84 85# Useful QWORD "arrays" for simpler memory references 86# MSG, DIGEST, K_t, W_t are arrays 87# WK_2(t) points to 1 of 2 qwords at frame.WK depending on t being odd/even 88 89# Input message (arg1) 90#define MSG(i) 8*i(msg) 91 92# Output Digest (arg2) 93#define DIGEST(i) 8*i(digest) 94 95# SHA Constants (static mem) 96#define K_t(i) 8*i+K512(%rip) 97 98# Message Schedule (stack frame) 99#define W_t(i) 8*i+frame_W(%rsp) 100 101# W[t]+K[t] (stack frame) 102#define WK_2(i) 8*((i%2))+frame_WK(%rsp) 103 104.macro RotateState 105 # Rotate symbols a..h right 106 TMP = h_64 107 h_64 = g_64 108 g_64 = f_64 109 f_64 = e_64 110 e_64 = d_64 111 d_64 = c_64 112 c_64 = b_64 113 b_64 = a_64 114 a_64 = TMP 115.endm 116 117.macro RORQ p1 p2 118 # shld is faster than ror on Sandybridge 119 shld $(64-\p2), \p1, \p1 120.endm 121 122.macro SHA512_Round rnd 123 # Compute Round %%t 124 mov f_64, T1 # T1 = f 125 mov e_64, tmp0 # tmp = e 126 xor g_64, T1 # T1 = f ^ g 127 RORQ tmp0, 23 # 41 # tmp = e ror 23 128 and e_64, T1 # T1 = (f ^ g) & e 129 xor e_64, tmp0 # tmp = (e ror 23) ^ e 130 xor g_64, T1 # T1 = ((f ^ g) & e) ^ g = CH(e,f,g) 131 idx = \rnd 132 add WK_2(idx), T1 # W[t] + K[t] from message scheduler 133 RORQ tmp0, 4 # 18 # tmp = ((e ror 23) ^ e) ror 4 134 xor e_64, tmp0 # tmp = (((e ror 23) ^ e) ror 4) ^ e 135 mov a_64, T2 # T2 = a 136 add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h 137 RORQ tmp0, 14 # 14 # tmp = ((((e ror23)^e)ror4)^e)ror14 = S1(e) 138 add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e) 139 mov a_64, tmp0 # tmp = a 140 xor c_64, T2 # T2 = a ^ c 141 and c_64, tmp0 # tmp = a & c 142 and b_64, T2 # T2 = (a ^ c) & b 143 xor tmp0, T2 # T2 = ((a ^ c) & b) ^ (a & c) = Maj(a,b,c) 144 mov a_64, tmp0 # tmp = a 145 RORQ tmp0, 5 # 39 # tmp = a ror 5 146 xor a_64, tmp0 # tmp = (a ror 5) ^ a 147 add T1, d_64 # e(next_state) = d + T1 148 RORQ tmp0, 6 # 34 # tmp = ((a ror 5) ^ a) ror 6 149 xor a_64, tmp0 # tmp = (((a ror 5) ^ a) ror 6) ^ a 150 lea (T1, T2), h_64 # a(next_state) = T1 + Maj(a,b,c) 151 RORQ tmp0, 28 # 28 # tmp = ((((a ror5)^a)ror6)^a)ror28 = S0(a) 152 add tmp0, h_64 # a(next_state) = T1 + Maj(a,b,c) S0(a) 153 RotateState 154.endm 155 156.macro SHA512_2Sched_2Round_avx rnd 157 # Compute rounds t-2 and t-1 158 # Compute message schedule QWORDS t and t+1 159 160 # Two rounds are computed based on the values for K[t-2]+W[t-2] and 161 # K[t-1]+W[t-1] which were previously stored at WK_2 by the message 162 # scheduler. 163 # The two new schedule QWORDS are stored at [W_t(t)] and [W_t(t+1)]. 164 # They are then added to their respective SHA512 constants at 165 # [K_t(t)] and [K_t(t+1)] and stored at dqword [WK_2(t)] 166 # For brievity, the comments following vectored instructions only refer to 167 # the first of a pair of QWORDS. 168 # Eg. XMM4=W[t-2] really means XMM4={W[t-2]|W[t-1]} 169 # The computation of the message schedule and the rounds are tightly 170 # stitched to take advantage of instruction-level parallelism. 171 172 idx = \rnd - 2 173 vmovdqa W_t(idx), %xmm4 # XMM4 = W[t-2] 174 idx = \rnd - 15 175 vmovdqu W_t(idx), %xmm5 # XMM5 = W[t-15] 176 mov f_64, T1 177 vpsrlq $61, %xmm4, %xmm0 # XMM0 = W[t-2]>>61 178 mov e_64, tmp0 179 vpsrlq $1, %xmm5, %xmm6 # XMM6 = W[t-15]>>1 180 xor g_64, T1 181 RORQ tmp0, 23 # 41 182 vpsrlq $19, %xmm4, %xmm1 # XMM1 = W[t-2]>>19 183 and e_64, T1 184 xor e_64, tmp0 185 vpxor %xmm1, %xmm0, %xmm0 # XMM0 = W[t-2]>>61 ^ W[t-2]>>19 186 xor g_64, T1 187 idx = \rnd 188 add WK_2(idx), T1# 189 vpsrlq $8, %xmm5, %xmm7 # XMM7 = W[t-15]>>8 190 RORQ tmp0, 4 # 18 191 vpsrlq $6, %xmm4, %xmm2 # XMM2 = W[t-2]>>6 192 xor e_64, tmp0 193 mov a_64, T2 194 add h_64, T1 195 vpxor %xmm7, %xmm6, %xmm6 # XMM6 = W[t-15]>>1 ^ W[t-15]>>8 196 RORQ tmp0, 14 # 14 197 add tmp0, T1 198 vpsrlq $7, %xmm5, %xmm8 # XMM8 = W[t-15]>>7 199 mov a_64, tmp0 200 xor c_64, T2 201 vpsllq $(64-61), %xmm4, %xmm3 # XMM3 = W[t-2]<<3 202 and c_64, tmp0 203 and b_64, T2 204 vpxor %xmm3, %xmm2, %xmm2 # XMM2 = W[t-2]>>6 ^ W[t-2]<<3 205 xor tmp0, T2 206 mov a_64, tmp0 207 vpsllq $(64-1), %xmm5, %xmm9 # XMM9 = W[t-15]<<63 208 RORQ tmp0, 5 # 39 209 vpxor %xmm9, %xmm8, %xmm8 # XMM8 = W[t-15]>>7 ^ W[t-15]<<63 210 xor a_64, tmp0 211 add T1, d_64 212 RORQ tmp0, 6 # 34 213 xor a_64, tmp0 214 vpxor %xmm8, %xmm6, %xmm6 # XMM6 = W[t-15]>>1 ^ W[t-15]>>8 ^ 215 # W[t-15]>>7 ^ W[t-15]<<63 216 lea (T1, T2), h_64 217 RORQ tmp0, 28 # 28 218 vpsllq $(64-19), %xmm4, %xmm4 # XMM4 = W[t-2]<<25 219 add tmp0, h_64 220 RotateState 221 vpxor %xmm4, %xmm0, %xmm0 # XMM0 = W[t-2]>>61 ^ W[t-2]>>19 ^ 222 # W[t-2]<<25 223 mov f_64, T1 224 vpxor %xmm2, %xmm0, %xmm0 # XMM0 = s1(W[t-2]) 225 mov e_64, tmp0 226 xor g_64, T1 227 idx = \rnd - 16 228 vpaddq W_t(idx), %xmm0, %xmm0 # XMM0 = s1(W[t-2]) + W[t-16] 229 idx = \rnd - 7 230 vmovdqu W_t(idx), %xmm1 # XMM1 = W[t-7] 231 RORQ tmp0, 23 # 41 232 and e_64, T1 233 xor e_64, tmp0 234 xor g_64, T1 235 vpsllq $(64-8), %xmm5, %xmm5 # XMM5 = W[t-15]<<56 236 idx = \rnd + 1 237 add WK_2(idx), T1 238 vpxor %xmm5, %xmm6, %xmm6 # XMM6 = s0(W[t-15]) 239 RORQ tmp0, 4 # 18 240 vpaddq %xmm6, %xmm0, %xmm0 # XMM0 = s1(W[t-2]) + W[t-16] + s0(W[t-15]) 241 xor e_64, tmp0 242 vpaddq %xmm1, %xmm0, %xmm0 # XMM0 = W[t] = s1(W[t-2]) + W[t-7] + 243 # s0(W[t-15]) + W[t-16] 244 mov a_64, T2 245 add h_64, T1 246 RORQ tmp0, 14 # 14 247 add tmp0, T1 248 idx = \rnd 249 vmovdqa %xmm0, W_t(idx) # Store W[t] 250 vpaddq K_t(idx), %xmm0, %xmm0 # Compute W[t]+K[t] 251 vmovdqa %xmm0, WK_2(idx) # Store W[t]+K[t] for next rounds 252 mov a_64, tmp0 253 xor c_64, T2 254 and c_64, tmp0 255 and b_64, T2 256 xor tmp0, T2 257 mov a_64, tmp0 258 RORQ tmp0, 5 # 39 259 xor a_64, tmp0 260 add T1, d_64 261 RORQ tmp0, 6 # 34 262 xor a_64, tmp0 263 lea (T1, T2), h_64 264 RORQ tmp0, 28 # 28 265 add tmp0, h_64 266 RotateState 267.endm 268 269######################################################################## 270# void sha512_transform_avx(sha512_state *state, const u8 *data, int blocks) 271# Purpose: Updates the SHA512 digest stored at "state" with the message 272# stored in "data". 273# The size of the message pointed to by "data" must be an integer multiple 274# of SHA512 message blocks. 275# "blocks" is the message length in SHA512 blocks 276######################################################################## 277SYM_TYPED_FUNC_START(sha512_transform_avx) 278 test msglen, msglen 279 je .Lnowork 280 281 # Save GPRs 282 push %rbx 283 push %r12 284 push %r13 285 push %r14 286 push %r15 287 288 # Allocate Stack Space 289 push %rbp 290 mov %rsp, %rbp 291 sub $frame_size, %rsp 292 and $~(0x20 - 1), %rsp 293 294.Lupdateblock: 295 296 # Load state variables 297 mov DIGEST(0), a_64 298 mov DIGEST(1), b_64 299 mov DIGEST(2), c_64 300 mov DIGEST(3), d_64 301 mov DIGEST(4), e_64 302 mov DIGEST(5), f_64 303 mov DIGEST(6), g_64 304 mov DIGEST(7), h_64 305 306 t = 0 307 .rept 80/2 + 1 308 # (80 rounds) / (2 rounds/iteration) + (1 iteration) 309 # +1 iteration because the scheduler leads hashing by 1 iteration 310 .if t < 2 311 # BSWAP 2 QWORDS 312 vmovdqa XMM_QWORD_BSWAP(%rip), %xmm1 313 vmovdqu MSG(t), %xmm0 314 vpshufb %xmm1, %xmm0, %xmm0 # BSWAP 315 vmovdqa %xmm0, W_t(t) # Store Scheduled Pair 316 vpaddq K_t(t), %xmm0, %xmm0 # Compute W[t]+K[t] 317 vmovdqa %xmm0, WK_2(t) # Store into WK for rounds 318 .elseif t < 16 319 # BSWAP 2 QWORDS# Compute 2 Rounds 320 vmovdqu MSG(t), %xmm0 321 vpshufb %xmm1, %xmm0, %xmm0 # BSWAP 322 SHA512_Round t-2 # Round t-2 323 vmovdqa %xmm0, W_t(t) # Store Scheduled Pair 324 vpaddq K_t(t), %xmm0, %xmm0 # Compute W[t]+K[t] 325 SHA512_Round t-1 # Round t-1 326 vmovdqa %xmm0, WK_2(t)# Store W[t]+K[t] into WK 327 .elseif t < 79 328 # Schedule 2 QWORDS# Compute 2 Rounds 329 SHA512_2Sched_2Round_avx t 330 .else 331 # Compute 2 Rounds 332 SHA512_Round t-2 333 SHA512_Round t-1 334 .endif 335 t = t+2 336 .endr 337 338 # Update digest 339 add a_64, DIGEST(0) 340 add b_64, DIGEST(1) 341 add c_64, DIGEST(2) 342 add d_64, DIGEST(3) 343 add e_64, DIGEST(4) 344 add f_64, DIGEST(5) 345 add g_64, DIGEST(6) 346 add h_64, DIGEST(7) 347 348 # Advance to next message block 349 add $16*8, msg 350 dec msglen 351 jnz .Lupdateblock 352 353 # Restore Stack Pointer 354 mov %rbp, %rsp 355 pop %rbp 356 357 # Restore GPRs 358 pop %r15 359 pop %r14 360 pop %r13 361 pop %r12 362 pop %rbx 363 364.Lnowork: 365 RET 366SYM_FUNC_END(sha512_transform_avx) 367 368######################################################################## 369### Binary Data 370 371.section .rodata.cst16.XMM_QWORD_BSWAP, "aM", @progbits, 16 372.align 16 373# Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb. 374XMM_QWORD_BSWAP: 375 .octa 0x08090a0b0c0d0e0f0001020304050607 376 377# Mergeable 640-byte rodata section. This allows linker to merge the table 378# with other, exactly the same 640-byte fragment of another rodata section 379# (if such section exists). 380.section .rodata.cst640.K512, "aM", @progbits, 640 381.align 64 382# K[t] used in SHA512 hashing 383K512: 384 .quad 0x428a2f98d728ae22,0x7137449123ef65cd 385 .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc 386 .quad 0x3956c25bf348b538,0x59f111f1b605d019 387 .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118 388 .quad 0xd807aa98a3030242,0x12835b0145706fbe 389 .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2 390 .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1 391 .quad 0x9bdc06a725c71235,0xc19bf174cf692694 392 .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3 393 .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65 394 .quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483 395 .quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5 396 .quad 0x983e5152ee66dfab,0xa831c66d2db43210 397 .quad 0xb00327c898fb213f,0xbf597fc7beef0ee4 398 .quad 0xc6e00bf33da88fc2,0xd5a79147930aa725 399 .quad 0x06ca6351e003826f,0x142929670a0e6e70 400 .quad 0x27b70a8546d22ffc,0x2e1b21385c26c926 401 .quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df 402 .quad 0x650a73548baf63de,0x766a0abb3c77b2a8 403 .quad 0x81c2c92e47edaee6,0x92722c851482353b 404 .quad 0xa2bfe8a14cf10364,0xa81a664bbc423001 405 .quad 0xc24b8b70d0f89791,0xc76c51a30654be30 406 .quad 0xd192e819d6ef5218,0xd69906245565a910 407 .quad 0xf40e35855771202a,0x106aa07032bbd1b8 408 .quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53 409 .quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8 410 .quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb 411 .quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3 412 .quad 0x748f82ee5defb2fc,0x78a5636f43172f60 413 .quad 0x84c87814a1f0ab72,0x8cc702081a6439ec 414 .quad 0x90befffa23631e28,0xa4506cebde82bde9 415 .quad 0xbef9a3f7b2c67915,0xc67178f2e372532b 416 .quad 0xca273eceea26619c,0xd186b8c721c0c207 417 .quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178 418 .quad 0x06f067aa72176fba,0x0a637dc5a2c898a6 419 .quad 0x113f9804bef90dae,0x1b710b35131c471b 420 .quad 0x28db77f523047d84,0x32caab7b40c72493 421 .quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c 422 .quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a 423 .quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817 424