1 // SPDX-License-Identifier: GPL-2.0 2 #include "misc.h" 3 #include <asm/bootparam.h> 4 #include <asm/bootparam_utils.h> 5 #include <asm/e820/types.h> 6 #include <asm/processor.h> 7 #include "../string.h" 8 #include "efi.h" 9 10 #define BIOS_START_MIN 0x20000U /* 128K, less than this is insane */ 11 #define BIOS_START_MAX 0x9f000U /* 640K, absolute maximum */ 12 13 /* __pgtable_l5_enabled needs to be in .data to avoid being cleared along with .bss */ 14 unsigned int __section(".data") __pgtable_l5_enabled; 15 unsigned int __section(".data") pgdir_shift = 39; 16 unsigned int __section(".data") ptrs_per_p4d = 1; 17 18 /* Buffer to preserve trampoline memory */ 19 static char trampoline_save[TRAMPOLINE_32BIT_SIZE]; 20 21 /* 22 * Trampoline address will be printed by extract_kernel() for debugging 23 * purposes. 24 * 25 * Avoid putting the pointer into .bss as it will be cleared between 26 * configure_5level_paging() and extract_kernel(). 27 */ 28 unsigned long *trampoline_32bit __section(".data"); 29 30 int cmdline_find_option_bool(const char *option); 31 32 static unsigned long find_trampoline_placement(void) 33 { 34 unsigned long bios_start = 0, ebda_start = 0; 35 struct boot_e820_entry *entry; 36 char *signature; 37 int i; 38 39 /* 40 * Find a suitable spot for the trampoline. 41 * This code is based on reserve_bios_regions(). 42 */ 43 44 /* 45 * EFI systems may not provide legacy ROM. The memory may not be mapped 46 * at all. 47 * 48 * Only look for values in the legacy ROM for non-EFI system. 49 */ 50 signature = (char *)&boot_params_ptr->efi_info.efi_loader_signature; 51 if (strncmp(signature, EFI32_LOADER_SIGNATURE, 4) && 52 strncmp(signature, EFI64_LOADER_SIGNATURE, 4)) { 53 ebda_start = *(unsigned short *)0x40e << 4; 54 bios_start = *(unsigned short *)0x413 << 10; 55 } 56 57 if (bios_start < BIOS_START_MIN || bios_start > BIOS_START_MAX) 58 bios_start = BIOS_START_MAX; 59 60 if (ebda_start > BIOS_START_MIN && ebda_start < bios_start) 61 bios_start = ebda_start; 62 63 bios_start = round_down(bios_start, PAGE_SIZE); 64 65 /* Find the first usable memory region under bios_start. */ 66 for (i = boot_params_ptr->e820_entries - 1; i >= 0; i--) { 67 unsigned long new = bios_start; 68 69 entry = &boot_params_ptr->e820_table[i]; 70 71 /* Skip all entries above bios_start. */ 72 if (bios_start <= entry->addr) 73 continue; 74 75 /* Skip non-RAM entries. */ 76 if (entry->type != E820_TYPE_RAM) 77 continue; 78 79 /* Adjust bios_start to the end of the entry if needed. */ 80 if (bios_start > entry->addr + entry->size) 81 new = entry->addr + entry->size; 82 83 /* Keep bios_start page-aligned. */ 84 new = round_down(new, PAGE_SIZE); 85 86 /* Skip the entry if it's too small. */ 87 if (new - TRAMPOLINE_32BIT_SIZE < entry->addr) 88 continue; 89 90 /* Protect against underflow. */ 91 if (new - TRAMPOLINE_32BIT_SIZE > bios_start) 92 break; 93 94 bios_start = new; 95 break; 96 } 97 98 /* Place the trampoline just below the end of low memory */ 99 return bios_start - TRAMPOLINE_32BIT_SIZE; 100 } 101 102 asmlinkage void configure_5level_paging(struct boot_params *bp, void *pgtable) 103 { 104 void (*toggle_la57)(void *cr3); 105 bool l5_required = false; 106 107 /* Initialize boot_params. Required for cmdline_find_option_bool(). */ 108 sanitize_boot_params(bp); 109 boot_params_ptr = bp; 110 111 /* 112 * Check if LA57 is desired and supported. 113 * 114 * There are several parts to the check: 115 * - if user asked to disable 5-level paging: no5lvl in cmdline 116 * - if the machine supports 5-level paging: 117 * + CPUID leaf 7 is supported 118 * + the leaf has the feature bit set 119 */ 120 if (!cmdline_find_option_bool("no5lvl") && 121 native_cpuid_eax(0) >= 7 && (native_cpuid_ecx(7) & BIT(16))) { 122 l5_required = true; 123 124 /* Initialize variables for 5-level paging */ 125 __pgtable_l5_enabled = 1; 126 pgdir_shift = 48; 127 ptrs_per_p4d = 512; 128 } 129 130 /* 131 * The trampoline will not be used if the paging mode is already set to 132 * the desired one. 133 */ 134 if (l5_required == !!(native_read_cr4() & X86_CR4_LA57)) 135 return; 136 137 trampoline_32bit = (unsigned long *)find_trampoline_placement(); 138 139 /* Preserve trampoline memory */ 140 memcpy(trampoline_save, trampoline_32bit, TRAMPOLINE_32BIT_SIZE); 141 142 /* Clear trampoline memory first */ 143 memset(trampoline_32bit, 0, TRAMPOLINE_32BIT_SIZE); 144 145 /* Copy trampoline code in place */ 146 toggle_la57 = memcpy(trampoline_32bit + 147 TRAMPOLINE_32BIT_CODE_OFFSET / sizeof(unsigned long), 148 &trampoline_32bit_src, TRAMPOLINE_32BIT_CODE_SIZE); 149 150 /* 151 * Avoid the need for a stack in the 32-bit trampoline code, by using 152 * LJMP rather than LRET to return back to long mode. LJMP takes an 153 * immediate absolute address, which needs to be adjusted based on the 154 * placement of the trampoline. 155 */ 156 *(u32 *)((u8 *)toggle_la57 + trampoline_ljmp_imm_offset) += 157 (unsigned long)toggle_la57; 158 159 /* 160 * The code below prepares page table in trampoline memory. 161 * 162 * The new page table will be used by trampoline code for switching 163 * from 4- to 5-level paging or vice versa. 164 */ 165 166 if (l5_required) { 167 /* 168 * For 4- to 5-level paging transition, set up current CR3 as 169 * the first and the only entry in a new top-level page table. 170 */ 171 *trampoline_32bit = __native_read_cr3() | _PAGE_TABLE_NOENC; 172 } else { 173 unsigned long src; 174 175 /* 176 * For 5- to 4-level paging transition, copy page table pointed 177 * by first entry in the current top-level page table as our 178 * new top-level page table. 179 * 180 * We cannot just point to the page table from trampoline as it 181 * may be above 4G. 182 */ 183 src = *(unsigned long *)__native_read_cr3() & PAGE_MASK; 184 memcpy(trampoline_32bit, (void *)src, PAGE_SIZE); 185 } 186 187 toggle_la57(trampoline_32bit); 188 189 /* 190 * Move the top level page table out of trampoline memory. 191 */ 192 memcpy(pgtable, trampoline_32bit, PAGE_SIZE); 193 native_write_cr3((unsigned long)pgtable); 194 195 /* Restore trampoline memory */ 196 memcpy(trampoline_32bit, trampoline_save, TRAMPOLINE_32BIT_SIZE); 197 } 198