1 // SPDX-License-Identifier: GPL-2.0 2 #include "misc.h" 3 #include <asm/bootparam.h> 4 #include <asm/bootparam_utils.h> 5 #include <asm/e820/types.h> 6 #include <asm/processor.h> 7 #include "pgtable.h" 8 #include "../string.h" 9 #include "efi.h" 10 11 #define BIOS_START_MIN 0x20000U /* 128K, less than this is insane */ 12 #define BIOS_START_MAX 0x9f000U /* 640K, absolute maximum */ 13 14 #ifdef CONFIG_X86_5LEVEL 15 /* __pgtable_l5_enabled needs to be in .data to avoid being cleared along with .bss */ 16 unsigned int __section(".data") __pgtable_l5_enabled; 17 unsigned int __section(".data") pgdir_shift = 39; 18 unsigned int __section(".data") ptrs_per_p4d = 1; 19 #endif 20 21 /* Buffer to preserve trampoline memory */ 22 static char trampoline_save[TRAMPOLINE_32BIT_SIZE]; 23 24 /* 25 * Trampoline address will be printed by extract_kernel() for debugging 26 * purposes. 27 * 28 * Avoid putting the pointer into .bss as it will be cleared between 29 * configure_5level_paging() and extract_kernel(). 30 */ 31 unsigned long *trampoline_32bit __section(".data"); 32 33 int cmdline_find_option_bool(const char *option); 34 35 static unsigned long find_trampoline_placement(void) 36 { 37 unsigned long bios_start = 0, ebda_start = 0; 38 struct boot_e820_entry *entry; 39 char *signature; 40 int i; 41 42 /* 43 * Find a suitable spot for the trampoline. 44 * This code is based on reserve_bios_regions(). 45 */ 46 47 /* 48 * EFI systems may not provide legacy ROM. The memory may not be mapped 49 * at all. 50 * 51 * Only look for values in the legacy ROM for non-EFI system. 52 */ 53 signature = (char *)&boot_params_ptr->efi_info.efi_loader_signature; 54 if (strncmp(signature, EFI32_LOADER_SIGNATURE, 4) && 55 strncmp(signature, EFI64_LOADER_SIGNATURE, 4)) { 56 ebda_start = *(unsigned short *)0x40e << 4; 57 bios_start = *(unsigned short *)0x413 << 10; 58 } 59 60 if (bios_start < BIOS_START_MIN || bios_start > BIOS_START_MAX) 61 bios_start = BIOS_START_MAX; 62 63 if (ebda_start > BIOS_START_MIN && ebda_start < bios_start) 64 bios_start = ebda_start; 65 66 bios_start = round_down(bios_start, PAGE_SIZE); 67 68 /* Find the first usable memory region under bios_start. */ 69 for (i = boot_params_ptr->e820_entries - 1; i >= 0; i--) { 70 unsigned long new = bios_start; 71 72 entry = &boot_params_ptr->e820_table[i]; 73 74 /* Skip all entries above bios_start. */ 75 if (bios_start <= entry->addr) 76 continue; 77 78 /* Skip non-RAM entries. */ 79 if (entry->type != E820_TYPE_RAM) 80 continue; 81 82 /* Adjust bios_start to the end of the entry if needed. */ 83 if (bios_start > entry->addr + entry->size) 84 new = entry->addr + entry->size; 85 86 /* Keep bios_start page-aligned. */ 87 new = round_down(new, PAGE_SIZE); 88 89 /* Skip the entry if it's too small. */ 90 if (new - TRAMPOLINE_32BIT_SIZE < entry->addr) 91 continue; 92 93 /* Protect against underflow. */ 94 if (new - TRAMPOLINE_32BIT_SIZE > bios_start) 95 break; 96 97 bios_start = new; 98 break; 99 } 100 101 /* Place the trampoline just below the end of low memory */ 102 return bios_start - TRAMPOLINE_32BIT_SIZE; 103 } 104 105 asmlinkage void configure_5level_paging(struct boot_params *bp, void *pgtable) 106 { 107 void (*toggle_la57)(void *cr3); 108 bool l5_required = false; 109 110 /* Initialize boot_params. Required for cmdline_find_option_bool(). */ 111 sanitize_boot_params(bp); 112 boot_params_ptr = bp; 113 114 /* 115 * Check if LA57 is desired and supported. 116 * 117 * There are several parts to the check: 118 * - if the kernel supports 5-level paging: CONFIG_X86_5LEVEL=y 119 * - if user asked to disable 5-level paging: no5lvl in cmdline 120 * - if the machine supports 5-level paging: 121 * + CPUID leaf 7 is supported 122 * + the leaf has the feature bit set 123 * 124 * That's substitute for boot_cpu_has() in early boot code. 125 */ 126 if (IS_ENABLED(CONFIG_X86_5LEVEL) && 127 !cmdline_find_option_bool("no5lvl") && 128 native_cpuid_eax(0) >= 7 && 129 (native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) { 130 l5_required = true; 131 132 /* Initialize variables for 5-level paging */ 133 __pgtable_l5_enabled = 1; 134 pgdir_shift = 48; 135 ptrs_per_p4d = 512; 136 } 137 138 /* 139 * The trampoline will not be used if the paging mode is already set to 140 * the desired one. 141 */ 142 if (l5_required == !!(native_read_cr4() & X86_CR4_LA57)) 143 return; 144 145 trampoline_32bit = (unsigned long *)find_trampoline_placement(); 146 147 /* Preserve trampoline memory */ 148 memcpy(trampoline_save, trampoline_32bit, TRAMPOLINE_32BIT_SIZE); 149 150 /* Clear trampoline memory first */ 151 memset(trampoline_32bit, 0, TRAMPOLINE_32BIT_SIZE); 152 153 /* Copy trampoline code in place */ 154 toggle_la57 = memcpy(trampoline_32bit + 155 TRAMPOLINE_32BIT_CODE_OFFSET / sizeof(unsigned long), 156 &trampoline_32bit_src, TRAMPOLINE_32BIT_CODE_SIZE); 157 158 /* 159 * Avoid the need for a stack in the 32-bit trampoline code, by using 160 * LJMP rather than LRET to return back to long mode. LJMP takes an 161 * immediate absolute address, which needs to be adjusted based on the 162 * placement of the trampoline. 163 */ 164 *(u32 *)((u8 *)toggle_la57 + trampoline_ljmp_imm_offset) += 165 (unsigned long)toggle_la57; 166 167 /* 168 * The code below prepares page table in trampoline memory. 169 * 170 * The new page table will be used by trampoline code for switching 171 * from 4- to 5-level paging or vice versa. 172 */ 173 174 if (l5_required) { 175 /* 176 * For 4- to 5-level paging transition, set up current CR3 as 177 * the first and the only entry in a new top-level page table. 178 */ 179 *trampoline_32bit = __native_read_cr3() | _PAGE_TABLE_NOENC; 180 } else { 181 unsigned long src; 182 183 /* 184 * For 5- to 4-level paging transition, copy page table pointed 185 * by first entry in the current top-level page table as our 186 * new top-level page table. 187 * 188 * We cannot just point to the page table from trampoline as it 189 * may be above 4G. 190 */ 191 src = *(unsigned long *)__native_read_cr3() & PAGE_MASK; 192 memcpy(trampoline_32bit, (void *)src, PAGE_SIZE); 193 } 194 195 toggle_la57(trampoline_32bit); 196 197 /* 198 * Move the top level page table out of trampoline memory. 199 */ 200 memcpy(pgtable, trampoline_32bit, PAGE_SIZE); 201 native_write_cr3((unsigned long)pgtable); 202 203 /* Restore trampoline memory */ 204 memcpy(trampoline_32bit, trampoline_save, TRAMPOLINE_32BIT_SIZE); 205 } 206