1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/boot/head.S 4 * 5 * Copyright (C) 1991, 1992, 1993 Linus Torvalds 6 */ 7 8/* 9 * head.S contains the 32-bit startup code. 10 * 11 * NOTE!!! Startup happens at absolute address 0x00001000, which is also where 12 * the page directory will exist. The startup code will be overwritten by 13 * the page directory. [According to comments etc elsewhere on a compressed 14 * kernel it will end up at 0x1000 + 1Mb I hope so as I assume this. - AC] 15 * 16 * Page 0 is deliberately kept safe, since System Management Mode code in 17 * laptops may need to access the BIOS data stored there. This is also 18 * useful for future device drivers that either access the BIOS via VM86 19 * mode. 20 */ 21 22/* 23 * High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996 24 */ 25 .code32 26 .text 27 28#include <linux/init.h> 29#include <linux/linkage.h> 30#include <asm/segment.h> 31#include <asm/boot.h> 32#include <asm/msr.h> 33#include <asm/processor-flags.h> 34#include <asm/asm-offsets.h> 35#include <asm/bootparam.h> 36#include <asm/desc_defs.h> 37#include <asm/trapnr.h> 38 39/* 40 * Fix alignment at 16 bytes. Following CONFIG_FUNCTION_ALIGNMENT will result 41 * in assembly errors due to trying to move .org backward due to the excessive 42 * alignment. 43 */ 44#undef __ALIGN 45#define __ALIGN .balign 16, 0x90 46 47/* 48 * Locally defined symbols should be marked hidden: 49 */ 50 .hidden _bss 51 .hidden _ebss 52 .hidden _end 53 54 __HEAD 55 56/* 57 * This macro gives the relative virtual address of X, i.e. the offset of X 58 * from startup_32. This is the same as the link-time virtual address of X, 59 * since startup_32 is at 0, but defining it this way tells the 60 * assembler/linker that we do not want the actual run-time address of X. This 61 * prevents the linker from trying to create unwanted run-time relocation 62 * entries for the reference when the compressed kernel is linked as PIE. 63 * 64 * A reference X(%reg) will result in the link-time VA of X being stored with 65 * the instruction, and a run-time R_X86_64_RELATIVE relocation entry that 66 * adds the 64-bit base address where the kernel is loaded. 67 * 68 * Replacing it with (X-startup_32)(%reg) results in the offset being stored, 69 * and no run-time relocation. 70 * 71 * The macro should be used as a displacement with a base register containing 72 * the run-time address of startup_32 [i.e. rva(X)(%reg)], or as an immediate 73 * [$ rva(X)]. 74 * 75 * This macro can only be used from within the .head.text section, since the 76 * expression requires startup_32 to be in the same section as the code being 77 * assembled. 78 */ 79#define rva(X) ((X) - startup_32) 80 81 .code32 82SYM_FUNC_START(startup_32) 83 /* 84 * 32bit entry is 0 and it is ABI so immutable! 85 * If we come here directly from a bootloader, 86 * kernel(text+data+bss+brk) ramdisk, zero_page, command line 87 * all need to be under the 4G limit. 88 */ 89 cld 90 cli 91 92/* 93 * Calculate the delta between where we were compiled to run 94 * at and where we were actually loaded at. This can only be done 95 * with a short local call on x86. Nothing else will tell us what 96 * address we are running at. The reserved chunk of the real-mode 97 * data at 0x1e4 (defined as a scratch field) are used as the stack 98 * for this calculation. Only 4 bytes are needed. 99 */ 100 leal (BP_scratch+4)(%esi), %esp 101 call 1f 1021: popl %ebp 103 subl $ rva(1b), %ebp 104 105 /* Load new GDT with the 64bit segments using 32bit descriptor */ 106 leal rva(gdt)(%ebp), %eax 107 movl %eax, 2(%eax) 108 lgdt (%eax) 109 110 /* Load segment registers with our descriptors */ 111 movl $__BOOT_DS, %eax 112 movl %eax, %ds 113 movl %eax, %es 114 movl %eax, %fs 115 movl %eax, %gs 116 movl %eax, %ss 117 118 /* Setup a stack and load CS from current GDT */ 119 leal rva(boot_stack_end)(%ebp), %esp 120 121 pushl $__KERNEL32_CS 122 leal rva(1f)(%ebp), %eax 123 pushl %eax 124 lretl 1251: 126 127 /* Setup Exception handling for SEV-ES */ 128#ifdef CONFIG_AMD_MEM_ENCRYPT 129 call startup32_load_idt 130#endif 131 132 /* Make sure cpu supports long mode. */ 133 call verify_cpu 134 testl %eax, %eax 135 jnz .Lno_longmode 136 137/* 138 * Compute the delta between where we were compiled to run at 139 * and where the code will actually run at. 140 * 141 * %ebp contains the address we are loaded at by the boot loader and %ebx 142 * contains the address where we should move the kernel image temporarily 143 * for safe in-place decompression. 144 */ 145 146#ifdef CONFIG_RELOCATABLE 147 movl %ebp, %ebx 148 movl BP_kernel_alignment(%esi), %eax 149 decl %eax 150 addl %eax, %ebx 151 notl %eax 152 andl %eax, %ebx 153 cmpl $LOAD_PHYSICAL_ADDR, %ebx 154 jae 1f 155#endif 156 movl $LOAD_PHYSICAL_ADDR, %ebx 1571: 158 159 /* Target address to relocate to for decompression */ 160 addl BP_init_size(%esi), %ebx 161 subl $ rva(_end), %ebx 162 163/* 164 * Prepare for entering 64 bit mode 165 */ 166 167 /* Enable PAE mode */ 168 movl %cr4, %eax 169 orl $X86_CR4_PAE, %eax 170 movl %eax, %cr4 171 172 /* 173 * Build early 4G boot pagetable 174 */ 175 xorl %edx, %edx 176#ifdef CONFIG_AMD_MEM_ENCRYPT 177 call get_sev_encryption_bit 178 xorl %edx, %edx 179 testl %eax, %eax 180 jz 1f 181 182 /* Encryption bit is always above bit 31 */ 183 subl $32, %eax 184 185 /* 186 * If SEV is active then set the encryption mask in the page tables. 187 * This will ensure that when the kernel is copied and decompressed it 188 * will be done so encrypted. 189 */ 190 bts %eax, %edx 191 192 /* 193 * Set MSR_AMD64_SEV_ENABLED_BIT in sev_status so that 194 * startup32_check_sev_cbit() will do a check. sev_enable() will 195 * initialize sev_status with all the bits reported by 196 * MSR_AMD_SEV_STATUS later, but only MSR_AMD64_SEV_ENABLED_BIT 197 * needs to be set for now. 198 */ 199 movl $1, rva(sev_status)(%ebp) 2001: 201#endif 202 203 /* Initialize Page tables to 0 */ 204 leal rva(pgtable)(%ebx), %edi 205 xorl %eax, %eax 206 movl $(BOOT_INIT_PGT_SIZE/4), %ecx 207 rep stosl 208 209 /* Build Level 4 */ 210 leal rva(pgtable + 0)(%ebx), %edi 211 leal 0x1007 (%edi), %eax 212 movl %eax, 0(%edi) 213 addl %edx, 4(%edi) 214 215 /* Build Level 3 */ 216 leal rva(pgtable + 0x1000)(%ebx), %edi 217 leal 0x1007(%edi), %eax 218 movl $4, %ecx 2191: movl %eax, 0x00(%edi) 220 addl %edx, 0x04(%edi) 221 addl $0x00001000, %eax 222 addl $8, %edi 223 decl %ecx 224 jnz 1b 225 226 /* Build Level 2 */ 227 leal rva(pgtable + 0x2000)(%ebx), %edi 228 movl $0x00000183, %eax 229 movl $2048, %ecx 2301: movl %eax, 0(%edi) 231 addl %edx, 4(%edi) 232 addl $0x00200000, %eax 233 addl $8, %edi 234 decl %ecx 235 jnz 1b 236 237 /* Enable the boot page tables */ 238 leal rva(pgtable)(%ebx), %eax 239 movl %eax, %cr3 240 241 /* Enable Long mode in EFER (Extended Feature Enable Register) */ 242 movl $MSR_EFER, %ecx 243 rdmsr 244 btsl $_EFER_LME, %eax 245 wrmsr 246 247 /* After gdt is loaded */ 248 xorl %eax, %eax 249 lldt %ax 250 movl $__BOOT_TSS, %eax 251 ltr %ax 252 253#ifdef CONFIG_AMD_MEM_ENCRYPT 254 /* Check if the C-bit position is correct when SEV is active */ 255 call startup32_check_sev_cbit 256#endif 257 258 /* 259 * Setup for the jump to 64bit mode 260 * 261 * When the jump is performed we will be in long mode but 262 * in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1 263 * (and in turn EFER.LMA = 1). To jump into 64bit mode we use 264 * the new gdt/idt that has __KERNEL_CS with CS.L = 1. 265 * We place all of the values on our mini stack so lret can 266 * used to perform that far jump. 267 */ 268 leal rva(startup_64)(%ebp), %eax 269 pushl $__KERNEL_CS 270 pushl %eax 271 272 /* Enter paged protected Mode, activating Long Mode */ 273 movl $CR0_STATE, %eax 274 movl %eax, %cr0 275 276 /* Jump from 32bit compatibility mode into 64bit mode. */ 277 lret 278SYM_FUNC_END(startup_32) 279 280 .code64 281 .org 0x200 282SYM_CODE_START(startup_64) 283 /* 284 * 64bit entry is 0x200 and it is ABI so immutable! 285 * We come here either from startup_32 or directly from a 286 * 64bit bootloader. 287 * If we come here from a bootloader, kernel(text+data+bss+brk), 288 * ramdisk, zero_page, command line could be above 4G. 289 * We depend on an identity mapped page table being provided 290 * that maps our entire kernel(text+data+bss+brk), zero page 291 * and command line. 292 */ 293 294 cld 295 cli 296 297 /* Setup data segments. */ 298 xorl %eax, %eax 299 movl %eax, %ds 300 movl %eax, %es 301 movl %eax, %ss 302 movl %eax, %fs 303 movl %eax, %gs 304 305 /* 306 * Compute the decompressed kernel start address. It is where 307 * we were loaded at aligned to a 2M boundary. %rbp contains the 308 * decompressed kernel start address. 309 * 310 * If it is a relocatable kernel then decompress and run the kernel 311 * from load address aligned to 2MB addr, otherwise decompress and 312 * run the kernel from LOAD_PHYSICAL_ADDR 313 * 314 * We cannot rely on the calculation done in 32-bit mode, since we 315 * may have been invoked via the 64-bit entry point. 316 */ 317 318 /* Start with the delta to where the kernel will run at. */ 319#ifdef CONFIG_RELOCATABLE 320 leaq startup_32(%rip) /* - $startup_32 */, %rbp 321 movl BP_kernel_alignment(%rsi), %eax 322 decl %eax 323 addq %rax, %rbp 324 notq %rax 325 andq %rax, %rbp 326 cmpq $LOAD_PHYSICAL_ADDR, %rbp 327 jae 1f 328#endif 329 movq $LOAD_PHYSICAL_ADDR, %rbp 3301: 331 332 /* Target address to relocate to for decompression */ 333 movl BP_init_size(%rsi), %ebx 334 subl $ rva(_end), %ebx 335 addq %rbp, %rbx 336 337 /* Set up the stack */ 338 leaq rva(boot_stack_end)(%rbx), %rsp 339 340 /* 341 * At this point we are in long mode with 4-level paging enabled, 342 * but we might want to enable 5-level paging or vice versa. 343 * 344 * The problem is that we cannot do it directly. Setting or clearing 345 * CR4.LA57 in long mode would trigger #GP. So we need to switch off 346 * long mode and paging first. 347 * 348 * We also need a trampoline in lower memory to switch over from 349 * 4- to 5-level paging for cases when the bootloader puts the kernel 350 * above 4G, but didn't enable 5-level paging for us. 351 * 352 * The same trampoline can be used to switch from 5- to 4-level paging 353 * mode, like when starting 4-level paging kernel via kexec() when 354 * original kernel worked in 5-level paging mode. 355 * 356 * For the trampoline, we need the top page table to reside in lower 357 * memory as we don't have a way to load 64-bit values into CR3 in 358 * 32-bit mode. 359 */ 360 361 /* Make sure we have GDT with 32-bit code segment */ 362 leaq gdt64(%rip), %rax 363 addq %rax, 2(%rax) 364 lgdt (%rax) 365 366 /* Reload CS so IRET returns to a CS actually in the GDT */ 367 pushq $__KERNEL_CS 368 leaq .Lon_kernel_cs(%rip), %rax 369 pushq %rax 370 lretq 371 372.Lon_kernel_cs: 373 /* 374 * RSI holds a pointer to a boot_params structure provided by the 375 * loader, and this needs to be preserved across C function calls. So 376 * move it into a callee saved register. 377 */ 378 movq %rsi, %r15 379 380 call load_stage1_idt 381 382#ifdef CONFIG_AMD_MEM_ENCRYPT 383 /* 384 * Now that the stage1 interrupt handlers are set up, #VC exceptions from 385 * CPUID instructions can be properly handled for SEV-ES guests. 386 * 387 * For SEV-SNP, the CPUID table also needs to be set up in advance of any 388 * CPUID instructions being issued, so go ahead and do that now via 389 * sev_enable(), which will also handle the rest of the SEV-related 390 * detection/setup to ensure that has been done in advance of any dependent 391 * code. Pass the boot_params pointer as the first argument. 392 */ 393 movq %r15, %rdi 394 call sev_enable 395#endif 396 397 /* Preserve only the CR4 bits that must be preserved, and clear the rest */ 398 movq %cr4, %rax 399 andl $(X86_CR4_PAE | X86_CR4_MCE | X86_CR4_LA57), %eax 400 movq %rax, %cr4 401 402 /* 403 * configure_5level_paging() updates the number of paging levels using 404 * a trampoline in 32-bit addressable memory if the current number does 405 * not match the desired number. 406 * 407 * Pass the boot_params pointer as the first argument. The second 408 * argument is the relocated address of the page table to use instead 409 * of the page table in trampoline memory (if required). 410 */ 411 movq %r15, %rdi 412 leaq rva(top_pgtable)(%rbx), %rsi 413 call configure_5level_paging 414 415 /* Zero EFLAGS */ 416 pushq $0 417 popfq 418 419/* 420 * Copy the compressed kernel to the end of our buffer 421 * where decompression in place becomes safe. 422 */ 423 leaq (_bss-8)(%rip), %rsi 424 leaq rva(_bss-8)(%rbx), %rdi 425 movl $(_bss - startup_32), %ecx 426 shrl $3, %ecx 427 std 428 rep movsq 429 cld 430 431 /* 432 * The GDT may get overwritten either during the copy we just did or 433 * during extract_kernel below. To avoid any issues, repoint the GDTR 434 * to the new copy of the GDT. 435 */ 436 leaq rva(gdt64)(%rbx), %rax 437 leaq rva(gdt)(%rbx), %rdx 438 movq %rdx, 2(%rax) 439 lgdt (%rax) 440 441/* 442 * Jump to the relocated address. 443 */ 444 leaq rva(.Lrelocated)(%rbx), %rax 445 jmp *%rax 446SYM_CODE_END(startup_64) 447 448 .text 449SYM_FUNC_START_LOCAL_NOALIGN(.Lrelocated) 450 451/* 452 * Clear BSS (stack is currently empty) 453 */ 454 xorl %eax, %eax 455 leaq _bss(%rip), %rdi 456 leaq _ebss(%rip), %rcx 457 subq %rdi, %rcx 458 shrq $3, %rcx 459 rep stosq 460 461 call load_stage2_idt 462 463 /* Pass boot_params to initialize_identity_maps() */ 464 movq %r15, %rdi 465 call initialize_identity_maps 466 467/* 468 * Do the extraction, and jump to the new kernel.. 469 */ 470 /* pass struct boot_params pointer and output target address */ 471 movq %r15, %rdi 472 movq %rbp, %rsi 473 call extract_kernel /* returns kernel entry point in %rax */ 474 475/* 476 * Jump to the decompressed kernel. 477 */ 478 movq %r15, %rsi 479 jmp *%rax 480SYM_FUNC_END(.Lrelocated) 481 482 .code32 483SYM_FUNC_START_LOCAL_NOALIGN(.Lno_longmode) 484 /* This isn't an x86-64 CPU, so hang intentionally, we cannot continue */ 4851: 486 hlt 487 jmp 1b 488SYM_FUNC_END(.Lno_longmode) 489 490 .globl verify_cpu 491#include "../../kernel/verify_cpu.S" 492 493 .data 494SYM_DATA_START_LOCAL(gdt64) 495 .word gdt_end - gdt - 1 496 .quad gdt - gdt64 497SYM_DATA_END(gdt64) 498 .balign 8 499SYM_DATA_START_LOCAL(gdt) 500 .word gdt_end - gdt - 1 501 .long 0 502 .word 0 503 .quad 0x00cf9a000000ffff /* __KERNEL32_CS */ 504 .quad 0x00af9a000000ffff /* __KERNEL_CS */ 505 .quad 0x00cf92000000ffff /* __KERNEL_DS */ 506 .quad 0x0080890000000000 /* TS descriptor */ 507 .quad 0x0000000000000000 /* TS continued */ 508SYM_DATA_END_LABEL(gdt, SYM_L_LOCAL, gdt_end) 509 510SYM_DATA_START(boot_idt_desc) 511 .word boot_idt_end - boot_idt - 1 512 .quad 0 513SYM_DATA_END(boot_idt_desc) 514 .balign 8 515SYM_DATA_START(boot_idt) 516 .rept BOOT_IDT_ENTRIES 517 .quad 0 518 .quad 0 519 .endr 520SYM_DATA_END_LABEL(boot_idt, SYM_L_GLOBAL, boot_idt_end) 521 522/* 523 * Stack and heap for uncompression 524 */ 525 .bss 526 .balign 4 527SYM_DATA_START_LOCAL(boot_stack) 528 .fill BOOT_STACK_SIZE, 1, 0 529 .balign 16 530SYM_DATA_END_LABEL(boot_stack, SYM_L_LOCAL, boot_stack_end) 531 532/* 533 * Space for page tables (not in .bss so not zeroed) 534 */ 535 .section ".pgtable","aw",@nobits 536 .balign 4096 537SYM_DATA_LOCAL(pgtable, .fill BOOT_PGT_SIZE, 1, 0) 538 539/* 540 * The page table is going to be used instead of page table in the trampoline 541 * memory. 542 */ 543SYM_DATA_LOCAL(top_pgtable, .fill PAGE_SIZE, 1, 0) 544