1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 Intel Corporation 4 * Author: Johannes Berg <johannes@sipsolutions.net> 5 */ 6 #include <linux/module.h> 7 #include <linux/pci.h> 8 #include <linux/virtio.h> 9 #include <linux/virtio_config.h> 10 #include <linux/logic_iomem.h> 11 #include <linux/of_platform.h> 12 #include <linux/irqdomain.h> 13 #include <linux/virtio_pcidev.h> 14 #include <linux/virtio-uml.h> 15 #include <linux/delay.h> 16 #include <linux/msi.h> 17 #include <asm/unaligned.h> 18 #include <irq_kern.h> 19 20 #define MAX_DEVICES 8 21 #define MAX_MSI_VECTORS 32 22 #define CFG_SPACE_SIZE 4096 23 24 /* for MSI-X we have a 32-bit payload */ 25 #define MAX_IRQ_MSG_SIZE (sizeof(struct virtio_pcidev_msg) + sizeof(u32)) 26 #define NUM_IRQ_MSGS 10 27 28 #define HANDLE_NO_FREE(ptr) ((void *)((unsigned long)(ptr) | 1)) 29 #define HANDLE_IS_NO_FREE(ptr) ((unsigned long)(ptr) & 1) 30 31 struct um_pci_device { 32 struct virtio_device *vdev; 33 34 /* for now just standard BARs */ 35 u8 resptr[PCI_STD_NUM_BARS]; 36 37 struct virtqueue *cmd_vq, *irq_vq; 38 39 #define UM_PCI_STAT_WAITING 0 40 unsigned long status; 41 42 int irq; 43 44 bool platform; 45 }; 46 47 struct um_pci_device_reg { 48 struct um_pci_device *dev; 49 void __iomem *iomem; 50 }; 51 52 static struct pci_host_bridge *bridge; 53 static DEFINE_MUTEX(um_pci_mtx); 54 static struct um_pci_device *um_pci_platform_device; 55 static struct um_pci_device_reg um_pci_devices[MAX_DEVICES]; 56 static struct fwnode_handle *um_pci_fwnode; 57 static struct irq_domain *um_pci_inner_domain; 58 static struct irq_domain *um_pci_msi_domain; 59 static unsigned long um_pci_msi_used[BITS_TO_LONGS(MAX_MSI_VECTORS)]; 60 61 static unsigned int um_pci_max_delay_us = 40000; 62 module_param_named(max_delay_us, um_pci_max_delay_us, uint, 0644); 63 64 struct um_pci_message_buffer { 65 struct virtio_pcidev_msg hdr; 66 u8 data[8]; 67 }; 68 69 static struct um_pci_message_buffer __percpu *um_pci_msg_bufs; 70 71 static int um_pci_send_cmd(struct um_pci_device *dev, 72 struct virtio_pcidev_msg *cmd, 73 unsigned int cmd_size, 74 const void *extra, unsigned int extra_size, 75 void *out, unsigned int out_size) 76 { 77 struct scatterlist out_sg, extra_sg, in_sg; 78 struct scatterlist *sgs_list[] = { 79 [0] = &out_sg, 80 [1] = extra ? &extra_sg : &in_sg, 81 [2] = extra ? &in_sg : NULL, 82 }; 83 struct um_pci_message_buffer *buf; 84 int delay_count = 0; 85 int ret, len; 86 bool posted; 87 88 if (WARN_ON(cmd_size < sizeof(*cmd) || cmd_size > sizeof(*buf))) 89 return -EINVAL; 90 91 switch (cmd->op) { 92 case VIRTIO_PCIDEV_OP_CFG_WRITE: 93 case VIRTIO_PCIDEV_OP_MMIO_WRITE: 94 case VIRTIO_PCIDEV_OP_MMIO_MEMSET: 95 /* in PCI, writes are posted, so don't wait */ 96 posted = !out; 97 WARN_ON(!posted); 98 break; 99 default: 100 posted = false; 101 break; 102 } 103 104 buf = get_cpu_var(um_pci_msg_bufs); 105 if (buf) 106 memcpy(buf, cmd, cmd_size); 107 108 if (posted) { 109 u8 *ncmd = kmalloc(cmd_size + extra_size, GFP_ATOMIC); 110 111 if (ncmd) { 112 memcpy(ncmd, cmd, cmd_size); 113 if (extra) 114 memcpy(ncmd + cmd_size, extra, extra_size); 115 cmd = (void *)ncmd; 116 cmd_size += extra_size; 117 extra = NULL; 118 extra_size = 0; 119 } else { 120 /* try without allocating memory */ 121 posted = false; 122 cmd = (void *)buf; 123 } 124 } else { 125 cmd = (void *)buf; 126 } 127 128 sg_init_one(&out_sg, cmd, cmd_size); 129 if (extra) 130 sg_init_one(&extra_sg, extra, extra_size); 131 if (out) 132 sg_init_one(&in_sg, out, out_size); 133 134 /* add to internal virtio queue */ 135 ret = virtqueue_add_sgs(dev->cmd_vq, sgs_list, 136 extra ? 2 : 1, 137 out ? 1 : 0, 138 posted ? cmd : HANDLE_NO_FREE(cmd), 139 GFP_ATOMIC); 140 if (ret) { 141 if (posted) 142 kfree(cmd); 143 goto out; 144 } 145 146 if (posted) { 147 virtqueue_kick(dev->cmd_vq); 148 ret = 0; 149 goto out; 150 } 151 152 /* kick and poll for getting a response on the queue */ 153 set_bit(UM_PCI_STAT_WAITING, &dev->status); 154 virtqueue_kick(dev->cmd_vq); 155 156 while (1) { 157 void *completed = virtqueue_get_buf(dev->cmd_vq, &len); 158 159 if (completed == HANDLE_NO_FREE(cmd)) 160 break; 161 162 if (completed && !HANDLE_IS_NO_FREE(completed)) 163 kfree(completed); 164 165 if (WARN_ONCE(virtqueue_is_broken(dev->cmd_vq) || 166 ++delay_count > um_pci_max_delay_us, 167 "um virt-pci delay: %d", delay_count)) { 168 ret = -EIO; 169 break; 170 } 171 udelay(1); 172 } 173 clear_bit(UM_PCI_STAT_WAITING, &dev->status); 174 175 out: 176 put_cpu_var(um_pci_msg_bufs); 177 return ret; 178 } 179 180 static unsigned long um_pci_cfgspace_read(void *priv, unsigned int offset, 181 int size) 182 { 183 struct um_pci_device_reg *reg = priv; 184 struct um_pci_device *dev = reg->dev; 185 struct virtio_pcidev_msg hdr = { 186 .op = VIRTIO_PCIDEV_OP_CFG_READ, 187 .size = size, 188 .addr = offset, 189 }; 190 /* buf->data is maximum size - we may only use parts of it */ 191 struct um_pci_message_buffer *buf; 192 u8 *data; 193 unsigned long ret = ULONG_MAX; 194 size_t bytes = sizeof(buf->data); 195 196 if (!dev) 197 return ULONG_MAX; 198 199 buf = get_cpu_var(um_pci_msg_bufs); 200 data = buf->data; 201 202 if (buf) 203 memset(data, 0xff, bytes); 204 205 switch (size) { 206 case 1: 207 case 2: 208 case 4: 209 #ifdef CONFIG_64BIT 210 case 8: 211 #endif 212 break; 213 default: 214 WARN(1, "invalid config space read size %d\n", size); 215 goto out; 216 } 217 218 if (um_pci_send_cmd(dev, &hdr, sizeof(hdr), NULL, 0, data, bytes)) 219 goto out; 220 221 switch (size) { 222 case 1: 223 ret = data[0]; 224 break; 225 case 2: 226 ret = le16_to_cpup((void *)data); 227 break; 228 case 4: 229 ret = le32_to_cpup((void *)data); 230 break; 231 #ifdef CONFIG_64BIT 232 case 8: 233 ret = le64_to_cpup((void *)data); 234 break; 235 #endif 236 default: 237 break; 238 } 239 240 out: 241 put_cpu_var(um_pci_msg_bufs); 242 return ret; 243 } 244 245 static void um_pci_cfgspace_write(void *priv, unsigned int offset, int size, 246 unsigned long val) 247 { 248 struct um_pci_device_reg *reg = priv; 249 struct um_pci_device *dev = reg->dev; 250 struct { 251 struct virtio_pcidev_msg hdr; 252 /* maximum size - we may only use parts of it */ 253 u8 data[8]; 254 } msg = { 255 .hdr = { 256 .op = VIRTIO_PCIDEV_OP_CFG_WRITE, 257 .size = size, 258 .addr = offset, 259 }, 260 }; 261 262 if (!dev) 263 return; 264 265 switch (size) { 266 case 1: 267 msg.data[0] = (u8)val; 268 break; 269 case 2: 270 put_unaligned_le16(val, (void *)msg.data); 271 break; 272 case 4: 273 put_unaligned_le32(val, (void *)msg.data); 274 break; 275 #ifdef CONFIG_64BIT 276 case 8: 277 put_unaligned_le64(val, (void *)msg.data); 278 break; 279 #endif 280 default: 281 WARN(1, "invalid config space write size %d\n", size); 282 return; 283 } 284 285 WARN_ON(um_pci_send_cmd(dev, &msg.hdr, sizeof(msg), NULL, 0, NULL, 0)); 286 } 287 288 static const struct logic_iomem_ops um_pci_device_cfgspace_ops = { 289 .read = um_pci_cfgspace_read, 290 .write = um_pci_cfgspace_write, 291 }; 292 293 static void um_pci_bar_copy_from(void *priv, void *buffer, 294 unsigned int offset, int size) 295 { 296 u8 *resptr = priv; 297 struct um_pci_device *dev = container_of(resptr - *resptr, 298 struct um_pci_device, 299 resptr[0]); 300 struct virtio_pcidev_msg hdr = { 301 .op = VIRTIO_PCIDEV_OP_MMIO_READ, 302 .bar = *resptr, 303 .size = size, 304 .addr = offset, 305 }; 306 307 memset(buffer, 0xff, size); 308 309 um_pci_send_cmd(dev, &hdr, sizeof(hdr), NULL, 0, buffer, size); 310 } 311 312 static unsigned long um_pci_bar_read(void *priv, unsigned int offset, 313 int size) 314 { 315 /* buf->data is maximum size - we may only use parts of it */ 316 struct um_pci_message_buffer *buf; 317 u8 *data; 318 unsigned long ret = ULONG_MAX; 319 320 buf = get_cpu_var(um_pci_msg_bufs); 321 data = buf->data; 322 323 switch (size) { 324 case 1: 325 case 2: 326 case 4: 327 #ifdef CONFIG_64BIT 328 case 8: 329 #endif 330 break; 331 default: 332 WARN(1, "invalid config space read size %d\n", size); 333 goto out; 334 } 335 336 um_pci_bar_copy_from(priv, data, offset, size); 337 338 switch (size) { 339 case 1: 340 ret = data[0]; 341 break; 342 case 2: 343 ret = le16_to_cpup((void *)data); 344 break; 345 case 4: 346 ret = le32_to_cpup((void *)data); 347 break; 348 #ifdef CONFIG_64BIT 349 case 8: 350 ret = le64_to_cpup((void *)data); 351 break; 352 #endif 353 default: 354 break; 355 } 356 357 out: 358 put_cpu_var(um_pci_msg_bufs); 359 return ret; 360 } 361 362 static void um_pci_bar_copy_to(void *priv, unsigned int offset, 363 const void *buffer, int size) 364 { 365 u8 *resptr = priv; 366 struct um_pci_device *dev = container_of(resptr - *resptr, 367 struct um_pci_device, 368 resptr[0]); 369 struct virtio_pcidev_msg hdr = { 370 .op = VIRTIO_PCIDEV_OP_MMIO_WRITE, 371 .bar = *resptr, 372 .size = size, 373 .addr = offset, 374 }; 375 376 um_pci_send_cmd(dev, &hdr, sizeof(hdr), buffer, size, NULL, 0); 377 } 378 379 static void um_pci_bar_write(void *priv, unsigned int offset, int size, 380 unsigned long val) 381 { 382 /* maximum size - we may only use parts of it */ 383 u8 data[8]; 384 385 switch (size) { 386 case 1: 387 data[0] = (u8)val; 388 break; 389 case 2: 390 put_unaligned_le16(val, (void *)data); 391 break; 392 case 4: 393 put_unaligned_le32(val, (void *)data); 394 break; 395 #ifdef CONFIG_64BIT 396 case 8: 397 put_unaligned_le64(val, (void *)data); 398 break; 399 #endif 400 default: 401 WARN(1, "invalid config space write size %d\n", size); 402 return; 403 } 404 405 um_pci_bar_copy_to(priv, offset, data, size); 406 } 407 408 static void um_pci_bar_set(void *priv, unsigned int offset, u8 value, int size) 409 { 410 u8 *resptr = priv; 411 struct um_pci_device *dev = container_of(resptr - *resptr, 412 struct um_pci_device, 413 resptr[0]); 414 struct { 415 struct virtio_pcidev_msg hdr; 416 u8 data; 417 } msg = { 418 .hdr = { 419 .op = VIRTIO_PCIDEV_OP_CFG_WRITE, 420 .bar = *resptr, 421 .size = size, 422 .addr = offset, 423 }, 424 .data = value, 425 }; 426 427 um_pci_send_cmd(dev, &msg.hdr, sizeof(msg), NULL, 0, NULL, 0); 428 } 429 430 static const struct logic_iomem_ops um_pci_device_bar_ops = { 431 .read = um_pci_bar_read, 432 .write = um_pci_bar_write, 433 .set = um_pci_bar_set, 434 .copy_from = um_pci_bar_copy_from, 435 .copy_to = um_pci_bar_copy_to, 436 }; 437 438 static void __iomem *um_pci_map_bus(struct pci_bus *bus, unsigned int devfn, 439 int where) 440 { 441 struct um_pci_device_reg *dev; 442 unsigned int busn = bus->number; 443 444 if (busn > 0) 445 return NULL; 446 447 /* not allowing functions for now ... */ 448 if (devfn % 8) 449 return NULL; 450 451 if (devfn / 8 >= ARRAY_SIZE(um_pci_devices)) 452 return NULL; 453 454 dev = &um_pci_devices[devfn / 8]; 455 if (!dev) 456 return NULL; 457 458 return (void __iomem *)((unsigned long)dev->iomem + where); 459 } 460 461 static struct pci_ops um_pci_ops = { 462 .map_bus = um_pci_map_bus, 463 .read = pci_generic_config_read, 464 .write = pci_generic_config_write, 465 }; 466 467 static void um_pci_rescan(void) 468 { 469 pci_lock_rescan_remove(); 470 pci_rescan_bus(bridge->bus); 471 pci_unlock_rescan_remove(); 472 } 473 474 static void um_pci_irq_vq_addbuf(struct virtqueue *vq, void *buf, bool kick) 475 { 476 struct scatterlist sg[1]; 477 478 sg_init_one(sg, buf, MAX_IRQ_MSG_SIZE); 479 if (virtqueue_add_inbuf(vq, sg, 1, buf, GFP_ATOMIC)) 480 kfree(buf); 481 else if (kick) 482 virtqueue_kick(vq); 483 } 484 485 static void um_pci_handle_irq_message(struct virtqueue *vq, 486 struct virtio_pcidev_msg *msg) 487 { 488 struct virtio_device *vdev = vq->vdev; 489 struct um_pci_device *dev = vdev->priv; 490 491 if (!dev->irq) 492 return; 493 494 /* we should properly chain interrupts, but on ARCH=um we don't care */ 495 496 switch (msg->op) { 497 case VIRTIO_PCIDEV_OP_INT: 498 generic_handle_irq(dev->irq); 499 break; 500 case VIRTIO_PCIDEV_OP_MSI: 501 /* our MSI message is just the interrupt number */ 502 if (msg->size == sizeof(u32)) 503 generic_handle_irq(le32_to_cpup((void *)msg->data)); 504 else 505 generic_handle_irq(le16_to_cpup((void *)msg->data)); 506 break; 507 case VIRTIO_PCIDEV_OP_PME: 508 /* nothing to do - we already woke up due to the message */ 509 break; 510 default: 511 dev_err(&vdev->dev, "unexpected virt-pci message %d\n", msg->op); 512 break; 513 } 514 } 515 516 static void um_pci_cmd_vq_cb(struct virtqueue *vq) 517 { 518 struct virtio_device *vdev = vq->vdev; 519 struct um_pci_device *dev = vdev->priv; 520 void *cmd; 521 int len; 522 523 if (test_bit(UM_PCI_STAT_WAITING, &dev->status)) 524 return; 525 526 while ((cmd = virtqueue_get_buf(vq, &len))) { 527 if (WARN_ON(HANDLE_IS_NO_FREE(cmd))) 528 continue; 529 kfree(cmd); 530 } 531 } 532 533 static void um_pci_irq_vq_cb(struct virtqueue *vq) 534 { 535 struct virtio_pcidev_msg *msg; 536 int len; 537 538 while ((msg = virtqueue_get_buf(vq, &len))) { 539 if (len >= sizeof(*msg)) 540 um_pci_handle_irq_message(vq, msg); 541 542 /* recycle the message buffer */ 543 um_pci_irq_vq_addbuf(vq, msg, true); 544 } 545 } 546 547 #ifdef CONFIG_OF 548 /* Copied from arch/x86/kernel/devicetree.c */ 549 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 550 { 551 struct device_node *np; 552 553 for_each_node_by_type(np, "pci") { 554 const void *prop; 555 unsigned int bus_min; 556 557 prop = of_get_property(np, "bus-range", NULL); 558 if (!prop) 559 continue; 560 bus_min = be32_to_cpup(prop); 561 if (bus->number == bus_min) 562 return np; 563 } 564 return NULL; 565 } 566 #endif 567 568 static int um_pci_init_vqs(struct um_pci_device *dev) 569 { 570 struct virtqueue_info vqs_info[] = { 571 { "cmd", um_pci_cmd_vq_cb }, 572 { "irq", um_pci_irq_vq_cb }, 573 }; 574 struct virtqueue *vqs[2]; 575 int err, i; 576 577 err = virtio_find_vqs(dev->vdev, 2, vqs, vqs_info, NULL); 578 if (err) 579 return err; 580 581 dev->cmd_vq = vqs[0]; 582 dev->irq_vq = vqs[1]; 583 584 virtio_device_ready(dev->vdev); 585 586 for (i = 0; i < NUM_IRQ_MSGS; i++) { 587 void *msg = kzalloc(MAX_IRQ_MSG_SIZE, GFP_KERNEL); 588 589 if (msg) 590 um_pci_irq_vq_addbuf(dev->irq_vq, msg, false); 591 } 592 593 virtqueue_kick(dev->irq_vq); 594 595 return 0; 596 } 597 598 static void __um_pci_virtio_platform_remove(struct virtio_device *vdev, 599 struct um_pci_device *dev) 600 { 601 virtio_reset_device(vdev); 602 vdev->config->del_vqs(vdev); 603 604 mutex_lock(&um_pci_mtx); 605 um_pci_platform_device = NULL; 606 mutex_unlock(&um_pci_mtx); 607 608 kfree(dev); 609 } 610 611 static int um_pci_virtio_platform_probe(struct virtio_device *vdev, 612 struct um_pci_device *dev) 613 { 614 int ret; 615 616 dev->platform = true; 617 618 mutex_lock(&um_pci_mtx); 619 620 if (um_pci_platform_device) { 621 mutex_unlock(&um_pci_mtx); 622 ret = -EBUSY; 623 goto out_free; 624 } 625 626 ret = um_pci_init_vqs(dev); 627 if (ret) { 628 mutex_unlock(&um_pci_mtx); 629 goto out_free; 630 } 631 632 um_pci_platform_device = dev; 633 634 mutex_unlock(&um_pci_mtx); 635 636 ret = of_platform_default_populate(vdev->dev.of_node, NULL, &vdev->dev); 637 if (ret) 638 __um_pci_virtio_platform_remove(vdev, dev); 639 640 return ret; 641 642 out_free: 643 kfree(dev); 644 return ret; 645 } 646 647 static int um_pci_virtio_probe(struct virtio_device *vdev) 648 { 649 struct um_pci_device *dev; 650 int i, free = -1; 651 int err = -ENOSPC; 652 653 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 654 if (!dev) 655 return -ENOMEM; 656 657 dev->vdev = vdev; 658 vdev->priv = dev; 659 660 if (of_device_is_compatible(vdev->dev.of_node, "simple-bus")) 661 return um_pci_virtio_platform_probe(vdev, dev); 662 663 mutex_lock(&um_pci_mtx); 664 for (i = 0; i < MAX_DEVICES; i++) { 665 if (um_pci_devices[i].dev) 666 continue; 667 free = i; 668 break; 669 } 670 671 if (free < 0) 672 goto error; 673 674 err = um_pci_init_vqs(dev); 675 if (err) 676 goto error; 677 678 dev->irq = irq_alloc_desc(numa_node_id()); 679 if (dev->irq < 0) { 680 err = dev->irq; 681 goto err_reset; 682 } 683 um_pci_devices[free].dev = dev; 684 vdev->priv = dev; 685 686 mutex_unlock(&um_pci_mtx); 687 688 device_set_wakeup_enable(&vdev->dev, true); 689 690 /* 691 * In order to do suspend-resume properly, don't allow VQs 692 * to be suspended. 693 */ 694 virtio_uml_set_no_vq_suspend(vdev, true); 695 696 um_pci_rescan(); 697 return 0; 698 err_reset: 699 virtio_reset_device(vdev); 700 vdev->config->del_vqs(vdev); 701 error: 702 mutex_unlock(&um_pci_mtx); 703 kfree(dev); 704 return err; 705 } 706 707 static void um_pci_virtio_remove(struct virtio_device *vdev) 708 { 709 struct um_pci_device *dev = vdev->priv; 710 int i; 711 712 if (dev->platform) { 713 of_platform_depopulate(&vdev->dev); 714 __um_pci_virtio_platform_remove(vdev, dev); 715 return; 716 } 717 718 device_set_wakeup_enable(&vdev->dev, false); 719 720 mutex_lock(&um_pci_mtx); 721 for (i = 0; i < MAX_DEVICES; i++) { 722 if (um_pci_devices[i].dev != dev) 723 continue; 724 725 um_pci_devices[i].dev = NULL; 726 irq_free_desc(dev->irq); 727 728 break; 729 } 730 mutex_unlock(&um_pci_mtx); 731 732 if (i < MAX_DEVICES) { 733 struct pci_dev *pci_dev; 734 735 pci_dev = pci_get_slot(bridge->bus, i); 736 if (pci_dev) 737 pci_stop_and_remove_bus_device_locked(pci_dev); 738 } 739 740 /* Stop all virtqueues */ 741 virtio_reset_device(vdev); 742 dev->cmd_vq = NULL; 743 dev->irq_vq = NULL; 744 vdev->config->del_vqs(vdev); 745 746 kfree(dev); 747 } 748 749 static struct virtio_device_id id_table[] = { 750 { CONFIG_UML_PCI_OVER_VIRTIO_DEVICE_ID, VIRTIO_DEV_ANY_ID }, 751 { 0 }, 752 }; 753 MODULE_DEVICE_TABLE(virtio, id_table); 754 755 static struct virtio_driver um_pci_virtio_driver = { 756 .driver.name = "virtio-pci", 757 .id_table = id_table, 758 .probe = um_pci_virtio_probe, 759 .remove = um_pci_virtio_remove, 760 }; 761 762 static struct resource virt_cfgspace_resource = { 763 .name = "PCI config space", 764 .start = 0xf0000000 - MAX_DEVICES * CFG_SPACE_SIZE, 765 .end = 0xf0000000 - 1, 766 .flags = IORESOURCE_MEM, 767 }; 768 769 static long um_pci_map_cfgspace(unsigned long offset, size_t size, 770 const struct logic_iomem_ops **ops, 771 void **priv) 772 { 773 if (WARN_ON(size > CFG_SPACE_SIZE || offset % CFG_SPACE_SIZE)) 774 return -EINVAL; 775 776 if (offset / CFG_SPACE_SIZE < MAX_DEVICES) { 777 *ops = &um_pci_device_cfgspace_ops; 778 *priv = &um_pci_devices[offset / CFG_SPACE_SIZE]; 779 return 0; 780 } 781 782 WARN(1, "cannot map offset 0x%lx/0x%zx\n", offset, size); 783 return -ENOENT; 784 } 785 786 static const struct logic_iomem_region_ops um_pci_cfgspace_ops = { 787 .map = um_pci_map_cfgspace, 788 }; 789 790 static struct resource virt_iomem_resource = { 791 .name = "PCI iomem", 792 .start = 0xf0000000, 793 .end = 0xffffffff, 794 .flags = IORESOURCE_MEM, 795 }; 796 797 struct um_pci_map_iomem_data { 798 unsigned long offset; 799 size_t size; 800 const struct logic_iomem_ops **ops; 801 void **priv; 802 long ret; 803 }; 804 805 static int um_pci_map_iomem_walk(struct pci_dev *pdev, void *_data) 806 { 807 struct um_pci_map_iomem_data *data = _data; 808 struct um_pci_device_reg *reg = &um_pci_devices[pdev->devfn / 8]; 809 struct um_pci_device *dev; 810 int i; 811 812 if (!reg->dev) 813 return 0; 814 815 for (i = 0; i < ARRAY_SIZE(dev->resptr); i++) { 816 struct resource *r = &pdev->resource[i]; 817 818 if ((r->flags & IORESOURCE_TYPE_BITS) != IORESOURCE_MEM) 819 continue; 820 821 /* 822 * must be the whole or part of the resource, 823 * not allowed to only overlap 824 */ 825 if (data->offset < r->start || data->offset > r->end) 826 continue; 827 if (data->offset + data->size - 1 > r->end) 828 continue; 829 830 dev = reg->dev; 831 *data->ops = &um_pci_device_bar_ops; 832 dev->resptr[i] = i; 833 *data->priv = &dev->resptr[i]; 834 data->ret = data->offset - r->start; 835 836 /* no need to continue */ 837 return 1; 838 } 839 840 return 0; 841 } 842 843 static long um_pci_map_iomem(unsigned long offset, size_t size, 844 const struct logic_iomem_ops **ops, 845 void **priv) 846 { 847 struct um_pci_map_iomem_data data = { 848 /* we want the full address here */ 849 .offset = offset + virt_iomem_resource.start, 850 .size = size, 851 .ops = ops, 852 .priv = priv, 853 .ret = -ENOENT, 854 }; 855 856 pci_walk_bus(bridge->bus, um_pci_map_iomem_walk, &data); 857 return data.ret; 858 } 859 860 static const struct logic_iomem_region_ops um_pci_iomem_ops = { 861 .map = um_pci_map_iomem, 862 }; 863 864 static void um_pci_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 865 { 866 /* 867 * This is a very low address and not actually valid 'physical' memory 868 * in UML, so we can simply map MSI(-X) vectors to there, it cannot be 869 * legitimately written to by the device in any other way. 870 * We use the (virtual) IRQ number here as the message to simplify the 871 * code that receives the message, where for now we simply trust the 872 * device to send the correct message. 873 */ 874 msg->address_hi = 0; 875 msg->address_lo = 0xa0000; 876 msg->data = data->irq; 877 } 878 879 static struct irq_chip um_pci_msi_bottom_irq_chip = { 880 .name = "UM virtio MSI", 881 .irq_compose_msi_msg = um_pci_compose_msi_msg, 882 }; 883 884 static int um_pci_inner_domain_alloc(struct irq_domain *domain, 885 unsigned int virq, unsigned int nr_irqs, 886 void *args) 887 { 888 unsigned long bit; 889 890 WARN_ON(nr_irqs != 1); 891 892 mutex_lock(&um_pci_mtx); 893 bit = find_first_zero_bit(um_pci_msi_used, MAX_MSI_VECTORS); 894 if (bit >= MAX_MSI_VECTORS) { 895 mutex_unlock(&um_pci_mtx); 896 return -ENOSPC; 897 } 898 899 set_bit(bit, um_pci_msi_used); 900 mutex_unlock(&um_pci_mtx); 901 902 irq_domain_set_info(domain, virq, bit, &um_pci_msi_bottom_irq_chip, 903 domain->host_data, handle_simple_irq, 904 NULL, NULL); 905 906 return 0; 907 } 908 909 static void um_pci_inner_domain_free(struct irq_domain *domain, 910 unsigned int virq, unsigned int nr_irqs) 911 { 912 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 913 914 mutex_lock(&um_pci_mtx); 915 916 if (!test_bit(d->hwirq, um_pci_msi_used)) 917 pr_err("trying to free unused MSI#%lu\n", d->hwirq); 918 else 919 __clear_bit(d->hwirq, um_pci_msi_used); 920 921 mutex_unlock(&um_pci_mtx); 922 } 923 924 static const struct irq_domain_ops um_pci_inner_domain_ops = { 925 .alloc = um_pci_inner_domain_alloc, 926 .free = um_pci_inner_domain_free, 927 }; 928 929 static struct irq_chip um_pci_msi_irq_chip = { 930 .name = "UM virtio PCIe MSI", 931 .irq_mask = pci_msi_mask_irq, 932 .irq_unmask = pci_msi_unmask_irq, 933 }; 934 935 static struct msi_domain_info um_pci_msi_domain_info = { 936 .flags = MSI_FLAG_USE_DEF_DOM_OPS | 937 MSI_FLAG_USE_DEF_CHIP_OPS | 938 MSI_FLAG_PCI_MSIX, 939 .chip = &um_pci_msi_irq_chip, 940 }; 941 942 static struct resource busn_resource = { 943 .name = "PCI busn", 944 .start = 0, 945 .end = 0, 946 .flags = IORESOURCE_BUS, 947 }; 948 949 static int um_pci_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin) 950 { 951 struct um_pci_device_reg *reg = &um_pci_devices[pdev->devfn / 8]; 952 953 if (WARN_ON(!reg->dev)) 954 return -EINVAL; 955 956 /* Yes, we map all pins to the same IRQ ... doesn't matter for now. */ 957 return reg->dev->irq; 958 } 959 960 void *pci_root_bus_fwnode(struct pci_bus *bus) 961 { 962 return um_pci_fwnode; 963 } 964 965 static long um_pci_map_platform(unsigned long offset, size_t size, 966 const struct logic_iomem_ops **ops, 967 void **priv) 968 { 969 if (!um_pci_platform_device) 970 return -ENOENT; 971 972 *ops = &um_pci_device_bar_ops; 973 *priv = &um_pci_platform_device->resptr[0]; 974 975 return offset; 976 } 977 978 static const struct logic_iomem_region_ops um_pci_platform_ops = { 979 .map = um_pci_map_platform, 980 }; 981 982 static struct resource virt_platform_resource = { 983 .name = "platform", 984 .start = 0x10000000, 985 .end = 0x1fffffff, 986 .flags = IORESOURCE_MEM, 987 }; 988 989 static int __init um_pci_init(void) 990 { 991 struct irq_domain_info inner_domain_info = { 992 .size = MAX_MSI_VECTORS, 993 .hwirq_max = MAX_MSI_VECTORS, 994 .ops = &um_pci_inner_domain_ops, 995 }; 996 int err, i; 997 998 WARN_ON(logic_iomem_add_region(&virt_cfgspace_resource, 999 &um_pci_cfgspace_ops)); 1000 WARN_ON(logic_iomem_add_region(&virt_iomem_resource, 1001 &um_pci_iomem_ops)); 1002 WARN_ON(logic_iomem_add_region(&virt_platform_resource, 1003 &um_pci_platform_ops)); 1004 1005 if (WARN(CONFIG_UML_PCI_OVER_VIRTIO_DEVICE_ID < 0, 1006 "No virtio device ID configured for PCI - no PCI support\n")) 1007 return 0; 1008 1009 um_pci_msg_bufs = alloc_percpu(struct um_pci_message_buffer); 1010 if (!um_pci_msg_bufs) 1011 return -ENOMEM; 1012 1013 bridge = pci_alloc_host_bridge(0); 1014 if (!bridge) { 1015 err = -ENOMEM; 1016 goto free; 1017 } 1018 1019 um_pci_fwnode = irq_domain_alloc_named_fwnode("um-pci"); 1020 if (!um_pci_fwnode) { 1021 err = -ENOMEM; 1022 goto free; 1023 } 1024 1025 inner_domain_info.fwnode = um_pci_fwnode; 1026 um_pci_inner_domain = irq_domain_instantiate(&inner_domain_info); 1027 if (IS_ERR(um_pci_inner_domain)) { 1028 err = PTR_ERR(um_pci_inner_domain); 1029 goto free; 1030 } 1031 1032 um_pci_msi_domain = pci_msi_create_irq_domain(um_pci_fwnode, 1033 &um_pci_msi_domain_info, 1034 um_pci_inner_domain); 1035 if (!um_pci_msi_domain) { 1036 err = -ENOMEM; 1037 goto free; 1038 } 1039 1040 pci_add_resource(&bridge->windows, &virt_iomem_resource); 1041 pci_add_resource(&bridge->windows, &busn_resource); 1042 bridge->ops = &um_pci_ops; 1043 bridge->map_irq = um_pci_map_irq; 1044 1045 for (i = 0; i < MAX_DEVICES; i++) { 1046 resource_size_t start; 1047 1048 start = virt_cfgspace_resource.start + i * CFG_SPACE_SIZE; 1049 um_pci_devices[i].iomem = ioremap(start, CFG_SPACE_SIZE); 1050 if (WARN(!um_pci_devices[i].iomem, "failed to map %d\n", i)) { 1051 err = -ENOMEM; 1052 goto free; 1053 } 1054 } 1055 1056 err = pci_host_probe(bridge); 1057 if (err) 1058 goto free; 1059 1060 err = register_virtio_driver(&um_pci_virtio_driver); 1061 if (err) 1062 goto free; 1063 return 0; 1064 free: 1065 if (!IS_ERR_OR_NULL(um_pci_inner_domain)) 1066 irq_domain_remove(um_pci_inner_domain); 1067 if (um_pci_fwnode) 1068 irq_domain_free_fwnode(um_pci_fwnode); 1069 if (bridge) { 1070 pci_free_resource_list(&bridge->windows); 1071 pci_free_host_bridge(bridge); 1072 } 1073 free_percpu(um_pci_msg_bufs); 1074 return err; 1075 } 1076 module_init(um_pci_init); 1077 1078 static void __exit um_pci_exit(void) 1079 { 1080 unregister_virtio_driver(&um_pci_virtio_driver); 1081 irq_domain_remove(um_pci_msi_domain); 1082 irq_domain_remove(um_pci_inner_domain); 1083 pci_free_resource_list(&bridge->windows); 1084 pci_free_host_bridge(bridge); 1085 free_percpu(um_pci_msg_bufs); 1086 } 1087 module_exit(um_pci_exit); 1088