1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/moduleloader.h> 3 #include <linux/workqueue.h> 4 #include <linux/netdevice.h> 5 #include <linux/filter.h> 6 #include <linux/bpf.h> 7 #include <linux/cache.h> 8 #include <linux/if_vlan.h> 9 10 #include <asm/cacheflush.h> 11 #include <asm/ptrace.h> 12 13 #include "bpf_jit_64.h" 14 15 static inline bool is_simm13(unsigned int value) 16 { 17 return value + 0x1000 < 0x2000; 18 } 19 20 static inline bool is_simm10(unsigned int value) 21 { 22 return value + 0x200 < 0x400; 23 } 24 25 static inline bool is_simm5(unsigned int value) 26 { 27 return value + 0x10 < 0x20; 28 } 29 30 static inline bool is_sethi(unsigned int value) 31 { 32 return (value & ~0x3fffff) == 0; 33 } 34 35 static void bpf_flush_icache(void *start_, void *end_) 36 { 37 /* Cheetah's I-cache is fully coherent. */ 38 if (tlb_type == spitfire) { 39 unsigned long start = (unsigned long) start_; 40 unsigned long end = (unsigned long) end_; 41 42 start &= ~7UL; 43 end = (end + 7UL) & ~7UL; 44 while (start < end) { 45 flushi(start); 46 start += 32; 47 } 48 } 49 } 50 51 #define S13(X) ((X) & 0x1fff) 52 #define S5(X) ((X) & 0x1f) 53 #define IMMED 0x00002000 54 #define RD(X) ((X) << 25) 55 #define RS1(X) ((X) << 14) 56 #define RS2(X) ((X)) 57 #define OP(X) ((X) << 30) 58 #define OP2(X) ((X) << 22) 59 #define OP3(X) ((X) << 19) 60 #define COND(X) (((X) & 0xf) << 25) 61 #define CBCOND(X) (((X) & 0x1f) << 25) 62 #define F1(X) OP(X) 63 #define F2(X, Y) (OP(X) | OP2(Y)) 64 #define F3(X, Y) (OP(X) | OP3(Y)) 65 #define ASI(X) (((X) & 0xff) << 5) 66 67 #define CONDN COND(0x0) 68 #define CONDE COND(0x1) 69 #define CONDLE COND(0x2) 70 #define CONDL COND(0x3) 71 #define CONDLEU COND(0x4) 72 #define CONDCS COND(0x5) 73 #define CONDNEG COND(0x6) 74 #define CONDVC COND(0x7) 75 #define CONDA COND(0x8) 76 #define CONDNE COND(0x9) 77 #define CONDG COND(0xa) 78 #define CONDGE COND(0xb) 79 #define CONDGU COND(0xc) 80 #define CONDCC COND(0xd) 81 #define CONDPOS COND(0xe) 82 #define CONDVS COND(0xf) 83 84 #define CONDGEU CONDCC 85 #define CONDLU CONDCS 86 87 #define WDISP22(X) (((X) >> 2) & 0x3fffff) 88 #define WDISP19(X) (((X) >> 2) & 0x7ffff) 89 90 /* The 10-bit branch displacement for CBCOND is split into two fields */ 91 static u32 WDISP10(u32 off) 92 { 93 u32 ret = ((off >> 2) & 0xff) << 5; 94 95 ret |= ((off >> (2 + 8)) & 0x03) << 19; 96 97 return ret; 98 } 99 100 #define CBCONDE CBCOND(0x09) 101 #define CBCONDLE CBCOND(0x0a) 102 #define CBCONDL CBCOND(0x0b) 103 #define CBCONDLEU CBCOND(0x0c) 104 #define CBCONDCS CBCOND(0x0d) 105 #define CBCONDN CBCOND(0x0e) 106 #define CBCONDVS CBCOND(0x0f) 107 #define CBCONDNE CBCOND(0x19) 108 #define CBCONDG CBCOND(0x1a) 109 #define CBCONDGE CBCOND(0x1b) 110 #define CBCONDGU CBCOND(0x1c) 111 #define CBCONDCC CBCOND(0x1d) 112 #define CBCONDPOS CBCOND(0x1e) 113 #define CBCONDVC CBCOND(0x1f) 114 115 #define CBCONDGEU CBCONDCC 116 #define CBCONDLU CBCONDCS 117 118 #define ANNUL (1 << 29) 119 #define XCC (1 << 21) 120 121 #define BRANCH (F2(0, 1) | XCC) 122 #define CBCOND_OP (F2(0, 3) | XCC) 123 124 #define BA (BRANCH | CONDA) 125 #define BG (BRANCH | CONDG) 126 #define BL (BRANCH | CONDL) 127 #define BLE (BRANCH | CONDLE) 128 #define BGU (BRANCH | CONDGU) 129 #define BLEU (BRANCH | CONDLEU) 130 #define BGE (BRANCH | CONDGE) 131 #define BGEU (BRANCH | CONDGEU) 132 #define BLU (BRANCH | CONDLU) 133 #define BE (BRANCH | CONDE) 134 #define BNE (BRANCH | CONDNE) 135 136 #define SETHI(K, REG) \ 137 (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff)) 138 #define OR_LO(K, REG) \ 139 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG)) 140 141 #define ADD F3(2, 0x00) 142 #define AND F3(2, 0x01) 143 #define ANDCC F3(2, 0x11) 144 #define OR F3(2, 0x02) 145 #define XOR F3(2, 0x03) 146 #define SUB F3(2, 0x04) 147 #define SUBCC F3(2, 0x14) 148 #define MUL F3(2, 0x0a) 149 #define MULX F3(2, 0x09) 150 #define UDIVX F3(2, 0x0d) 151 #define DIV F3(2, 0x0e) 152 #define SLL F3(2, 0x25) 153 #define SLLX (F3(2, 0x25)|(1<<12)) 154 #define SRA F3(2, 0x27) 155 #define SRAX (F3(2, 0x27)|(1<<12)) 156 #define SRL F3(2, 0x26) 157 #define SRLX (F3(2, 0x26)|(1<<12)) 158 #define JMPL F3(2, 0x38) 159 #define SAVE F3(2, 0x3c) 160 #define RESTORE F3(2, 0x3d) 161 #define CALL F1(1) 162 #define BR F2(0, 0x01) 163 #define RD_Y F3(2, 0x28) 164 #define WR_Y F3(2, 0x30) 165 166 #define LD32 F3(3, 0x00) 167 #define LD8 F3(3, 0x01) 168 #define LD16 F3(3, 0x02) 169 #define LD64 F3(3, 0x0b) 170 #define LD64A F3(3, 0x1b) 171 #define ST8 F3(3, 0x05) 172 #define ST16 F3(3, 0x06) 173 #define ST32 F3(3, 0x04) 174 #define ST64 F3(3, 0x0e) 175 176 #define CAS F3(3, 0x3c) 177 #define CASX F3(3, 0x3e) 178 179 #define LDPTR LD64 180 #define BASE_STACKFRAME 176 181 182 #define LD32I (LD32 | IMMED) 183 #define LD8I (LD8 | IMMED) 184 #define LD16I (LD16 | IMMED) 185 #define LD64I (LD64 | IMMED) 186 #define LDPTRI (LDPTR | IMMED) 187 #define ST32I (ST32 | IMMED) 188 189 struct jit_ctx { 190 struct bpf_prog *prog; 191 unsigned int *offset; 192 int idx; 193 int epilogue_offset; 194 bool tmp_1_used; 195 bool tmp_2_used; 196 bool tmp_3_used; 197 bool saw_frame_pointer; 198 bool saw_call; 199 bool saw_tail_call; 200 u32 *image; 201 }; 202 203 #define TMP_REG_1 (MAX_BPF_JIT_REG + 0) 204 #define TMP_REG_2 (MAX_BPF_JIT_REG + 1) 205 #define TMP_REG_3 (MAX_BPF_JIT_REG + 2) 206 207 /* Map BPF registers to SPARC registers */ 208 static const int bpf2sparc[] = { 209 /* return value from in-kernel function, and exit value from eBPF */ 210 [BPF_REG_0] = O5, 211 212 /* arguments from eBPF program to in-kernel function */ 213 [BPF_REG_1] = O0, 214 [BPF_REG_2] = O1, 215 [BPF_REG_3] = O2, 216 [BPF_REG_4] = O3, 217 [BPF_REG_5] = O4, 218 219 /* callee saved registers that in-kernel function will preserve */ 220 [BPF_REG_6] = L0, 221 [BPF_REG_7] = L1, 222 [BPF_REG_8] = L2, 223 [BPF_REG_9] = L3, 224 225 /* read-only frame pointer to access stack */ 226 [BPF_REG_FP] = L6, 227 228 [BPF_REG_AX] = G7, 229 230 /* temporary register for internal BPF JIT */ 231 [TMP_REG_1] = G1, 232 [TMP_REG_2] = G2, 233 [TMP_REG_3] = G3, 234 }; 235 236 static void emit(const u32 insn, struct jit_ctx *ctx) 237 { 238 if (ctx->image != NULL) 239 ctx->image[ctx->idx] = insn; 240 241 ctx->idx++; 242 } 243 244 static void emit_call(u32 *func, struct jit_ctx *ctx) 245 { 246 if (ctx->image != NULL) { 247 void *here = &ctx->image[ctx->idx]; 248 unsigned int off; 249 250 off = (void *)func - here; 251 ctx->image[ctx->idx] = CALL | ((off >> 2) & 0x3fffffff); 252 } 253 ctx->idx++; 254 } 255 256 static void emit_nop(struct jit_ctx *ctx) 257 { 258 emit(SETHI(0, G0), ctx); 259 } 260 261 static void emit_reg_move(u32 from, u32 to, struct jit_ctx *ctx) 262 { 263 emit(OR | RS1(G0) | RS2(from) | RD(to), ctx); 264 } 265 266 /* Emit 32-bit constant, zero extended. */ 267 static void emit_set_const(s32 K, u32 reg, struct jit_ctx *ctx) 268 { 269 emit(SETHI(K, reg), ctx); 270 emit(OR_LO(K, reg), ctx); 271 } 272 273 /* Emit 32-bit constant, sign extended. */ 274 static void emit_set_const_sext(s32 K, u32 reg, struct jit_ctx *ctx) 275 { 276 if (K >= 0) { 277 emit(SETHI(K, reg), ctx); 278 emit(OR_LO(K, reg), ctx); 279 } else { 280 u32 hbits = ~(u32) K; 281 u32 lbits = -0x400 | (u32) K; 282 283 emit(SETHI(hbits, reg), ctx); 284 emit(XOR | IMMED | RS1(reg) | S13(lbits) | RD(reg), ctx); 285 } 286 } 287 288 static void emit_alu(u32 opcode, u32 src, u32 dst, struct jit_ctx *ctx) 289 { 290 emit(opcode | RS1(dst) | RS2(src) | RD(dst), ctx); 291 } 292 293 static void emit_alu3(u32 opcode, u32 a, u32 b, u32 c, struct jit_ctx *ctx) 294 { 295 emit(opcode | RS1(a) | RS2(b) | RD(c), ctx); 296 } 297 298 static void emit_alu_K(unsigned int opcode, unsigned int dst, unsigned int imm, 299 struct jit_ctx *ctx) 300 { 301 bool small_immed = is_simm13(imm); 302 unsigned int insn = opcode; 303 304 insn |= RS1(dst) | RD(dst); 305 if (small_immed) { 306 emit(insn | IMMED | S13(imm), ctx); 307 } else { 308 unsigned int tmp = bpf2sparc[TMP_REG_1]; 309 310 ctx->tmp_1_used = true; 311 312 emit_set_const_sext(imm, tmp, ctx); 313 emit(insn | RS2(tmp), ctx); 314 } 315 } 316 317 static void emit_alu3_K(unsigned int opcode, unsigned int src, unsigned int imm, 318 unsigned int dst, struct jit_ctx *ctx) 319 { 320 bool small_immed = is_simm13(imm); 321 unsigned int insn = opcode; 322 323 insn |= RS1(src) | RD(dst); 324 if (small_immed) { 325 emit(insn | IMMED | S13(imm), ctx); 326 } else { 327 unsigned int tmp = bpf2sparc[TMP_REG_1]; 328 329 ctx->tmp_1_used = true; 330 331 emit_set_const_sext(imm, tmp, ctx); 332 emit(insn | RS2(tmp), ctx); 333 } 334 } 335 336 static void emit_loadimm32(s32 K, unsigned int dest, struct jit_ctx *ctx) 337 { 338 if (K >= 0 && is_simm13(K)) { 339 /* or %g0, K, DEST */ 340 emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx); 341 } else { 342 emit_set_const(K, dest, ctx); 343 } 344 } 345 346 static void emit_loadimm(s32 K, unsigned int dest, struct jit_ctx *ctx) 347 { 348 if (is_simm13(K)) { 349 /* or %g0, K, DEST */ 350 emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx); 351 } else { 352 emit_set_const(K, dest, ctx); 353 } 354 } 355 356 static void emit_loadimm_sext(s32 K, unsigned int dest, struct jit_ctx *ctx) 357 { 358 if (is_simm13(K)) { 359 /* or %g0, K, DEST */ 360 emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx); 361 } else { 362 emit_set_const_sext(K, dest, ctx); 363 } 364 } 365 366 static void analyze_64bit_constant(u32 high_bits, u32 low_bits, 367 int *hbsp, int *lbsp, int *abbasp) 368 { 369 int lowest_bit_set, highest_bit_set, all_bits_between_are_set; 370 int i; 371 372 lowest_bit_set = highest_bit_set = -1; 373 i = 0; 374 do { 375 if ((lowest_bit_set == -1) && ((low_bits >> i) & 1)) 376 lowest_bit_set = i; 377 if ((highest_bit_set == -1) && ((high_bits >> (32 - i - 1)) & 1)) 378 highest_bit_set = (64 - i - 1); 379 } while (++i < 32 && (highest_bit_set == -1 || 380 lowest_bit_set == -1)); 381 if (i == 32) { 382 i = 0; 383 do { 384 if (lowest_bit_set == -1 && ((high_bits >> i) & 1)) 385 lowest_bit_set = i + 32; 386 if (highest_bit_set == -1 && 387 ((low_bits >> (32 - i - 1)) & 1)) 388 highest_bit_set = 32 - i - 1; 389 } while (++i < 32 && (highest_bit_set == -1 || 390 lowest_bit_set == -1)); 391 } 392 393 all_bits_between_are_set = 1; 394 for (i = lowest_bit_set; i <= highest_bit_set; i++) { 395 if (i < 32) { 396 if ((low_bits & (1 << i)) != 0) 397 continue; 398 } else { 399 if ((high_bits & (1 << (i - 32))) != 0) 400 continue; 401 } 402 all_bits_between_are_set = 0; 403 break; 404 } 405 *hbsp = highest_bit_set; 406 *lbsp = lowest_bit_set; 407 *abbasp = all_bits_between_are_set; 408 } 409 410 static unsigned long create_simple_focus_bits(unsigned long high_bits, 411 unsigned long low_bits, 412 int lowest_bit_set, int shift) 413 { 414 long hi, lo; 415 416 if (lowest_bit_set < 32) { 417 lo = (low_bits >> lowest_bit_set) << shift; 418 hi = ((high_bits << (32 - lowest_bit_set)) << shift); 419 } else { 420 lo = 0; 421 hi = ((high_bits >> (lowest_bit_set - 32)) << shift); 422 } 423 return hi | lo; 424 } 425 426 static bool const64_is_2insns(unsigned long high_bits, 427 unsigned long low_bits) 428 { 429 int highest_bit_set, lowest_bit_set, all_bits_between_are_set; 430 431 if (high_bits == 0 || high_bits == 0xffffffff) 432 return true; 433 434 analyze_64bit_constant(high_bits, low_bits, 435 &highest_bit_set, &lowest_bit_set, 436 &all_bits_between_are_set); 437 438 if ((highest_bit_set == 63 || lowest_bit_set == 0) && 439 all_bits_between_are_set != 0) 440 return true; 441 442 if (highest_bit_set - lowest_bit_set < 21) 443 return true; 444 445 return false; 446 } 447 448 static void sparc_emit_set_const64_quick2(unsigned long high_bits, 449 unsigned long low_imm, 450 unsigned int dest, 451 int shift_count, struct jit_ctx *ctx) 452 { 453 emit_loadimm32(high_bits, dest, ctx); 454 455 /* Now shift it up into place. */ 456 emit_alu_K(SLLX, dest, shift_count, ctx); 457 458 /* If there is a low immediate part piece, finish up by 459 * putting that in as well. 460 */ 461 if (low_imm != 0) 462 emit(OR | IMMED | RS1(dest) | S13(low_imm) | RD(dest), ctx); 463 } 464 465 static void emit_loadimm64(u64 K, unsigned int dest, struct jit_ctx *ctx) 466 { 467 int all_bits_between_are_set, lowest_bit_set, highest_bit_set; 468 unsigned int tmp = bpf2sparc[TMP_REG_1]; 469 u32 low_bits = (K & 0xffffffff); 470 u32 high_bits = (K >> 32); 471 472 /* These two tests also take care of all of the one 473 * instruction cases. 474 */ 475 if (high_bits == 0xffffffff && (low_bits & 0x80000000)) 476 return emit_loadimm_sext(K, dest, ctx); 477 if (high_bits == 0x00000000) 478 return emit_loadimm32(K, dest, ctx); 479 480 analyze_64bit_constant(high_bits, low_bits, &highest_bit_set, 481 &lowest_bit_set, &all_bits_between_are_set); 482 483 /* 1) mov -1, %reg 484 * sllx %reg, shift, %reg 485 * 2) mov -1, %reg 486 * srlx %reg, shift, %reg 487 * 3) mov some_small_const, %reg 488 * sllx %reg, shift, %reg 489 */ 490 if (((highest_bit_set == 63 || lowest_bit_set == 0) && 491 all_bits_between_are_set != 0) || 492 ((highest_bit_set - lowest_bit_set) < 12)) { 493 int shift = lowest_bit_set; 494 long the_const = -1; 495 496 if ((highest_bit_set != 63 && lowest_bit_set != 0) || 497 all_bits_between_are_set == 0) { 498 the_const = 499 create_simple_focus_bits(high_bits, low_bits, 500 lowest_bit_set, 0); 501 } else if (lowest_bit_set == 0) 502 shift = -(63 - highest_bit_set); 503 504 emit(OR | IMMED | RS1(G0) | S13(the_const) | RD(dest), ctx); 505 if (shift > 0) 506 emit_alu_K(SLLX, dest, shift, ctx); 507 else if (shift < 0) 508 emit_alu_K(SRLX, dest, -shift, ctx); 509 510 return; 511 } 512 513 /* Now a range of 22 or less bits set somewhere. 514 * 1) sethi %hi(focus_bits), %reg 515 * sllx %reg, shift, %reg 516 * 2) sethi %hi(focus_bits), %reg 517 * srlx %reg, shift, %reg 518 */ 519 if ((highest_bit_set - lowest_bit_set) < 21) { 520 unsigned long focus_bits = 521 create_simple_focus_bits(high_bits, low_bits, 522 lowest_bit_set, 10); 523 524 emit(SETHI(focus_bits, dest), ctx); 525 526 /* If lowest_bit_set == 10 then a sethi alone could 527 * have done it. 528 */ 529 if (lowest_bit_set < 10) 530 emit_alu_K(SRLX, dest, 10 - lowest_bit_set, ctx); 531 else if (lowest_bit_set > 10) 532 emit_alu_K(SLLX, dest, lowest_bit_set - 10, ctx); 533 return; 534 } 535 536 /* Ok, now 3 instruction sequences. */ 537 if (low_bits == 0) { 538 emit_loadimm32(high_bits, dest, ctx); 539 emit_alu_K(SLLX, dest, 32, ctx); 540 return; 541 } 542 543 /* We may be able to do something quick 544 * when the constant is negated, so try that. 545 */ 546 if (const64_is_2insns((~high_bits) & 0xffffffff, 547 (~low_bits) & 0xfffffc00)) { 548 /* NOTE: The trailing bits get XOR'd so we need the 549 * non-negated bits, not the negated ones. 550 */ 551 unsigned long trailing_bits = low_bits & 0x3ff; 552 553 if ((((~high_bits) & 0xffffffff) == 0 && 554 ((~low_bits) & 0x80000000) == 0) || 555 (((~high_bits) & 0xffffffff) == 0xffffffff && 556 ((~low_bits) & 0x80000000) != 0)) { 557 unsigned long fast_int = (~low_bits & 0xffffffff); 558 559 if ((is_sethi(fast_int) && 560 (~high_bits & 0xffffffff) == 0)) { 561 emit(SETHI(fast_int, dest), ctx); 562 } else if (is_simm13(fast_int)) { 563 emit(OR | IMMED | RS1(G0) | S13(fast_int) | RD(dest), ctx); 564 } else { 565 emit_loadimm64(fast_int, dest, ctx); 566 } 567 } else { 568 u64 n = ((~low_bits) & 0xfffffc00) | 569 (((unsigned long)((~high_bits) & 0xffffffff))<<32); 570 emit_loadimm64(n, dest, ctx); 571 } 572 573 low_bits = -0x400 | trailing_bits; 574 575 emit(XOR | IMMED | RS1(dest) | S13(low_bits) | RD(dest), ctx); 576 return; 577 } 578 579 /* 1) sethi %hi(xxx), %reg 580 * or %reg, %lo(xxx), %reg 581 * sllx %reg, yyy, %reg 582 */ 583 if ((highest_bit_set - lowest_bit_set) < 32) { 584 unsigned long focus_bits = 585 create_simple_focus_bits(high_bits, low_bits, 586 lowest_bit_set, 0); 587 588 /* So what we know is that the set bits straddle the 589 * middle of the 64-bit word. 590 */ 591 sparc_emit_set_const64_quick2(focus_bits, 0, dest, 592 lowest_bit_set, ctx); 593 return; 594 } 595 596 /* 1) sethi %hi(high_bits), %reg 597 * or %reg, %lo(high_bits), %reg 598 * sllx %reg, 32, %reg 599 * or %reg, low_bits, %reg 600 */ 601 if (is_simm13(low_bits) && ((int)low_bits > 0)) { 602 sparc_emit_set_const64_quick2(high_bits, low_bits, 603 dest, 32, ctx); 604 return; 605 } 606 607 /* Oh well, we tried... Do a full 64-bit decomposition. */ 608 ctx->tmp_1_used = true; 609 610 emit_loadimm32(high_bits, tmp, ctx); 611 emit_loadimm32(low_bits, dest, ctx); 612 emit_alu_K(SLLX, tmp, 32, ctx); 613 emit(OR | RS1(dest) | RS2(tmp) | RD(dest), ctx); 614 } 615 616 static void emit_branch(unsigned int br_opc, unsigned int from_idx, unsigned int to_idx, 617 struct jit_ctx *ctx) 618 { 619 unsigned int off = to_idx - from_idx; 620 621 if (br_opc & XCC) 622 emit(br_opc | WDISP19(off << 2), ctx); 623 else 624 emit(br_opc | WDISP22(off << 2), ctx); 625 } 626 627 static void emit_cbcond(unsigned int cb_opc, unsigned int from_idx, unsigned int to_idx, 628 const u8 dst, const u8 src, struct jit_ctx *ctx) 629 { 630 unsigned int off = to_idx - from_idx; 631 632 emit(cb_opc | WDISP10(off << 2) | RS1(dst) | RS2(src), ctx); 633 } 634 635 static void emit_cbcondi(unsigned int cb_opc, unsigned int from_idx, unsigned int to_idx, 636 const u8 dst, s32 imm, struct jit_ctx *ctx) 637 { 638 unsigned int off = to_idx - from_idx; 639 640 emit(cb_opc | IMMED | WDISP10(off << 2) | RS1(dst) | S5(imm), ctx); 641 } 642 643 #define emit_read_y(REG, CTX) emit(RD_Y | RD(REG), CTX) 644 #define emit_write_y(REG, CTX) emit(WR_Y | IMMED | RS1(REG) | S13(0), CTX) 645 646 #define emit_cmp(R1, R2, CTX) \ 647 emit(SUBCC | RS1(R1) | RS2(R2) | RD(G0), CTX) 648 649 #define emit_cmpi(R1, IMM, CTX) \ 650 emit(SUBCC | IMMED | RS1(R1) | S13(IMM) | RD(G0), CTX) 651 652 #define emit_btst(R1, R2, CTX) \ 653 emit(ANDCC | RS1(R1) | RS2(R2) | RD(G0), CTX) 654 655 #define emit_btsti(R1, IMM, CTX) \ 656 emit(ANDCC | IMMED | RS1(R1) | S13(IMM) | RD(G0), CTX) 657 658 static int emit_compare_and_branch(const u8 code, const u8 dst, u8 src, 659 const s32 imm, bool is_imm, int branch_dst, 660 struct jit_ctx *ctx) 661 { 662 bool use_cbcond = (sparc64_elf_hwcap & AV_SPARC_CBCOND) != 0; 663 const u8 tmp = bpf2sparc[TMP_REG_1]; 664 665 branch_dst = ctx->offset[branch_dst]; 666 667 if (!is_simm10(branch_dst - ctx->idx) || 668 BPF_OP(code) == BPF_JSET) 669 use_cbcond = false; 670 671 if (is_imm) { 672 bool fits = true; 673 674 if (use_cbcond) { 675 if (!is_simm5(imm)) 676 fits = false; 677 } else if (!is_simm13(imm)) { 678 fits = false; 679 } 680 if (!fits) { 681 ctx->tmp_1_used = true; 682 emit_loadimm_sext(imm, tmp, ctx); 683 src = tmp; 684 is_imm = false; 685 } 686 } 687 688 if (!use_cbcond) { 689 u32 br_opcode; 690 691 if (BPF_OP(code) == BPF_JSET) { 692 if (is_imm) 693 emit_btsti(dst, imm, ctx); 694 else 695 emit_btst(dst, src, ctx); 696 } else { 697 if (is_imm) 698 emit_cmpi(dst, imm, ctx); 699 else 700 emit_cmp(dst, src, ctx); 701 } 702 switch (BPF_OP(code)) { 703 case BPF_JEQ: 704 br_opcode = BE; 705 break; 706 case BPF_JGT: 707 br_opcode = BGU; 708 break; 709 case BPF_JLT: 710 br_opcode = BLU; 711 break; 712 case BPF_JGE: 713 br_opcode = BGEU; 714 break; 715 case BPF_JLE: 716 br_opcode = BLEU; 717 break; 718 case BPF_JSET: 719 case BPF_JNE: 720 br_opcode = BNE; 721 break; 722 case BPF_JSGT: 723 br_opcode = BG; 724 break; 725 case BPF_JSLT: 726 br_opcode = BL; 727 break; 728 case BPF_JSGE: 729 br_opcode = BGE; 730 break; 731 case BPF_JSLE: 732 br_opcode = BLE; 733 break; 734 default: 735 /* Make sure we dont leak kernel information to the 736 * user. 737 */ 738 return -EFAULT; 739 } 740 emit_branch(br_opcode, ctx->idx, branch_dst, ctx); 741 emit_nop(ctx); 742 } else { 743 u32 cbcond_opcode; 744 745 switch (BPF_OP(code)) { 746 case BPF_JEQ: 747 cbcond_opcode = CBCONDE; 748 break; 749 case BPF_JGT: 750 cbcond_opcode = CBCONDGU; 751 break; 752 case BPF_JLT: 753 cbcond_opcode = CBCONDLU; 754 break; 755 case BPF_JGE: 756 cbcond_opcode = CBCONDGEU; 757 break; 758 case BPF_JLE: 759 cbcond_opcode = CBCONDLEU; 760 break; 761 case BPF_JNE: 762 cbcond_opcode = CBCONDNE; 763 break; 764 case BPF_JSGT: 765 cbcond_opcode = CBCONDG; 766 break; 767 case BPF_JSLT: 768 cbcond_opcode = CBCONDL; 769 break; 770 case BPF_JSGE: 771 cbcond_opcode = CBCONDGE; 772 break; 773 case BPF_JSLE: 774 cbcond_opcode = CBCONDLE; 775 break; 776 default: 777 /* Make sure we dont leak kernel information to the 778 * user. 779 */ 780 return -EFAULT; 781 } 782 cbcond_opcode |= CBCOND_OP; 783 if (is_imm) 784 emit_cbcondi(cbcond_opcode, ctx->idx, branch_dst, 785 dst, imm, ctx); 786 else 787 emit_cbcond(cbcond_opcode, ctx->idx, branch_dst, 788 dst, src, ctx); 789 } 790 return 0; 791 } 792 793 /* Just skip the save instruction and the ctx register move. */ 794 #define BPF_TAILCALL_PROLOGUE_SKIP 16 795 #define BPF_TAILCALL_CNT_SP_OFF (STACK_BIAS + 128) 796 797 static void build_prologue(struct jit_ctx *ctx) 798 { 799 s32 stack_needed = BASE_STACKFRAME; 800 801 if (ctx->saw_frame_pointer || ctx->saw_tail_call) { 802 struct bpf_prog *prog = ctx->prog; 803 u32 stack_depth; 804 805 stack_depth = prog->aux->stack_depth; 806 stack_needed += round_up(stack_depth, 16); 807 } 808 809 if (ctx->saw_tail_call) 810 stack_needed += 8; 811 812 /* save %sp, -176, %sp */ 813 emit(SAVE | IMMED | RS1(SP) | S13(-stack_needed) | RD(SP), ctx); 814 815 /* tail_call_cnt = 0 */ 816 if (ctx->saw_tail_call) { 817 u32 off = BPF_TAILCALL_CNT_SP_OFF; 818 819 emit(ST32 | IMMED | RS1(SP) | S13(off) | RD(G0), ctx); 820 } else { 821 emit_nop(ctx); 822 } 823 if (ctx->saw_frame_pointer) { 824 const u8 vfp = bpf2sparc[BPF_REG_FP]; 825 826 emit(ADD | IMMED | RS1(FP) | S13(STACK_BIAS) | RD(vfp), ctx); 827 } 828 829 emit_reg_move(I0, O0, ctx); 830 /* If you add anything here, adjust BPF_TAILCALL_PROLOGUE_SKIP above. */ 831 } 832 833 static void build_epilogue(struct jit_ctx *ctx) 834 { 835 ctx->epilogue_offset = ctx->idx; 836 837 /* ret (jmpl %i7 + 8, %g0) */ 838 emit(JMPL | IMMED | RS1(I7) | S13(8) | RD(G0), ctx); 839 840 /* restore %i5, %g0, %o0 */ 841 emit(RESTORE | RS1(bpf2sparc[BPF_REG_0]) | RS2(G0) | RD(O0), ctx); 842 } 843 844 static void emit_tail_call(struct jit_ctx *ctx) 845 { 846 const u8 bpf_array = bpf2sparc[BPF_REG_2]; 847 const u8 bpf_index = bpf2sparc[BPF_REG_3]; 848 const u8 tmp = bpf2sparc[TMP_REG_1]; 849 u32 off; 850 851 ctx->saw_tail_call = true; 852 853 off = offsetof(struct bpf_array, map.max_entries); 854 emit(LD32 | IMMED | RS1(bpf_array) | S13(off) | RD(tmp), ctx); 855 emit_cmp(bpf_index, tmp, ctx); 856 #define OFFSET1 17 857 emit_branch(BGEU, ctx->idx, ctx->idx + OFFSET1, ctx); 858 emit_nop(ctx); 859 860 off = BPF_TAILCALL_CNT_SP_OFF; 861 emit(LD32 | IMMED | RS1(SP) | S13(off) | RD(tmp), ctx); 862 emit_cmpi(tmp, MAX_TAIL_CALL_CNT, ctx); 863 #define OFFSET2 13 864 emit_branch(BGU, ctx->idx, ctx->idx + OFFSET2, ctx); 865 emit_nop(ctx); 866 867 emit_alu_K(ADD, tmp, 1, ctx); 868 off = BPF_TAILCALL_CNT_SP_OFF; 869 emit(ST32 | IMMED | RS1(SP) | S13(off) | RD(tmp), ctx); 870 871 emit_alu3_K(SLL, bpf_index, 3, tmp, ctx); 872 emit_alu(ADD, bpf_array, tmp, ctx); 873 off = offsetof(struct bpf_array, ptrs); 874 emit(LD64 | IMMED | RS1(tmp) | S13(off) | RD(tmp), ctx); 875 876 emit_cmpi(tmp, 0, ctx); 877 #define OFFSET3 5 878 emit_branch(BE, ctx->idx, ctx->idx + OFFSET3, ctx); 879 emit_nop(ctx); 880 881 off = offsetof(struct bpf_prog, bpf_func); 882 emit(LD64 | IMMED | RS1(tmp) | S13(off) | RD(tmp), ctx); 883 884 off = BPF_TAILCALL_PROLOGUE_SKIP; 885 emit(JMPL | IMMED | RS1(tmp) | S13(off) | RD(G0), ctx); 886 emit_nop(ctx); 887 } 888 889 static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx) 890 { 891 const u8 code = insn->code; 892 const u8 dst = bpf2sparc[insn->dst_reg]; 893 const u8 src = bpf2sparc[insn->src_reg]; 894 const int i = insn - ctx->prog->insnsi; 895 const s16 off = insn->off; 896 const s32 imm = insn->imm; 897 898 if (insn->src_reg == BPF_REG_FP) 899 ctx->saw_frame_pointer = true; 900 901 switch (code) { 902 /* dst = src */ 903 case BPF_ALU | BPF_MOV | BPF_X: 904 emit_alu3_K(SRL, src, 0, dst, ctx); 905 break; 906 case BPF_ALU64 | BPF_MOV | BPF_X: 907 emit_reg_move(src, dst, ctx); 908 break; 909 /* dst = dst OP src */ 910 case BPF_ALU | BPF_ADD | BPF_X: 911 case BPF_ALU64 | BPF_ADD | BPF_X: 912 emit_alu(ADD, src, dst, ctx); 913 goto do_alu32_trunc; 914 case BPF_ALU | BPF_SUB | BPF_X: 915 case BPF_ALU64 | BPF_SUB | BPF_X: 916 emit_alu(SUB, src, dst, ctx); 917 goto do_alu32_trunc; 918 case BPF_ALU | BPF_AND | BPF_X: 919 case BPF_ALU64 | BPF_AND | BPF_X: 920 emit_alu(AND, src, dst, ctx); 921 goto do_alu32_trunc; 922 case BPF_ALU | BPF_OR | BPF_X: 923 case BPF_ALU64 | BPF_OR | BPF_X: 924 emit_alu(OR, src, dst, ctx); 925 goto do_alu32_trunc; 926 case BPF_ALU | BPF_XOR | BPF_X: 927 case BPF_ALU64 | BPF_XOR | BPF_X: 928 emit_alu(XOR, src, dst, ctx); 929 goto do_alu32_trunc; 930 case BPF_ALU | BPF_MUL | BPF_X: 931 emit_alu(MUL, src, dst, ctx); 932 goto do_alu32_trunc; 933 case BPF_ALU64 | BPF_MUL | BPF_X: 934 emit_alu(MULX, src, dst, ctx); 935 break; 936 case BPF_ALU | BPF_DIV | BPF_X: 937 emit_write_y(G0, ctx); 938 emit_alu(DIV, src, dst, ctx); 939 break; 940 case BPF_ALU64 | BPF_DIV | BPF_X: 941 emit_alu(UDIVX, src, dst, ctx); 942 break; 943 case BPF_ALU | BPF_MOD | BPF_X: { 944 const u8 tmp = bpf2sparc[TMP_REG_1]; 945 946 ctx->tmp_1_used = true; 947 948 emit_write_y(G0, ctx); 949 emit_alu3(DIV, dst, src, tmp, ctx); 950 emit_alu3(MULX, tmp, src, tmp, ctx); 951 emit_alu3(SUB, dst, tmp, dst, ctx); 952 goto do_alu32_trunc; 953 } 954 case BPF_ALU64 | BPF_MOD | BPF_X: { 955 const u8 tmp = bpf2sparc[TMP_REG_1]; 956 957 ctx->tmp_1_used = true; 958 959 emit_alu3(UDIVX, dst, src, tmp, ctx); 960 emit_alu3(MULX, tmp, src, tmp, ctx); 961 emit_alu3(SUB, dst, tmp, dst, ctx); 962 break; 963 } 964 case BPF_ALU | BPF_LSH | BPF_X: 965 emit_alu(SLL, src, dst, ctx); 966 goto do_alu32_trunc; 967 case BPF_ALU64 | BPF_LSH | BPF_X: 968 emit_alu(SLLX, src, dst, ctx); 969 break; 970 case BPF_ALU | BPF_RSH | BPF_X: 971 emit_alu(SRL, src, dst, ctx); 972 break; 973 case BPF_ALU64 | BPF_RSH | BPF_X: 974 emit_alu(SRLX, src, dst, ctx); 975 break; 976 case BPF_ALU | BPF_ARSH | BPF_X: 977 emit_alu(SRA, src, dst, ctx); 978 goto do_alu32_trunc; 979 case BPF_ALU64 | BPF_ARSH | BPF_X: 980 emit_alu(SRAX, src, dst, ctx); 981 break; 982 983 /* dst = -dst */ 984 case BPF_ALU | BPF_NEG: 985 case BPF_ALU64 | BPF_NEG: 986 emit(SUB | RS1(0) | RS2(dst) | RD(dst), ctx); 987 goto do_alu32_trunc; 988 989 case BPF_ALU | BPF_END | BPF_FROM_BE: 990 switch (imm) { 991 case 16: 992 emit_alu_K(SLL, dst, 16, ctx); 993 emit_alu_K(SRL, dst, 16, ctx); 994 break; 995 case 32: 996 emit_alu_K(SRL, dst, 0, ctx); 997 break; 998 case 64: 999 /* nop */ 1000 break; 1001 1002 } 1003 break; 1004 1005 /* dst = BSWAP##imm(dst) */ 1006 case BPF_ALU | BPF_END | BPF_FROM_LE: { 1007 const u8 tmp = bpf2sparc[TMP_REG_1]; 1008 const u8 tmp2 = bpf2sparc[TMP_REG_2]; 1009 1010 ctx->tmp_1_used = true; 1011 switch (imm) { 1012 case 16: 1013 emit_alu3_K(AND, dst, 0xff, tmp, ctx); 1014 emit_alu3_K(SRL, dst, 8, dst, ctx); 1015 emit_alu3_K(AND, dst, 0xff, dst, ctx); 1016 emit_alu3_K(SLL, tmp, 8, tmp, ctx); 1017 emit_alu(OR, tmp, dst, ctx); 1018 break; 1019 1020 case 32: 1021 ctx->tmp_2_used = true; 1022 emit_alu3_K(SRL, dst, 24, tmp, ctx); /* tmp = dst >> 24 */ 1023 emit_alu3_K(SRL, dst, 16, tmp2, ctx); /* tmp2 = dst >> 16 */ 1024 emit_alu3_K(AND, tmp2, 0xff, tmp2, ctx);/* tmp2 = tmp2 & 0xff */ 1025 emit_alu3_K(SLL, tmp2, 8, tmp2, ctx); /* tmp2 = tmp2 << 8 */ 1026 emit_alu(OR, tmp2, tmp, ctx); /* tmp = tmp | tmp2 */ 1027 emit_alu3_K(SRL, dst, 8, tmp2, ctx); /* tmp2 = dst >> 8 */ 1028 emit_alu3_K(AND, tmp2, 0xff, tmp2, ctx);/* tmp2 = tmp2 & 0xff */ 1029 emit_alu3_K(SLL, tmp2, 16, tmp2, ctx); /* tmp2 = tmp2 << 16 */ 1030 emit_alu(OR, tmp2, tmp, ctx); /* tmp = tmp | tmp2 */ 1031 emit_alu3_K(AND, dst, 0xff, dst, ctx); /* dst = dst & 0xff */ 1032 emit_alu3_K(SLL, dst, 24, dst, ctx); /* dst = dst << 24 */ 1033 emit_alu(OR, tmp, dst, ctx); /* dst = dst | tmp */ 1034 break; 1035 1036 case 64: 1037 emit_alu3_K(ADD, SP, STACK_BIAS + 128, tmp, ctx); 1038 emit(ST64 | RS1(tmp) | RS2(G0) | RD(dst), ctx); 1039 emit(LD64A | ASI(ASI_PL) | RS1(tmp) | RS2(G0) | RD(dst), ctx); 1040 break; 1041 } 1042 break; 1043 } 1044 /* dst = imm */ 1045 case BPF_ALU | BPF_MOV | BPF_K: 1046 emit_loadimm32(imm, dst, ctx); 1047 break; 1048 case BPF_ALU64 | BPF_MOV | BPF_K: 1049 emit_loadimm_sext(imm, dst, ctx); 1050 break; 1051 /* dst = dst OP imm */ 1052 case BPF_ALU | BPF_ADD | BPF_K: 1053 case BPF_ALU64 | BPF_ADD | BPF_K: 1054 emit_alu_K(ADD, dst, imm, ctx); 1055 goto do_alu32_trunc; 1056 case BPF_ALU | BPF_SUB | BPF_K: 1057 case BPF_ALU64 | BPF_SUB | BPF_K: 1058 emit_alu_K(SUB, dst, imm, ctx); 1059 goto do_alu32_trunc; 1060 case BPF_ALU | BPF_AND | BPF_K: 1061 case BPF_ALU64 | BPF_AND | BPF_K: 1062 emit_alu_K(AND, dst, imm, ctx); 1063 goto do_alu32_trunc; 1064 case BPF_ALU | BPF_OR | BPF_K: 1065 case BPF_ALU64 | BPF_OR | BPF_K: 1066 emit_alu_K(OR, dst, imm, ctx); 1067 goto do_alu32_trunc; 1068 case BPF_ALU | BPF_XOR | BPF_K: 1069 case BPF_ALU64 | BPF_XOR | BPF_K: 1070 emit_alu_K(XOR, dst, imm, ctx); 1071 goto do_alu32_trunc; 1072 case BPF_ALU | BPF_MUL | BPF_K: 1073 emit_alu_K(MUL, dst, imm, ctx); 1074 goto do_alu32_trunc; 1075 case BPF_ALU64 | BPF_MUL | BPF_K: 1076 emit_alu_K(MULX, dst, imm, ctx); 1077 break; 1078 case BPF_ALU | BPF_DIV | BPF_K: 1079 if (imm == 0) 1080 return -EINVAL; 1081 1082 emit_write_y(G0, ctx); 1083 emit_alu_K(DIV, dst, imm, ctx); 1084 goto do_alu32_trunc; 1085 case BPF_ALU64 | BPF_DIV | BPF_K: 1086 if (imm == 0) 1087 return -EINVAL; 1088 1089 emit_alu_K(UDIVX, dst, imm, ctx); 1090 break; 1091 case BPF_ALU64 | BPF_MOD | BPF_K: 1092 case BPF_ALU | BPF_MOD | BPF_K: { 1093 const u8 tmp = bpf2sparc[TMP_REG_2]; 1094 unsigned int div; 1095 1096 if (imm == 0) 1097 return -EINVAL; 1098 1099 div = (BPF_CLASS(code) == BPF_ALU64) ? UDIVX : DIV; 1100 1101 ctx->tmp_2_used = true; 1102 1103 if (BPF_CLASS(code) != BPF_ALU64) 1104 emit_write_y(G0, ctx); 1105 if (is_simm13(imm)) { 1106 emit(div | IMMED | RS1(dst) | S13(imm) | RD(tmp), ctx); 1107 emit(MULX | IMMED | RS1(tmp) | S13(imm) | RD(tmp), ctx); 1108 emit(SUB | RS1(dst) | RS2(tmp) | RD(dst), ctx); 1109 } else { 1110 const u8 tmp1 = bpf2sparc[TMP_REG_1]; 1111 1112 ctx->tmp_1_used = true; 1113 1114 emit_set_const_sext(imm, tmp1, ctx); 1115 emit(div | RS1(dst) | RS2(tmp1) | RD(tmp), ctx); 1116 emit(MULX | RS1(tmp) | RS2(tmp1) | RD(tmp), ctx); 1117 emit(SUB | RS1(dst) | RS2(tmp) | RD(dst), ctx); 1118 } 1119 goto do_alu32_trunc; 1120 } 1121 case BPF_ALU | BPF_LSH | BPF_K: 1122 emit_alu_K(SLL, dst, imm, ctx); 1123 goto do_alu32_trunc; 1124 case BPF_ALU64 | BPF_LSH | BPF_K: 1125 emit_alu_K(SLLX, dst, imm, ctx); 1126 break; 1127 case BPF_ALU | BPF_RSH | BPF_K: 1128 emit_alu_K(SRL, dst, imm, ctx); 1129 break; 1130 case BPF_ALU64 | BPF_RSH | BPF_K: 1131 emit_alu_K(SRLX, dst, imm, ctx); 1132 break; 1133 case BPF_ALU | BPF_ARSH | BPF_K: 1134 emit_alu_K(SRA, dst, imm, ctx); 1135 goto do_alu32_trunc; 1136 case BPF_ALU64 | BPF_ARSH | BPF_K: 1137 emit_alu_K(SRAX, dst, imm, ctx); 1138 break; 1139 1140 do_alu32_trunc: 1141 if (BPF_CLASS(code) == BPF_ALU) 1142 emit_alu_K(SRL, dst, 0, ctx); 1143 break; 1144 1145 /* JUMP off */ 1146 case BPF_JMP | BPF_JA: 1147 emit_branch(BA, ctx->idx, ctx->offset[i + off], ctx); 1148 emit_nop(ctx); 1149 break; 1150 /* IF (dst COND src) JUMP off */ 1151 case BPF_JMP | BPF_JEQ | BPF_X: 1152 case BPF_JMP | BPF_JGT | BPF_X: 1153 case BPF_JMP | BPF_JLT | BPF_X: 1154 case BPF_JMP | BPF_JGE | BPF_X: 1155 case BPF_JMP | BPF_JLE | BPF_X: 1156 case BPF_JMP | BPF_JNE | BPF_X: 1157 case BPF_JMP | BPF_JSGT | BPF_X: 1158 case BPF_JMP | BPF_JSLT | BPF_X: 1159 case BPF_JMP | BPF_JSGE | BPF_X: 1160 case BPF_JMP | BPF_JSLE | BPF_X: 1161 case BPF_JMP | BPF_JSET | BPF_X: { 1162 int err; 1163 1164 err = emit_compare_and_branch(code, dst, src, 0, false, i + off, ctx); 1165 if (err) 1166 return err; 1167 break; 1168 } 1169 /* IF (dst COND imm) JUMP off */ 1170 case BPF_JMP | BPF_JEQ | BPF_K: 1171 case BPF_JMP | BPF_JGT | BPF_K: 1172 case BPF_JMP | BPF_JLT | BPF_K: 1173 case BPF_JMP | BPF_JGE | BPF_K: 1174 case BPF_JMP | BPF_JLE | BPF_K: 1175 case BPF_JMP | BPF_JNE | BPF_K: 1176 case BPF_JMP | BPF_JSGT | BPF_K: 1177 case BPF_JMP | BPF_JSLT | BPF_K: 1178 case BPF_JMP | BPF_JSGE | BPF_K: 1179 case BPF_JMP | BPF_JSLE | BPF_K: 1180 case BPF_JMP | BPF_JSET | BPF_K: { 1181 int err; 1182 1183 err = emit_compare_and_branch(code, dst, 0, imm, true, i + off, ctx); 1184 if (err) 1185 return err; 1186 break; 1187 } 1188 1189 /* function call */ 1190 case BPF_JMP | BPF_CALL: 1191 { 1192 u8 *func = ((u8 *)__bpf_call_base) + imm; 1193 1194 ctx->saw_call = true; 1195 1196 emit_call((u32 *)func, ctx); 1197 emit_nop(ctx); 1198 1199 emit_reg_move(O0, bpf2sparc[BPF_REG_0], ctx); 1200 break; 1201 } 1202 1203 /* tail call */ 1204 case BPF_JMP | BPF_TAIL_CALL: 1205 emit_tail_call(ctx); 1206 break; 1207 1208 /* function return */ 1209 case BPF_JMP | BPF_EXIT: 1210 /* Optimization: when last instruction is EXIT, 1211 simply fallthrough to epilogue. */ 1212 if (i == ctx->prog->len - 1) 1213 break; 1214 emit_branch(BA, ctx->idx, ctx->epilogue_offset, ctx); 1215 emit_nop(ctx); 1216 break; 1217 1218 /* dst = imm64 */ 1219 case BPF_LD | BPF_IMM | BPF_DW: 1220 { 1221 const struct bpf_insn insn1 = insn[1]; 1222 u64 imm64; 1223 1224 imm64 = (u64)insn1.imm << 32 | (u32)imm; 1225 emit_loadimm64(imm64, dst, ctx); 1226 1227 return 1; 1228 } 1229 1230 /* LDX: dst = *(size *)(src + off) */ 1231 case BPF_LDX | BPF_MEM | BPF_W: 1232 case BPF_LDX | BPF_MEM | BPF_H: 1233 case BPF_LDX | BPF_MEM | BPF_B: 1234 case BPF_LDX | BPF_MEM | BPF_DW: { 1235 const u8 tmp = bpf2sparc[TMP_REG_1]; 1236 u32 opcode = 0, rs2; 1237 1238 ctx->tmp_1_used = true; 1239 switch (BPF_SIZE(code)) { 1240 case BPF_W: 1241 opcode = LD32; 1242 break; 1243 case BPF_H: 1244 opcode = LD16; 1245 break; 1246 case BPF_B: 1247 opcode = LD8; 1248 break; 1249 case BPF_DW: 1250 opcode = LD64; 1251 break; 1252 } 1253 1254 if (is_simm13(off)) { 1255 opcode |= IMMED; 1256 rs2 = S13(off); 1257 } else { 1258 emit_loadimm(off, tmp, ctx); 1259 rs2 = RS2(tmp); 1260 } 1261 emit(opcode | RS1(src) | rs2 | RD(dst), ctx); 1262 break; 1263 } 1264 /* ST: *(size *)(dst + off) = imm */ 1265 case BPF_ST | BPF_MEM | BPF_W: 1266 case BPF_ST | BPF_MEM | BPF_H: 1267 case BPF_ST | BPF_MEM | BPF_B: 1268 case BPF_ST | BPF_MEM | BPF_DW: { 1269 const u8 tmp = bpf2sparc[TMP_REG_1]; 1270 const u8 tmp2 = bpf2sparc[TMP_REG_2]; 1271 u32 opcode = 0, rs2; 1272 1273 ctx->tmp_2_used = true; 1274 emit_loadimm(imm, tmp2, ctx); 1275 1276 switch (BPF_SIZE(code)) { 1277 case BPF_W: 1278 opcode = ST32; 1279 break; 1280 case BPF_H: 1281 opcode = ST16; 1282 break; 1283 case BPF_B: 1284 opcode = ST8; 1285 break; 1286 case BPF_DW: 1287 opcode = ST64; 1288 break; 1289 } 1290 1291 if (is_simm13(off)) { 1292 opcode |= IMMED; 1293 rs2 = S13(off); 1294 } else { 1295 ctx->tmp_1_used = true; 1296 emit_loadimm(off, tmp, ctx); 1297 rs2 = RS2(tmp); 1298 } 1299 emit(opcode | RS1(dst) | rs2 | RD(tmp2), ctx); 1300 break; 1301 } 1302 1303 /* STX: *(size *)(dst + off) = src */ 1304 case BPF_STX | BPF_MEM | BPF_W: 1305 case BPF_STX | BPF_MEM | BPF_H: 1306 case BPF_STX | BPF_MEM | BPF_B: 1307 case BPF_STX | BPF_MEM | BPF_DW: { 1308 const u8 tmp = bpf2sparc[TMP_REG_1]; 1309 u32 opcode = 0, rs2; 1310 1311 switch (BPF_SIZE(code)) { 1312 case BPF_W: 1313 opcode = ST32; 1314 break; 1315 case BPF_H: 1316 opcode = ST16; 1317 break; 1318 case BPF_B: 1319 opcode = ST8; 1320 break; 1321 case BPF_DW: 1322 opcode = ST64; 1323 break; 1324 } 1325 if (is_simm13(off)) { 1326 opcode |= IMMED; 1327 rs2 = S13(off); 1328 } else { 1329 ctx->tmp_1_used = true; 1330 emit_loadimm(off, tmp, ctx); 1331 rs2 = RS2(tmp); 1332 } 1333 emit(opcode | RS1(dst) | rs2 | RD(src), ctx); 1334 break; 1335 } 1336 1337 /* STX XADD: lock *(u32 *)(dst + off) += src */ 1338 case BPF_STX | BPF_XADD | BPF_W: { 1339 const u8 tmp = bpf2sparc[TMP_REG_1]; 1340 const u8 tmp2 = bpf2sparc[TMP_REG_2]; 1341 const u8 tmp3 = bpf2sparc[TMP_REG_3]; 1342 1343 ctx->tmp_1_used = true; 1344 ctx->tmp_2_used = true; 1345 ctx->tmp_3_used = true; 1346 emit_loadimm(off, tmp, ctx); 1347 emit_alu3(ADD, dst, tmp, tmp, ctx); 1348 1349 emit(LD32 | RS1(tmp) | RS2(G0) | RD(tmp2), ctx); 1350 emit_alu3(ADD, tmp2, src, tmp3, ctx); 1351 emit(CAS | ASI(ASI_P) | RS1(tmp) | RS2(tmp2) | RD(tmp3), ctx); 1352 emit_cmp(tmp2, tmp3, ctx); 1353 emit_branch(BNE, 4, 0, ctx); 1354 emit_nop(ctx); 1355 break; 1356 } 1357 /* STX XADD: lock *(u64 *)(dst + off) += src */ 1358 case BPF_STX | BPF_XADD | BPF_DW: { 1359 const u8 tmp = bpf2sparc[TMP_REG_1]; 1360 const u8 tmp2 = bpf2sparc[TMP_REG_2]; 1361 const u8 tmp3 = bpf2sparc[TMP_REG_3]; 1362 1363 ctx->tmp_1_used = true; 1364 ctx->tmp_2_used = true; 1365 ctx->tmp_3_used = true; 1366 emit_loadimm(off, tmp, ctx); 1367 emit_alu3(ADD, dst, tmp, tmp, ctx); 1368 1369 emit(LD64 | RS1(tmp) | RS2(G0) | RD(tmp2), ctx); 1370 emit_alu3(ADD, tmp2, src, tmp3, ctx); 1371 emit(CASX | ASI(ASI_P) | RS1(tmp) | RS2(tmp2) | RD(tmp3), ctx); 1372 emit_cmp(tmp2, tmp3, ctx); 1373 emit_branch(BNE, 4, 0, ctx); 1374 emit_nop(ctx); 1375 break; 1376 } 1377 1378 default: 1379 pr_err_once("unknown opcode %02x\n", code); 1380 return -EINVAL; 1381 } 1382 1383 return 0; 1384 } 1385 1386 static int build_body(struct jit_ctx *ctx) 1387 { 1388 const struct bpf_prog *prog = ctx->prog; 1389 int i; 1390 1391 for (i = 0; i < prog->len; i++) { 1392 const struct bpf_insn *insn = &prog->insnsi[i]; 1393 int ret; 1394 1395 ret = build_insn(insn, ctx); 1396 1397 if (ret > 0) { 1398 i++; 1399 ctx->offset[i] = ctx->idx; 1400 continue; 1401 } 1402 ctx->offset[i] = ctx->idx; 1403 if (ret) 1404 return ret; 1405 } 1406 return 0; 1407 } 1408 1409 static void jit_fill_hole(void *area, unsigned int size) 1410 { 1411 u32 *ptr; 1412 /* We are guaranteed to have aligned memory. */ 1413 for (ptr = area; size >= sizeof(u32); size -= sizeof(u32)) 1414 *ptr++ = 0x91d02005; /* ta 5 */ 1415 } 1416 1417 struct sparc64_jit_data { 1418 struct bpf_binary_header *header; 1419 u8 *image; 1420 struct jit_ctx ctx; 1421 }; 1422 1423 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog) 1424 { 1425 struct bpf_prog *tmp, *orig_prog = prog; 1426 struct sparc64_jit_data *jit_data; 1427 struct bpf_binary_header *header; 1428 bool tmp_blinded = false; 1429 bool extra_pass = false; 1430 struct jit_ctx ctx; 1431 u32 image_size; 1432 u8 *image_ptr; 1433 int pass; 1434 1435 if (!prog->jit_requested) 1436 return orig_prog; 1437 1438 tmp = bpf_jit_blind_constants(prog); 1439 /* If blinding was requested and we failed during blinding, 1440 * we must fall back to the interpreter. 1441 */ 1442 if (IS_ERR(tmp)) 1443 return orig_prog; 1444 if (tmp != prog) { 1445 tmp_blinded = true; 1446 prog = tmp; 1447 } 1448 1449 jit_data = prog->aux->jit_data; 1450 if (!jit_data) { 1451 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL); 1452 if (!jit_data) { 1453 prog = orig_prog; 1454 goto out; 1455 } 1456 prog->aux->jit_data = jit_data; 1457 } 1458 if (jit_data->ctx.offset) { 1459 ctx = jit_data->ctx; 1460 image_ptr = jit_data->image; 1461 header = jit_data->header; 1462 extra_pass = true; 1463 image_size = sizeof(u32) * ctx.idx; 1464 goto skip_init_ctx; 1465 } 1466 1467 memset(&ctx, 0, sizeof(ctx)); 1468 ctx.prog = prog; 1469 1470 ctx.offset = kcalloc(prog->len, sizeof(unsigned int), GFP_KERNEL); 1471 if (ctx.offset == NULL) { 1472 prog = orig_prog; 1473 goto out_off; 1474 } 1475 1476 /* Fake pass to detect features used, and get an accurate assessment 1477 * of what the final image size will be. 1478 */ 1479 if (build_body(&ctx)) { 1480 prog = orig_prog; 1481 goto out_off; 1482 } 1483 build_prologue(&ctx); 1484 build_epilogue(&ctx); 1485 1486 /* Now we know the actual image size. */ 1487 image_size = sizeof(u32) * ctx.idx; 1488 header = bpf_jit_binary_alloc(image_size, &image_ptr, 1489 sizeof(u32), jit_fill_hole); 1490 if (header == NULL) { 1491 prog = orig_prog; 1492 goto out_off; 1493 } 1494 1495 ctx.image = (u32 *)image_ptr; 1496 skip_init_ctx: 1497 for (pass = 1; pass < 3; pass++) { 1498 ctx.idx = 0; 1499 1500 build_prologue(&ctx); 1501 1502 if (build_body(&ctx)) { 1503 bpf_jit_binary_free(header); 1504 prog = orig_prog; 1505 goto out_off; 1506 } 1507 1508 build_epilogue(&ctx); 1509 1510 if (bpf_jit_enable > 1) 1511 pr_info("Pass %d: shrink = %d, seen = [%c%c%c%c%c%c]\n", pass, 1512 image_size - (ctx.idx * 4), 1513 ctx.tmp_1_used ? '1' : ' ', 1514 ctx.tmp_2_used ? '2' : ' ', 1515 ctx.tmp_3_used ? '3' : ' ', 1516 ctx.saw_frame_pointer ? 'F' : ' ', 1517 ctx.saw_call ? 'C' : ' ', 1518 ctx.saw_tail_call ? 'T' : ' '); 1519 } 1520 1521 if (bpf_jit_enable > 1) 1522 bpf_jit_dump(prog->len, image_size, pass, ctx.image); 1523 1524 bpf_flush_icache(header, (u8 *)header + (header->pages * PAGE_SIZE)); 1525 1526 if (!prog->is_func || extra_pass) { 1527 bpf_jit_binary_lock_ro(header); 1528 } else { 1529 jit_data->ctx = ctx; 1530 jit_data->image = image_ptr; 1531 jit_data->header = header; 1532 } 1533 1534 prog->bpf_func = (void *)ctx.image; 1535 prog->jited = 1; 1536 prog->jited_len = image_size; 1537 1538 if (!prog->is_func || extra_pass) { 1539 out_off: 1540 kfree(ctx.offset); 1541 kfree(jit_data); 1542 prog->aux->jit_data = NULL; 1543 } 1544 out: 1545 if (tmp_blinded) 1546 bpf_jit_prog_release_other(prog, prog == orig_prog ? 1547 tmp : orig_prog); 1548 return prog; 1549 } 1550