1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * srmmu.c: SRMMU specific routines for memory management. 4 * 5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 6 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com) 7 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) 8 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 9 * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org) 10 */ 11 12 #include <linux/seq_file.h> 13 #include <linux/spinlock.h> 14 #include <linux/memblock.h> 15 #include <linux/pagemap.h> 16 #include <linux/vmalloc.h> 17 #include <linux/kdebug.h> 18 #include <linux/export.h> 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/log2.h> 22 #include <linux/gfp.h> 23 #include <linux/fs.h> 24 #include <linux/mm.h> 25 26 #include <asm/mmu_context.h> 27 #include <asm/cacheflush.h> 28 #include <asm/tlbflush.h> 29 #include <asm/io-unit.h> 30 #include <asm/pgalloc.h> 31 #include <asm/pgtable.h> 32 #include <asm/bitext.h> 33 #include <asm/vaddrs.h> 34 #include <asm/cache.h> 35 #include <asm/traps.h> 36 #include <asm/oplib.h> 37 #include <asm/mbus.h> 38 #include <asm/page.h> 39 #include <asm/asi.h> 40 #include <asm/smp.h> 41 #include <asm/io.h> 42 43 /* Now the cpu specific definitions. */ 44 #include <asm/turbosparc.h> 45 #include <asm/tsunami.h> 46 #include <asm/viking.h> 47 #include <asm/swift.h> 48 #include <asm/leon.h> 49 #include <asm/mxcc.h> 50 #include <asm/ross.h> 51 52 #include "mm_32.h" 53 54 enum mbus_module srmmu_modtype; 55 static unsigned int hwbug_bitmask; 56 int vac_cache_size; 57 EXPORT_SYMBOL(vac_cache_size); 58 int vac_line_size; 59 60 extern struct resource sparc_iomap; 61 62 extern unsigned long last_valid_pfn; 63 64 static pgd_t *srmmu_swapper_pg_dir; 65 66 const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops; 67 EXPORT_SYMBOL(sparc32_cachetlb_ops); 68 69 #ifdef CONFIG_SMP 70 const struct sparc32_cachetlb_ops *local_ops; 71 72 #define FLUSH_BEGIN(mm) 73 #define FLUSH_END 74 #else 75 #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) { 76 #define FLUSH_END } 77 #endif 78 79 int flush_page_for_dma_global = 1; 80 81 char *srmmu_name; 82 83 ctxd_t *srmmu_ctx_table_phys; 84 static ctxd_t *srmmu_context_table; 85 86 int viking_mxcc_present; 87 static DEFINE_SPINLOCK(srmmu_context_spinlock); 88 89 static int is_hypersparc; 90 91 static int srmmu_cache_pagetables; 92 93 /* these will be initialized in srmmu_nocache_calcsize() */ 94 static unsigned long srmmu_nocache_size; 95 static unsigned long srmmu_nocache_end; 96 97 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */ 98 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4) 99 100 /* The context table is a nocache user with the biggest alignment needs. */ 101 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS) 102 103 void *srmmu_nocache_pool; 104 static struct bit_map srmmu_nocache_map; 105 106 static inline int srmmu_pmd_none(pmd_t pmd) 107 { return !(pmd_val(pmd) & 0xFFFFFFF); } 108 109 /* XXX should we hyper_flush_whole_icache here - Anton */ 110 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp) 111 { 112 pte_t pte; 113 114 pte = __pte((SRMMU_ET_PTD | (__nocache_pa(pgdp) >> 4))); 115 set_pte((pte_t *)ctxp, pte); 116 } 117 118 /* 119 * Locations of MSI Registers. 120 */ 121 #define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */ 122 123 /* 124 * Useful bits in the MSI Registers. 125 */ 126 #define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */ 127 128 static void msi_set_sync(void) 129 { 130 __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t" 131 "andn %%g3, %2, %%g3\n\t" 132 "sta %%g3, [%0] %1\n\t" : : 133 "r" (MSI_MBUS_ARBEN), 134 "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3"); 135 } 136 137 void pmd_set(pmd_t *pmdp, pte_t *ptep) 138 { 139 unsigned long ptp = __nocache_pa(ptep) >> 4; 140 set_pte((pte_t *)&pmd_val(*pmdp), __pte(SRMMU_ET_PTD | ptp)); 141 } 142 143 /* 144 * size: bytes to allocate in the nocache area. 145 * align: bytes, number to align at. 146 * Returns the virtual address of the allocated area. 147 */ 148 static void *__srmmu_get_nocache(int size, int align) 149 { 150 int offset, minsz = 1 << SRMMU_NOCACHE_BITMAP_SHIFT; 151 unsigned long addr; 152 153 if (size < minsz) { 154 printk(KERN_ERR "Size 0x%x too small for nocache request\n", 155 size); 156 size = minsz; 157 } 158 if (size & (minsz - 1)) { 159 printk(KERN_ERR "Size 0x%x unaligned in nocache request\n", 160 size); 161 size += minsz - 1; 162 } 163 BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX); 164 165 offset = bit_map_string_get(&srmmu_nocache_map, 166 size >> SRMMU_NOCACHE_BITMAP_SHIFT, 167 align >> SRMMU_NOCACHE_BITMAP_SHIFT); 168 if (offset == -1) { 169 printk(KERN_ERR "srmmu: out of nocache %d: %d/%d\n", 170 size, (int) srmmu_nocache_size, 171 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT); 172 return NULL; 173 } 174 175 addr = SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT); 176 return (void *)addr; 177 } 178 179 void *srmmu_get_nocache(int size, int align) 180 { 181 void *tmp; 182 183 tmp = __srmmu_get_nocache(size, align); 184 185 if (tmp) 186 memset(tmp, 0, size); 187 188 return tmp; 189 } 190 191 void srmmu_free_nocache(void *addr, int size) 192 { 193 unsigned long vaddr; 194 int offset; 195 196 vaddr = (unsigned long)addr; 197 if (vaddr < SRMMU_NOCACHE_VADDR) { 198 printk("Vaddr %lx is smaller than nocache base 0x%lx\n", 199 vaddr, (unsigned long)SRMMU_NOCACHE_VADDR); 200 BUG(); 201 } 202 if (vaddr + size > srmmu_nocache_end) { 203 printk("Vaddr %lx is bigger than nocache end 0x%lx\n", 204 vaddr, srmmu_nocache_end); 205 BUG(); 206 } 207 if (!is_power_of_2(size)) { 208 printk("Size 0x%x is not a power of 2\n", size); 209 BUG(); 210 } 211 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) { 212 printk("Size 0x%x is too small\n", size); 213 BUG(); 214 } 215 if (vaddr & (size - 1)) { 216 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size); 217 BUG(); 218 } 219 220 offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT; 221 size = size >> SRMMU_NOCACHE_BITMAP_SHIFT; 222 223 bit_map_clear(&srmmu_nocache_map, offset, size); 224 } 225 226 static void srmmu_early_allocate_ptable_skeleton(unsigned long start, 227 unsigned long end); 228 229 /* Return how much physical memory we have. */ 230 static unsigned long __init probe_memory(void) 231 { 232 unsigned long total = 0; 233 int i; 234 235 for (i = 0; sp_banks[i].num_bytes; i++) 236 total += sp_banks[i].num_bytes; 237 238 return total; 239 } 240 241 /* 242 * Reserve nocache dynamically proportionally to the amount of 243 * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002 244 */ 245 static void __init srmmu_nocache_calcsize(void) 246 { 247 unsigned long sysmemavail = probe_memory() / 1024; 248 int srmmu_nocache_npages; 249 250 srmmu_nocache_npages = 251 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256; 252 253 /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */ 254 // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256; 255 if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES) 256 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES; 257 258 /* anything above 1280 blows up */ 259 if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES) 260 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES; 261 262 srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE; 263 srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size; 264 } 265 266 static void __init srmmu_nocache_init(void) 267 { 268 void *srmmu_nocache_bitmap; 269 unsigned int bitmap_bits; 270 pgd_t *pgd; 271 p4d_t *p4d; 272 pud_t *pud; 273 pmd_t *pmd; 274 pte_t *pte; 275 unsigned long paddr, vaddr; 276 unsigned long pteval; 277 278 bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT; 279 280 srmmu_nocache_pool = memblock_alloc_or_panic(srmmu_nocache_size, 281 SRMMU_NOCACHE_ALIGN_MAX); 282 memset(srmmu_nocache_pool, 0, srmmu_nocache_size); 283 284 srmmu_nocache_bitmap = 285 memblock_alloc_or_panic(BITS_TO_LONGS(bitmap_bits) * sizeof(long), 286 SMP_CACHE_BYTES); 287 bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits); 288 289 srmmu_swapper_pg_dir = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE); 290 memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE); 291 init_mm.pgd = srmmu_swapper_pg_dir; 292 293 srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end); 294 295 paddr = __pa((unsigned long)srmmu_nocache_pool); 296 vaddr = SRMMU_NOCACHE_VADDR; 297 298 while (vaddr < srmmu_nocache_end) { 299 pgd = pgd_offset_k(vaddr); 300 p4d = p4d_offset(pgd, vaddr); 301 pud = pud_offset(p4d, vaddr); 302 pmd = pmd_offset(__nocache_fix(pud), vaddr); 303 pte = pte_offset_kernel(__nocache_fix(pmd), vaddr); 304 305 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV); 306 307 if (srmmu_cache_pagetables) 308 pteval |= SRMMU_CACHE; 309 310 set_pte(__nocache_fix(pte), __pte(pteval)); 311 312 vaddr += PAGE_SIZE; 313 paddr += PAGE_SIZE; 314 } 315 316 flush_cache_all(); 317 flush_tlb_all(); 318 } 319 320 pgd_t *get_pgd_fast(void) 321 { 322 pgd_t *pgd = NULL; 323 324 pgd = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE); 325 if (pgd) { 326 pgd_t *init = pgd_offset_k(0); 327 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t)); 328 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD, 329 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); 330 } 331 332 return pgd; 333 } 334 335 /* 336 * Hardware needs alignment to 256 only, but we align to whole page size 337 * to reduce fragmentation problems due to the buddy principle. 338 * XXX Provide actual fragmentation statistics in /proc. 339 * 340 * Alignments up to the page size are the same for physical and virtual 341 * addresses of the nocache area. 342 */ 343 pgtable_t pte_alloc_one(struct mm_struct *mm) 344 { 345 pte_t *ptep; 346 struct page *page; 347 348 if (!(ptep = pte_alloc_one_kernel(mm))) 349 return NULL; 350 page = pfn_to_page(__nocache_pa((unsigned long)ptep) >> PAGE_SHIFT); 351 spin_lock(&mm->page_table_lock); 352 if (page_ref_inc_return(page) == 2 && 353 !pagetable_pte_ctor(mm, page_ptdesc(page))) { 354 page_ref_dec(page); 355 ptep = NULL; 356 } 357 spin_unlock(&mm->page_table_lock); 358 359 return ptep; 360 } 361 362 void pte_free(struct mm_struct *mm, pgtable_t ptep) 363 { 364 struct page *page; 365 366 page = pfn_to_page(__nocache_pa((unsigned long)ptep) >> PAGE_SHIFT); 367 spin_lock(&mm->page_table_lock); 368 if (page_ref_dec_return(page) == 1) 369 pagetable_dtor(page_ptdesc(page)); 370 spin_unlock(&mm->page_table_lock); 371 372 srmmu_free_nocache(ptep, SRMMU_PTE_TABLE_SIZE); 373 } 374 375 /* context handling - a dynamically sized pool is used */ 376 #define NO_CONTEXT -1 377 378 struct ctx_list { 379 struct ctx_list *next; 380 struct ctx_list *prev; 381 unsigned int ctx_number; 382 struct mm_struct *ctx_mm; 383 }; 384 385 static struct ctx_list *ctx_list_pool; 386 static struct ctx_list ctx_free; 387 static struct ctx_list ctx_used; 388 389 /* At boot time we determine the number of contexts */ 390 static int num_contexts; 391 392 static inline void remove_from_ctx_list(struct ctx_list *entry) 393 { 394 entry->next->prev = entry->prev; 395 entry->prev->next = entry->next; 396 } 397 398 static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry) 399 { 400 entry->next = head; 401 (entry->prev = head->prev)->next = entry; 402 head->prev = entry; 403 } 404 #define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry) 405 #define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry) 406 407 408 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm) 409 { 410 struct ctx_list *ctxp; 411 412 ctxp = ctx_free.next; 413 if (ctxp != &ctx_free) { 414 remove_from_ctx_list(ctxp); 415 add_to_used_ctxlist(ctxp); 416 mm->context = ctxp->ctx_number; 417 ctxp->ctx_mm = mm; 418 return; 419 } 420 ctxp = ctx_used.next; 421 if (ctxp->ctx_mm == old_mm) 422 ctxp = ctxp->next; 423 if (ctxp == &ctx_used) 424 panic("out of mmu contexts"); 425 flush_cache_mm(ctxp->ctx_mm); 426 flush_tlb_mm(ctxp->ctx_mm); 427 remove_from_ctx_list(ctxp); 428 add_to_used_ctxlist(ctxp); 429 ctxp->ctx_mm->context = NO_CONTEXT; 430 ctxp->ctx_mm = mm; 431 mm->context = ctxp->ctx_number; 432 } 433 434 static inline void free_context(int context) 435 { 436 struct ctx_list *ctx_old; 437 438 ctx_old = ctx_list_pool + context; 439 remove_from_ctx_list(ctx_old); 440 add_to_free_ctxlist(ctx_old); 441 } 442 443 static void __init sparc_context_init(int numctx) 444 { 445 int ctx; 446 unsigned long size; 447 448 size = numctx * sizeof(struct ctx_list); 449 ctx_list_pool = memblock_alloc_or_panic(size, SMP_CACHE_BYTES); 450 451 for (ctx = 0; ctx < numctx; ctx++) { 452 struct ctx_list *clist; 453 454 clist = (ctx_list_pool + ctx); 455 clist->ctx_number = ctx; 456 clist->ctx_mm = NULL; 457 } 458 ctx_free.next = ctx_free.prev = &ctx_free; 459 ctx_used.next = ctx_used.prev = &ctx_used; 460 for (ctx = 0; ctx < numctx; ctx++) 461 add_to_free_ctxlist(ctx_list_pool + ctx); 462 } 463 464 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, 465 struct task_struct *tsk) 466 { 467 unsigned long flags; 468 469 if (mm->context == NO_CONTEXT) { 470 spin_lock_irqsave(&srmmu_context_spinlock, flags); 471 alloc_context(old_mm, mm); 472 spin_unlock_irqrestore(&srmmu_context_spinlock, flags); 473 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd); 474 } 475 476 if (sparc_cpu_model == sparc_leon) 477 leon_switch_mm(); 478 479 if (is_hypersparc) 480 hyper_flush_whole_icache(); 481 482 srmmu_set_context(mm->context); 483 } 484 485 /* Low level IO area allocation on the SRMMU. */ 486 static inline void srmmu_mapioaddr(unsigned long physaddr, 487 unsigned long virt_addr, int bus_type) 488 { 489 pgd_t *pgdp; 490 p4d_t *p4dp; 491 pud_t *pudp; 492 pmd_t *pmdp; 493 pte_t *ptep; 494 unsigned long tmp; 495 496 physaddr &= PAGE_MASK; 497 pgdp = pgd_offset_k(virt_addr); 498 p4dp = p4d_offset(pgdp, virt_addr); 499 pudp = pud_offset(p4dp, virt_addr); 500 pmdp = pmd_offset(pudp, virt_addr); 501 ptep = pte_offset_kernel(pmdp, virt_addr); 502 tmp = (physaddr >> 4) | SRMMU_ET_PTE; 503 504 /* I need to test whether this is consistent over all 505 * sun4m's. The bus_type represents the upper 4 bits of 506 * 36-bit physical address on the I/O space lines... 507 */ 508 tmp |= (bus_type << 28); 509 tmp |= SRMMU_PRIV; 510 __flush_page_to_ram(virt_addr); 511 set_pte(ptep, __pte(tmp)); 512 } 513 514 void srmmu_mapiorange(unsigned int bus, unsigned long xpa, 515 unsigned long xva, unsigned int len) 516 { 517 while (len != 0) { 518 len -= PAGE_SIZE; 519 srmmu_mapioaddr(xpa, xva, bus); 520 xva += PAGE_SIZE; 521 xpa += PAGE_SIZE; 522 } 523 flush_tlb_all(); 524 } 525 526 static inline void srmmu_unmapioaddr(unsigned long virt_addr) 527 { 528 pgd_t *pgdp; 529 p4d_t *p4dp; 530 pud_t *pudp; 531 pmd_t *pmdp; 532 pte_t *ptep; 533 534 535 pgdp = pgd_offset_k(virt_addr); 536 p4dp = p4d_offset(pgdp, virt_addr); 537 pudp = pud_offset(p4dp, virt_addr); 538 pmdp = pmd_offset(pudp, virt_addr); 539 ptep = pte_offset_kernel(pmdp, virt_addr); 540 541 /* No need to flush uncacheable page. */ 542 __pte_clear(ptep); 543 } 544 545 void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len) 546 { 547 while (len != 0) { 548 len -= PAGE_SIZE; 549 srmmu_unmapioaddr(virt_addr); 550 virt_addr += PAGE_SIZE; 551 } 552 flush_tlb_all(); 553 } 554 555 /* tsunami.S */ 556 extern void tsunami_flush_cache_all(void); 557 extern void tsunami_flush_cache_mm(struct mm_struct *mm); 558 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 559 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page); 560 extern void tsunami_flush_page_to_ram(unsigned long page); 561 extern void tsunami_flush_page_for_dma(unsigned long page); 562 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); 563 extern void tsunami_flush_tlb_all(void); 564 extern void tsunami_flush_tlb_mm(struct mm_struct *mm); 565 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 566 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); 567 extern void tsunami_setup_blockops(void); 568 569 /* swift.S */ 570 extern void swift_flush_cache_all(void); 571 extern void swift_flush_cache_mm(struct mm_struct *mm); 572 extern void swift_flush_cache_range(struct vm_area_struct *vma, 573 unsigned long start, unsigned long end); 574 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page); 575 extern void swift_flush_page_to_ram(unsigned long page); 576 extern void swift_flush_page_for_dma(unsigned long page); 577 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); 578 extern void swift_flush_tlb_all(void); 579 extern void swift_flush_tlb_mm(struct mm_struct *mm); 580 extern void swift_flush_tlb_range(struct vm_area_struct *vma, 581 unsigned long start, unsigned long end); 582 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); 583 584 585 /* 586 * The following are all MBUS based SRMMU modules, and therefore could 587 * be found in a multiprocessor configuration. On the whole, these 588 * chips seems to be much more touchy about DVMA and page tables 589 * with respect to cache coherency. 590 */ 591 592 /* viking.S */ 593 extern void viking_flush_cache_all(void); 594 extern void viking_flush_cache_mm(struct mm_struct *mm); 595 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start, 596 unsigned long end); 597 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page); 598 extern void viking_flush_page_to_ram(unsigned long page); 599 extern void viking_flush_page_for_dma(unsigned long page); 600 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr); 601 extern void viking_flush_page(unsigned long page); 602 extern void viking_mxcc_flush_page(unsigned long page); 603 extern void viking_flush_tlb_all(void); 604 extern void viking_flush_tlb_mm(struct mm_struct *mm); 605 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, 606 unsigned long end); 607 extern void viking_flush_tlb_page(struct vm_area_struct *vma, 608 unsigned long page); 609 extern void sun4dsmp_flush_tlb_all(void); 610 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm); 611 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, 612 unsigned long end); 613 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma, 614 unsigned long page); 615 616 /* hypersparc.S */ 617 extern void hypersparc_flush_cache_all(void); 618 extern void hypersparc_flush_cache_mm(struct mm_struct *mm); 619 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 620 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page); 621 extern void hypersparc_flush_page_to_ram(unsigned long page); 622 extern void hypersparc_flush_page_for_dma(unsigned long page); 623 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); 624 extern void hypersparc_flush_tlb_all(void); 625 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm); 626 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 627 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); 628 extern void hypersparc_setup_blockops(void); 629 630 /* 631 * NOTE: All of this startup code assumes the low 16mb (approx.) of 632 * kernel mappings are done with one single contiguous chunk of 633 * ram. On small ram machines (classics mainly) we only get 634 * around 8mb mapped for us. 635 */ 636 637 static void __init early_pgtable_allocfail(char *type) 638 { 639 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type); 640 prom_halt(); 641 } 642 643 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start, 644 unsigned long end) 645 { 646 pgd_t *pgdp; 647 p4d_t *p4dp; 648 pud_t *pudp; 649 pmd_t *pmdp; 650 pte_t *ptep; 651 652 while (start < end) { 653 pgdp = pgd_offset_k(start); 654 p4dp = p4d_offset(pgdp, start); 655 pudp = pud_offset(p4dp, start); 656 if (pud_none(*__nocache_fix(pudp))) { 657 pmdp = __srmmu_get_nocache( 658 SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); 659 if (pmdp == NULL) 660 early_pgtable_allocfail("pmd"); 661 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE); 662 pud_set(__nocache_fix(pudp), pmdp); 663 } 664 pmdp = pmd_offset(__nocache_fix(pudp), start); 665 if (srmmu_pmd_none(*__nocache_fix(pmdp))) { 666 ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE); 667 if (ptep == NULL) 668 early_pgtable_allocfail("pte"); 669 memset(__nocache_fix(ptep), 0, PTE_SIZE); 670 pmd_set(__nocache_fix(pmdp), ptep); 671 } 672 if (start > (0xffffffffUL - PMD_SIZE)) 673 break; 674 start = (start + PMD_SIZE) & PMD_MASK; 675 } 676 } 677 678 static void __init srmmu_allocate_ptable_skeleton(unsigned long start, 679 unsigned long end) 680 { 681 pgd_t *pgdp; 682 p4d_t *p4dp; 683 pud_t *pudp; 684 pmd_t *pmdp; 685 pte_t *ptep; 686 687 while (start < end) { 688 pgdp = pgd_offset_k(start); 689 p4dp = p4d_offset(pgdp, start); 690 pudp = pud_offset(p4dp, start); 691 if (pud_none(*pudp)) { 692 pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); 693 if (pmdp == NULL) 694 early_pgtable_allocfail("pmd"); 695 memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE); 696 pud_set((pud_t *)pgdp, pmdp); 697 } 698 pmdp = pmd_offset(pudp, start); 699 if (srmmu_pmd_none(*pmdp)) { 700 ptep = __srmmu_get_nocache(PTE_SIZE, 701 PTE_SIZE); 702 if (ptep == NULL) 703 early_pgtable_allocfail("pte"); 704 memset(ptep, 0, PTE_SIZE); 705 pmd_set(pmdp, ptep); 706 } 707 if (start > (0xffffffffUL - PMD_SIZE)) 708 break; 709 start = (start + PMD_SIZE) & PMD_MASK; 710 } 711 } 712 713 /* These flush types are not available on all chips... */ 714 static inline unsigned long srmmu_probe(unsigned long vaddr) 715 { 716 unsigned long retval; 717 718 if (sparc_cpu_model != sparc_leon) { 719 720 vaddr &= PAGE_MASK; 721 __asm__ __volatile__("lda [%1] %2, %0\n\t" : 722 "=r" (retval) : 723 "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE)); 724 } else { 725 retval = leon_swprobe(vaddr, NULL); 726 } 727 return retval; 728 } 729 730 /* 731 * This is much cleaner than poking around physical address space 732 * looking at the prom's page table directly which is what most 733 * other OS's do. Yuck... this is much better. 734 */ 735 static void __init srmmu_inherit_prom_mappings(unsigned long start, 736 unsigned long end) 737 { 738 unsigned long probed; 739 unsigned long addr; 740 pgd_t *pgdp; 741 p4d_t *p4dp; 742 pud_t *pudp; 743 pmd_t *pmdp; 744 pte_t *ptep; 745 int what; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */ 746 747 while (start <= end) { 748 if (start == 0) 749 break; /* probably wrap around */ 750 if (start == 0xfef00000) 751 start = KADB_DEBUGGER_BEGVM; 752 probed = srmmu_probe(start); 753 if (!probed) { 754 /* continue probing until we find an entry */ 755 start += PAGE_SIZE; 756 continue; 757 } 758 759 /* A red snapper, see what it really is. */ 760 what = 0; 761 addr = start - PAGE_SIZE; 762 763 if (!(start & ~(PMD_MASK))) { 764 if (srmmu_probe(addr + PMD_SIZE) == probed) 765 what = 1; 766 } 767 768 if (!(start & ~(PGDIR_MASK))) { 769 if (srmmu_probe(addr + PGDIR_SIZE) == probed) 770 what = 2; 771 } 772 773 pgdp = pgd_offset_k(start); 774 p4dp = p4d_offset(pgdp, start); 775 pudp = pud_offset(p4dp, start); 776 if (what == 2) { 777 *__nocache_fix(pgdp) = __pgd(probed); 778 start += PGDIR_SIZE; 779 continue; 780 } 781 if (pud_none(*__nocache_fix(pudp))) { 782 pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, 783 SRMMU_PMD_TABLE_SIZE); 784 if (pmdp == NULL) 785 early_pgtable_allocfail("pmd"); 786 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE); 787 pud_set(__nocache_fix(pudp), pmdp); 788 } 789 pmdp = pmd_offset(__nocache_fix(pudp), start); 790 if (what == 1) { 791 *(pmd_t *)__nocache_fix(pmdp) = __pmd(probed); 792 start += PMD_SIZE; 793 continue; 794 } 795 if (srmmu_pmd_none(*__nocache_fix(pmdp))) { 796 ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE); 797 if (ptep == NULL) 798 early_pgtable_allocfail("pte"); 799 memset(__nocache_fix(ptep), 0, PTE_SIZE); 800 pmd_set(__nocache_fix(pmdp), ptep); 801 } 802 ptep = pte_offset_kernel(__nocache_fix(pmdp), start); 803 *__nocache_fix(ptep) = __pte(probed); 804 start += PAGE_SIZE; 805 } 806 } 807 808 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID) 809 810 /* Create a third-level SRMMU 16MB page mapping. */ 811 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base) 812 { 813 pgd_t *pgdp = pgd_offset_k(vaddr); 814 unsigned long big_pte; 815 816 big_pte = KERNEL_PTE(phys_base >> 4); 817 *__nocache_fix(pgdp) = __pgd(big_pte); 818 } 819 820 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */ 821 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry) 822 { 823 unsigned long pstart = (sp_banks[sp_entry].base_addr & PGDIR_MASK); 824 unsigned long vstart = (vbase & PGDIR_MASK); 825 unsigned long vend = PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes); 826 /* Map "low" memory only */ 827 const unsigned long min_vaddr = PAGE_OFFSET; 828 const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM; 829 830 if (vstart < min_vaddr || vstart >= max_vaddr) 831 return vstart; 832 833 if (vend > max_vaddr || vend < min_vaddr) 834 vend = max_vaddr; 835 836 while (vstart < vend) { 837 do_large_mapping(vstart, pstart); 838 vstart += PGDIR_SIZE; pstart += PGDIR_SIZE; 839 } 840 return vstart; 841 } 842 843 static void __init map_kernel(void) 844 { 845 int i; 846 847 if (phys_base > 0) { 848 do_large_mapping(PAGE_OFFSET, phys_base); 849 } 850 851 for (i = 0; sp_banks[i].num_bytes != 0; i++) { 852 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i); 853 } 854 } 855 856 void (*poke_srmmu)(void) = NULL; 857 858 void __init arch_zone_limits_init(unsigned long *max_zone_pfns) 859 { 860 max_zone_pfns[ZONE_DMA] = max_low_pfn; 861 max_zone_pfns[ZONE_NORMAL] = max_low_pfn; 862 max_zone_pfns[ZONE_HIGHMEM] = highend_pfn; 863 } 864 865 void __init srmmu_paging_init(void) 866 { 867 int i; 868 phandle cpunode; 869 char node_str[128]; 870 pgd_t *pgd; 871 p4d_t *p4d; 872 pud_t *pud; 873 pmd_t *pmd; 874 pte_t *pte; 875 unsigned long pages_avail; 876 877 init_mm.context = (unsigned long) NO_CONTEXT; 878 sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */ 879 880 if (sparc_cpu_model == sun4d) 881 num_contexts = 65536; /* We know it is Viking */ 882 else { 883 /* Find the number of contexts on the srmmu. */ 884 cpunode = prom_getchild(prom_root_node); 885 num_contexts = 0; 886 while (cpunode != 0) { 887 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str)); 888 if (!strcmp(node_str, "cpu")) { 889 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8); 890 break; 891 } 892 cpunode = prom_getsibling(cpunode); 893 } 894 } 895 896 if (!num_contexts) { 897 prom_printf("Something wrong, can't find cpu node in paging_init.\n"); 898 prom_halt(); 899 } 900 901 pages_avail = 0; 902 last_valid_pfn = bootmem_init(&pages_avail); 903 904 srmmu_nocache_calcsize(); 905 srmmu_nocache_init(); 906 srmmu_inherit_prom_mappings(0xfe400000, (LINUX_OPPROM_ENDVM - PAGE_SIZE)); 907 map_kernel(); 908 909 /* ctx table has to be physically aligned to its size */ 910 srmmu_context_table = __srmmu_get_nocache(num_contexts * sizeof(ctxd_t), num_contexts * sizeof(ctxd_t)); 911 srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa(srmmu_context_table); 912 913 for (i = 0; i < num_contexts; i++) 914 srmmu_ctxd_set(__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir); 915 916 flush_cache_all(); 917 srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys); 918 #ifdef CONFIG_SMP 919 /* Stop from hanging here... */ 920 local_ops->tlb_all(); 921 #else 922 flush_tlb_all(); 923 #endif 924 poke_srmmu(); 925 926 srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END); 927 srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END); 928 929 srmmu_allocate_ptable_skeleton( 930 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP); 931 srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END); 932 933 pgd = pgd_offset_k(PKMAP_BASE); 934 p4d = p4d_offset(pgd, PKMAP_BASE); 935 pud = pud_offset(p4d, PKMAP_BASE); 936 pmd = pmd_offset(pud, PKMAP_BASE); 937 pte = pte_offset_kernel(pmd, PKMAP_BASE); 938 pkmap_page_table = pte; 939 940 flush_cache_all(); 941 flush_tlb_all(); 942 943 sparc_context_init(num_contexts); 944 } 945 946 void mmu_info(struct seq_file *m) 947 { 948 seq_printf(m, 949 "MMU type\t: %s\n" 950 "contexts\t: %d\n" 951 "nocache total\t: %ld\n" 952 "nocache used\t: %d\n", 953 srmmu_name, 954 num_contexts, 955 srmmu_nocache_size, 956 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT); 957 } 958 959 int init_new_context(struct task_struct *tsk, struct mm_struct *mm) 960 { 961 mm->context = NO_CONTEXT; 962 return 0; 963 } 964 965 void destroy_context(struct mm_struct *mm) 966 { 967 unsigned long flags; 968 969 if (mm->context != NO_CONTEXT) { 970 flush_cache_mm(mm); 971 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir); 972 flush_tlb_mm(mm); 973 spin_lock_irqsave(&srmmu_context_spinlock, flags); 974 free_context(mm->context); 975 spin_unlock_irqrestore(&srmmu_context_spinlock, flags); 976 mm->context = NO_CONTEXT; 977 } 978 } 979 980 /* Init various srmmu chip types. */ 981 static void __init srmmu_is_bad(void) 982 { 983 prom_printf("Could not determine SRMMU chip type.\n"); 984 prom_halt(); 985 } 986 987 static void __init init_vac_layout(void) 988 { 989 phandle nd; 990 int cache_lines; 991 char node_str[128]; 992 #ifdef CONFIG_SMP 993 int cpu = 0; 994 unsigned long max_size = 0; 995 unsigned long min_line_size = 0x10000000; 996 #endif 997 998 nd = prom_getchild(prom_root_node); 999 while ((nd = prom_getsibling(nd)) != 0) { 1000 prom_getstring(nd, "device_type", node_str, sizeof(node_str)); 1001 if (!strcmp(node_str, "cpu")) { 1002 vac_line_size = prom_getint(nd, "cache-line-size"); 1003 if (vac_line_size == -1) { 1004 prom_printf("can't determine cache-line-size, halting.\n"); 1005 prom_halt(); 1006 } 1007 cache_lines = prom_getint(nd, "cache-nlines"); 1008 if (cache_lines == -1) { 1009 prom_printf("can't determine cache-nlines, halting.\n"); 1010 prom_halt(); 1011 } 1012 1013 vac_cache_size = cache_lines * vac_line_size; 1014 #ifdef CONFIG_SMP 1015 if (vac_cache_size > max_size) 1016 max_size = vac_cache_size; 1017 if (vac_line_size < min_line_size) 1018 min_line_size = vac_line_size; 1019 //FIXME: cpus not contiguous!! 1020 cpu++; 1021 if (cpu >= nr_cpu_ids || !cpu_online(cpu)) 1022 break; 1023 #else 1024 break; 1025 #endif 1026 } 1027 } 1028 if (nd == 0) { 1029 prom_printf("No CPU nodes found, halting.\n"); 1030 prom_halt(); 1031 } 1032 #ifdef CONFIG_SMP 1033 vac_cache_size = max_size; 1034 vac_line_size = min_line_size; 1035 #endif 1036 printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n", 1037 (int)vac_cache_size, (int)vac_line_size); 1038 } 1039 1040 static void poke_hypersparc(void) 1041 { 1042 volatile unsigned long clear; 1043 unsigned long mreg = srmmu_get_mmureg(); 1044 1045 hyper_flush_unconditional_combined(); 1046 1047 mreg &= ~(HYPERSPARC_CWENABLE); 1048 mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE); 1049 mreg |= (HYPERSPARC_CMODE); 1050 1051 srmmu_set_mmureg(mreg); 1052 1053 #if 0 /* XXX I think this is bad news... -DaveM */ 1054 hyper_clear_all_tags(); 1055 #endif 1056 1057 put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE); 1058 hyper_flush_whole_icache(); 1059 clear = srmmu_get_faddr(); 1060 clear = srmmu_get_fstatus(); 1061 } 1062 1063 static const struct sparc32_cachetlb_ops hypersparc_ops = { 1064 .cache_all = hypersparc_flush_cache_all, 1065 .cache_mm = hypersparc_flush_cache_mm, 1066 .cache_page = hypersparc_flush_cache_page, 1067 .cache_range = hypersparc_flush_cache_range, 1068 .tlb_all = hypersparc_flush_tlb_all, 1069 .tlb_mm = hypersparc_flush_tlb_mm, 1070 .tlb_page = hypersparc_flush_tlb_page, 1071 .tlb_range = hypersparc_flush_tlb_range, 1072 .page_to_ram = hypersparc_flush_page_to_ram, 1073 .sig_insns = hypersparc_flush_sig_insns, 1074 .page_for_dma = hypersparc_flush_page_for_dma, 1075 }; 1076 1077 static void __init init_hypersparc(void) 1078 { 1079 srmmu_name = "ROSS HyperSparc"; 1080 srmmu_modtype = HyperSparc; 1081 1082 init_vac_layout(); 1083 1084 is_hypersparc = 1; 1085 sparc32_cachetlb_ops = &hypersparc_ops; 1086 1087 poke_srmmu = poke_hypersparc; 1088 1089 hypersparc_setup_blockops(); 1090 } 1091 1092 static void poke_swift(void) 1093 { 1094 unsigned long mreg; 1095 1096 /* Clear any crap from the cache or else... */ 1097 swift_flush_cache_all(); 1098 1099 /* Enable I & D caches */ 1100 mreg = srmmu_get_mmureg(); 1101 mreg |= (SWIFT_IE | SWIFT_DE); 1102 /* 1103 * The Swift branch folding logic is completely broken. At 1104 * trap time, if things are just right, if can mistakenly 1105 * think that a trap is coming from kernel mode when in fact 1106 * it is coming from user mode (it mis-executes the branch in 1107 * the trap code). So you see things like crashme completely 1108 * hosing your machine which is completely unacceptable. Turn 1109 * this shit off... nice job Fujitsu. 1110 */ 1111 mreg &= ~(SWIFT_BF); 1112 srmmu_set_mmureg(mreg); 1113 } 1114 1115 static const struct sparc32_cachetlb_ops swift_ops = { 1116 .cache_all = swift_flush_cache_all, 1117 .cache_mm = swift_flush_cache_mm, 1118 .cache_page = swift_flush_cache_page, 1119 .cache_range = swift_flush_cache_range, 1120 .tlb_all = swift_flush_tlb_all, 1121 .tlb_mm = swift_flush_tlb_mm, 1122 .tlb_page = swift_flush_tlb_page, 1123 .tlb_range = swift_flush_tlb_range, 1124 .page_to_ram = swift_flush_page_to_ram, 1125 .sig_insns = swift_flush_sig_insns, 1126 .page_for_dma = swift_flush_page_for_dma, 1127 }; 1128 1129 #define SWIFT_MASKID_ADDR 0x10003018 1130 static void __init init_swift(void) 1131 { 1132 unsigned long swift_rev; 1133 1134 __asm__ __volatile__("lda [%1] %2, %0\n\t" 1135 "srl %0, 0x18, %0\n\t" : 1136 "=r" (swift_rev) : 1137 "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS)); 1138 srmmu_name = "Fujitsu Swift"; 1139 switch (swift_rev) { 1140 case 0x11: 1141 case 0x20: 1142 case 0x23: 1143 case 0x30: 1144 srmmu_modtype = Swift_lots_o_bugs; 1145 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN); 1146 /* 1147 * Gee george, I wonder why Sun is so hush hush about 1148 * this hardware bug... really braindamage stuff going 1149 * on here. However I think we can find a way to avoid 1150 * all of the workaround overhead under Linux. Basically, 1151 * any page fault can cause kernel pages to become user 1152 * accessible (the mmu gets confused and clears some of 1153 * the ACC bits in kernel ptes). Aha, sounds pretty 1154 * horrible eh? But wait, after extensive testing it appears 1155 * that if you use pgd_t level large kernel pte's (like the 1156 * 4MB pages on the Pentium) the bug does not get tripped 1157 * at all. This avoids almost all of the major overhead. 1158 * Welcome to a world where your vendor tells you to, 1159 * "apply this kernel patch" instead of "sorry for the 1160 * broken hardware, send it back and we'll give you 1161 * properly functioning parts" 1162 */ 1163 break; 1164 case 0x25: 1165 case 0x31: 1166 srmmu_modtype = Swift_bad_c; 1167 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN; 1168 /* 1169 * You see Sun allude to this hardware bug but never 1170 * admit things directly, they'll say things like, 1171 * "the Swift chip cache problems" or similar. 1172 */ 1173 break; 1174 default: 1175 srmmu_modtype = Swift_ok; 1176 break; 1177 } 1178 1179 sparc32_cachetlb_ops = &swift_ops; 1180 flush_page_for_dma_global = 0; 1181 1182 /* 1183 * Are you now convinced that the Swift is one of the 1184 * biggest VLSI abortions of all time? Bravo Fujitsu! 1185 * Fujitsu, the !#?!%$'d up processor people. I bet if 1186 * you examined the microcode of the Swift you'd find 1187 * XXX's all over the place. 1188 */ 1189 poke_srmmu = poke_swift; 1190 } 1191 1192 static void turbosparc_flush_cache_all(void) 1193 { 1194 flush_user_windows(); 1195 turbosparc_idflash_clear(); 1196 } 1197 1198 static void turbosparc_flush_cache_mm(struct mm_struct *mm) 1199 { 1200 FLUSH_BEGIN(mm) 1201 flush_user_windows(); 1202 turbosparc_idflash_clear(); 1203 FLUSH_END 1204 } 1205 1206 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) 1207 { 1208 FLUSH_BEGIN(vma->vm_mm) 1209 flush_user_windows(); 1210 turbosparc_idflash_clear(); 1211 FLUSH_END 1212 } 1213 1214 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page) 1215 { 1216 FLUSH_BEGIN(vma->vm_mm) 1217 flush_user_windows(); 1218 if (vma->vm_flags & VM_EXEC) 1219 turbosparc_flush_icache(); 1220 turbosparc_flush_dcache(); 1221 FLUSH_END 1222 } 1223 1224 /* TurboSparc is copy-back, if we turn it on, but this does not work. */ 1225 static void turbosparc_flush_page_to_ram(unsigned long page) 1226 { 1227 #ifdef TURBOSPARC_WRITEBACK 1228 volatile unsigned long clear; 1229 1230 if (srmmu_probe(page)) 1231 turbosparc_flush_page_cache(page); 1232 clear = srmmu_get_fstatus(); 1233 #endif 1234 } 1235 1236 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) 1237 { 1238 } 1239 1240 static void turbosparc_flush_page_for_dma(unsigned long page) 1241 { 1242 turbosparc_flush_dcache(); 1243 } 1244 1245 static void turbosparc_flush_tlb_all(void) 1246 { 1247 srmmu_flush_whole_tlb(); 1248 } 1249 1250 static void turbosparc_flush_tlb_mm(struct mm_struct *mm) 1251 { 1252 FLUSH_BEGIN(mm) 1253 srmmu_flush_whole_tlb(); 1254 FLUSH_END 1255 } 1256 1257 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) 1258 { 1259 FLUSH_BEGIN(vma->vm_mm) 1260 srmmu_flush_whole_tlb(); 1261 FLUSH_END 1262 } 1263 1264 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) 1265 { 1266 FLUSH_BEGIN(vma->vm_mm) 1267 srmmu_flush_whole_tlb(); 1268 FLUSH_END 1269 } 1270 1271 1272 static void poke_turbosparc(void) 1273 { 1274 unsigned long mreg = srmmu_get_mmureg(); 1275 unsigned long ccreg; 1276 1277 /* Clear any crap from the cache or else... */ 1278 turbosparc_flush_cache_all(); 1279 /* Temporarily disable I & D caches */ 1280 mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); 1281 mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */ 1282 srmmu_set_mmureg(mreg); 1283 1284 ccreg = turbosparc_get_ccreg(); 1285 1286 #ifdef TURBOSPARC_WRITEBACK 1287 ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */ 1288 ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE); 1289 /* Write-back D-cache, emulate VLSI 1290 * abortion number three, not number one */ 1291 #else 1292 /* For now let's play safe, optimize later */ 1293 ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE); 1294 /* Do DVMA snooping in Dcache, Write-thru D-cache */ 1295 ccreg &= ~(TURBOSPARC_uS2); 1296 /* Emulate VLSI abortion number three, not number one */ 1297 #endif 1298 1299 switch (ccreg & 7) { 1300 case 0: /* No SE cache */ 1301 case 7: /* Test mode */ 1302 break; 1303 default: 1304 ccreg |= (TURBOSPARC_SCENABLE); 1305 } 1306 turbosparc_set_ccreg(ccreg); 1307 1308 mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */ 1309 mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */ 1310 srmmu_set_mmureg(mreg); 1311 } 1312 1313 static const struct sparc32_cachetlb_ops turbosparc_ops = { 1314 .cache_all = turbosparc_flush_cache_all, 1315 .cache_mm = turbosparc_flush_cache_mm, 1316 .cache_page = turbosparc_flush_cache_page, 1317 .cache_range = turbosparc_flush_cache_range, 1318 .tlb_all = turbosparc_flush_tlb_all, 1319 .tlb_mm = turbosparc_flush_tlb_mm, 1320 .tlb_page = turbosparc_flush_tlb_page, 1321 .tlb_range = turbosparc_flush_tlb_range, 1322 .page_to_ram = turbosparc_flush_page_to_ram, 1323 .sig_insns = turbosparc_flush_sig_insns, 1324 .page_for_dma = turbosparc_flush_page_for_dma, 1325 }; 1326 1327 static void __init init_turbosparc(void) 1328 { 1329 srmmu_name = "Fujitsu TurboSparc"; 1330 srmmu_modtype = TurboSparc; 1331 sparc32_cachetlb_ops = &turbosparc_ops; 1332 poke_srmmu = poke_turbosparc; 1333 } 1334 1335 static void poke_tsunami(void) 1336 { 1337 unsigned long mreg = srmmu_get_mmureg(); 1338 1339 tsunami_flush_icache(); 1340 tsunami_flush_dcache(); 1341 mreg &= ~TSUNAMI_ITD; 1342 mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB); 1343 srmmu_set_mmureg(mreg); 1344 } 1345 1346 static const struct sparc32_cachetlb_ops tsunami_ops = { 1347 .cache_all = tsunami_flush_cache_all, 1348 .cache_mm = tsunami_flush_cache_mm, 1349 .cache_page = tsunami_flush_cache_page, 1350 .cache_range = tsunami_flush_cache_range, 1351 .tlb_all = tsunami_flush_tlb_all, 1352 .tlb_mm = tsunami_flush_tlb_mm, 1353 .tlb_page = tsunami_flush_tlb_page, 1354 .tlb_range = tsunami_flush_tlb_range, 1355 .page_to_ram = tsunami_flush_page_to_ram, 1356 .sig_insns = tsunami_flush_sig_insns, 1357 .page_for_dma = tsunami_flush_page_for_dma, 1358 }; 1359 1360 static void __init init_tsunami(void) 1361 { 1362 /* 1363 * Tsunami's pretty sane, Sun and TI actually got it 1364 * somewhat right this time. Fujitsu should have 1365 * taken some lessons from them. 1366 */ 1367 1368 srmmu_name = "TI Tsunami"; 1369 srmmu_modtype = Tsunami; 1370 sparc32_cachetlb_ops = &tsunami_ops; 1371 poke_srmmu = poke_tsunami; 1372 1373 tsunami_setup_blockops(); 1374 } 1375 1376 static void poke_viking(void) 1377 { 1378 unsigned long mreg = srmmu_get_mmureg(); 1379 static int smp_catch; 1380 1381 if (viking_mxcc_present) { 1382 unsigned long mxcc_control = mxcc_get_creg(); 1383 1384 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE); 1385 mxcc_control &= ~(MXCC_CTL_RRC); 1386 mxcc_set_creg(mxcc_control); 1387 1388 /* 1389 * We don't need memory parity checks. 1390 * XXX This is a mess, have to dig out later. ecd. 1391 viking_mxcc_turn_off_parity(&mreg, &mxcc_control); 1392 */ 1393 1394 /* We do cache ptables on MXCC. */ 1395 mreg |= VIKING_TCENABLE; 1396 } else { 1397 unsigned long bpreg; 1398 1399 mreg &= ~(VIKING_TCENABLE); 1400 if (smp_catch++) { 1401 /* Must disable mixed-cmd mode here for other cpu's. */ 1402 bpreg = viking_get_bpreg(); 1403 bpreg &= ~(VIKING_ACTION_MIX); 1404 viking_set_bpreg(bpreg); 1405 1406 /* Just in case PROM does something funny. */ 1407 msi_set_sync(); 1408 } 1409 } 1410 1411 mreg |= VIKING_SPENABLE; 1412 mreg |= (VIKING_ICENABLE | VIKING_DCENABLE); 1413 mreg |= VIKING_SBENABLE; 1414 mreg &= ~(VIKING_ACENABLE); 1415 srmmu_set_mmureg(mreg); 1416 } 1417 1418 static struct sparc32_cachetlb_ops viking_ops __ro_after_init = { 1419 .cache_all = viking_flush_cache_all, 1420 .cache_mm = viking_flush_cache_mm, 1421 .cache_page = viking_flush_cache_page, 1422 .cache_range = viking_flush_cache_range, 1423 .tlb_all = viking_flush_tlb_all, 1424 .tlb_mm = viking_flush_tlb_mm, 1425 .tlb_page = viking_flush_tlb_page, 1426 .tlb_range = viking_flush_tlb_range, 1427 .page_to_ram = viking_flush_page_to_ram, 1428 .sig_insns = viking_flush_sig_insns, 1429 .page_for_dma = viking_flush_page_for_dma, 1430 }; 1431 1432 #ifdef CONFIG_SMP 1433 /* On sun4d the cpu broadcasts local TLB flushes, so we can just 1434 * perform the local TLB flush and all the other cpus will see it. 1435 * But, unfortunately, there is a bug in the sun4d XBUS backplane 1436 * that requires that we add some synchronization to these flushes. 1437 * 1438 * The bug is that the fifo which keeps track of all the pending TLB 1439 * broadcasts in the system is an entry or two too small, so if we 1440 * have too many going at once we'll overflow that fifo and lose a TLB 1441 * flush resulting in corruption. 1442 * 1443 * Our workaround is to take a global spinlock around the TLB flushes, 1444 * which guarentees we won't ever have too many pending. It's a big 1445 * hammer, but a semaphore like system to make sure we only have N TLB 1446 * flushes going at once will require SMP locking anyways so there's 1447 * no real value in trying any harder than this. 1448 */ 1449 static struct sparc32_cachetlb_ops viking_sun4d_smp_ops __ro_after_init = { 1450 .cache_all = viking_flush_cache_all, 1451 .cache_mm = viking_flush_cache_mm, 1452 .cache_page = viking_flush_cache_page, 1453 .cache_range = viking_flush_cache_range, 1454 .tlb_all = sun4dsmp_flush_tlb_all, 1455 .tlb_mm = sun4dsmp_flush_tlb_mm, 1456 .tlb_page = sun4dsmp_flush_tlb_page, 1457 .tlb_range = sun4dsmp_flush_tlb_range, 1458 .page_to_ram = viking_flush_page_to_ram, 1459 .sig_insns = viking_flush_sig_insns, 1460 .page_for_dma = viking_flush_page_for_dma, 1461 }; 1462 #endif 1463 1464 static void __init init_viking(void) 1465 { 1466 unsigned long mreg = srmmu_get_mmureg(); 1467 1468 /* Ahhh, the viking. SRMMU VLSI abortion number two... */ 1469 if (mreg & VIKING_MMODE) { 1470 srmmu_name = "TI Viking"; 1471 viking_mxcc_present = 0; 1472 msi_set_sync(); 1473 1474 /* 1475 * We need this to make sure old viking takes no hits 1476 * on its cache for dma snoops to workaround the 1477 * "load from non-cacheable memory" interrupt bug. 1478 * This is only necessary because of the new way in 1479 * which we use the IOMMU. 1480 */ 1481 viking_ops.page_for_dma = viking_flush_page; 1482 #ifdef CONFIG_SMP 1483 viking_sun4d_smp_ops.page_for_dma = viking_flush_page; 1484 #endif 1485 flush_page_for_dma_global = 0; 1486 } else { 1487 srmmu_name = "TI Viking/MXCC"; 1488 viking_mxcc_present = 1; 1489 srmmu_cache_pagetables = 1; 1490 } 1491 1492 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *) 1493 &viking_ops; 1494 #ifdef CONFIG_SMP 1495 if (sparc_cpu_model == sun4d) 1496 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *) 1497 &viking_sun4d_smp_ops; 1498 #endif 1499 1500 poke_srmmu = poke_viking; 1501 } 1502 1503 /* Probe for the srmmu chip version. */ 1504 static void __init get_srmmu_type(void) 1505 { 1506 unsigned long mreg, psr; 1507 unsigned long mod_typ, mod_rev, psr_typ, psr_vers; 1508 1509 srmmu_modtype = SRMMU_INVAL_MOD; 1510 hwbug_bitmask = 0; 1511 1512 mreg = srmmu_get_mmureg(); psr = get_psr(); 1513 mod_typ = (mreg & 0xf0000000) >> 28; 1514 mod_rev = (mreg & 0x0f000000) >> 24; 1515 psr_typ = (psr >> 28) & 0xf; 1516 psr_vers = (psr >> 24) & 0xf; 1517 1518 /* First, check for sparc-leon. */ 1519 if (sparc_cpu_model == sparc_leon) { 1520 init_leon(); 1521 return; 1522 } 1523 1524 /* Second, check for HyperSparc or Cypress. */ 1525 if (mod_typ == 1) { 1526 switch (mod_rev) { 1527 case 7: 1528 /* UP or MP Hypersparc */ 1529 init_hypersparc(); 1530 break; 1531 case 0: 1532 case 2: 1533 case 10: 1534 case 11: 1535 case 12: 1536 case 13: 1537 case 14: 1538 case 15: 1539 default: 1540 prom_printf("Sparc-Linux Cypress support does not longer exit.\n"); 1541 prom_halt(); 1542 break; 1543 } 1544 return; 1545 } 1546 1547 /* Now Fujitsu TurboSparc. It might happen that it is 1548 * in Swift emulation mode, so we will check later... 1549 */ 1550 if (psr_typ == 0 && psr_vers == 5) { 1551 init_turbosparc(); 1552 return; 1553 } 1554 1555 /* Next check for Fujitsu Swift. */ 1556 if (psr_typ == 0 && psr_vers == 4) { 1557 phandle cpunode; 1558 char node_str[128]; 1559 1560 /* Look if it is not a TurboSparc emulating Swift... */ 1561 cpunode = prom_getchild(prom_root_node); 1562 while ((cpunode = prom_getsibling(cpunode)) != 0) { 1563 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str)); 1564 if (!strcmp(node_str, "cpu")) { 1565 if (!prom_getintdefault(cpunode, "psr-implementation", 1) && 1566 prom_getintdefault(cpunode, "psr-version", 1) == 5) { 1567 init_turbosparc(); 1568 return; 1569 } 1570 break; 1571 } 1572 } 1573 1574 init_swift(); 1575 return; 1576 } 1577 1578 /* Now the Viking family of srmmu. */ 1579 if (psr_typ == 4 && 1580 ((psr_vers == 0) || 1581 ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) { 1582 init_viking(); 1583 return; 1584 } 1585 1586 /* Finally the Tsunami. */ 1587 if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) { 1588 init_tsunami(); 1589 return; 1590 } 1591 1592 /* Oh well */ 1593 srmmu_is_bad(); 1594 } 1595 1596 #ifdef CONFIG_SMP 1597 /* Local cross-calls. */ 1598 static void smp_flush_page_for_dma(unsigned long page) 1599 { 1600 xc1(local_ops->page_for_dma, page); 1601 local_ops->page_for_dma(page); 1602 } 1603 1604 static void smp_flush_cache_all(void) 1605 { 1606 xc0(local_ops->cache_all); 1607 local_ops->cache_all(); 1608 } 1609 1610 static void smp_flush_tlb_all(void) 1611 { 1612 xc0(local_ops->tlb_all); 1613 local_ops->tlb_all(); 1614 } 1615 1616 static bool any_other_mm_cpus(struct mm_struct *mm) 1617 { 1618 return cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids; 1619 } 1620 1621 static void smp_flush_cache_mm(struct mm_struct *mm) 1622 { 1623 if (mm->context != NO_CONTEXT) { 1624 if (any_other_mm_cpus(mm)) 1625 xc1(local_ops->cache_mm, (unsigned long)mm); 1626 local_ops->cache_mm(mm); 1627 } 1628 } 1629 1630 static void smp_flush_tlb_mm(struct mm_struct *mm) 1631 { 1632 if (mm->context != NO_CONTEXT) { 1633 if (any_other_mm_cpus(mm)) { 1634 xc1(local_ops->tlb_mm, (unsigned long)mm); 1635 if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm) 1636 cpumask_copy(mm_cpumask(mm), 1637 cpumask_of(smp_processor_id())); 1638 } 1639 local_ops->tlb_mm(mm); 1640 } 1641 } 1642 1643 static void smp_flush_cache_range(struct vm_area_struct *vma, 1644 unsigned long start, 1645 unsigned long end) 1646 { 1647 struct mm_struct *mm = vma->vm_mm; 1648 1649 if (mm->context != NO_CONTEXT) { 1650 if (any_other_mm_cpus(mm)) 1651 xc3(local_ops->cache_range, (unsigned long)vma, start, 1652 end); 1653 local_ops->cache_range(vma, start, end); 1654 } 1655 } 1656 1657 static void smp_flush_tlb_range(struct vm_area_struct *vma, 1658 unsigned long start, 1659 unsigned long end) 1660 { 1661 struct mm_struct *mm = vma->vm_mm; 1662 1663 if (mm->context != NO_CONTEXT) { 1664 if (any_other_mm_cpus(mm)) 1665 xc3(local_ops->tlb_range, (unsigned long)vma, start, 1666 end); 1667 local_ops->tlb_range(vma, start, end); 1668 } 1669 } 1670 1671 static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page) 1672 { 1673 struct mm_struct *mm = vma->vm_mm; 1674 1675 if (mm->context != NO_CONTEXT) { 1676 if (any_other_mm_cpus(mm)) 1677 xc2(local_ops->cache_page, (unsigned long)vma, page); 1678 local_ops->cache_page(vma, page); 1679 } 1680 } 1681 1682 static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) 1683 { 1684 struct mm_struct *mm = vma->vm_mm; 1685 1686 if (mm->context != NO_CONTEXT) { 1687 if (any_other_mm_cpus(mm)) 1688 xc2(local_ops->tlb_page, (unsigned long)vma, page); 1689 local_ops->tlb_page(vma, page); 1690 } 1691 } 1692 1693 static void smp_flush_page_to_ram(unsigned long page) 1694 { 1695 /* Current theory is that those who call this are the one's 1696 * who have just dirtied their cache with the pages contents 1697 * in kernel space, therefore we only run this on local cpu. 1698 * 1699 * XXX This experiment failed, research further... -DaveM 1700 */ 1701 #if 1 1702 xc1(local_ops->page_to_ram, page); 1703 #endif 1704 local_ops->page_to_ram(page); 1705 } 1706 1707 static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) 1708 { 1709 if (any_other_mm_cpus(mm)) 1710 xc2(local_ops->sig_insns, (unsigned long)mm, insn_addr); 1711 local_ops->sig_insns(mm, insn_addr); 1712 } 1713 1714 static struct sparc32_cachetlb_ops smp_cachetlb_ops __ro_after_init = { 1715 .cache_all = smp_flush_cache_all, 1716 .cache_mm = smp_flush_cache_mm, 1717 .cache_page = smp_flush_cache_page, 1718 .cache_range = smp_flush_cache_range, 1719 .tlb_all = smp_flush_tlb_all, 1720 .tlb_mm = smp_flush_tlb_mm, 1721 .tlb_page = smp_flush_tlb_page, 1722 .tlb_range = smp_flush_tlb_range, 1723 .page_to_ram = smp_flush_page_to_ram, 1724 .sig_insns = smp_flush_sig_insns, 1725 .page_for_dma = smp_flush_page_for_dma, 1726 }; 1727 #endif 1728 1729 /* Load up routines and constants for sun4m and sun4d mmu */ 1730 void __init load_mmu(void) 1731 { 1732 /* Functions */ 1733 get_srmmu_type(); 1734 1735 #ifdef CONFIG_SMP 1736 /* El switcheroo... */ 1737 local_ops = sparc32_cachetlb_ops; 1738 1739 if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) { 1740 smp_cachetlb_ops.tlb_all = local_ops->tlb_all; 1741 smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm; 1742 smp_cachetlb_ops.tlb_range = local_ops->tlb_range; 1743 smp_cachetlb_ops.tlb_page = local_ops->tlb_page; 1744 } 1745 1746 if (poke_srmmu == poke_viking) { 1747 /* Avoid unnecessary cross calls. */ 1748 smp_cachetlb_ops.cache_all = local_ops->cache_all; 1749 smp_cachetlb_ops.cache_mm = local_ops->cache_mm; 1750 smp_cachetlb_ops.cache_range = local_ops->cache_range; 1751 smp_cachetlb_ops.cache_page = local_ops->cache_page; 1752 1753 smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram; 1754 smp_cachetlb_ops.sig_insns = local_ops->sig_insns; 1755 smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma; 1756 } 1757 1758 /* It really is const after this point. */ 1759 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *) 1760 &smp_cachetlb_ops; 1761 #endif 1762 1763 if (sparc_cpu_model != sun4d) 1764 ld_mmu_iommu(); 1765 #ifdef CONFIG_SMP 1766 if (sparc_cpu_model == sun4d) 1767 sun4d_init_smp(); 1768 else if (sparc_cpu_model == sparc_leon) 1769 leon_init_smp(); 1770 else 1771 sun4m_init_smp(); 1772 #endif 1773 } 1774